[mirror_ubuntu-zesty-kernel.git] / arch / x86 / kernel / cpu / intel.c

#include <linux/init.h>
#include <linux/kernel.h>

#include <linux/string.h>
#include <linux/bitops.h>
#include <linux/smp.h>
#include <linux/sched.h>
#include <linux/thread_info.h>
#include <linux/module.h>

#include <asm/processor.h>
#include <asm/pgtable.h>
#include <asm/msr.h>
#include <asm/uaccess.h>
#include <asm/ds.h>
#include <asm/bugs.h>
#include <asm/cpu.h>

#ifdef CONFIG_X86_64
#include <asm/topology.h>
#include <asm/numa_64.h>
#endif

#include "cpu.h"

#ifdef CONFIG_X86_LOCAL_APIC
#include <asm/mpspec.h>
#include <asm/apic.h>
#endif

static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
{
	/* Unmask CPUID levels if masked: */
	if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
		u64 misc_enable;

		rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);

		if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
			misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
			wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
			c->cpuid_level = cpuid_eax(0);
		}
	}

	if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
		(c->x86 == 0x6 && c->x86_model >= 0x0e))
		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);

#ifdef CONFIG_X86_64
	set_cpu_cap(c, X86_FEATURE_SYSENTER32);
#else
	/* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
	if (c->x86 == 15 && c->x86_cache_alignment == 64)
		c->x86_cache_alignment = 128;
#endif

	/* CPUID workaround for 0F33/0F34 CPU */
	if (c->x86 == 0xF && c->x86_model == 0x3
	    && (c->x86_mask == 0x3 || c->x86_mask == 0x4))
		c->x86_phys_bits = 36;

	/*
	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
	 * with P/T states and does not stop in deep C-states.
	 *
	 * It is also reliable across cores and sockets. (but not across
	 * cabinets - we turn it off in that case explicitly.)
	 */
	if (c->x86_power & (1 << 8)) {
		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
		set_cpu_cap(c, X86_FEATURE_TSC_RELIABLE);
		sched_clock_stable = 1;
	}

	/*
	 * There is a known erratum on Pentium III and Core Solo
	 * and Core Duo CPUs.
	 * " Page with PAT set to WC while associated MTRR is UC
	 *   may consolidate to UC "
	 * Because of this erratum, it is better to stick with
	 * setting WC in MTRR rather than using PAT on these CPUs.
	 *
	 * Enable PAT WC only on P4, Core 2 or later CPUs.
	 */
	if (c->x86 == 6 && c->x86_model < 15)
		clear_cpu_cap(c, X86_FEATURE_PAT);
}

#ifdef CONFIG_X86_32
/*
 *	Early probe support logic for ppro memory erratum #50
 *
 *	This is called before we do cpu ident work
 */

int __cpuinit ppro_with_ram_bug(void)
{
	/* Uses data from early_cpu_detect now */
	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
	    boot_cpu_data.x86 == 6 &&
	    boot_cpu_data.x86_model == 1 &&
	    boot_cpu_data.x86_mask < 8) {
		printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
		return 1;
	}
	return 0;
}

#ifdef CONFIG_X86_F00F_BUG
static void __cpuinit trap_init_f00f_bug(void)
{
	__set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);

	/*
	 * Update the IDT descriptor and reload the IDT so that
	 * it uses the read-only mapped virtual address.
	 */
	idt_descr.address = fix_to_virt(FIX_F00F_IDT);
	load_idt(&idt_descr);
}
#endif

static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c)
{
#ifdef CONFIG_SMP
	/* calling is from identify_secondary_cpu() ? */
	if (c->cpu_index == boot_cpu_id)
		return;

	/*
	 * Mask B, Pentium, but not Pentium MMX
	 */
	if (c->x86 == 5 &&
	    c->x86_mask >= 1 && c->x86_mask <= 4 &&
	    c->x86_model <= 3) {
		/*
		 * Remember we have B step Pentia with bugs
		 */
		WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
				    "with B stepping processors.\n");
	}
#endif
}

static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
{
	unsigned long lo, hi;

#ifdef CONFIG_X86_F00F_BUG
	/*
	 * All current models of Pentium and Pentium with MMX technology CPUs
	 * have the F0 0F bug, which lets nonprivileged users lock up the system.
	 * Note that the workaround only should be initialized once...
	 */
	c->f00f_bug = 0;
	if (!paravirt_enabled() && c->x86 == 5) {
		static int f00f_workaround_enabled;

		c->f00f_bug = 1;
		if (!f00f_workaround_enabled) {
			trap_init_f00f_bug();
			printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
			f00f_workaround_enabled = 1;
		}
	}
#endif

	/*
	 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
	 * model 3 mask 3
	 */
	if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
		clear_cpu_cap(c, X86_FEATURE_SEP);

	/*
	 * P4 Xeon errata 037 workaround.
	 * Hardware prefetcher may cause stale data to be loaded into the cache.
	 */
	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
		rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
		if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) {
			printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
			printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
			lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;
			wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
		}
	}

	/*
	 * See if we have a good local APIC by checking for buggy Pentia,
	 * i.e. all B steppings and the C2 stepping of P54C when using their
	 * integrated APIC (see 11AP erratum in "Pentium Processor
	 * Specification Update").
	 */
	if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
	    (c->x86_mask < 0x6 || c->x86_mask == 0xb))
		set_cpu_cap(c, X86_FEATURE_11AP);


#ifdef CONFIG_X86_INTEL_USERCOPY
	/*
	 * Set up the preferred alignment for movsl bulk memory moves
	 */
	switch (c->x86) {
	case 4:		/* 486: untested */
		break;
	case 5:		/* Old Pentia: untested */
		break;
	case 6:		/* PII/PIII only like movsl with 8-byte alignment */
		movsl_mask.mask = 7;
		break;
	case 15:	/* P4 is OK down to 8-byte alignment */
		movsl_mask.mask = 7;
		break;
	}
#endif

#ifdef CONFIG_X86_NUMAQ
	numaq_tsc_disable();
#endif

	intel_smp_check(c);
}
#else
static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
{
}
#endif

static void __cpuinit srat_detect_node(void)
{
#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
	unsigned node;
	int cpu = smp_processor_id();
	int apicid = hard_smp_processor_id();

	/* Don't do the funky fallback heuristics the AMD version employs
	   for now. */
	node = apicid_to_node[apicid];
	if (node == NUMA_NO_NODE || !node_online(node))
		node = first_node(node_online_map);
	numa_set_node(cpu, node);

	printk(KERN_INFO "CPU %d/0x%x -> Node %d\n", cpu, apicid, node);
#endif
}

/*
 * find out the number of processor cores on the die
 */
static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
{
	unsigned int eax, ebx, ecx, edx;

	if (c->cpuid_level < 4)
		return 1;

	/* Intel has a non-standard dependency on %ecx for this CPUID level. */
	cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
	if (eax & 0x1f)
		return ((eax >> 26) + 1);
	else
		return 1;
}

static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
{
	/* Intel VMX MSR indicated features */
#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW	0x00200000
#define X86_VMX_FEATURE_PROC_CTLS_VNMI		0x00400000
#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS	0x80000000
#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC	0x00000001
#define X86_VMX_FEATURE_PROC_CTLS2_EPT		0x00000002
#define X86_VMX_FEATURE_PROC_CTLS2_VPID		0x00000020

	u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;

	clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
	clear_cpu_cap(c, X86_FEATURE_VNMI);
	clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
	clear_cpu_cap(c, X86_FEATURE_EPT);
	clear_cpu_cap(c, X86_FEATURE_VPID);

	rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
	msr_ctl = vmx_msr_high | vmx_msr_low;
	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
		set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
		set_cpu_cap(c, X86_FEATURE_VNMI);
	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
		rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
		      vmx_msr_low, vmx_msr_high);
		msr_ctl2 = vmx_msr_high | vmx_msr_low;
		if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
		    (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
			set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
		if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
			set_cpu_cap(c, X86_FEATURE_EPT);
		if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
			set_cpu_cap(c, X86_FEATURE_VPID);
	}
}

static void __cpuinit init_intel(struct cpuinfo_x86 *c)
{
	unsigned int l2 = 0;

	early_init_intel(c);

	intel_workarounds(c);

	/*
	 * Detect the extended topology information if available. This
	 * will reinitialise the initial_apicid which will be used
	 * in init_intel_cacheinfo()
	 */
	detect_extended_topology(c);

	l2 = init_intel_cacheinfo(c);
	if (c->cpuid_level > 9) {
		unsigned eax = cpuid_eax(10);
		/* Check for version and the number of counters */
		if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
			set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
	}

	if (cpu_has_xmm2)
		set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
	if (cpu_has_ds) {
		unsigned int l1;
		rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
		if (!(l1 & (1<<11)))
			set_cpu_cap(c, X86_FEATURE_BTS);
		if (!(l1 & (1<<12)))
			set_cpu_cap(c, X86_FEATURE_PEBS);
		ds_init_intel(c);
	}

	if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush)
		set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR);

#ifdef CONFIG_X86_64
	if (c->x86 == 15)
		c->x86_cache_alignment = c->x86_clflush_size * 2;
	if (c->x86 == 6)
		set_cpu_cap(c, X86_FEATURE_REP_GOOD);
#else
	/*
	 * Names for the Pentium II/Celeron processors
	 * detectable only by also checking the cache size.
	 * Dixon is NOT a Celeron.
	 */
	if (c->x86 == 6) {
		char *p = NULL;

		switch (c->x86_model) {
		case 5:
			if (c->x86_mask == 0) {
				if (l2 == 0)
					p = "Celeron (Covington)";
				else if (l2 == 256)
					p = "Mobile Pentium II (Dixon)";
			}
			break;

		case 6:
			if (l2 == 128)
				p = "Celeron (Mendocino)";
			else if (c->x86_mask == 0 || c->x86_mask == 5)
				p = "Celeron-A";
			break;

		case 8:
			if (l2 == 128)
				p = "Celeron (Coppermine)";
			break;
		}

		if (p)
			strcpy(c->x86_model_id, p);
	}

	if (c->x86 == 15)
		set_cpu_cap(c, X86_FEATURE_P4);
	if (c->x86 == 6)
		set_cpu_cap(c, X86_FEATURE_P3);
#endif

	if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
		/*
		 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
		 * detection.
		 */
		c->x86_max_cores = intel_num_cpu_cores(c);
#ifdef CONFIG_X86_32
		detect_ht(c);
#endif
	}

	/* Work around errata */
	srat_detect_node();

	if (cpu_has(c, X86_FEATURE_VMX))
		detect_vmx_virtcap(c);
}

#ifdef CONFIG_X86_32
static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
{
	/*
	 * Intel PIII Tualatin. This comes in two flavours.
	 * One has 256kb of cache, the other 512. We have no way
	 * to determine which, so we use a boottime override
	 * for the 512kb model, and assume 256 otherwise.
	 */
	if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
		size = 256;
	return size;
}
#endif

static const struct cpu_dev __cpuinitconst intel_cpu_dev = {
	.c_vendor	= "Intel",
	.c_ident	= { "GenuineIntel" },
#ifdef CONFIG_X86_32
	.c_models = {
		{ .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
		  {
			  [0] = "486 DX-25/33",
			  [1] = "486 DX-50",
			  [2] = "486 SX",
			  [3] = "486 DX/2",
			  [4] = "486 SL",
			  [5] = "486 SX/2",
			  [7] = "486 DX/2-WB",
			  [8] = "486 DX/4",
			  [9] = "486 DX/4-WB"
		  }
		},
		{ .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
		  {
			  [0] = "Pentium 60/66 A-step",
			  [1] = "Pentium 60/66",
			  [2] = "Pentium 75 - 200",
			  [3] = "OverDrive PODP5V83",
			  [4] = "Pentium MMX",
			  [7] = "Mobile Pentium 75 - 200",
			  [8] = "Mobile Pentium MMX"
		  }
		},
		{ .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
		  {
			  [0] = "Pentium Pro A-step",
			  [1] = "Pentium Pro",
			  [3] = "Pentium II (Klamath)",
			  [4] = "Pentium II (Deschutes)",
			  [5] = "Pentium II (Deschutes)",
			  [6] = "Mobile Pentium II",
			  [7] = "Pentium III (Katmai)",
			  [8] = "Pentium III (Coppermine)",
			  [10] = "Pentium III (Cascades)",
			  [11] = "Pentium III (Tualatin)",
		  }
		},
		{ .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
		  {
			  [0] = "Pentium 4 (Unknown)",
			  [1] = "Pentium 4 (Willamette)",
			  [2] = "Pentium 4 (Northwood)",
			  [4] = "Pentium 4 (Foster)",
			  [5] = "Pentium 4 (Foster)",
		  }
		},
	},
	.c_size_cache	= intel_size_cache,
#endif
	.c_early_init   = early_init_intel,
	.c_init		= init_intel,
	.c_x86_vendor	= X86_VENDOR_INTEL,
};

cpu_dev_register(intel_cpu_dev);
Commit	Line	Data
1da177e4 LT	1	#include <linux/init.h>
	2	#include <linux/kernel.h>
	3
	4	#include <linux/string.h>
	5	#include <linux/bitops.h>
	6	#include <linux/smp.h>
83ce4009	7	#include <linux/sched.h>
1da177e4	8	#include <linux/thread_info.h>
53e86b91	9	#include <linux/module.h>
1da177e4 LT	10
1da177e4 LT	11	#include <asm/processor.h>
d72b1b4f	12	#include <asm/pgtable.h>
1da177e4 LT	13	#include <asm/msr.h>
1da177e4 LT	14	#include <asm/uaccess.h>
eee3af4a	15	#include <asm/ds.h>
73bdb73f	16	#include <asm/bugs.h>
1f442d70	17	#include <asm/cpu.h>
1da177e4	18
185f3b9d YL	19	#ifdef CONFIG_X86_64
	20	#include <asm/topology.h>
	21	#include <asm/numa_64.h>
	22	#endif
	23
1da177e4 LT	24	#include "cpu.h"
	25
	26	#ifdef CONFIG_X86_LOCAL_APIC
	27	#include <asm/mpspec.h>
	28	#include <asm/apic.h>
1da177e4 LT	29	#endif
1da177e4 LT	30
03ae5768	31	static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
1da177e4	32	{
99fb4d34	33	/* Unmask CPUID levels if masked: */
30a0fb94	34	if (c->x86 > 6 \|\| (c->x86 == 6 && c->x86_model >= 0xd)) {
99fb4d34	35	u64 misc_enable;
066941bd	36
99fb4d34 IM	37	rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
	38
	39	if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
	40	misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
	41	wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
	42	c->cpuid_level = cpuid_eax(0);
	43	}
066941bd PA	44	}
066941bd PA	45
2b16a235 AK	46	if ((c->x86 == 0xf && c->x86_model >= 0x03) \|\|
	47	(c->x86 == 0x6 && c->x86_model >= 0x0e))
	48	set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
185f3b9d YL	49
	50	#ifdef CONFIG_X86_64
	51	set_cpu_cap(c, X86_FEATURE_SYSENTER32);
	52	#else
	53	/* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
	54	if (c->x86 == 15 && c->x86_cache_alignment == 64)
	55	c->x86_cache_alignment = 128;
	56	#endif
40fb1715	57
13c6c532 JB	58	/* CPUID workaround for 0F33/0F34 CPU */
	59	if (c->x86 == 0xF && c->x86_model == 0x3
	60	&& (c->x86_mask == 0x3 \|\| c->x86_mask == 0x4))
	61	c->x86_phys_bits = 36;
	62
40fb1715 VP	63	/*
40fb1715 VP	64	* c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
83ce4009 IM	65	* with P/T states and does not stop in deep C-states.
	66	*
	67	* It is also reliable across cores and sockets. (but not across
	68	* cabinets - we turn it off in that case explicitly.)
40fb1715 VP	69	*/
	70	if (c->x86_power & (1 << 8)) {
	71	set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
	72	set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
83ce4009 IM	73	set_cpu_cap(c, X86_FEATURE_TSC_RELIABLE);
83ce4009 IM	74	sched_clock_stable = 1;
40fb1715 VP	75	}
40fb1715 VP	76
75a04811 PA	77	/*
	78	* There is a known erratum on Pentium III and Core Solo
	79	* and Core Duo CPUs.
	80	* " Page with PAT set to WC while associated MTRR is UC
	81	* may consolidate to UC "
	82	* Because of this erratum, it is better to stick with
	83	* setting WC in MTRR rather than using PAT on these CPUs.
	84	*
	85	* Enable PAT WC only on P4, Core 2 or later CPUs.
	86	*/
	87	if (c->x86 == 6 && c->x86_model < 15)
	88	clear_cpu_cap(c, X86_FEATURE_PAT);
1da177e4 LT	89	}
1da177e4 LT	90
185f3b9d	91	#ifdef CONFIG_X86_32
1da177e4 LT	92	/*
	93	* Early probe support logic for ppro memory erratum #50
	94	*
	95	* This is called before we do cpu ident work
	96	*/
65eb6b43	97
3bc9b76b	98	int __cpuinit ppro_with_ram_bug(void)
1da177e4 LT	99	{
	100	/* Uses data from early_cpu_detect now */
	101	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
	102	boot_cpu_data.x86 == 6 &&
	103	boot_cpu_data.x86_model == 1 &&
	104	boot_cpu_data.x86_mask < 8) {
	105	printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
	106	return 1;
	107	}
	108	return 0;
	109	}
65eb6b43	110
4052704d YL	111	#ifdef CONFIG_X86_F00F_BUG
	112	static void __cpuinit trap_init_f00f_bug(void)
	113	{
	114	__set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
1da177e4	115
4052704d YL	116	/*
	117	* Update the IDT descriptor and reload the IDT so that
	118	* it uses the read-only mapped virtual address.
	119	*/
	120	idt_descr.address = fix_to_virt(FIX_F00F_IDT);
	121	load_idt(&idt_descr);
	122	}
	123	#endif
	124
1f442d70 YL	125	static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c)
	126	{
	127	#ifdef CONFIG_SMP
	128	/* calling is from identify_secondary_cpu() ? */
	129	if (c->cpu_index == boot_cpu_id)
	130	return;
	131
	132	/*
	133	* Mask B, Pentium, but not Pentium MMX
	134	*/
	135	if (c->x86 == 5 &&
	136	c->x86_mask >= 1 && c->x86_mask <= 4 &&
	137	c->x86_model <= 3) {
	138	/*
	139	* Remember we have B step Pentia with bugs
	140	*/
	141	WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
	142	"with B stepping processors.\n");
	143	}
	144	#endif
	145	}
	146
4052704d	147	static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
1da177e4 LT	148	{
	149	unsigned long lo, hi;
	150
4052704d YL	151	#ifdef CONFIG_X86_F00F_BUG
	152	/*
	153	* All current models of Pentium and Pentium with MMX technology CPUs
	154	* have the F0 0F bug, which lets nonprivileged users lock up the system.
	155	* Note that the workaround only should be initialized once...
	156	*/
	157	c->f00f_bug = 0;
	158	if (!paravirt_enabled() && c->x86 == 5) {
	159	static int f00f_workaround_enabled;
	160
	161	c->f00f_bug = 1;
	162	if (!f00f_workaround_enabled) {
	163	trap_init_f00f_bug();
	164	printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
	165	f00f_workaround_enabled = 1;
	166	}
	167	}
	168	#endif
	169
	170	/*
	171	* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
	172	* model 3 mask 3
	173	*/
	174	if ((c->x86<<8 \| c->x86_model<<4 \| c->x86_mask) < 0x633)
	175	clear_cpu_cap(c, X86_FEATURE_SEP);
	176
	177	/*
	178	* P4 Xeon errata 037 workaround.
	179	* Hardware prefetcher may cause stale data to be loaded into the cache.
	180	*/
1da177e4	181	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
65eb6b43	182	rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
ecab22aa	183	if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) {
1da177e4 LT	184	printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
1da177e4 LT	185	printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
ecab22aa	186	lo \|= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;
1da177e4 LT	187	wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
	188	}
	189	}
1da177e4	190
4052704d YL	191	/*
	192	* See if we have a good local APIC by checking for buggy Pentia,
	193	* i.e. all B steppings and the C2 stepping of P54C when using their
	194	* integrated APIC (see 11AP erratum in "Pentium Processor
	195	* Specification Update").
	196	*/
	197	if (cpu_has_apic && (c->x86<<8 \| c->x86_model<<4) == 0x520 &&
	198	(c->x86_mask < 0x6 \|\| c->x86_mask == 0xb))
	199	set_cpu_cap(c, X86_FEATURE_11AP);
185f3b9d	200
185f3b9d	201
4052704d	202	#ifdef CONFIG_X86_INTEL_USERCOPY
185f3b9d	203	/*
4052704d	204	* Set up the preferred alignment for movsl bulk memory moves
185f3b9d	205	*/
4052704d YL	206	switch (c->x86) {
	207	case 4: /* 486: untested */
	208	break;
	209	case 5: /* Old Pentia: untested */
	210	break;
	211	case 6: /* PII/PIII only like movsl with 8-byte alignment */
	212	movsl_mask.mask = 7;
	213	break;
	214	case 15: /* P4 is OK down to 8-byte alignment */
	215	movsl_mask.mask = 7;
	216	break;
	217	}
185f3b9d	218	#endif
4052704d YL	219
	220	#ifdef CONFIG_X86_NUMAQ
	221	numaq_tsc_disable();
	222	#endif
1f442d70 YL	223
1f442d70 YL	224	intel_smp_check(c);
4052704d YL	225	}
	226	#else
	227	static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
	228	{
	229	}
185f3b9d YL	230	#endif
	231
	232	static void __cpuinit srat_detect_node(void)
	233	{
	234	#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
	235	unsigned node;
	236	int cpu = smp_processor_id();
	237	int apicid = hard_smp_processor_id();
	238
	239	/* Don't do the funky fallback heuristics the AMD version employs
	240	for now. */
	241	node = apicid_to_node[apicid];
	242	if (node == NUMA_NO_NODE \|\| !node_online(node))
	243	node = first_node(node_online_map);
	244	numa_set_node(cpu, node);
	245
823b259b	246	printk(KERN_INFO "CPU %d/0x%x -> Node %d\n", cpu, apicid, node);
185f3b9d YL	247	#endif
	248	}
	249
3dd9d514 AK	250	/*
	251	* find out the number of processor cores on the die
	252	*/
f69feff7	253	static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
3dd9d514	254	{
f2ab4461	255	unsigned int eax, ebx, ecx, edx;
3dd9d514 AK	256
	257	if (c->cpuid_level < 4)
	258	return 1;
	259
f2ab4461 ZA	260	/* Intel has a non-standard dependency on %ecx for this CPUID level. */
f2ab4461 ZA	261	cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
3dd9d514 AK	262	if (eax & 0x1f)
	263	return ((eax >> 26) + 1);
	264	else
	265	return 1;
	266	}
	267
e38e05a8 SY	268	static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
	269	{
	270	/* Intel VMX MSR indicated features */
	271	#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
	272	#define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
	273	#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
	274	#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
	275	#define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
	276	#define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
	277
	278	u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
	279
	280	clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
	281	clear_cpu_cap(c, X86_FEATURE_VNMI);
	282	clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
	283	clear_cpu_cap(c, X86_FEATURE_EPT);
	284	clear_cpu_cap(c, X86_FEATURE_VPID);
	285
	286	rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
	287	msr_ctl = vmx_msr_high \| vmx_msr_low;
	288	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
	289	set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
	290	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
	291	set_cpu_cap(c, X86_FEATURE_VNMI);
	292	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
	293	rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
	294	vmx_msr_low, vmx_msr_high);
	295	msr_ctl2 = vmx_msr_high \| vmx_msr_low;
	296	if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
	297	(msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
	298	set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
	299	if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
	300	set_cpu_cap(c, X86_FEATURE_EPT);
	301	if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
	302	set_cpu_cap(c, X86_FEATURE_VPID);
	303	}
	304	}
	305
3bc9b76b	306	static void __cpuinit init_intel(struct cpuinfo_x86 *c)
1da177e4 LT	307	{
1da177e4 LT	308	unsigned int l2 = 0;
1da177e4	309
2b16a235 AK	310	early_init_intel(c);
2b16a235 AK	311
4052704d	312	intel_workarounds(c);
1da177e4	313
345077cd SS	314	/*
	315	* Detect the extended topology information if available. This
	316	* will reinitialise the initial_apicid which will be used
	317	* in init_intel_cacheinfo()
	318	*/
	319	detect_extended_topology(c);
	320
1da177e4	321	l2 = init_intel_cacheinfo(c);
65eb6b43	322	if (c->cpuid_level > 9) {
0080e667 VP	323	unsigned eax = cpuid_eax(10);
	324	/* Check for version and the number of counters */
	325	if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
d0e95ebd	326	set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
0080e667	327	}
1da177e4	328
4052704d YL	329	if (cpu_has_xmm2)
	330	set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
	331	if (cpu_has_ds) {
	332	unsigned int l1;
	333	rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
	334	if (!(l1 & (1<<11)))
	335	set_cpu_cap(c, X86_FEATURE_BTS);
	336	if (!(l1 & (1<<12)))
	337	set_cpu_cap(c, X86_FEATURE_PEBS);
	338	ds_init_intel(c);
	339	}
1da177e4	340
e736ad54 PV	341	if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush)
	342	set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR);
	343
4052704d YL	344	#ifdef CONFIG_X86_64
	345	if (c->x86 == 15)
	346	c->x86_cache_alignment = c->x86_clflush_size * 2;
	347	if (c->x86 == 6)
	348	set_cpu_cap(c, X86_FEATURE_REP_GOOD);
	349	#else
65eb6b43 PC	350	/*
	351	* Names for the Pentium II/Celeron processors
	352	* detectable only by also checking the cache size.
	353	* Dixon is NOT a Celeron.
	354	*/
1da177e4	355	if (c->x86 == 6) {
4052704d YL	356	char *p = NULL;
4052704d YL	357
1da177e4 LT	358	switch (c->x86_model) {
	359	case 5:
	360	if (c->x86_mask == 0) {
	361	if (l2 == 0)
	362	p = "Celeron (Covington)";
	363	else if (l2 == 256)
	364	p = "Mobile Pentium II (Dixon)";
	365	}
	366	break;
65eb6b43	367
1da177e4 LT	368	case 6:
	369	if (l2 == 128)
	370	p = "Celeron (Mendocino)";
	371	else if (c->x86_mask == 0 \|\| c->x86_mask == 5)
	372	p = "Celeron-A";
	373	break;
65eb6b43	374
1da177e4 LT	375	case 8:
	376	if (l2 == 128)
	377	p = "Celeron (Coppermine)";
	378	break;
	379	}
1da177e4	380
4052704d YL	381	if (p)
4052704d YL	382	strcpy(c->x86_model_id, p);
1da177e4	383	}
1da177e4	384
185f3b9d YL	385	if (c->x86 == 15)
	386	set_cpu_cap(c, X86_FEATURE_P4);
	387	if (c->x86 == 6)
	388	set_cpu_cap(c, X86_FEATURE_P3);
f4166c54	389	#endif
185f3b9d	390
185f3b9d YL	391	if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
	392	/*
	393	* let's use the legacy cpuid vector 0x1 and 0x4 for topology
	394	* detection.
	395	*/
	396	c->x86_max_cores = intel_num_cpu_cores(c);
	397	#ifdef CONFIG_X86_32
	398	detect_ht(c);
	399	#endif
	400	}
	401
	402	/* Work around errata */
	403	srat_detect_node();
e38e05a8 SY	404
	405	if (cpu_has(c, X86_FEATURE_VMX))
	406	detect_vmx_virtcap(c);
42ed458a	407	}
1da177e4	408
185f3b9d	409	#ifdef CONFIG_X86_32
65eb6b43	410	static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
1da177e4	411	{
65eb6b43 PC	412	/*
65eb6b43 PC	413	* Intel PIII Tualatin. This comes in two flavours.
1da177e4 LT	414	* One has 256kb of cache, the other 512. We have no way
	415	* to determine which, so we use a boottime override
	416	* for the 512kb model, and assume 256 otherwise.
	417	*/
	418	if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
	419	size = 256;
	420	return size;
	421	}
185f3b9d	422	#endif
1da177e4	423
02dde8b4	424	static const struct cpu_dev __cpuinitconst intel_cpu_dev = {
1da177e4	425	.c_vendor = "Intel",
65eb6b43	426	.c_ident = { "GenuineIntel" },
185f3b9d	427	#ifdef CONFIG_X86_32
1da177e4	428	.c_models = {
65eb6b43 PC	429	{ .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
	430	{
	431	[0] = "486 DX-25/33",
	432	[1] = "486 DX-50",
	433	[2] = "486 SX",
	434	[3] = "486 DX/2",
	435	[4] = "486 SL",
	436	[5] = "486 SX/2",
	437	[7] = "486 DX/2-WB",
	438	[8] = "486 DX/4",
1da177e4 LT	439	[9] = "486 DX/4-WB"
	440	}
	441	},
	442	{ .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
65eb6b43 PC	443	{
	444	[0] = "Pentium 60/66 A-step",
	445	[1] = "Pentium 60/66",
1da177e4	446	[2] = "Pentium 75 - 200",
65eb6b43	447	[3] = "OverDrive PODP5V83",
1da177e4	448	[4] = "Pentium MMX",
65eb6b43	449	[7] = "Mobile Pentium 75 - 200",
1da177e4 LT	450	[8] = "Mobile Pentium MMX"
	451	}
	452	},
	453	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
65eb6b43	454	{
1da177e4	455	[0] = "Pentium Pro A-step",
65eb6b43 PC	456	[1] = "Pentium Pro",
	457	[3] = "Pentium II (Klamath)",
	458	[4] = "Pentium II (Deschutes)",
	459	[5] = "Pentium II (Deschutes)",
1da177e4	460	[6] = "Mobile Pentium II",
65eb6b43 PC	461	[7] = "Pentium III (Katmai)",
65eb6b43 PC	462	[8] = "Pentium III (Coppermine)",
1da177e4 LT	463	[10] = "Pentium III (Cascades)",
	464	[11] = "Pentium III (Tualatin)",
	465	}
	466	},
	467	{ .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
	468	{
	469	[0] = "Pentium 4 (Unknown)",
	470	[1] = "Pentium 4 (Willamette)",
	471	[2] = "Pentium 4 (Northwood)",
	472	[4] = "Pentium 4 (Foster)",
	473	[5] = "Pentium 4 (Foster)",
	474	}
	475	},
	476	},
185f3b9d YL	477	.c_size_cache = intel_size_cache,
185f3b9d YL	478	#endif
03ae5768	479	.c_early_init = early_init_intel,
1da177e4	480	.c_init = init_intel,
10a434fc	481	.c_x86_vendor = X86_VENDOR_INTEL,
1da177e4 LT	482	};
1da177e4 LT	483
10a434fc	484	cpu_dev_register(intel_cpu_dev);
1da177e4	485