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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
c767a54b | 10 | |
e9eee03e IM |
11 | #include <linux/thread_info.h> |
12 | #include <linux/capability.h> | |
13 | #include <linux/miscdevice.h> | |
14 | #include <linux/ratelimit.h> | |
e9eee03e | 15 | #include <linux/rcupdate.h> |
e9eee03e | 16 | #include <linux/kobject.h> |
14a02530 | 17 | #include <linux/uaccess.h> |
e9eee03e IM |
18 | #include <linux/kdebug.h> |
19 | #include <linux/kernel.h> | |
20 | #include <linux/percpu.h> | |
1da177e4 | 21 | #include <linux/string.h> |
8a25a2fd | 22 | #include <linux/device.h> |
f3c6ea1b | 23 | #include <linux/syscore_ops.h> |
3c079792 | 24 | #include <linux/delay.h> |
8c566ef5 | 25 | #include <linux/ctype.h> |
e9eee03e | 26 | #include <linux/sched.h> |
0d7482e3 | 27 | #include <linux/sysfs.h> |
e9eee03e | 28 | #include <linux/types.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
e9eee03e IM |
30 | #include <linux/init.h> |
31 | #include <linux/kmod.h> | |
32 | #include <linux/poll.h> | |
3c079792 | 33 | #include <linux/nmi.h> |
e9eee03e | 34 | #include <linux/cpu.h> |
011d8261 | 35 | #include <linux/ras.h> |
14a02530 | 36 | #include <linux/smp.h> |
e9eee03e | 37 | #include <linux/fs.h> |
9b1beaf2 | 38 | #include <linux/mm.h> |
5be9ed25 | 39 | #include <linux/debugfs.h> |
b77e70bf | 40 | #include <linux/irq_work.h> |
69c60c88 | 41 | #include <linux/export.h> |
3637efb0 | 42 | #include <linux/jump_label.h> |
284ce401 | 43 | #include <linux/set_memory.h> |
e9eee03e | 44 | |
3f5a7896 | 45 | #include <asm/intel-family.h> |
d88203d1 | 46 | #include <asm/processor.h> |
95927475 | 47 | #include <asm/traps.h> |
375074cc | 48 | #include <asm/tlbflush.h> |
e9eee03e IM |
49 | #include <asm/mce.h> |
50 | #include <asm/msr.h> | |
5bc32950 | 51 | #include <asm/reboot.h> |
1da177e4 | 52 | |
21afaf18 | 53 | #include "internal.h" |
711c2e48 | 54 | |
5de97c9f | 55 | static DEFINE_MUTEX(mce_log_mutex); |
f56e8a07 | 56 | |
b3b7c479 SH |
57 | /* sysfs synchronization */ |
58 | static DEFINE_MUTEX(mce_sysfs_mutex); | |
59 | ||
8968f9d3 HS |
60 | #define CREATE_TRACE_POINTS |
61 | #include <trace/events/mce.h> | |
62 | ||
3f2f0680 | 63 | #define SPINUNIT 100 /* 100ns */ |
3c079792 | 64 | |
01ca79f1 AK |
65 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
66 | ||
1462594b | 67 | struct mce_bank *mce_banks __read_mostly; |
bf80bbd7 | 68 | struct mce_vendor_flags mce_flags __read_mostly; |
cebe1820 | 69 | |
d203f0b8 | 70 | struct mca_config mca_cfg __read_mostly = { |
84c2559d | 71 | .bootlog = -1, |
d203f0b8 BP |
72 | /* |
73 | * Tolerant levels: | |
74 | * 0: always panic on uncorrected errors, log corrected errors | |
75 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
76 | * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors | |
77 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
78 | */ | |
84c2559d BP |
79 | .tolerant = 1, |
80 | .monarch_timeout = -1 | |
d203f0b8 BP |
81 | }; |
82 | ||
3c079792 | 83 | static DEFINE_PER_CPU(struct mce, mces_seen); |
5de97c9f TL |
84 | static unsigned long mce_need_notify; |
85 | static int cpu_missing; | |
3c079792 | 86 | |
0644414e NR |
87 | /* |
88 | * MCA banks polled by the period polling timer for corrected events. | |
89 | * With Intel CMCI, this only has MCA banks which do not support CMCI (if any). | |
90 | */ | |
ee031c31 AK |
91 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { |
92 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
93 | }; | |
94 | ||
c3d1fb56 NR |
95 | /* |
96 | * MCA banks controlled through firmware first for corrected errors. | |
97 | * This is a global list of banks for which we won't enable CMCI and we | |
98 | * won't poll. Firmware controls these banks and is responsible for | |
99 | * reporting corrected errors through GHES. Uncorrected/recoverable | |
100 | * errors are still notified through a machine check. | |
101 | */ | |
102 | mce_banks_t mce_banks_ce_disabled; | |
103 | ||
061120ae CG |
104 | static struct work_struct mce_work; |
105 | static struct irq_work mce_irq_work; | |
9b1beaf2 | 106 | |
61b0fccd TL |
107 | static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs); |
108 | ||
3653ada5 BP |
109 | /* |
110 | * CPU/chipset specific EDAC code can register a notifier call here to print | |
111 | * MCE errors in a human-readable form. | |
112 | */ | |
0dc9c639 | 113 | BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain); |
3653ada5 | 114 | |
b5f2fa4e AK |
115 | /* Do initial initialization of a struct mce */ |
116 | void mce_setup(struct mce *m) | |
117 | { | |
118 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 119 | m->cpu = m->extcpu = smp_processor_id(); |
bc39f010 AB |
120 | /* need the internal __ version to avoid deadlocks */ |
121 | m->time = __ktime_get_real_seconds(); | |
8ee08347 AK |
122 | m->cpuvendor = boot_cpu_data.x86_vendor; |
123 | m->cpuid = cpuid_eax(1); | |
8ee08347 | 124 | m->socketid = cpu_data(m->extcpu).phys_proc_id; |
8ee08347 AK |
125 | m->apicid = cpu_data(m->extcpu).initial_apicid; |
126 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
3f5a7896 TL |
127 | |
128 | if (this_cpu_has(X86_FEATURE_INTEL_PPIN)) | |
129 | rdmsrl(MSR_PPIN, m->ppin); | |
fa94d0c6 TL |
130 | |
131 | m->microcode = boot_cpu_data.microcode; | |
b5f2fa4e AK |
132 | } |
133 | ||
ea149b36 AK |
134 | DEFINE_PER_CPU(struct mce, injectm); |
135 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
136 | ||
fe3ed20f | 137 | void mce_log(struct mce *m) |
1da177e4 | 138 | { |
fe3ed20f | 139 | if (!mce_gen_pool_add(m)) |
f29a7aff | 140 | irq_work_queue(&mce_irq_work); |
1da177e4 LT |
141 | } |
142 | ||
a79da384 | 143 | void mce_inject_log(struct mce *m) |
09371957 | 144 | { |
5de97c9f | 145 | mutex_lock(&mce_log_mutex); |
a79da384 | 146 | mce_log(m); |
5de97c9f | 147 | mutex_unlock(&mce_log_mutex); |
09371957 | 148 | } |
a79da384 | 149 | EXPORT_SYMBOL_GPL(mce_inject_log); |
09371957 | 150 | |
fd4cf79f | 151 | static struct notifier_block mce_srao_nb; |
09371957 | 152 | |
011d8261 BP |
153 | /* |
154 | * We run the default notifier if we have only the SRAO, the first and the | |
155 | * default notifier registered. I.e., the mandatory NUM_DEFAULT_NOTIFIERS | |
156 | * notifiers registered on the chain. | |
157 | */ | |
158 | #define NUM_DEFAULT_NOTIFIERS 3 | |
cd9c57ca BP |
159 | static atomic_t num_notifiers; |
160 | ||
3653ada5 BP |
161 | void mce_register_decode_chain(struct notifier_block *nb) |
162 | { | |
415601b1 | 163 | if (WARN_ON(nb->priority > MCE_PRIO_MCELOG && nb->priority < MCE_PRIO_EDAC)) |
32b40a82 | 164 | return; |
cd9c57ca | 165 | |
32b40a82 | 166 | atomic_inc(&num_notifiers); |
fd4cf79f | 167 | |
0dc9c639 | 168 | blocking_notifier_chain_register(&x86_mce_decoder_chain, nb); |
3653ada5 BP |
169 | } |
170 | EXPORT_SYMBOL_GPL(mce_register_decode_chain); | |
171 | ||
172 | void mce_unregister_decode_chain(struct notifier_block *nb) | |
173 | { | |
cd9c57ca BP |
174 | atomic_dec(&num_notifiers); |
175 | ||
0dc9c639 | 176 | blocking_notifier_chain_unregister(&x86_mce_decoder_chain, nb); |
3653ada5 BP |
177 | } |
178 | EXPORT_SYMBOL_GPL(mce_unregister_decode_chain); | |
179 | ||
a9750a31 YG |
180 | static inline u32 ctl_reg(int bank) |
181 | { | |
182 | return MSR_IA32_MCx_CTL(bank); | |
183 | } | |
184 | ||
185 | static inline u32 status_reg(int bank) | |
186 | { | |
187 | return MSR_IA32_MCx_STATUS(bank); | |
188 | } | |
189 | ||
190 | static inline u32 addr_reg(int bank) | |
191 | { | |
192 | return MSR_IA32_MCx_ADDR(bank); | |
193 | } | |
194 | ||
195 | static inline u32 misc_reg(int bank) | |
196 | { | |
197 | return MSR_IA32_MCx_MISC(bank); | |
198 | } | |
199 | ||
200 | static inline u32 smca_ctl_reg(int bank) | |
201 | { | |
202 | return MSR_AMD64_SMCA_MCx_CTL(bank); | |
203 | } | |
204 | ||
205 | static inline u32 smca_status_reg(int bank) | |
206 | { | |
207 | return MSR_AMD64_SMCA_MCx_STATUS(bank); | |
208 | } | |
209 | ||
210 | static inline u32 smca_addr_reg(int bank) | |
211 | { | |
212 | return MSR_AMD64_SMCA_MCx_ADDR(bank); | |
213 | } | |
214 | ||
215 | static inline u32 smca_misc_reg(int bank) | |
216 | { | |
217 | return MSR_AMD64_SMCA_MCx_MISC(bank); | |
218 | } | |
219 | ||
220 | struct mca_msr_regs msr_ops = { | |
221 | .ctl = ctl_reg, | |
222 | .status = status_reg, | |
223 | .addr = addr_reg, | |
224 | .misc = misc_reg | |
225 | }; | |
226 | ||
cd9c57ca | 227 | static void __print_mce(struct mce *m) |
1da177e4 | 228 | { |
cd9c57ca BP |
229 | pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n", |
230 | m->extcpu, | |
231 | (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""), | |
232 | m->mcgstatus, m->bank, m->status); | |
f436f8bb | 233 | |
65ea5b03 | 234 | if (m->ip) { |
a2d7b0d4 | 235 | pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", |
f436f8bb | 236 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
cd9c57ca | 237 | m->cs, m->ip); |
f436f8bb | 238 | |
1da177e4 | 239 | if (m->cs == __KERNEL_CS) |
c80c5ec1 | 240 | pr_cont("{%pS}", (void *)(unsigned long)m->ip); |
f436f8bb | 241 | pr_cont("\n"); |
1da177e4 | 242 | } |
f436f8bb | 243 | |
a2d7b0d4 | 244 | pr_emerg(HW_ERR "TSC %llx ", m->tsc); |
1da177e4 | 245 | if (m->addr) |
f436f8bb | 246 | pr_cont("ADDR %llx ", m->addr); |
1da177e4 | 247 | if (m->misc) |
f436f8bb | 248 | pr_cont("MISC %llx ", m->misc); |
549d042d | 249 | |
4b711f92 YG |
250 | if (mce_flags.smca) { |
251 | if (m->synd) | |
252 | pr_cont("SYND %llx ", m->synd); | |
253 | if (m->ipid) | |
254 | pr_cont("IPID %llx ", m->ipid); | |
255 | } | |
256 | ||
f436f8bb | 257 | pr_cont("\n"); |
506ed6b5 AK |
258 | /* |
259 | * Note this output is parsed by external tools and old fields | |
260 | * should not be changed. | |
261 | */ | |
881e23e5 | 262 | pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n", |
506ed6b5 | 263 | m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, |
fa94d0c6 | 264 | m->microcode); |
cd9c57ca BP |
265 | } |
266 | ||
267 | static void print_mce(struct mce *m) | |
268 | { | |
cd9c57ca | 269 | __print_mce(m); |
b2fbf6f2 | 270 | |
ac78bd72 | 271 | if (m->cpuvendor != X86_VENDOR_AMD && m->cpuvendor != X86_VENDOR_HYGON) |
b2fbf6f2 | 272 | pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); |
86503560 AK |
273 | } |
274 | ||
f94b61c2 AK |
275 | #define PANIC_TIMEOUT 5 /* 5 seconds */ |
276 | ||
c7c9b392 | 277 | static atomic_t mce_panicked; |
f94b61c2 | 278 | |
bf783f9f | 279 | static int fake_panic; |
c7c9b392 | 280 | static atomic_t mce_fake_panicked; |
bf783f9f | 281 | |
f94b61c2 AK |
282 | /* Panic in progress. Enable interrupts and wait for final IPI */ |
283 | static void wait_for_panic(void) | |
284 | { | |
285 | long timeout = PANIC_TIMEOUT*USEC_PER_SEC; | |
f436f8bb | 286 | |
f94b61c2 AK |
287 | preempt_disable(); |
288 | local_irq_enable(); | |
289 | while (timeout-- > 0) | |
290 | udelay(1); | |
29b0f591 | 291 | if (panic_timeout == 0) |
7af19e4a | 292 | panic_timeout = mca_cfg.panic_timeout; |
f94b61c2 AK |
293 | panic("Panicing machine check CPU died"); |
294 | } | |
295 | ||
6c80f87e | 296 | static void mce_panic(const char *msg, struct mce *final, char *exp) |
d88203d1 | 297 | { |
5541c93c TL |
298 | int apei_err = 0; |
299 | struct llist_node *pending; | |
300 | struct mce_evt_llist *l; | |
e02e68d3 | 301 | |
bf783f9f HY |
302 | if (!fake_panic) { |
303 | /* | |
304 | * Make sure only one CPU runs in machine check panic | |
305 | */ | |
c7c9b392 | 306 | if (atomic_inc_return(&mce_panicked) > 1) |
bf783f9f HY |
307 | wait_for_panic(); |
308 | barrier(); | |
f94b61c2 | 309 | |
bf783f9f HY |
310 | bust_spinlocks(1); |
311 | console_verbose(); | |
312 | } else { | |
313 | /* Don't log too much for fake panic */ | |
c7c9b392 | 314 | if (atomic_inc_return(&mce_fake_panicked) > 1) |
bf783f9f HY |
315 | return; |
316 | } | |
5541c93c | 317 | pending = mce_gen_pool_prepare_records(); |
a0189c70 | 318 | /* First print corrected ones that are still unlogged */ |
5541c93c TL |
319 | llist_for_each_entry(l, pending, llnode) { |
320 | struct mce *m = &l->mce; | |
482908b4 | 321 | if (!(m->status & MCI_STATUS_UC)) { |
77e26cca | 322 | print_mce(m); |
482908b4 HY |
323 | if (!apei_err) |
324 | apei_err = apei_write_mce(m); | |
325 | } | |
a0189c70 AK |
326 | } |
327 | /* Now print uncorrected but with the final one last */ | |
5541c93c TL |
328 | llist_for_each_entry(l, pending, llnode) { |
329 | struct mce *m = &l->mce; | |
77e26cca HS |
330 | if (!(m->status & MCI_STATUS_UC)) |
331 | continue; | |
5541c93c | 332 | if (!final || mce_cmp(m, final)) { |
77e26cca | 333 | print_mce(m); |
482908b4 HY |
334 | if (!apei_err) |
335 | apei_err = apei_write_mce(m); | |
336 | } | |
1da177e4 | 337 | } |
482908b4 | 338 | if (final) { |
77e26cca | 339 | print_mce(final); |
482908b4 HY |
340 | if (!apei_err) |
341 | apei_err = apei_write_mce(final); | |
342 | } | |
3c079792 | 343 | if (cpu_missing) |
a2d7b0d4 | 344 | pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n"); |
bd19a5e6 | 345 | if (exp) |
a2d7b0d4 | 346 | pr_emerg(HW_ERR "Machine check: %s\n", exp); |
bf783f9f HY |
347 | if (!fake_panic) { |
348 | if (panic_timeout == 0) | |
7af19e4a | 349 | panic_timeout = mca_cfg.panic_timeout; |
bf783f9f HY |
350 | panic(msg); |
351 | } else | |
a2d7b0d4 | 352 | pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); |
d88203d1 | 353 | } |
1da177e4 | 354 | |
ea149b36 AK |
355 | /* Support code for software error injection */ |
356 | ||
357 | static int msr_to_offset(u32 msr) | |
358 | { | |
0a3aee0d | 359 | unsigned bank = __this_cpu_read(injectm.bank); |
f436f8bb | 360 | |
84c2559d | 361 | if (msr == mca_cfg.rip_msr) |
ea149b36 | 362 | return offsetof(struct mce, ip); |
d9d73fcc | 363 | if (msr == msr_ops.status(bank)) |
ea149b36 | 364 | return offsetof(struct mce, status); |
d9d73fcc | 365 | if (msr == msr_ops.addr(bank)) |
ea149b36 | 366 | return offsetof(struct mce, addr); |
d9d73fcc | 367 | if (msr == msr_ops.misc(bank)) |
ea149b36 AK |
368 | return offsetof(struct mce, misc); |
369 | if (msr == MSR_IA32_MCG_STATUS) | |
370 | return offsetof(struct mce, mcgstatus); | |
371 | return -1; | |
372 | } | |
373 | ||
5f8c1a54 AK |
374 | /* MSR access wrappers used for error injection */ |
375 | static u64 mce_rdmsrl(u32 msr) | |
376 | { | |
377 | u64 v; | |
11868a2d | 378 | |
0a3aee0d | 379 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 380 | int offset = msr_to_offset(msr); |
11868a2d | 381 | |
ea149b36 AK |
382 | if (offset < 0) |
383 | return 0; | |
89cbc767 | 384 | return *(u64 *)((char *)this_cpu_ptr(&injectm) + offset); |
ea149b36 | 385 | } |
11868a2d IM |
386 | |
387 | if (rdmsrl_safe(msr, &v)) { | |
38c54ccb | 388 | WARN_ONCE(1, "mce: Unable to read MSR 0x%x!\n", msr); |
11868a2d IM |
389 | /* |
390 | * Return zero in case the access faulted. This should | |
391 | * not happen normally but can happen if the CPU does | |
392 | * something weird, or if the code is buggy. | |
393 | */ | |
394 | v = 0; | |
395 | } | |
396 | ||
5f8c1a54 AK |
397 | return v; |
398 | } | |
399 | ||
400 | static void mce_wrmsrl(u32 msr, u64 v) | |
401 | { | |
0a3aee0d | 402 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 403 | int offset = msr_to_offset(msr); |
11868a2d | 404 | |
ea149b36 | 405 | if (offset >= 0) |
89cbc767 | 406 | *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v; |
ea149b36 AK |
407 | return; |
408 | } | |
5f8c1a54 AK |
409 | wrmsrl(msr, v); |
410 | } | |
411 | ||
b8325c5b HS |
412 | /* |
413 | * Collect all global (w.r.t. this processor) status about this machine | |
414 | * check into our "mce" struct so that we can use it later to assess | |
415 | * the severity of the problem as we read per-bank specific details. | |
416 | */ | |
417 | static inline void mce_gather_info(struct mce *m, struct pt_regs *regs) | |
418 | { | |
419 | mce_setup(m); | |
420 | ||
421 | m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); | |
422 | if (regs) { | |
423 | /* | |
424 | * Get the address of the instruction at the time of | |
425 | * the machine check error. | |
426 | */ | |
427 | if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) { | |
428 | m->ip = regs->ip; | |
429 | m->cs = regs->cs; | |
a129a7c8 AK |
430 | |
431 | /* | |
432 | * When in VM86 mode make the cs look like ring 3 | |
433 | * always. This is a lie, but it's better than passing | |
434 | * the additional vm86 bit around everywhere. | |
435 | */ | |
436 | if (v8086_mode(regs)) | |
437 | m->cs |= 3; | |
b8325c5b HS |
438 | } |
439 | /* Use accurate RIP reporting if available. */ | |
84c2559d BP |
440 | if (mca_cfg.rip_msr) |
441 | m->ip = mce_rdmsrl(mca_cfg.rip_msr); | |
b8325c5b HS |
442 | } |
443 | } | |
444 | ||
88ccbedd | 445 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 446 | { |
1462594b | 447 | if (mca_cfg.disabled) |
5b4408fd | 448 | return 0; |
3d1712c9 | 449 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
450 | } |
451 | ||
9b1beaf2 AK |
452 | static void mce_schedule_work(void) |
453 | { | |
a2c2727d | 454 | if (!mce_gen_pool_empty()) |
061120ae | 455 | schedule_work(&mce_work); |
9b1beaf2 AK |
456 | } |
457 | ||
b77e70bf | 458 | static void mce_irq_work_cb(struct irq_work *entry) |
ccc3c319 | 459 | { |
9b1beaf2 | 460 | mce_schedule_work(); |
ccc3c319 | 461 | } |
ccc3c319 AK |
462 | |
463 | static void mce_report_event(struct pt_regs *regs) | |
464 | { | |
465 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { | |
9ff36ee9 | 466 | mce_notify_irq(); |
9b1beaf2 AK |
467 | /* |
468 | * Triggering the work queue here is just an insurance | |
469 | * policy in case the syscall exit notify handler | |
470 | * doesn't run soon enough or ends up running on the | |
471 | * wrong CPU (can happen when audit sleeps) | |
472 | */ | |
473 | mce_schedule_work(); | |
ccc3c319 AK |
474 | return; |
475 | } | |
476 | ||
061120ae | 477 | irq_work_queue(&mce_irq_work); |
ccc3c319 AK |
478 | } |
479 | ||
feab21f8 BP |
480 | /* |
481 | * Check if the address reported by the CPU is in a format we can parse. | |
482 | * It would be possible to add code for most other cases, but all would | |
483 | * be somewhat complicated (e.g. segment offset would require an instruction | |
484 | * parser). So only support physical addresses up to page granuality for now. | |
485 | */ | |
e8a308e5 | 486 | int mce_usable_address(struct mce *m) |
feab21f8 | 487 | { |
c6a9583f | 488 | if (!(m->status & MCI_STATUS_ADDRV)) |
feab21f8 BP |
489 | return 0; |
490 | ||
491 | /* Checks after this one are Intel-specific: */ | |
492 | if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) | |
493 | return 1; | |
494 | ||
c6a9583f BP |
495 | if (!(m->status & MCI_STATUS_MISCV)) |
496 | return 0; | |
497 | ||
feab21f8 BP |
498 | if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) |
499 | return 0; | |
c6a9583f | 500 | |
feab21f8 BP |
501 | if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) |
502 | return 0; | |
c6a9583f | 503 | |
feab21f8 BP |
504 | return 1; |
505 | } | |
e8a308e5 | 506 | EXPORT_SYMBOL_GPL(mce_usable_address); |
feab21f8 | 507 | |
2d1f4061 | 508 | bool mce_is_memory_error(struct mce *m) |
011d8261 | 509 | { |
ac78bd72 PW |
510 | if (m->cpuvendor == X86_VENDOR_AMD || |
511 | m->cpuvendor == X86_VENDOR_HYGON) { | |
c6708d50 | 512 | return amd_mce_is_memory_error(m); |
2d1f4061 | 513 | } else if (m->cpuvendor == X86_VENDOR_INTEL) { |
011d8261 BP |
514 | /* |
515 | * Intel SDM Volume 3B - 15.9.2 Compound Error Codes | |
516 | * | |
517 | * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for | |
518 | * indicating a memory error. Bit 8 is used for indicating a | |
519 | * cache hierarchy error. The combination of bit 2 and bit 3 | |
520 | * is used for indicating a `generic' cache hierarchy error | |
521 | * But we can't just blindly check the above bits, because if | |
522 | * bit 11 is set, then it is a bus/interconnect error - and | |
523 | * either way the above bits just gives more detail on what | |
524 | * bus/interconnect error happened. Note that bit 12 can be | |
525 | * ignored, as it's the "filter" bit. | |
526 | */ | |
527 | return (m->status & 0xef80) == BIT(7) || | |
528 | (m->status & 0xef00) == BIT(8) || | |
529 | (m->status & 0xeffc) == 0xc; | |
530 | } | |
531 | ||
532 | return false; | |
533 | } | |
2d1f4061 | 534 | EXPORT_SYMBOL_GPL(mce_is_memory_error); |
011d8261 | 535 | |
5d96c934 | 536 | bool mce_is_correctable(struct mce *m) |
179eb850 YG |
537 | { |
538 | if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED) | |
539 | return false; | |
540 | ||
ac78bd72 PW |
541 | if (m->cpuvendor == X86_VENDOR_HYGON && m->status & MCI_STATUS_DEFERRED) |
542 | return false; | |
543 | ||
179eb850 YG |
544 | if (m->status & MCI_STATUS_UC) |
545 | return false; | |
546 | ||
547 | return true; | |
548 | } | |
5d96c934 | 549 | EXPORT_SYMBOL_GPL(mce_is_correctable); |
179eb850 | 550 | |
011d8261 BP |
551 | static bool cec_add_mce(struct mce *m) |
552 | { | |
553 | if (!m) | |
554 | return false; | |
555 | ||
556 | /* We eat only correctable DRAM errors with usable addresses. */ | |
2d1f4061 | 557 | if (mce_is_memory_error(m) && |
179eb850 | 558 | mce_is_correctable(m) && |
011d8261 BP |
559 | mce_usable_address(m)) |
560 | if (!cec_add_elem(m->addr >> PAGE_SHIFT)) | |
561 | return true; | |
562 | ||
563 | return false; | |
564 | } | |
565 | ||
566 | static int mce_first_notifier(struct notifier_block *nb, unsigned long val, | |
567 | void *data) | |
568 | { | |
569 | struct mce *m = (struct mce *)data; | |
011d8261 BP |
570 | |
571 | if (!m) | |
572 | return NOTIFY_DONE; | |
573 | ||
574 | if (cec_add_mce(m)) | |
575 | return NOTIFY_STOP; | |
576 | ||
577 | /* Emit the trace record: */ | |
578 | trace_mce_record(m); | |
579 | ||
011d8261 BP |
580 | set_bit(0, &mce_need_notify); |
581 | ||
582 | mce_notify_irq(); | |
583 | ||
584 | return NOTIFY_DONE; | |
585 | } | |
586 | ||
587 | static struct notifier_block first_nb = { | |
588 | .notifier_call = mce_first_notifier, | |
589 | .priority = MCE_PRIO_FIRST, | |
590 | }; | |
591 | ||
fd4cf79f CG |
592 | static int srao_decode_notifier(struct notifier_block *nb, unsigned long val, |
593 | void *data) | |
594 | { | |
595 | struct mce *mce = (struct mce *)data; | |
596 | unsigned long pfn; | |
597 | ||
598 | if (!mce) | |
599 | return NOTIFY_DONE; | |
600 | ||
c0ec382e | 601 | if (mce_usable_address(mce) && (mce->severity == MCE_AO_SEVERITY)) { |
fd4cf79f | 602 | pfn = mce->addr >> PAGE_SHIFT; |
fd0e786d | 603 | if (!memory_failure(pfn, 0)) |
284ce401 | 604 | set_mce_nospec(pfn); |
fd4cf79f CG |
605 | } |
606 | ||
607 | return NOTIFY_OK; | |
ccc3c319 | 608 | } |
fd4cf79f CG |
609 | static struct notifier_block mce_srao_nb = { |
610 | .notifier_call = srao_decode_notifier, | |
9026cc82 | 611 | .priority = MCE_PRIO_SRAO, |
fd4cf79f | 612 | }; |
ccc3c319 | 613 | |
cd9c57ca BP |
614 | static int mce_default_notifier(struct notifier_block *nb, unsigned long val, |
615 | void *data) | |
616 | { | |
617 | struct mce *m = (struct mce *)data; | |
618 | ||
619 | if (!m) | |
620 | return NOTIFY_DONE; | |
621 | ||
011d8261 | 622 | if (atomic_read(&num_notifiers) > NUM_DEFAULT_NOTIFIERS) |
cc66afea AK |
623 | return NOTIFY_DONE; |
624 | ||
cd9c57ca BP |
625 | __print_mce(m); |
626 | ||
627 | return NOTIFY_DONE; | |
628 | } | |
629 | ||
630 | static struct notifier_block mce_default_nb = { | |
631 | .notifier_call = mce_default_notifier, | |
632 | /* lowest prio, we want it to run last. */ | |
9026cc82 | 633 | .priority = MCE_PRIO_LOWEST, |
cd9c57ca BP |
634 | }; |
635 | ||
85f92694 TL |
636 | /* |
637 | * Read ADDR and MISC registers. | |
638 | */ | |
639 | static void mce_read_aux(struct mce *m, int i) | |
640 | { | |
641 | if (m->status & MCI_STATUS_MISCV) | |
d9d73fcc | 642 | m->misc = mce_rdmsrl(msr_ops.misc(i)); |
db819d60 | 643 | |
85f92694 | 644 | if (m->status & MCI_STATUS_ADDRV) { |
d9d73fcc | 645 | m->addr = mce_rdmsrl(msr_ops.addr(i)); |
85f92694 TL |
646 | |
647 | /* | |
648 | * Mask the reported address by the reported granularity. | |
649 | */ | |
1462594b | 650 | if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) { |
85f92694 TL |
651 | u8 shift = MCI_MISC_ADDR_LSB(m->misc); |
652 | m->addr >>= shift; | |
653 | m->addr <<= shift; | |
654 | } | |
4f29b73b YG |
655 | |
656 | /* | |
657 | * Extract [55:<lsb>] where lsb is the least significant | |
658 | * *valid* bit of the address bits. | |
659 | */ | |
660 | if (mce_flags.smca) { | |
661 | u8 lsb = (m->addr >> 56) & 0x3f; | |
662 | ||
663 | m->addr &= GENMASK_ULL(55, lsb); | |
664 | } | |
85f92694 | 665 | } |
db819d60 | 666 | |
5828c46f YG |
667 | if (mce_flags.smca) { |
668 | m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i)); | |
669 | ||
670 | if (m->status & MCI_STATUS_SYNDV) | |
671 | m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i)); | |
672 | } | |
85f92694 TL |
673 | } |
674 | ||
ca84f696 AK |
675 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
676 | ||
d88203d1 | 677 | /* |
b79109c3 AK |
678 | * Poll for corrected events or events that happened before reset. |
679 | * Those are just logged through /dev/mcelog. | |
680 | * | |
681 | * This is executed in standard interrupt context. | |
ed7290d0 AK |
682 | * |
683 | * Note: spec recommends to panic for fatal unsignalled | |
684 | * errors here. However this would be quite problematic -- | |
685 | * we would need to reimplement the Monarch handling and | |
686 | * it would mess up the exclusion between exception handler | |
a97673a1 | 687 | * and poll handler -- * so we skip this for now. |
ed7290d0 AK |
688 | * These cases should not happen anyways, or only when the CPU |
689 | * is already totally * confused. In this case it's likely it will | |
690 | * not fully execute the machine check handler either. | |
b79109c3 | 691 | */ |
3f2f0680 | 692 | bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 | 693 | { |
8b38937b | 694 | bool error_seen = false; |
b79109c3 AK |
695 | struct mce m; |
696 | int i; | |
697 | ||
c6ae41e7 | 698 | this_cpu_inc(mce_poll_count); |
ca84f696 | 699 | |
b8325c5b | 700 | mce_gather_info(&m, NULL); |
b79109c3 | 701 | |
669c00f0 BP |
702 | if (flags & MCP_TIMESTAMP) |
703 | m.tsc = rdtsc(); | |
54467353 | 704 | |
d203f0b8 | 705 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 706 | if (!mce_banks[i].ctl || !test_bit(i, *b)) |
b79109c3 AK |
707 | continue; |
708 | ||
709 | m.misc = 0; | |
710 | m.addr = 0; | |
711 | m.bank = i; | |
b79109c3 AK |
712 | |
713 | barrier(); | |
d9d73fcc | 714 | m.status = mce_rdmsrl(msr_ops.status(i)); |
b79109c3 AK |
715 | if (!(m.status & MCI_STATUS_VAL)) |
716 | continue; | |
717 | ||
718 | /* | |
ed7290d0 AK |
719 | * Uncorrected or signalled events are handled by the exception |
720 | * handler when it is enabled, so don't process those here. | |
b79109c3 AK |
721 | * |
722 | * TBD do the same check for MCI_STATUS_EN here? | |
723 | */ | |
ed7290d0 | 724 | if (!(flags & MCP_UC) && |
1462594b | 725 | (m.status & (mca_cfg.ser ? MCI_STATUS_S : MCI_STATUS_UC))) |
b79109c3 AK |
726 | continue; |
727 | ||
8b38937b TL |
728 | error_seen = true; |
729 | ||
85f92694 | 730 | mce_read_aux(&m, i); |
b79109c3 | 731 | |
e2de64ec | 732 | m.severity = mce_severity(&m, mca_cfg.tolerant, NULL, false); |
fa92c586 | 733 | |
b79109c3 AK |
734 | /* |
735 | * Don't get the IP here because it's unlikely to | |
736 | * have anything to do with the actual error location. | |
737 | */ | |
8b38937b | 738 | if (!(flags & MCP_DONTLOG) && !mca_cfg.dont_log_ce) |
5679af4c | 739 | mce_log(&m); |
c0ec382e | 740 | else if (mce_usable_address(&m)) { |
8b38937b TL |
741 | /* |
742 | * Although we skipped logging this, we still want | |
743 | * to take action. Add to the pool so the registered | |
744 | * notifiers will see it. | |
745 | */ | |
746 | if (!mce_gen_pool_add(&m)) | |
747 | mce_schedule_work(); | |
3f2f0680 | 748 | } |
b79109c3 AK |
749 | |
750 | /* | |
751 | * Clear state for this bank. | |
752 | */ | |
d9d73fcc | 753 | mce_wrmsrl(msr_ops.status(i), 0); |
b79109c3 AK |
754 | } |
755 | ||
756 | /* | |
757 | * Don't clear MCG_STATUS here because it's only defined for | |
758 | * exceptions. | |
759 | */ | |
88921be3 AK |
760 | |
761 | sync_core(); | |
3f2f0680 | 762 | |
8b38937b | 763 | return error_seen; |
b79109c3 | 764 | } |
ea149b36 | 765 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 | 766 | |
bd19a5e6 AK |
767 | /* |
768 | * Do a quick check if any of the events requires a panic. | |
769 | * This decides if we keep the events around or clear them. | |
770 | */ | |
61b0fccd TL |
771 | static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp, |
772 | struct pt_regs *regs) | |
bd19a5e6 | 773 | { |
17fea54b | 774 | char *tmp; |
1f74c8a6 | 775 | int i; |
bd19a5e6 | 776 | |
d203f0b8 | 777 | for (i = 0; i < mca_cfg.banks; i++) { |
d9d73fcc | 778 | m->status = mce_rdmsrl(msr_ops.status(i)); |
1f74c8a6 BP |
779 | if (!(m->status & MCI_STATUS_VAL)) |
780 | continue; | |
781 | ||
782 | __set_bit(i, validp); | |
783 | if (quirk_no_way_out) | |
784 | quirk_no_way_out(i, m, regs); | |
17fea54b BP |
785 | |
786 | if (mce_severity(m, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) { | |
d28af26f | 787 | m->bank = i; |
1f74c8a6 | 788 | mce_read_aux(m, i); |
17fea54b | 789 | *msg = tmp; |
1f74c8a6 | 790 | return 1; |
17fea54b | 791 | } |
bd19a5e6 | 792 | } |
1f74c8a6 | 793 | return 0; |
bd19a5e6 AK |
794 | } |
795 | ||
3c079792 AK |
796 | /* |
797 | * Variable to establish order between CPUs while scanning. | |
798 | * Each CPU spins initially until executing is equal its number. | |
799 | */ | |
800 | static atomic_t mce_executing; | |
801 | ||
802 | /* | |
803 | * Defines order of CPUs on entry. First CPU becomes Monarch. | |
804 | */ | |
805 | static atomic_t mce_callin; | |
806 | ||
807 | /* | |
808 | * Check if a timeout waiting for other CPUs happened. | |
809 | */ | |
6c80f87e | 810 | static int mce_timed_out(u64 *t, const char *msg) |
3c079792 AK |
811 | { |
812 | /* | |
813 | * The others already did panic for some reason. | |
814 | * Bail out like in a timeout. | |
815 | * rmb() to tell the compiler that system_state | |
816 | * might have been modified by someone else. | |
817 | */ | |
818 | rmb(); | |
c7c9b392 | 819 | if (atomic_read(&mce_panicked)) |
3c079792 | 820 | wait_for_panic(); |
84c2559d | 821 | if (!mca_cfg.monarch_timeout) |
3c079792 AK |
822 | goto out; |
823 | if ((s64)*t < SPINUNIT) { | |
716079f6 | 824 | if (mca_cfg.tolerant <= 1) |
6c80f87e | 825 | mce_panic(msg, NULL, NULL); |
3c079792 AK |
826 | cpu_missing = 1; |
827 | return 1; | |
828 | } | |
829 | *t -= SPINUNIT; | |
830 | out: | |
831 | touch_nmi_watchdog(); | |
832 | return 0; | |
833 | } | |
834 | ||
835 | /* | |
836 | * The Monarch's reign. The Monarch is the CPU who entered | |
837 | * the machine check handler first. It waits for the others to | |
838 | * raise the exception too and then grades them. When any | |
839 | * error is fatal panic. Only then let the others continue. | |
840 | * | |
841 | * The other CPUs entering the MCE handler will be controlled by the | |
842 | * Monarch. They are called Subjects. | |
843 | * | |
844 | * This way we prevent any potential data corruption in a unrecoverable case | |
845 | * and also makes sure always all CPU's errors are examined. | |
846 | * | |
680b6cfd | 847 | * Also this detects the case of a machine check event coming from outer |
3c079792 AK |
848 | * space (not detected by any CPUs) In this case some external agent wants |
849 | * us to shut down, so panic too. | |
850 | * | |
851 | * The other CPUs might still decide to panic if the handler happens | |
852 | * in a unrecoverable place, but in this case the system is in a semi-stable | |
853 | * state and won't corrupt anything by itself. It's ok to let the others | |
854 | * continue for a bit first. | |
855 | * | |
856 | * All the spin loops have timeouts; when a timeout happens a CPU | |
857 | * typically elects itself to be Monarch. | |
858 | */ | |
859 | static void mce_reign(void) | |
860 | { | |
861 | int cpu; | |
862 | struct mce *m = NULL; | |
863 | int global_worst = 0; | |
864 | char *msg = NULL; | |
865 | char *nmsg = NULL; | |
866 | ||
867 | /* | |
868 | * This CPU is the Monarch and the other CPUs have run | |
869 | * through their handlers. | |
870 | * Grade the severity of the errors of all the CPUs. | |
871 | */ | |
872 | for_each_possible_cpu(cpu) { | |
d203f0b8 BP |
873 | int severity = mce_severity(&per_cpu(mces_seen, cpu), |
874 | mca_cfg.tolerant, | |
e3480271 | 875 | &nmsg, true); |
3c079792 AK |
876 | if (severity > global_worst) { |
877 | msg = nmsg; | |
878 | global_worst = severity; | |
879 | m = &per_cpu(mces_seen, cpu); | |
880 | } | |
881 | } | |
882 | ||
883 | /* | |
884 | * Cannot recover? Panic here then. | |
885 | * This dumps all the mces in the log buffer and stops the | |
886 | * other CPUs. | |
887 | */ | |
d203f0b8 | 888 | if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) |
8af7043a | 889 | mce_panic("Fatal machine check", m, msg); |
3c079792 AK |
890 | |
891 | /* | |
892 | * For UC somewhere we let the CPU who detects it handle it. | |
893 | * Also must let continue the others, otherwise the handling | |
894 | * CPU could deadlock on a lock. | |
895 | */ | |
896 | ||
897 | /* | |
898 | * No machine check event found. Must be some external | |
899 | * source or one CPU is hung. Panic. | |
900 | */ | |
d203f0b8 | 901 | if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3) |
8af7043a | 902 | mce_panic("Fatal machine check from unknown source", NULL, NULL); |
3c079792 AK |
903 | |
904 | /* | |
905 | * Now clear all the mces_seen so that they don't reappear on | |
906 | * the next mce. | |
907 | */ | |
908 | for_each_possible_cpu(cpu) | |
909 | memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); | |
910 | } | |
911 | ||
912 | static atomic_t global_nwo; | |
913 | ||
914 | /* | |
915 | * Start of Monarch synchronization. This waits until all CPUs have | |
916 | * entered the exception handler and then determines if any of them | |
917 | * saw a fatal event that requires panic. Then it executes them | |
918 | * in the entry order. | |
919 | * TBD double check parallel CPU hotunplug | |
920 | */ | |
7fb06fc9 | 921 | static int mce_start(int *no_way_out) |
3c079792 | 922 | { |
7fb06fc9 | 923 | int order; |
3c079792 | 924 | int cpus = num_online_cpus(); |
84c2559d | 925 | u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; |
3c079792 | 926 | |
7fb06fc9 HS |
927 | if (!timeout) |
928 | return -1; | |
3c079792 | 929 | |
7fb06fc9 | 930 | atomic_add(*no_way_out, &global_nwo); |
184e1fdf | 931 | /* |
bf92b1fe DB |
932 | * Rely on the implied barrier below, such that global_nwo |
933 | * is updated before mce_callin. | |
184e1fdf | 934 | */ |
a95436e4 | 935 | order = atomic_inc_return(&mce_callin); |
3c079792 AK |
936 | |
937 | /* | |
938 | * Wait for everyone. | |
939 | */ | |
940 | while (atomic_read(&mce_callin) != cpus) { | |
6c80f87e AL |
941 | if (mce_timed_out(&timeout, |
942 | "Timeout: Not all CPUs entered broadcast exception handler")) { | |
3c079792 | 943 | atomic_set(&global_nwo, 0); |
7fb06fc9 | 944 | return -1; |
3c079792 AK |
945 | } |
946 | ndelay(SPINUNIT); | |
947 | } | |
948 | ||
184e1fdf HY |
949 | /* |
950 | * mce_callin should be read before global_nwo | |
951 | */ | |
952 | smp_rmb(); | |
3c079792 | 953 | |
7fb06fc9 HS |
954 | if (order == 1) { |
955 | /* | |
956 | * Monarch: Starts executing now, the others wait. | |
957 | */ | |
3c079792 | 958 | atomic_set(&mce_executing, 1); |
7fb06fc9 HS |
959 | } else { |
960 | /* | |
961 | * Subject: Now start the scanning loop one by one in | |
962 | * the original callin order. | |
963 | * This way when there are any shared banks it will be | |
964 | * only seen by one CPU before cleared, avoiding duplicates. | |
965 | */ | |
966 | while (atomic_read(&mce_executing) < order) { | |
6c80f87e AL |
967 | if (mce_timed_out(&timeout, |
968 | "Timeout: Subject CPUs unable to finish machine check processing")) { | |
7fb06fc9 HS |
969 | atomic_set(&global_nwo, 0); |
970 | return -1; | |
971 | } | |
972 | ndelay(SPINUNIT); | |
973 | } | |
3c079792 AK |
974 | } |
975 | ||
976 | /* | |
7fb06fc9 | 977 | * Cache the global no_way_out state. |
3c079792 | 978 | */ |
7fb06fc9 HS |
979 | *no_way_out = atomic_read(&global_nwo); |
980 | ||
981 | return order; | |
3c079792 AK |
982 | } |
983 | ||
984 | /* | |
985 | * Synchronize between CPUs after main scanning loop. | |
986 | * This invokes the bulk of the Monarch processing. | |
987 | */ | |
988 | static int mce_end(int order) | |
989 | { | |
990 | int ret = -1; | |
84c2559d | 991 | u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; |
3c079792 AK |
992 | |
993 | if (!timeout) | |
994 | goto reset; | |
995 | if (order < 0) | |
996 | goto reset; | |
997 | ||
998 | /* | |
999 | * Allow others to run. | |
1000 | */ | |
1001 | atomic_inc(&mce_executing); | |
1002 | ||
1003 | if (order == 1) { | |
1004 | /* CHECKME: Can this race with a parallel hotplug? */ | |
1005 | int cpus = num_online_cpus(); | |
1006 | ||
1007 | /* | |
1008 | * Monarch: Wait for everyone to go through their scanning | |
1009 | * loops. | |
1010 | */ | |
1011 | while (atomic_read(&mce_executing) <= cpus) { | |
6c80f87e AL |
1012 | if (mce_timed_out(&timeout, |
1013 | "Timeout: Monarch CPU unable to finish machine check processing")) | |
3c079792 AK |
1014 | goto reset; |
1015 | ndelay(SPINUNIT); | |
1016 | } | |
1017 | ||
1018 | mce_reign(); | |
1019 | barrier(); | |
1020 | ret = 0; | |
1021 | } else { | |
1022 | /* | |
1023 | * Subject: Wait for Monarch to finish. | |
1024 | */ | |
1025 | while (atomic_read(&mce_executing) != 0) { | |
6c80f87e AL |
1026 | if (mce_timed_out(&timeout, |
1027 | "Timeout: Monarch CPU did not finish machine check processing")) | |
3c079792 AK |
1028 | goto reset; |
1029 | ndelay(SPINUNIT); | |
1030 | } | |
1031 | ||
1032 | /* | |
1033 | * Don't reset anything. That's done by the Monarch. | |
1034 | */ | |
1035 | return 0; | |
1036 | } | |
1037 | ||
1038 | /* | |
1039 | * Reset all global state. | |
1040 | */ | |
1041 | reset: | |
1042 | atomic_set(&global_nwo, 0); | |
1043 | atomic_set(&mce_callin, 0); | |
1044 | barrier(); | |
1045 | ||
1046 | /* | |
1047 | * Let others run again. | |
1048 | */ | |
1049 | atomic_set(&mce_executing, 0); | |
1050 | return ret; | |
1051 | } | |
1052 | ||
1053 | static void mce_clear_state(unsigned long *toclear) | |
1054 | { | |
1055 | int i; | |
1056 | ||
d203f0b8 | 1057 | for (i = 0; i < mca_cfg.banks; i++) { |
3c079792 | 1058 | if (test_bit(i, toclear)) |
d9d73fcc | 1059 | mce_wrmsrl(msr_ops.status(i), 0); |
3c079792 AK |
1060 | } |
1061 | } | |
1062 | ||
b2f9d678 TL |
1063 | static int do_memory_failure(struct mce *m) |
1064 | { | |
1065 | int flags = MF_ACTION_REQUIRED; | |
1066 | int ret; | |
1067 | ||
1068 | pr_err("Uncorrected hardware memory error in user-access at %llx", m->addr); | |
1069 | if (!(m->mcgstatus & MCG_STATUS_RIPV)) | |
1070 | flags |= MF_MUST_KILL; | |
83b57531 | 1071 | ret = memory_failure(m->addr >> PAGE_SHIFT, flags); |
b2f9d678 TL |
1072 | if (ret) |
1073 | pr_err("Memory error not recovered"); | |
fd0e786d | 1074 | else |
284ce401 | 1075 | set_mce_nospec(m->addr >> PAGE_SHIFT); |
b2f9d678 TL |
1076 | return ret; |
1077 | } | |
1078 | ||
d3d6923c BP |
1079 | |
1080 | /* | |
1081 | * Cases where we avoid rendezvous handler timeout: | |
1082 | * 1) If this CPU is offline. | |
1083 | * | |
1084 | * 2) If crashing_cpu was set, e.g. we're entering kdump and we need to | |
1085 | * skip those CPUs which remain looping in the 1st kernel - see | |
1086 | * crash_nmi_callback(). | |
1087 | * | |
1088 | * Note: there still is a small window between kexec-ing and the new, | |
1089 | * kdump kernel establishing a new #MC handler where a broadcasted MCE | |
1090 | * might not get handled properly. | |
1091 | */ | |
1092 | static bool __mc_check_crashing_cpu(int cpu) | |
1093 | { | |
1094 | if (cpu_is_offline(cpu) || | |
1095 | (crashing_cpu != -1 && crashing_cpu != cpu)) { | |
1096 | u64 mcgstatus; | |
1097 | ||
1098 | mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); | |
1099 | if (mcgstatus & MCG_STATUS_RIPV) { | |
1100 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); | |
1101 | return true; | |
1102 | } | |
1103 | } | |
1104 | return false; | |
1105 | } | |
1106 | ||
f35565e3 BP |
1107 | static void __mc_scan_banks(struct mce *m, struct mce *final, |
1108 | unsigned long *toclear, unsigned long *valid_banks, | |
1109 | int no_way_out, int *worst) | |
1110 | { | |
1111 | struct mca_config *cfg = &mca_cfg; | |
1112 | int severity, i; | |
1113 | ||
1114 | for (i = 0; i < cfg->banks; i++) { | |
1115 | __clear_bit(i, toclear); | |
1116 | if (!test_bit(i, valid_banks)) | |
1117 | continue; | |
d5c84ef2 | 1118 | |
f35565e3 BP |
1119 | if (!mce_banks[i].ctl) |
1120 | continue; | |
1121 | ||
1122 | m->misc = 0; | |
1123 | m->addr = 0; | |
1124 | m->bank = i; | |
1125 | ||
1126 | m->status = mce_rdmsrl(msr_ops.status(i)); | |
d5c84ef2 | 1127 | if (!(m->status & MCI_STATUS_VAL)) |
f35565e3 BP |
1128 | continue; |
1129 | ||
1130 | /* | |
d5c84ef2 BP |
1131 | * Corrected or non-signaled errors are handled by |
1132 | * machine_check_poll(). Leave them alone, unless this panics. | |
f35565e3 BP |
1133 | */ |
1134 | if (!(m->status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) && | |
1135 | !no_way_out) | |
1136 | continue; | |
1137 | ||
d5c84ef2 | 1138 | /* Set taint even when machine check was not enabled. */ |
f35565e3 BP |
1139 | add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); |
1140 | ||
1141 | severity = mce_severity(m, cfg->tolerant, NULL, true); | |
1142 | ||
1143 | /* | |
1144 | * When machine check was for corrected/deferred handler don't | |
d5c84ef2 | 1145 | * touch, unless we're panicking. |
f35565e3 BP |
1146 | */ |
1147 | if ((severity == MCE_KEEP_SEVERITY || | |
1148 | severity == MCE_UCNA_SEVERITY) && !no_way_out) | |
1149 | continue; | |
d5c84ef2 | 1150 | |
f35565e3 | 1151 | __set_bit(i, toclear); |
d5c84ef2 BP |
1152 | |
1153 | /* Machine check event was not enabled. Clear, but ignore. */ | |
1154 | if (severity == MCE_NO_SEVERITY) | |
f35565e3 | 1155 | continue; |
f35565e3 BP |
1156 | |
1157 | mce_read_aux(m, i); | |
1158 | ||
1159 | /* assuming valid severity level != 0 */ | |
1160 | m->severity = severity; | |
1161 | ||
1162 | mce_log(m); | |
1163 | ||
1164 | if (severity > *worst) { | |
1165 | *final = *m; | |
1166 | *worst = severity; | |
1167 | } | |
1168 | } | |
1169 | ||
1170 | /* mce_clear_state will clear *final, save locally for use later */ | |
1171 | *m = *final; | |
1172 | } | |
1173 | ||
b79109c3 AK |
1174 | /* |
1175 | * The actual machine check handler. This only handles real | |
1176 | * exceptions when something got corrupted coming in through int 18. | |
1177 | * | |
1178 | * This is executed in NMI context not subject to normal locking rules. This | |
1179 | * implies that most kernel services cannot be safely used. Don't even | |
1180 | * think about putting a printk in there! | |
3c079792 AK |
1181 | * |
1182 | * On Intel systems this is entered on all CPUs in parallel through | |
1183 | * MCE broadcast. However some CPUs might be broken beyond repair, | |
1184 | * so be always careful when synchronizing with others. | |
1da177e4 | 1185 | */ |
e9eee03e | 1186 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 | 1187 | { |
d3d6923c BP |
1188 | DECLARE_BITMAP(valid_banks, MAX_NR_BANKS); |
1189 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); | |
1462594b | 1190 | struct mca_config *cfg = &mca_cfg; |
d3d6923c BP |
1191 | int cpu = smp_processor_id(); |
1192 | char *msg = "Unknown"; | |
3c079792 | 1193 | struct mce m, *final; |
3c079792 | 1194 | int worst = 0; |
fead35c6 | 1195 | |
3c079792 AK |
1196 | /* |
1197 | * Establish sequential order between the CPUs entering the machine | |
1198 | * check handler. | |
1199 | */ | |
fead35c6 | 1200 | int order = -1; |
d3d6923c | 1201 | |
bd78432c TH |
1202 | /* |
1203 | * If no_way_out gets set, there is no safe way to recover from this | |
d203f0b8 | 1204 | * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway. |
bd78432c TH |
1205 | */ |
1206 | int no_way_out = 0; | |
d3d6923c | 1207 | |
bd78432c TH |
1208 | /* |
1209 | * If kill_it gets set, there might be a way to recover from this | |
1210 | * error. | |
1211 | */ | |
1212 | int kill_it = 0; | |
fead35c6 YG |
1213 | |
1214 | /* | |
1215 | * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES | |
1216 | * on Intel. | |
1217 | */ | |
1218 | int lmce = 1; | |
1da177e4 | 1219 | |
d3d6923c BP |
1220 | if (__mc_check_crashing_cpu(cpu)) |
1221 | return; | |
d90167a9 | 1222 | |
8c84014f | 1223 | ist_enter(regs); |
95927475 | 1224 | |
c6ae41e7 | 1225 | this_cpu_inc(mce_exception_count); |
01ca79f1 | 1226 | |
b8325c5b | 1227 | mce_gather_info(&m, regs); |
669c00f0 | 1228 | m.tsc = rdtsc(); |
b5f2fa4e | 1229 | |
89cbc767 | 1230 | final = this_cpu_ptr(&mces_seen); |
3c079792 AK |
1231 | *final = m; |
1232 | ||
95022b8c | 1233 | memset(valid_banks, 0, sizeof(valid_banks)); |
61b0fccd | 1234 | no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs); |
680b6cfd | 1235 | |
1da177e4 LT |
1236 | barrier(); |
1237 | ||
ed7290d0 | 1238 | /* |
a8c321fb TL |
1239 | * When no restart IP might need to kill or panic. |
1240 | * Assume the worst for now, but if we find the | |
1241 | * severity is MCE_AR_SEVERITY we have other options. | |
ed7290d0 AK |
1242 | */ |
1243 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
1244 | kill_it = 1; | |
1245 | ||
3c079792 | 1246 | /* |
fead35c6 YG |
1247 | * Check if this MCE is signaled to only this logical processor, |
1248 | * on Intel only. | |
3c079792 | 1249 | */ |
fead35c6 YG |
1250 | if (m.cpuvendor == X86_VENDOR_INTEL) |
1251 | lmce = m.mcgstatus & MCG_STATUS_LMCES; | |
1252 | ||
1253 | /* | |
40c36e27 TL |
1254 | * Local machine check may already know that we have to panic. |
1255 | * Broadcast machine check begins rendezvous in mce_start() | |
fead35c6 YG |
1256 | * Go through all banks in exclusion of the other CPUs. This way we |
1257 | * don't report duplicated events on shared banks because the first one | |
40c36e27 | 1258 | * to see it will clear it. |
fead35c6 | 1259 | */ |
40c36e27 TL |
1260 | if (lmce) { |
1261 | if (no_way_out) | |
1262 | mce_panic("Fatal local machine check", &m, msg); | |
1263 | } else { | |
243d657e | 1264 | order = mce_start(&no_way_out); |
40c36e27 | 1265 | } |
243d657e | 1266 | |
f35565e3 | 1267 | __mc_scan_banks(&m, final, toclear, valid_banks, no_way_out, &worst); |
a8c321fb | 1268 | |
3c079792 AK |
1269 | if (!no_way_out) |
1270 | mce_clear_state(toclear); | |
1271 | ||
e9eee03e | 1272 | /* |
3c079792 AK |
1273 | * Do most of the synchronization with other CPUs. |
1274 | * When there's any problem use only local no_way_out state. | |
e9eee03e | 1275 | */ |
243d657e AR |
1276 | if (!lmce) { |
1277 | if (mce_end(order) < 0) | |
1278 | no_way_out = worst >= MCE_PANIC_SEVERITY; | |
1279 | } else { | |
1280 | /* | |
40c36e27 TL |
1281 | * If there was a fatal machine check we should have |
1282 | * already called mce_panic earlier in this function. | |
1283 | * Since we re-read the banks, we might have found | |
1284 | * something new. Check again to see if we found a | |
1285 | * fatal error. We call "mce_severity()" again to | |
1286 | * make sure we have the right "msg". | |
243d657e | 1287 | */ |
40c36e27 TL |
1288 | if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) { |
1289 | mce_severity(&m, cfg->tolerant, &msg, true); | |
1290 | mce_panic("Local fatal machine check!", &m, msg); | |
1291 | } | |
243d657e | 1292 | } |
bd78432c TH |
1293 | |
1294 | /* | |
b2f9d678 TL |
1295 | * If tolerant is at an insane level we drop requests to kill |
1296 | * processes and continue even when there is no way out. | |
bd78432c | 1297 | */ |
b2f9d678 TL |
1298 | if (cfg->tolerant == 3) |
1299 | kill_it = 0; | |
1300 | else if (no_way_out) | |
1301 | mce_panic("Fatal machine check on current CPU", &m, msg); | |
e02e68d3 | 1302 | |
3c079792 AK |
1303 | if (worst > 0) |
1304 | mce_report_event(regs); | |
5f8c1a54 | 1305 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
45deca7d | 1306 | |
88921be3 | 1307 | sync_core(); |
d4812e16 | 1308 | |
b2f9d678 TL |
1309 | if (worst != MCE_AR_SEVERITY && !kill_it) |
1310 | goto out_ist; | |
d4812e16 | 1311 | |
b2f9d678 TL |
1312 | /* Fault was in user mode and we need to take some action */ |
1313 | if ((m.cs & 3) == 3) { | |
1314 | ist_begin_non_atomic(regs); | |
1315 | local_irq_enable(); | |
1316 | ||
1317 | if (kill_it || do_memory_failure(&m)) | |
1318 | force_sig(SIGBUS, current); | |
1319 | local_irq_disable(); | |
1320 | ist_end_non_atomic(); | |
1321 | } else { | |
81fd9c18 | 1322 | if (!fixup_exception(regs, X86_TRAP_MC, error_code, 0)) |
b2f9d678 | 1323 | mce_panic("Failed kernel mode recovery", &m, NULL); |
d4812e16 | 1324 | } |
b2f9d678 TL |
1325 | |
1326 | out_ist: | |
8c84014f | 1327 | ist_exit(regs); |
1da177e4 | 1328 | } |
ea149b36 | 1329 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 1330 | |
cd42f4a3 | 1331 | #ifndef CONFIG_MEMORY_FAILURE |
83b57531 | 1332 | int memory_failure(unsigned long pfn, int flags) |
9b1beaf2 | 1333 | { |
a8c321fb TL |
1334 | /* mce_severity() should not hand us an ACTION_REQUIRED error */ |
1335 | BUG_ON(flags & MF_ACTION_REQUIRED); | |
c767a54b JP |
1336 | pr_err("Uncorrected memory error in page 0x%lx ignored\n" |
1337 | "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", | |
1338 | pfn); | |
cd42f4a3 TL |
1339 | |
1340 | return 0; | |
9b1beaf2 | 1341 | } |
cd42f4a3 | 1342 | #endif |
9b1beaf2 | 1343 | |
1da177e4 | 1344 | /* |
8a336b0a TH |
1345 | * Periodic polling timer for "silent" machine check errors. If the |
1346 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
1347 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 1348 | */ |
3f2f0680 | 1349 | static unsigned long check_interval = INITIAL_CHECK_INTERVAL; |
e9eee03e | 1350 | |
82f7af09 | 1351 | static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */ |
52d168e2 | 1352 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 1353 | |
55babd8f CG |
1354 | static unsigned long mce_adjust_timer_default(unsigned long interval) |
1355 | { | |
1356 | return interval; | |
1357 | } | |
1358 | ||
3f2f0680 | 1359 | static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default; |
55babd8f | 1360 | |
0becc0ae | 1361 | static void __start_timer(struct timer_list *t, unsigned long interval) |
27f6c573 | 1362 | { |
3f2f0680 BP |
1363 | unsigned long when = jiffies + interval; |
1364 | unsigned long flags; | |
27f6c573 | 1365 | |
3f2f0680 | 1366 | local_irq_save(flags); |
27f6c573 | 1367 | |
0becc0ae TG |
1368 | if (!timer_pending(t) || time_before(when, t->expires)) |
1369 | mod_timer(t, round_jiffies(when)); | |
3f2f0680 BP |
1370 | |
1371 | local_irq_restore(flags); | |
27f6c573 CG |
1372 | } |
1373 | ||
92bb6cb1 | 1374 | static void mce_timer_fn(struct timer_list *t) |
1da177e4 | 1375 | { |
92bb6cb1 | 1376 | struct timer_list *cpu_t = this_cpu_ptr(&mce_timer); |
82f7af09 | 1377 | unsigned long iv; |
52d168e2 | 1378 | |
92bb6cb1 | 1379 | WARN_ON(cpu_t != t); |
3f2f0680 BP |
1380 | |
1381 | iv = __this_cpu_read(mce_next_interval); | |
52d168e2 | 1382 | |
89cbc767 | 1383 | if (mce_available(this_cpu_ptr(&cpu_info))) { |
54467353 | 1384 | machine_check_poll(0, this_cpu_ptr(&mce_poll_banks)); |
3f2f0680 BP |
1385 | |
1386 | if (mce_intel_cmci_poll()) { | |
1387 | iv = mce_adjust_timer(iv); | |
1388 | goto done; | |
1389 | } | |
e9eee03e | 1390 | } |
1da177e4 LT |
1391 | |
1392 | /* | |
3f2f0680 BP |
1393 | * Alert userspace if needed. If we logged an MCE, reduce the polling |
1394 | * interval, otherwise increase the polling interval. | |
1da177e4 | 1395 | */ |
3f2f0680 | 1396 | if (mce_notify_irq()) |
958fb3c5 | 1397 | iv = max(iv / 2, (unsigned long) HZ/100); |
3f2f0680 | 1398 | else |
82f7af09 | 1399 | iv = min(iv * 2, round_jiffies_relative(check_interval * HZ)); |
3f2f0680 BP |
1400 | |
1401 | done: | |
82f7af09 | 1402 | __this_cpu_write(mce_next_interval, iv); |
0becc0ae | 1403 | __start_timer(t, iv); |
55babd8f | 1404 | } |
e02e68d3 | 1405 | |
55babd8f CG |
1406 | /* |
1407 | * Ensure that the timer is firing in @interval from now. | |
1408 | */ | |
1409 | void mce_timer_kick(unsigned long interval) | |
1410 | { | |
89cbc767 | 1411 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
55babd8f CG |
1412 | unsigned long iv = __this_cpu_read(mce_next_interval); |
1413 | ||
0becc0ae | 1414 | __start_timer(t, interval); |
3f2f0680 | 1415 | |
55babd8f CG |
1416 | if (interval < iv) |
1417 | __this_cpu_write(mce_next_interval, interval); | |
e02e68d3 TH |
1418 | } |
1419 | ||
9aaef96f HS |
1420 | /* Must not be called in IRQ context where del_timer_sync() can deadlock */ |
1421 | static void mce_timer_delete_all(void) | |
1422 | { | |
1423 | int cpu; | |
1424 | ||
1425 | for_each_online_cpu(cpu) | |
1426 | del_timer_sync(&per_cpu(mce_timer, cpu)); | |
1427 | } | |
1428 | ||
e02e68d3 | 1429 | /* |
9bd98405 AK |
1430 | * Notify the user(s) about new machine check events. |
1431 | * Can be called from interrupt context, but not from machine check/NMI | |
1432 | * context. | |
e02e68d3 | 1433 | */ |
9ff36ee9 | 1434 | int mce_notify_irq(void) |
e02e68d3 | 1435 | { |
8457c84d AK |
1436 | /* Not more than two messages every minute */ |
1437 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
1438 | ||
1020bcbc | 1439 | if (test_and_clear_bit(0, &mce_need_notify)) { |
5de97c9f | 1440 | mce_work_trigger(); |
e02e68d3 | 1441 | |
8457c84d | 1442 | if (__ratelimit(&ratelimit)) |
a2d7b0d4 | 1443 | pr_info(HW_ERR "Machine check events logged\n"); |
e02e68d3 TH |
1444 | |
1445 | return 1; | |
1da177e4 | 1446 | } |
e02e68d3 TH |
1447 | return 0; |
1448 | } | |
9ff36ee9 | 1449 | EXPORT_SYMBOL_GPL(mce_notify_irq); |
8a336b0a | 1450 | |
148f9bb8 | 1451 | static int __mcheck_cpu_mce_banks_init(void) |
cebe1820 AK |
1452 | { |
1453 | int i; | |
d203f0b8 | 1454 | u8 num_banks = mca_cfg.banks; |
cebe1820 | 1455 | |
6396bb22 | 1456 | mce_banks = kcalloc(num_banks, sizeof(struct mce_bank), GFP_KERNEL); |
cebe1820 AK |
1457 | if (!mce_banks) |
1458 | return -ENOMEM; | |
d203f0b8 BP |
1459 | |
1460 | for (i = 0; i < num_banks; i++) { | |
cebe1820 | 1461 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1462 | |
cebe1820 AK |
1463 | b->ctl = -1ULL; |
1464 | b->init = 1; | |
1465 | } | |
1466 | return 0; | |
1467 | } | |
1468 | ||
d88203d1 | 1469 | /* |
1da177e4 LT |
1470 | * Initialize Machine Checks for a CPU. |
1471 | */ | |
148f9bb8 | 1472 | static int __mcheck_cpu_cap_init(void) |
1da177e4 | 1473 | { |
0d7482e3 | 1474 | unsigned b; |
e9eee03e | 1475 | u64 cap; |
1da177e4 LT |
1476 | |
1477 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
1478 | |
1479 | b = cap & MCG_BANKCNT_MASK; | |
d203f0b8 | 1480 | if (!mca_cfg.banks) |
c767a54b | 1481 | pr_info("CPU supports %d MCE banks\n", b); |
b659294b | 1482 | |
0d7482e3 | 1483 | if (b > MAX_NR_BANKS) { |
c767a54b | 1484 | pr_warn("Using only %u machine check banks out of %u\n", |
0d7482e3 AK |
1485 | MAX_NR_BANKS, b); |
1486 | b = MAX_NR_BANKS; | |
1487 | } | |
1488 | ||
1489 | /* Don't support asymmetric configurations today */ | |
d203f0b8 BP |
1490 | WARN_ON(mca_cfg.banks != 0 && b != mca_cfg.banks); |
1491 | mca_cfg.banks = b; | |
1492 | ||
cebe1820 | 1493 | if (!mce_banks) { |
cffd377e | 1494 | int err = __mcheck_cpu_mce_banks_init(); |
11868a2d | 1495 | |
cebe1820 AK |
1496 | if (err) |
1497 | return err; | |
1da177e4 | 1498 | } |
0d7482e3 | 1499 | |
94ad8474 | 1500 | /* Use accurate RIP reporting if available. */ |
01c6680a | 1501 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
84c2559d | 1502 | mca_cfg.rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 1503 | |
ed7290d0 | 1504 | if (cap & MCG_SER_P) |
09933946 | 1505 | mca_cfg.ser = 1; |
ed7290d0 | 1506 | |
0d7482e3 AK |
1507 | return 0; |
1508 | } | |
1509 | ||
5e09954a | 1510 | static void __mcheck_cpu_init_generic(void) |
0d7482e3 | 1511 | { |
84c2559d | 1512 | enum mcp_flags m_fl = 0; |
e9eee03e | 1513 | mce_banks_t all_banks; |
0d7482e3 | 1514 | u64 cap; |
0d7482e3 | 1515 | |
84c2559d BP |
1516 | if (!mca_cfg.bootlog) |
1517 | m_fl = MCP_DONTLOG; | |
1518 | ||
b79109c3 AK |
1519 | /* |
1520 | * Log the machine checks left over from the previous reset. | |
1521 | */ | |
ee031c31 | 1522 | bitmap_fill(all_banks, MAX_NR_BANKS); |
84c2559d | 1523 | machine_check_poll(MCP_UC | m_fl, &all_banks); |
1da177e4 | 1524 | |
375074cc | 1525 | cr4_set_bits(X86_CR4_MCE); |
1da177e4 | 1526 | |
0d7482e3 | 1527 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
1528 | if (cap & MCG_CTL_P) |
1529 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
bb91f8c0 AG |
1530 | } |
1531 | ||
1532 | static void __mcheck_cpu_init_clear_banks(void) | |
1533 | { | |
1534 | int i; | |
1da177e4 | 1535 | |
d203f0b8 | 1536 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 1537 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1538 | |
cebe1820 | 1539 | if (!b->init) |
06b7a7a5 | 1540 | continue; |
d9d73fcc YG |
1541 | wrmsrl(msr_ops.ctl(i), b->ctl); |
1542 | wrmsrl(msr_ops.status(i), 0); | |
d88203d1 | 1543 | } |
1da177e4 LT |
1544 | } |
1545 | ||
61b0fccd TL |
1546 | /* |
1547 | * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and | |
1548 | * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM | |
1549 | * Vol 3B Table 15-20). But this confuses both the code that determines | |
1550 | * whether the machine check occurred in kernel or user mode, and also | |
1551 | * the severity assessment code. Pretend that EIPV was set, and take the | |
1552 | * ip/cs values from the pt_regs that mce_gather_info() ignored earlier. | |
1553 | */ | |
1554 | static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs) | |
1555 | { | |
1556 | if (bank != 0) | |
1557 | return; | |
1558 | if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0) | |
1559 | return; | |
1560 | if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC| | |
1561 | MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV| | |
1562 | MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR| | |
1563 | MCACOD)) != | |
1564 | (MCI_STATUS_UC|MCI_STATUS_EN| | |
1565 | MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S| | |
1566 | MCI_STATUS_AR|MCACOD_INSTR)) | |
1567 | return; | |
1568 | ||
1569 | m->mcgstatus |= MCG_STATUS_EIPV; | |
1570 | m->ip = regs->ip; | |
1571 | m->cs = regs->cs; | |
1572 | } | |
1573 | ||
1da177e4 | 1574 | /* Add per CPU specific workarounds here */ |
148f9bb8 | 1575 | static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 1576 | { |
d203f0b8 BP |
1577 | struct mca_config *cfg = &mca_cfg; |
1578 | ||
e412cd25 | 1579 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { |
c767a54b | 1580 | pr_info("unknown CPU type - not enabling MCE support\n"); |
e412cd25 IM |
1581 | return -EOPNOTSUPP; |
1582 | } | |
1583 | ||
1da177e4 | 1584 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 1585 | if (c->x86_vendor == X86_VENDOR_AMD) { |
d203f0b8 | 1586 | if (c->x86 == 15 && cfg->banks > 4) { |
e9eee03e IM |
1587 | /* |
1588 | * disable GART TBL walk error reporting, which | |
1589 | * trips off incorrectly with the IOMMU & 3ware | |
1590 | * & Cerberus: | |
1591 | */ | |
cebe1820 | 1592 | clear_bit(10, (unsigned long *)&mce_banks[4].ctl); |
e9eee03e | 1593 | } |
6057077f | 1594 | if (c->x86 < 0x11 && cfg->bootlog < 0) { |
e9eee03e IM |
1595 | /* |
1596 | * Lots of broken BIOS around that don't clear them | |
1597 | * by default and leave crap in there. Don't log: | |
1598 | */ | |
84c2559d | 1599 | cfg->bootlog = 0; |
e9eee03e | 1600 | } |
2e6f694f AK |
1601 | /* |
1602 | * Various K7s with broken bank 0 around. Always disable | |
1603 | * by default. | |
1604 | */ | |
c9ce8712 | 1605 | if (c->x86 == 6 && cfg->banks > 0) |
cebe1820 | 1606 | mce_banks[0].ctl = 0; |
575203b4 | 1607 | |
bf80bbd7 AG |
1608 | /* |
1609 | * overflow_recov is supported for F15h Models 00h-0fh | |
1610 | * even though we don't have a CPUID bit for it. | |
1611 | */ | |
1612 | if (c->x86 == 0x15 && c->x86_model <= 0xf) | |
1613 | mce_flags.overflow_recov = 1; | |
1614 | ||
c9ce8712 BP |
1615 | /* |
1616 | * Turn off MC4_MISC thresholding banks on those models since | |
1617 | * they're not supported there. | |
1618 | */ | |
1619 | if (c->x86 == 0x15 && | |
1620 | (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) { | |
1621 | int i; | |
1622 | u64 hwcr; | |
1623 | bool need_toggle; | |
1624 | u32 msrs[] = { | |
575203b4 BP |
1625 | 0x00000413, /* MC4_MISC0 */ |
1626 | 0xc0000408, /* MC4_MISC1 */ | |
c9ce8712 | 1627 | }; |
575203b4 | 1628 | |
c9ce8712 | 1629 | rdmsrl(MSR_K7_HWCR, hwcr); |
575203b4 | 1630 | |
c9ce8712 BP |
1631 | /* McStatusWrEn has to be set */ |
1632 | need_toggle = !(hwcr & BIT(18)); | |
575203b4 | 1633 | |
c9ce8712 BP |
1634 | if (need_toggle) |
1635 | wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); | |
575203b4 | 1636 | |
c9ce8712 BP |
1637 | /* Clear CntP bit safely */ |
1638 | for (i = 0; i < ARRAY_SIZE(msrs); i++) | |
1639 | msr_clear_bit(msrs[i], 62); | |
575203b4 | 1640 | |
c9ce8712 BP |
1641 | /* restore old settings */ |
1642 | if (need_toggle) | |
1643 | wrmsrl(MSR_K7_HWCR, hwcr); | |
1644 | } | |
1da177e4 | 1645 | } |
e583538f | 1646 | |
06b7a7a5 AK |
1647 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
1648 | /* | |
1649 | * SDM documents that on family 6 bank 0 should not be written | |
1650 | * because it aliases to another special BIOS controlled | |
1651 | * register. | |
1652 | * But it's not aliased anymore on model 0x1a+ | |
1653 | * Don't ignore bank 0 completely because there could be a | |
1654 | * valid event later, merely don't write CTL0. | |
1655 | */ | |
1656 | ||
d203f0b8 | 1657 | if (c->x86 == 6 && c->x86_model < 0x1A && cfg->banks > 0) |
cebe1820 | 1658 | mce_banks[0].init = 0; |
3c079792 AK |
1659 | |
1660 | /* | |
1661 | * All newer Intel systems support MCE broadcasting. Enable | |
1662 | * synchronization with a one second timeout. | |
1663 | */ | |
1664 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && | |
84c2559d BP |
1665 | cfg->monarch_timeout < 0) |
1666 | cfg->monarch_timeout = USEC_PER_SEC; | |
c7f6fa44 | 1667 | |
e412cd25 IM |
1668 | /* |
1669 | * There are also broken BIOSes on some Pentium M and | |
1670 | * earlier systems: | |
1671 | */ | |
84c2559d BP |
1672 | if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0) |
1673 | cfg->bootlog = 0; | |
61b0fccd TL |
1674 | |
1675 | if (c->x86 == 6 && c->x86_model == 45) | |
1676 | quirk_no_way_out = quirk_sandybridge_ifu; | |
06b7a7a5 | 1677 | } |
84c2559d BP |
1678 | if (cfg->monarch_timeout < 0) |
1679 | cfg->monarch_timeout = 0; | |
1680 | if (cfg->bootlog != 0) | |
7af19e4a | 1681 | cfg->panic_timeout = 30; |
e412cd25 IM |
1682 | |
1683 | return 0; | |
d88203d1 | 1684 | } |
1da177e4 | 1685 | |
148f9bb8 | 1686 | static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) |
4efc0670 AK |
1687 | { |
1688 | if (c->x86 != 5) | |
3a97fc34 HS |
1689 | return 0; |
1690 | ||
4efc0670 AK |
1691 | switch (c->x86_vendor) { |
1692 | case X86_VENDOR_INTEL: | |
c6978369 | 1693 | intel_p5_mcheck_init(c); |
3a97fc34 | 1694 | return 1; |
4efc0670 AK |
1695 | break; |
1696 | case X86_VENDOR_CENTAUR: | |
1697 | winchip_mcheck_init(c); | |
3a97fc34 | 1698 | return 1; |
4efc0670 | 1699 | break; |
dc34bdd2 BP |
1700 | default: |
1701 | return 0; | |
4efc0670 | 1702 | } |
3a97fc34 HS |
1703 | |
1704 | return 0; | |
4efc0670 AK |
1705 | } |
1706 | ||
5204bf17 YG |
1707 | /* |
1708 | * Init basic CPU features needed for early decoding of MCEs. | |
1709 | */ | |
1710 | static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c) | |
1da177e4 | 1711 | { |
ac78bd72 | 1712 | if (c->x86_vendor == X86_VENDOR_AMD || c->x86_vendor == X86_VENDOR_HYGON) { |
14cddfd5 YG |
1713 | mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV); |
1714 | mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR); | |
1715 | mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA); | |
d9d73fcc | 1716 | |
d9d73fcc YG |
1717 | if (mce_flags.smca) { |
1718 | msr_ops.ctl = smca_ctl_reg; | |
1719 | msr_ops.status = smca_status_reg; | |
1720 | msr_ops.addr = smca_addr_reg; | |
1721 | msr_ops.misc = smca_misc_reg; | |
1722 | } | |
5204bf17 YG |
1723 | } |
1724 | } | |
c7f54d21 | 1725 | |
13e85822 DW |
1726 | static void mce_centaur_feature_init(struct cpuinfo_x86 *c) |
1727 | { | |
1728 | struct mca_config *cfg = &mca_cfg; | |
1729 | ||
1730 | /* | |
1731 | * All newer Centaur CPUs support MCE broadcasting. Enable | |
1732 | * synchronization with a one second timeout. | |
1733 | */ | |
1734 | if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) || | |
1735 | c->x86 > 6) { | |
1736 | if (cfg->monarch_timeout < 0) | |
1737 | cfg->monarch_timeout = USEC_PER_SEC; | |
1738 | } | |
1739 | } | |
1740 | ||
5204bf17 YG |
1741 | static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) |
1742 | { | |
1743 | switch (c->x86_vendor) { | |
1744 | case X86_VENDOR_INTEL: | |
1745 | mce_intel_feature_init(c); | |
1746 | mce_adjust_timer = cmci_intel_adjust_timer; | |
1747 | break; | |
c7f54d21 | 1748 | |
5204bf17 YG |
1749 | case X86_VENDOR_AMD: { |
1750 | mce_amd_feature_init(c); | |
89b831ef | 1751 | break; |
7559e13f | 1752 | } |
ac78bd72 PW |
1753 | |
1754 | case X86_VENDOR_HYGON: | |
1755 | mce_hygon_feature_init(c); | |
1756 | break; | |
1757 | ||
13e85822 DW |
1758 | case X86_VENDOR_CENTAUR: |
1759 | mce_centaur_feature_init(c); | |
1760 | break; | |
7559e13f | 1761 | |
1da177e4 LT |
1762 | default: |
1763 | break; | |
1764 | } | |
1765 | } | |
1766 | ||
8838eb6c AR |
1767 | static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c) |
1768 | { | |
1769 | switch (c->x86_vendor) { | |
1770 | case X86_VENDOR_INTEL: | |
1771 | mce_intel_feature_clear(c); | |
1772 | break; | |
1773 | default: | |
1774 | break; | |
1775 | } | |
1776 | } | |
1777 | ||
0becc0ae | 1778 | static void mce_start_timer(struct timer_list *t) |
52d168e2 | 1779 | { |
4f75d841 | 1780 | unsigned long iv = check_interval * HZ; |
bc09effa | 1781 | |
7af19e4a | 1782 | if (mca_cfg.ignore_ce || !iv) |
62fdac59 HS |
1783 | return; |
1784 | ||
0becc0ae TG |
1785 | this_cpu_write(mce_next_interval, iv); |
1786 | __start_timer(t, iv); | |
52d168e2 AK |
1787 | } |
1788 | ||
39f152ff SAS |
1789 | static void __mcheck_cpu_setup_timer(void) |
1790 | { | |
1791 | struct timer_list *t = this_cpu_ptr(&mce_timer); | |
39f152ff | 1792 | |
92bb6cb1 | 1793 | timer_setup(t, mce_timer_fn, TIMER_PINNED); |
39f152ff SAS |
1794 | } |
1795 | ||
26c3c283 TG |
1796 | static void __mcheck_cpu_init_timer(void) |
1797 | { | |
89cbc767 | 1798 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
26c3c283 | 1799 | |
92bb6cb1 | 1800 | timer_setup(t, mce_timer_fn, TIMER_PINNED); |
0becc0ae | 1801 | mce_start_timer(t); |
26c3c283 TG |
1802 | } |
1803 | ||
9eda8cb3 AK |
1804 | /* Handle unconfigured int18 (should never happen) */ |
1805 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
1806 | { | |
c767a54b | 1807 | pr_err("CPU#%d: Unexpected int18 (Machine Check)\n", |
9eda8cb3 AK |
1808 | smp_processor_id()); |
1809 | } | |
1810 | ||
1811 | /* Call the installed machine check handler for this CPU setup. */ | |
1812 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
1813 | unexpected_machine_check; | |
1814 | ||
6f41c34d TG |
1815 | dotraplinkage void do_mce(struct pt_regs *regs, long error_code) |
1816 | { | |
1817 | machine_check_vector(regs, error_code); | |
1818 | } | |
1819 | ||
d88203d1 | 1820 | /* |
1da177e4 | 1821 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 1822 | * Must be called with preempt off: |
1da177e4 | 1823 | */ |
148f9bb8 | 1824 | void mcheck_cpu_init(struct cpuinfo_x86 *c) |
1da177e4 | 1825 | { |
1462594b | 1826 | if (mca_cfg.disabled) |
4efc0670 AK |
1827 | return; |
1828 | ||
3a97fc34 HS |
1829 | if (__mcheck_cpu_ancient_init(c)) |
1830 | return; | |
4efc0670 | 1831 | |
5b4408fd | 1832 | if (!mce_available(c)) |
1da177e4 LT |
1833 | return; |
1834 | ||
5e09954a | 1835 | if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) { |
09933946 | 1836 | mca_cfg.disabled = 1; |
0d7482e3 AK |
1837 | return; |
1838 | } | |
0d7482e3 | 1839 | |
648ed940 | 1840 | if (mce_gen_pool_init()) { |
09933946 | 1841 | mca_cfg.disabled = 1; |
648ed940 CG |
1842 | pr_emerg("Couldn't allocate MCE records pool!\n"); |
1843 | return; | |
1844 | } | |
1845 | ||
5d727926 AK |
1846 | machine_check_vector = do_machine_check; |
1847 | ||
5204bf17 | 1848 | __mcheck_cpu_init_early(c); |
5e09954a BP |
1849 | __mcheck_cpu_init_generic(); |
1850 | __mcheck_cpu_init_vendor(c); | |
bb91f8c0 | 1851 | __mcheck_cpu_init_clear_banks(); |
39f152ff | 1852 | __mcheck_cpu_setup_timer(); |
1da177e4 LT |
1853 | } |
1854 | ||
8838eb6c AR |
1855 | /* |
1856 | * Called for each booted CPU to clear some machine checks opt-ins | |
1857 | */ | |
1858 | void mcheck_cpu_clear(struct cpuinfo_x86 *c) | |
1859 | { | |
1860 | if (mca_cfg.disabled) | |
1861 | return; | |
1862 | ||
1863 | if (!mce_available(c)) | |
1864 | return; | |
1865 | ||
1866 | /* | |
1867 | * Possibly to clear general settings generic to x86 | |
1868 | * __mcheck_cpu_clear_generic(c); | |
1869 | */ | |
1870 | __mcheck_cpu_clear_vendor(c); | |
1871 | ||
1da177e4 LT |
1872 | } |
1873 | ||
c3d1fb56 NR |
1874 | static void __mce_disable_bank(void *arg) |
1875 | { | |
1876 | int bank = *((int *)arg); | |
89cbc767 | 1877 | __clear_bit(bank, this_cpu_ptr(mce_poll_banks)); |
c3d1fb56 NR |
1878 | cmci_disable_bank(bank); |
1879 | } | |
1880 | ||
1881 | void mce_disable_bank(int bank) | |
1882 | { | |
1883 | if (bank >= mca_cfg.banks) { | |
1884 | pr_warn(FW_BUG | |
1885 | "Ignoring request to disable invalid MCA bank %d.\n", | |
1886 | bank); | |
1887 | return; | |
1888 | } | |
1889 | set_bit(bank, mce_banks_ce_disabled); | |
1890 | on_each_cpu(__mce_disable_bank, &bank, 1); | |
1891 | } | |
1892 | ||
13503fa9 | 1893 | /* |
62fdac59 HS |
1894 | * mce=off Disables machine check |
1895 | * mce=no_cmci Disables CMCI | |
88d53867 | 1896 | * mce=no_lmce Disables LMCE |
62fdac59 HS |
1897 | * mce=dont_log_ce Clears corrected events silently, no log created for CEs. |
1898 | * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. | |
3c079792 AK |
1899 | * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) |
1900 | * monarchtimeout is how long to wait for other CPUs on machine | |
1901 | * check, or 0 to not wait | |
6057077f YG |
1902 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD Fam10h |
1903 | and older. | |
13503fa9 | 1904 | * mce=nobootlog Don't log MCEs from before booting. |
450cc201 | 1905 | * mce=bios_cmci_threshold Don't program the CMCI threshold |
3637efb0 | 1906 | * mce=recovery force enable memcpy_mcsafe() |
13503fa9 | 1907 | */ |
1da177e4 LT |
1908 | static int __init mcheck_enable(char *str) |
1909 | { | |
d203f0b8 BP |
1910 | struct mca_config *cfg = &mca_cfg; |
1911 | ||
e3346fc4 | 1912 | if (*str == 0) { |
4efc0670 | 1913 | enable_p5_mce(); |
e3346fc4 BZ |
1914 | return 1; |
1915 | } | |
4efc0670 AK |
1916 | if (*str == '=') |
1917 | str++; | |
1da177e4 | 1918 | if (!strcmp(str, "off")) |
09933946 | 1919 | cfg->disabled = 1; |
62fdac59 | 1920 | else if (!strcmp(str, "no_cmci")) |
7af19e4a | 1921 | cfg->cmci_disabled = true; |
88d53867 | 1922 | else if (!strcmp(str, "no_lmce")) |
09933946 | 1923 | cfg->lmce_disabled = 1; |
62fdac59 | 1924 | else if (!strcmp(str, "dont_log_ce")) |
d203f0b8 | 1925 | cfg->dont_log_ce = true; |
62fdac59 | 1926 | else if (!strcmp(str, "ignore_ce")) |
7af19e4a | 1927 | cfg->ignore_ce = true; |
13503fa9 | 1928 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
84c2559d | 1929 | cfg->bootlog = (str[0] == 'b'); |
450cc201 | 1930 | else if (!strcmp(str, "bios_cmci_threshold")) |
09933946 | 1931 | cfg->bios_cmci_threshold = 1; |
0f68c088 | 1932 | else if (!strcmp(str, "recovery")) |
09933946 | 1933 | cfg->recovery = 1; |
3c079792 | 1934 | else if (isdigit(str[0])) { |
5c31b280 | 1935 | if (get_option(&str, &cfg->tolerant) == 2) |
84c2559d | 1936 | get_option(&str, &(cfg->monarch_timeout)); |
3c079792 | 1937 | } else { |
c767a54b | 1938 | pr_info("mce argument %s ignored. Please use /sys\n", str); |
13503fa9 HS |
1939 | return 0; |
1940 | } | |
9b41046c | 1941 | return 1; |
1da177e4 | 1942 | } |
4efc0670 | 1943 | __setup("mce", mcheck_enable); |
1da177e4 | 1944 | |
a2202aa2 | 1945 | int __init mcheck_init(void) |
b33a6363 | 1946 | { |
a2202aa2 | 1947 | mcheck_intel_therm_init(); |
011d8261 | 1948 | mce_register_decode_chain(&first_nb); |
eef4dfa0 | 1949 | mce_register_decode_chain(&mce_srao_nb); |
cd9c57ca | 1950 | mce_register_decode_chain(&mce_default_nb); |
43eaa2a1 | 1951 | mcheck_vendor_init_severity(); |
a2202aa2 | 1952 | |
cff4c039 | 1953 | INIT_WORK(&mce_work, mce_gen_pool_process); |
061120ae CG |
1954 | init_irq_work(&mce_irq_work, mce_irq_work_cb); |
1955 | ||
b33a6363 BP |
1956 | return 0; |
1957 | } | |
b33a6363 | 1958 | |
d88203d1 | 1959 | /* |
c7cece89 | 1960 | * mce_syscore: PM support |
d88203d1 | 1961 | */ |
1da177e4 | 1962 | |
973a2dd1 AK |
1963 | /* |
1964 | * Disable machine checks on suspend and shutdown. We can't really handle | |
1965 | * them later. | |
1966 | */ | |
6e06780a | 1967 | static void mce_disable_error_reporting(void) |
973a2dd1 AK |
1968 | { |
1969 | int i; | |
1970 | ||
d203f0b8 | 1971 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 1972 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1973 | |
cebe1820 | 1974 | if (b->init) |
d9d73fcc | 1975 | wrmsrl(msr_ops.ctl(i), 0); |
06b7a7a5 | 1976 | } |
6e06780a AR |
1977 | return; |
1978 | } | |
1979 | ||
1980 | static void vendor_disable_error_reporting(void) | |
1981 | { | |
1982 | /* | |
ac78bd72 PW |
1983 | * Don't clear on Intel or AMD or Hygon CPUs. Some of these MSRs |
1984 | * are socket-wide. | |
6e06780a AR |
1985 | * Disabling them for just a single offlined CPU is bad, since it will |
1986 | * inhibit reporting for all shared resources on the socket like the | |
1987 | * last level cache (LLC), the integrated memory controller (iMC), etc. | |
1988 | */ | |
ec338382 | 1989 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL || |
ac78bd72 | 1990 | boot_cpu_data.x86_vendor == X86_VENDOR_HYGON || |
ec338382 | 1991 | boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
6e06780a AR |
1992 | return; |
1993 | ||
1994 | mce_disable_error_reporting(); | |
973a2dd1 AK |
1995 | } |
1996 | ||
c7cece89 | 1997 | static int mce_syscore_suspend(void) |
973a2dd1 | 1998 | { |
6e06780a AR |
1999 | vendor_disable_error_reporting(); |
2000 | return 0; | |
973a2dd1 AK |
2001 | } |
2002 | ||
c7cece89 | 2003 | static void mce_syscore_shutdown(void) |
973a2dd1 | 2004 | { |
6e06780a | 2005 | vendor_disable_error_reporting(); |
973a2dd1 AK |
2006 | } |
2007 | ||
e9eee03e IM |
2008 | /* |
2009 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
2010 | * Only one CPU is active at this time, the others get re-added later using | |
2011 | * CPU hotplug: | |
2012 | */ | |
c7cece89 | 2013 | static void mce_syscore_resume(void) |
1da177e4 | 2014 | { |
5e09954a | 2015 | __mcheck_cpu_init_generic(); |
89cbc767 | 2016 | __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info)); |
bb91f8c0 | 2017 | __mcheck_cpu_init_clear_banks(); |
1da177e4 LT |
2018 | } |
2019 | ||
f3c6ea1b | 2020 | static struct syscore_ops mce_syscore_ops = { |
c7cece89 HS |
2021 | .suspend = mce_syscore_suspend, |
2022 | .shutdown = mce_syscore_shutdown, | |
2023 | .resume = mce_syscore_resume, | |
f3c6ea1b RW |
2024 | }; |
2025 | ||
c7cece89 | 2026 | /* |
8a25a2fd | 2027 | * mce_device: Sysfs support |
c7cece89 HS |
2028 | */ |
2029 | ||
52d168e2 AK |
2030 | static void mce_cpu_restart(void *data) |
2031 | { | |
89cbc767 | 2032 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
33edbf02 | 2033 | return; |
5e09954a | 2034 | __mcheck_cpu_init_generic(); |
bb91f8c0 | 2035 | __mcheck_cpu_init_clear_banks(); |
5e09954a | 2036 | __mcheck_cpu_init_timer(); |
52d168e2 AK |
2037 | } |
2038 | ||
1da177e4 | 2039 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
2040 | static void mce_restart(void) |
2041 | { | |
9aaef96f | 2042 | mce_timer_delete_all(); |
52d168e2 | 2043 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
2044 | } |
2045 | ||
9af43b54 | 2046 | /* Toggle features for corrected errors */ |
9aaef96f | 2047 | static void mce_disable_cmci(void *data) |
9af43b54 | 2048 | { |
89cbc767 | 2049 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
9af43b54 | 2050 | return; |
9af43b54 HS |
2051 | cmci_clear(); |
2052 | } | |
2053 | ||
2054 | static void mce_enable_ce(void *all) | |
2055 | { | |
89cbc767 | 2056 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
9af43b54 HS |
2057 | return; |
2058 | cmci_reenable(); | |
2059 | cmci_recheck(); | |
2060 | if (all) | |
5e09954a | 2061 | __mcheck_cpu_init_timer(); |
9af43b54 HS |
2062 | } |
2063 | ||
8a25a2fd | 2064 | static struct bus_type mce_subsys = { |
e9eee03e | 2065 | .name = "machinecheck", |
8a25a2fd | 2066 | .dev_name = "machinecheck", |
1da177e4 LT |
2067 | }; |
2068 | ||
d6126ef5 | 2069 | DEFINE_PER_CPU(struct device *, mce_device); |
e9eee03e | 2070 | |
8a25a2fd | 2071 | static inline struct mce_bank *attr_to_bank(struct device_attribute *attr) |
cebe1820 AK |
2072 | { |
2073 | return container_of(attr, struct mce_bank, attr); | |
2074 | } | |
0d7482e3 | 2075 | |
8a25a2fd | 2076 | static ssize_t show_bank(struct device *s, struct device_attribute *attr, |
0d7482e3 AK |
2077 | char *buf) |
2078 | { | |
cebe1820 | 2079 | return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl); |
0d7482e3 AK |
2080 | } |
2081 | ||
8a25a2fd | 2082 | static ssize_t set_bank(struct device *s, struct device_attribute *attr, |
9319cec8 | 2083 | const char *buf, size_t size) |
0d7482e3 | 2084 | { |
9319cec8 | 2085 | u64 new; |
e9eee03e | 2086 | |
164109e3 | 2087 | if (kstrtou64(buf, 0, &new) < 0) |
0d7482e3 | 2088 | return -EINVAL; |
e9eee03e | 2089 | |
cebe1820 | 2090 | attr_to_bank(attr)->ctl = new; |
0d7482e3 | 2091 | mce_restart(); |
e9eee03e | 2092 | |
9319cec8 | 2093 | return size; |
0d7482e3 | 2094 | } |
a98f0dd3 | 2095 | |
8a25a2fd KS |
2096 | static ssize_t set_ignore_ce(struct device *s, |
2097 | struct device_attribute *attr, | |
9af43b54 HS |
2098 | const char *buf, size_t size) |
2099 | { | |
2100 | u64 new; | |
2101 | ||
164109e3 | 2102 | if (kstrtou64(buf, 0, &new) < 0) |
9af43b54 HS |
2103 | return -EINVAL; |
2104 | ||
b3b7c479 | 2105 | mutex_lock(&mce_sysfs_mutex); |
7af19e4a | 2106 | if (mca_cfg.ignore_ce ^ !!new) { |
9af43b54 HS |
2107 | if (new) { |
2108 | /* disable ce features */ | |
9aaef96f HS |
2109 | mce_timer_delete_all(); |
2110 | on_each_cpu(mce_disable_cmci, NULL, 1); | |
7af19e4a | 2111 | mca_cfg.ignore_ce = true; |
9af43b54 HS |
2112 | } else { |
2113 | /* enable ce features */ | |
7af19e4a | 2114 | mca_cfg.ignore_ce = false; |
9af43b54 HS |
2115 | on_each_cpu(mce_enable_ce, (void *)1, 1); |
2116 | } | |
2117 | } | |
b3b7c479 SH |
2118 | mutex_unlock(&mce_sysfs_mutex); |
2119 | ||
9af43b54 HS |
2120 | return size; |
2121 | } | |
2122 | ||
8a25a2fd KS |
2123 | static ssize_t set_cmci_disabled(struct device *s, |
2124 | struct device_attribute *attr, | |
9af43b54 HS |
2125 | const char *buf, size_t size) |
2126 | { | |
2127 | u64 new; | |
2128 | ||
164109e3 | 2129 | if (kstrtou64(buf, 0, &new) < 0) |
9af43b54 HS |
2130 | return -EINVAL; |
2131 | ||
b3b7c479 | 2132 | mutex_lock(&mce_sysfs_mutex); |
7af19e4a | 2133 | if (mca_cfg.cmci_disabled ^ !!new) { |
9af43b54 HS |
2134 | if (new) { |
2135 | /* disable cmci */ | |
9aaef96f | 2136 | on_each_cpu(mce_disable_cmci, NULL, 1); |
7af19e4a | 2137 | mca_cfg.cmci_disabled = true; |
9af43b54 HS |
2138 | } else { |
2139 | /* enable cmci */ | |
7af19e4a | 2140 | mca_cfg.cmci_disabled = false; |
9af43b54 HS |
2141 | on_each_cpu(mce_enable_ce, NULL, 1); |
2142 | } | |
2143 | } | |
b3b7c479 SH |
2144 | mutex_unlock(&mce_sysfs_mutex); |
2145 | ||
9af43b54 HS |
2146 | return size; |
2147 | } | |
2148 | ||
8a25a2fd KS |
2149 | static ssize_t store_int_with_restart(struct device *s, |
2150 | struct device_attribute *attr, | |
b56f642d AK |
2151 | const char *buf, size_t size) |
2152 | { | |
b3b7c479 SH |
2153 | unsigned long old_check_interval = check_interval; |
2154 | ssize_t ret = device_store_ulong(s, attr, buf, size); | |
2155 | ||
2156 | if (check_interval == old_check_interval) | |
2157 | return ret; | |
2158 | ||
b3b7c479 | 2159 | mutex_lock(&mce_sysfs_mutex); |
b56f642d | 2160 | mce_restart(); |
b3b7c479 SH |
2161 | mutex_unlock(&mce_sysfs_mutex); |
2162 | ||
b56f642d AK |
2163 | return ret; |
2164 | } | |
2165 | ||
d203f0b8 | 2166 | static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant); |
84c2559d | 2167 | static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout); |
d203f0b8 | 2168 | static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce); |
e9eee03e | 2169 | |
8a25a2fd KS |
2170 | static struct dev_ext_attribute dev_attr_check_interval = { |
2171 | __ATTR(check_interval, 0644, device_show_int, store_int_with_restart), | |
b56f642d AK |
2172 | &check_interval |
2173 | }; | |
e9eee03e | 2174 | |
8a25a2fd | 2175 | static struct dev_ext_attribute dev_attr_ignore_ce = { |
7af19e4a BP |
2176 | __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce), |
2177 | &mca_cfg.ignore_ce | |
9af43b54 HS |
2178 | }; |
2179 | ||
8a25a2fd | 2180 | static struct dev_ext_attribute dev_attr_cmci_disabled = { |
7af19e4a BP |
2181 | __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled), |
2182 | &mca_cfg.cmci_disabled | |
9af43b54 HS |
2183 | }; |
2184 | ||
8a25a2fd KS |
2185 | static struct device_attribute *mce_device_attrs[] = { |
2186 | &dev_attr_tolerant.attr, | |
2187 | &dev_attr_check_interval.attr, | |
5de97c9f | 2188 | #ifdef CONFIG_X86_MCELOG_LEGACY |
8a25a2fd | 2189 | &dev_attr_trigger, |
5de97c9f | 2190 | #endif |
8a25a2fd KS |
2191 | &dev_attr_monarch_timeout.attr, |
2192 | &dev_attr_dont_log_ce.attr, | |
2193 | &dev_attr_ignore_ce.attr, | |
2194 | &dev_attr_cmci_disabled.attr, | |
a98f0dd3 AK |
2195 | NULL |
2196 | }; | |
1da177e4 | 2197 | |
8a25a2fd | 2198 | static cpumask_var_t mce_device_initialized; |
bae19fe0 | 2199 | |
e032d807 GKH |
2200 | static void mce_device_release(struct device *dev) |
2201 | { | |
2202 | kfree(dev); | |
2203 | } | |
2204 | ||
8a25a2fd | 2205 | /* Per cpu device init. All of the cpus still share the same ctrl bank: */ |
148f9bb8 | 2206 | static int mce_device_create(unsigned int cpu) |
1da177e4 | 2207 | { |
e032d807 | 2208 | struct device *dev; |
1da177e4 | 2209 | int err; |
b1f49f95 | 2210 | int i, j; |
92cb7612 | 2211 | |
90367556 | 2212 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
2213 | return -EIO; |
2214 | ||
7f34b935 SAS |
2215 | dev = per_cpu(mce_device, cpu); |
2216 | if (dev) | |
2217 | return 0; | |
2218 | ||
0e96f31e | 2219 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); |
e032d807 GKH |
2220 | if (!dev) |
2221 | return -ENOMEM; | |
8a25a2fd KS |
2222 | dev->id = cpu; |
2223 | dev->bus = &mce_subsys; | |
e032d807 | 2224 | dev->release = &mce_device_release; |
91c6d400 | 2225 | |
8a25a2fd | 2226 | err = device_register(dev); |
853d9b18 LK |
2227 | if (err) { |
2228 | put_device(dev); | |
d435d862 | 2229 | return err; |
853d9b18 | 2230 | } |
d435d862 | 2231 | |
8a25a2fd KS |
2232 | for (i = 0; mce_device_attrs[i]; i++) { |
2233 | err = device_create_file(dev, mce_device_attrs[i]); | |
d435d862 AM |
2234 | if (err) |
2235 | goto error; | |
2236 | } | |
d203f0b8 | 2237 | for (j = 0; j < mca_cfg.banks; j++) { |
8a25a2fd | 2238 | err = device_create_file(dev, &mce_banks[j].attr); |
0d7482e3 AK |
2239 | if (err) |
2240 | goto error2; | |
2241 | } | |
8a25a2fd | 2242 | cpumask_set_cpu(cpu, mce_device_initialized); |
d6126ef5 | 2243 | per_cpu(mce_device, cpu) = dev; |
91c6d400 | 2244 | |
d435d862 | 2245 | return 0; |
0d7482e3 | 2246 | error2: |
b1f49f95 | 2247 | while (--j >= 0) |
8a25a2fd | 2248 | device_remove_file(dev, &mce_banks[j].attr); |
d435d862 | 2249 | error: |
cb491fca | 2250 | while (--i >= 0) |
8a25a2fd | 2251 | device_remove_file(dev, mce_device_attrs[i]); |
cb491fca | 2252 | |
8a25a2fd | 2253 | device_unregister(dev); |
d435d862 | 2254 | |
91c6d400 AK |
2255 | return err; |
2256 | } | |
2257 | ||
148f9bb8 | 2258 | static void mce_device_remove(unsigned int cpu) |
91c6d400 | 2259 | { |
d6126ef5 | 2260 | struct device *dev = per_cpu(mce_device, cpu); |
73ca5358 SL |
2261 | int i; |
2262 | ||
8a25a2fd | 2263 | if (!cpumask_test_cpu(cpu, mce_device_initialized)) |
bae19fe0 AH |
2264 | return; |
2265 | ||
8a25a2fd KS |
2266 | for (i = 0; mce_device_attrs[i]; i++) |
2267 | device_remove_file(dev, mce_device_attrs[i]); | |
cb491fca | 2268 | |
d203f0b8 | 2269 | for (i = 0; i < mca_cfg.banks; i++) |
8a25a2fd | 2270 | device_remove_file(dev, &mce_banks[i].attr); |
cb491fca | 2271 | |
8a25a2fd KS |
2272 | device_unregister(dev); |
2273 | cpumask_clear_cpu(cpu, mce_device_initialized); | |
d6126ef5 | 2274 | per_cpu(mce_device, cpu) = NULL; |
91c6d400 | 2275 | } |
91c6d400 | 2276 | |
d6b75584 | 2277 | /* Make sure there are no machine checks on offlined CPUs. */ |
39f152ff | 2278 | static void mce_disable_cpu(void) |
d6b75584 | 2279 | { |
89cbc767 | 2280 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
d6b75584 | 2281 | return; |
767df1bd | 2282 | |
39f152ff | 2283 | if (!cpuhp_tasks_frozen) |
88ccbedd | 2284 | cmci_clear(); |
11868a2d | 2285 | |
6e06780a | 2286 | vendor_disable_error_reporting(); |
d6b75584 AK |
2287 | } |
2288 | ||
39f152ff | 2289 | static void mce_reenable_cpu(void) |
d6b75584 | 2290 | { |
e9eee03e | 2291 | int i; |
d6b75584 | 2292 | |
89cbc767 | 2293 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
d6b75584 | 2294 | return; |
e9eee03e | 2295 | |
39f152ff | 2296 | if (!cpuhp_tasks_frozen) |
88ccbedd | 2297 | cmci_reenable(); |
d203f0b8 | 2298 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2299 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2300 | |
cebe1820 | 2301 | if (b->init) |
d9d73fcc | 2302 | wrmsrl(msr_ops.ctl(i), b->ctl); |
06b7a7a5 | 2303 | } |
d6b75584 AK |
2304 | } |
2305 | ||
0e285d36 | 2306 | static int mce_cpu_dead(unsigned int cpu) |
91c6d400 | 2307 | { |
0e285d36 | 2308 | mce_intel_hcpu_update(cpu); |
91c6d400 | 2309 | |
0e285d36 SAS |
2310 | /* intentionally ignoring frozen here */ |
2311 | if (!cpuhp_tasks_frozen) | |
2312 | cmci_rediscover(); | |
2313 | return 0; | |
91c6d400 AK |
2314 | } |
2315 | ||
8c0eeac8 | 2316 | static int mce_cpu_online(unsigned int cpu) |
91c6d400 | 2317 | { |
0becc0ae | 2318 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
8c0eeac8 | 2319 | int ret; |
91c6d400 | 2320 | |
8c0eeac8 | 2321 | mce_device_create(cpu); |
38356c1f | 2322 | |
8c0eeac8 SAS |
2323 | ret = mce_threshold_create_device(cpu); |
2324 | if (ret) { | |
2325 | mce_device_remove(cpu); | |
2326 | return ret; | |
1a65f970 | 2327 | } |
8c0eeac8 | 2328 | mce_reenable_cpu(); |
0becc0ae | 2329 | mce_start_timer(t); |
8c0eeac8 | 2330 | return 0; |
91c6d400 AK |
2331 | } |
2332 | ||
8c0eeac8 SAS |
2333 | static int mce_cpu_pre_down(unsigned int cpu) |
2334 | { | |
0becc0ae | 2335 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
8c0eeac8 SAS |
2336 | |
2337 | mce_disable_cpu(); | |
2338 | del_timer_sync(t); | |
2339 | mce_threshold_remove_device(cpu); | |
2340 | mce_device_remove(cpu); | |
2341 | return 0; | |
2342 | } | |
91c6d400 | 2343 | |
cebe1820 | 2344 | static __init void mce_init_banks(void) |
0d7482e3 AK |
2345 | { |
2346 | int i; | |
2347 | ||
d203f0b8 | 2348 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2349 | struct mce_bank *b = &mce_banks[i]; |
8a25a2fd | 2350 | struct device_attribute *a = &b->attr; |
e9eee03e | 2351 | |
a07e4156 | 2352 | sysfs_attr_init(&a->attr); |
cebe1820 AK |
2353 | a->attr.name = b->attrname; |
2354 | snprintf(b->attrname, ATTR_LEN, "bank%d", i); | |
e9eee03e IM |
2355 | |
2356 | a->attr.mode = 0644; | |
2357 | a->show = show_bank; | |
2358 | a->store = set_bank; | |
0d7482e3 | 2359 | } |
0d7482e3 AK |
2360 | } |
2361 | ||
5e09954a | 2362 | static __init int mcheck_init_device(void) |
91c6d400 AK |
2363 | { |
2364 | int err; | |
91c6d400 | 2365 | |
c65e774f KS |
2366 | /* |
2367 | * Check if we have a spare virtual bit. This will only become | |
2368 | * a problem if/when we move beyond 5-level page tables. | |
2369 | */ | |
2370 | MAYBE_BUILD_BUG_ON(__VIRTUAL_MASK_SHIFT >= 63); | |
2371 | ||
9c15a24b MS |
2372 | if (!mce_available(&boot_cpu_data)) { |
2373 | err = -EIO; | |
2374 | goto err_out; | |
2375 | } | |
0d7482e3 | 2376 | |
9c15a24b MS |
2377 | if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) { |
2378 | err = -ENOMEM; | |
2379 | goto err_out; | |
2380 | } | |
996867d0 | 2381 | |
cebe1820 | 2382 | mce_init_banks(); |
0d7482e3 | 2383 | |
8a25a2fd | 2384 | err = subsys_system_register(&mce_subsys, NULL); |
d435d862 | 2385 | if (err) |
9c15a24b | 2386 | goto err_out_mem; |
91c6d400 | 2387 | |
0e285d36 SAS |
2388 | err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL, |
2389 | mce_cpu_dead); | |
2390 | if (err) | |
2391 | goto err_out_mem; | |
91c6d400 | 2392 | |
8c0eeac8 SAS |
2393 | err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online", |
2394 | mce_cpu_online, mce_cpu_pre_down); | |
2395 | if (err < 0) | |
0e285d36 | 2396 | goto err_out_online; |
93b62c3c | 2397 | |
9c15a24b MS |
2398 | register_syscore_ops(&mce_syscore_ops); |
2399 | ||
9c15a24b MS |
2400 | return 0; |
2401 | ||
0e285d36 SAS |
2402 | err_out_online: |
2403 | cpuhp_remove_state(CPUHP_X86_MCE_DEAD); | |
9c15a24b MS |
2404 | |
2405 | err_out_mem: | |
2406 | free_cpumask_var(mce_device_initialized); | |
2407 | ||
2408 | err_out: | |
5de97c9f | 2409 | pr_err("Unable to init MCE device (rc: %d)\n", err); |
e9eee03e | 2410 | |
1da177e4 | 2411 | return err; |
1da177e4 | 2412 | } |
cef12ee5 | 2413 | device_initcall_sync(mcheck_init_device); |
a988d334 | 2414 | |
d7c3c9a6 AK |
2415 | /* |
2416 | * Old style boot options parsing. Only for compatibility. | |
2417 | */ | |
2418 | static int __init mcheck_disable(char *str) | |
2419 | { | |
09933946 | 2420 | mca_cfg.disabled = 1; |
d7c3c9a6 AK |
2421 | return 1; |
2422 | } | |
2423 | __setup("nomce", mcheck_disable); | |
a988d334 | 2424 | |
5be9ed25 HY |
2425 | #ifdef CONFIG_DEBUG_FS |
2426 | struct dentry *mce_get_debugfs_dir(void) | |
a988d334 | 2427 | { |
5be9ed25 | 2428 | static struct dentry *dmce; |
a988d334 | 2429 | |
5be9ed25 HY |
2430 | if (!dmce) |
2431 | dmce = debugfs_create_dir("mce", NULL); | |
a988d334 | 2432 | |
5be9ed25 HY |
2433 | return dmce; |
2434 | } | |
a988d334 | 2435 | |
bf783f9f HY |
2436 | static void mce_reset(void) |
2437 | { | |
2438 | cpu_missing = 0; | |
c7c9b392 | 2439 | atomic_set(&mce_fake_panicked, 0); |
bf783f9f HY |
2440 | atomic_set(&mce_executing, 0); |
2441 | atomic_set(&mce_callin, 0); | |
2442 | atomic_set(&global_nwo, 0); | |
2443 | } | |
a988d334 | 2444 | |
bf783f9f HY |
2445 | static int fake_panic_get(void *data, u64 *val) |
2446 | { | |
2447 | *val = fake_panic; | |
2448 | return 0; | |
a988d334 IM |
2449 | } |
2450 | ||
bf783f9f | 2451 | static int fake_panic_set(void *data, u64 val) |
a988d334 | 2452 | { |
bf783f9f HY |
2453 | mce_reset(); |
2454 | fake_panic = val; | |
2455 | return 0; | |
a988d334 | 2456 | } |
a988d334 | 2457 | |
bf783f9f HY |
2458 | DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get, |
2459 | fake_panic_set, "%llu\n"); | |
d7c3c9a6 | 2460 | |
5e09954a | 2461 | static int __init mcheck_debugfs_init(void) |
d7c3c9a6 | 2462 | { |
bf783f9f HY |
2463 | struct dentry *dmce, *ffake_panic; |
2464 | ||
2465 | dmce = mce_get_debugfs_dir(); | |
2466 | if (!dmce) | |
2467 | return -ENOMEM; | |
2468 | ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL, | |
2469 | &fake_panic_fops); | |
2470 | if (!ffake_panic) | |
2471 | return -ENOMEM; | |
2472 | ||
2473 | return 0; | |
d7c3c9a6 | 2474 | } |
fd4cf79f CG |
2475 | #else |
2476 | static int __init mcheck_debugfs_init(void) { return -EINVAL; } | |
5be9ed25 | 2477 | #endif |
fd4cf79f | 2478 | |
3637efb0 TL |
2479 | DEFINE_STATIC_KEY_FALSE(mcsafe_key); |
2480 | EXPORT_SYMBOL_GPL(mcsafe_key); | |
2481 | ||
fd4cf79f CG |
2482 | static int __init mcheck_late_init(void) |
2483 | { | |
3637efb0 TL |
2484 | if (mca_cfg.recovery) |
2485 | static_branch_inc(&mcsafe_key); | |
2486 | ||
fd4cf79f | 2487 | mcheck_debugfs_init(); |
011d8261 | 2488 | cec_init(); |
fd4cf79f CG |
2489 | |
2490 | /* | |
2491 | * Flush out everything that has been logged during early boot, now that | |
2492 | * everything has been initialized (workqueues, decoders, ...). | |
2493 | */ | |
2494 | mce_schedule_work(); | |
2495 | ||
2496 | return 0; | |
2497 | } | |
2498 | late_initcall(mcheck_late_init); |