[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kernel / cpu / mcheck / mce-internal.h

#include <linux/device.h>
#include <asm/mce.h>

enum severity_level {
	MCE_NO_SEVERITY,
	MCE_DEFERRED_SEVERITY,
	MCE_UCNA_SEVERITY = MCE_DEFERRED_SEVERITY,
	MCE_KEEP_SEVERITY,
	MCE_SOME_SEVERITY,
	MCE_AO_SEVERITY,
	MCE_UC_SEVERITY,
	MCE_AR_SEVERITY,
	MCE_PANIC_SEVERITY,
};

extern struct blocking_notifier_head x86_mce_decoder_chain;

#define ATTR_LEN		16
#define INITIAL_CHECK_INTERVAL	5 * 60 /* 5 minutes */

/* One object for each MCE bank, shared by all CPUs */
struct mce_bank {
	u64			ctl;			/* subevents to enable */
	unsigned char init;				/* initialise bank? */
	struct device_attribute attr;			/* device attribute */
	char			attrname[ATTR_LEN];	/* attribute name */
};

struct mce_evt_llist {
	struct llist_node llnode;
	struct mce mce;
};

void mce_gen_pool_process(struct work_struct *__unused);
bool mce_gen_pool_empty(void);
int mce_gen_pool_add(struct mce *mce);
int mce_gen_pool_init(void);
struct llist_node *mce_gen_pool_prepare_records(void);

extern int (*mce_severity)(struct mce *a, int tolerant, char **msg, bool is_excp);
struct dentry *mce_get_debugfs_dir(void);

extern struct mce_bank *mce_banks;
extern mce_banks_t mce_banks_ce_disabled;

#ifdef CONFIG_X86_MCE_INTEL
unsigned long cmci_intel_adjust_timer(unsigned long interval);
bool mce_intel_cmci_poll(void);
void mce_intel_hcpu_update(unsigned long cpu);
void cmci_disable_bank(int bank);
#else
# define cmci_intel_adjust_timer mce_adjust_timer_default
static inline bool mce_intel_cmci_poll(void) { return false; }
static inline void mce_intel_hcpu_update(unsigned long cpu) { }
static inline void cmci_disable_bank(int bank) { }
#endif

void mce_timer_kick(unsigned long interval);

#ifdef CONFIG_ACPI_APEI
int apei_write_mce(struct mce *m);
ssize_t apei_read_mce(struct mce *m, u64 *record_id);
int apei_check_mce(void);
int apei_clear_mce(u64 record_id);
#else
static inline int apei_write_mce(struct mce *m)
{
	return -EINVAL;
}
static inline ssize_t apei_read_mce(struct mce *m, u64 *record_id)
{
	return 0;
}
static inline int apei_check_mce(void)
{
	return 0;
}
static inline int apei_clear_mce(u64 record_id)
{
	return -EINVAL;
}
#endif

void mce_inject_log(struct mce *m);

/*
 * We consider records to be equivalent if bank+status+addr+misc all match.
 * This is only used when the system is going down because of a fatal error
 * to avoid cluttering the console log with essentially repeated information.
 * In normal processing all errors seen are logged.
 */
static inline bool mce_cmp(struct mce *m1, struct mce *m2)
{
	return m1->bank != m2->bank ||
		m1->status != m2->status ||
		m1->addr != m2->addr ||
		m1->misc != m2->misc;
}
Commit	Line	Data
8a25a2fd	1	#include <linux/device.h>
817f32d0 AK	2	#include <asm/mce.h>
	3
	4	enum severity_level {
	5	MCE_NO_SEVERITY,
e3480271 CY	6	MCE_DEFERRED_SEVERITY,
e3480271 CY	7	MCE_UCNA_SEVERITY = MCE_DEFERRED_SEVERITY,
ed7290d0	8	MCE_KEEP_SEVERITY,
817f32d0	9	MCE_SOME_SEVERITY,
ed7290d0	10	MCE_AO_SEVERITY,
817f32d0	11	MCE_UC_SEVERITY,
ed7290d0	12	MCE_AR_SEVERITY,
817f32d0 AK	13	MCE_PANIC_SEVERITY,
	14	};
	15
0dc9c639	16	extern struct blocking_notifier_head x86_mce_decoder_chain;
648ed940	17
cebe1820	18	#define ATTR_LEN 16
3f2f0680	19	#define INITIAL_CHECK_INTERVAL 5 * 60 /* 5 minutes */
cebe1820 AK	20
	21	/* One object for each MCE bank, shared by all CPUs */
	22	struct mce_bank {
	23	u64 ctl; /* subevents to enable */
	24	unsigned char init; /* initialise bank? */
8a25a2fd	25	struct device_attribute attr; /* device attribute */
cebe1820 AK	26	char attrname[ATTR_LEN]; /* attribute name */
	27	};
	28
648ed940 CG	29	struct mce_evt_llist {
	30	struct llist_node llnode;
	31	struct mce mce;
	32	};
	33
cff4c039	34	void mce_gen_pool_process(struct work_struct *__unused);
648ed940 CG	35	bool mce_gen_pool_empty(void);
	36	int mce_gen_pool_add(struct mce *mce);
	37	int mce_gen_pool_init(void);
5541c93c	38	struct llist_node *mce_gen_pool_prepare_records(void);
648ed940	39
43eaa2a1	40	extern int (mce_severity)(struct mce a, int tolerant, char **msg, bool is_excp);
5be9ed25	41	struct dentry *mce_get_debugfs_dir(void);
ed7290d0	42
cebe1820	43	extern struct mce_bank *mce_banks;
c3d1fb56	44	extern mce_banks_t mce_banks_ce_disabled;
cebe1820	45
55babd8f	46	#ifdef CONFIG_X86_MCE_INTEL
3f2f0680 BP	47	unsigned long cmci_intel_adjust_timer(unsigned long interval);
3f2f0680 BP	48	bool mce_intel_cmci_poll(void);
55babd8f	49	void mce_intel_hcpu_update(unsigned long cpu);
c3d1fb56	50	void cmci_disable_bank(int bank);
55babd8f	51	#else
3f2f0680 BP	52	# define cmci_intel_adjust_timer mce_adjust_timer_default
3f2f0680 BP	53	static inline bool mce_intel_cmci_poll(void) { return false; }
55babd8f	54	static inline void mce_intel_hcpu_update(unsigned long cpu) { }
c3d1fb56	55	static inline void cmci_disable_bank(int bank) { }
55babd8f CG	56	#endif
	57
	58	void mce_timer_kick(unsigned long interval);
	59
482908b4 HY	60	#ifdef CONFIG_ACPI_APEI
	61	int apei_write_mce(struct mce *m);
	62	ssize_t apei_read_mce(struct mce m, u64 record_id);
	63	int apei_check_mce(void);
	64	int apei_clear_mce(u64 record_id);
	65	#else
	66	static inline int apei_write_mce(struct mce *m)
	67	{
	68	return -EINVAL;
	69	}
	70	static inline ssize_t apei_read_mce(struct mce m, u64 record_id)
	71	{
	72	return 0;
	73	}
	74	static inline int apei_check_mce(void)
	75	{
	76	return 0;
	77	}
	78	static inline int apei_clear_mce(u64 record_id)
	79	{
	80	return -EINVAL;
	81	}
	82	#endif
a79da384 BP	83
a79da384 BP	84	void mce_inject_log(struct mce *m);
5541c93c TL	85
	86	/*
	87	* We consider records to be equivalent if bank+status+addr+misc all match.
	88	* This is only used when the system is going down because of a fatal error
	89	* to avoid cluttering the console log with essentially repeated information.
	90	* In normal processing all errors seen are logged.
	91	*/
	92	static inline bool mce_cmp(struct mce m1, struct mce m2)
	93	{
	94	return m1->bank != m2->bank \|\|
	95	m1->status != m2->status \|\|
	96	m1->addr != m2->addr \|\|
	97	m1->misc != m2->misc;
	98	}