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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
c767a54b JP |
10 | |
11 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
12 | ||
e9eee03e IM |
13 | #include <linux/thread_info.h> |
14 | #include <linux/capability.h> | |
15 | #include <linux/miscdevice.h> | |
16 | #include <linux/ratelimit.h> | |
17 | #include <linux/kallsyms.h> | |
18 | #include <linux/rcupdate.h> | |
e9eee03e | 19 | #include <linux/kobject.h> |
14a02530 | 20 | #include <linux/uaccess.h> |
e9eee03e IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/kernel.h> | |
23 | #include <linux/percpu.h> | |
1da177e4 | 24 | #include <linux/string.h> |
8a25a2fd | 25 | #include <linux/device.h> |
f3c6ea1b | 26 | #include <linux/syscore_ops.h> |
3c079792 | 27 | #include <linux/delay.h> |
8c566ef5 | 28 | #include <linux/ctype.h> |
e9eee03e | 29 | #include <linux/sched.h> |
0d7482e3 | 30 | #include <linux/sysfs.h> |
e9eee03e | 31 | #include <linux/types.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
e9eee03e IM |
33 | #include <linux/init.h> |
34 | #include <linux/kmod.h> | |
35 | #include <linux/poll.h> | |
3c079792 | 36 | #include <linux/nmi.h> |
e9eee03e | 37 | #include <linux/cpu.h> |
14a02530 | 38 | #include <linux/smp.h> |
e9eee03e | 39 | #include <linux/fs.h> |
9b1beaf2 | 40 | #include <linux/mm.h> |
5be9ed25 | 41 | #include <linux/debugfs.h> |
b77e70bf | 42 | #include <linux/irq_work.h> |
69c60c88 | 43 | #include <linux/export.h> |
e9eee03e | 44 | |
d88203d1 | 45 | #include <asm/processor.h> |
95927475 | 46 | #include <asm/traps.h> |
375074cc | 47 | #include <asm/tlbflush.h> |
e9eee03e IM |
48 | #include <asm/mce.h> |
49 | #include <asm/msr.h> | |
1da177e4 | 50 | |
bd19a5e6 | 51 | #include "mce-internal.h" |
711c2e48 | 52 | |
93b62c3c | 53 | static DEFINE_MUTEX(mce_chrdev_read_mutex); |
2aa2b50d | 54 | |
f56e8a07 | 55 | #define rcu_dereference_check_mce(p) \ |
e90328b8 PM |
56 | ({ \ |
57 | rcu_lockdep_assert(rcu_read_lock_sched_held() || \ | |
58 | lockdep_is_held(&mce_chrdev_read_mutex), \ | |
59 | "suspicious rcu_dereference_check_mce() usage"); \ | |
60 | smp_load_acquire(&(p)); \ | |
61 | }) | |
f56e8a07 | 62 | |
8968f9d3 HS |
63 | #define CREATE_TRACE_POINTS |
64 | #include <trace/events/mce.h> | |
65 | ||
3f2f0680 | 66 | #define SPINUNIT 100 /* 100ns */ |
3c079792 | 67 | |
01ca79f1 AK |
68 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
69 | ||
1462594b | 70 | struct mce_bank *mce_banks __read_mostly; |
bf80bbd7 | 71 | struct mce_vendor_flags mce_flags __read_mostly; |
cebe1820 | 72 | |
d203f0b8 | 73 | struct mca_config mca_cfg __read_mostly = { |
84c2559d | 74 | .bootlog = -1, |
d203f0b8 BP |
75 | /* |
76 | * Tolerant levels: | |
77 | * 0: always panic on uncorrected errors, log corrected errors | |
78 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
79 | * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors | |
80 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
81 | */ | |
84c2559d BP |
82 | .tolerant = 1, |
83 | .monarch_timeout = -1 | |
d203f0b8 BP |
84 | }; |
85 | ||
1020bcbc HS |
86 | /* User mode helper program triggered by machine check event */ |
87 | static unsigned long mce_need_notify; | |
88 | static char mce_helper[128]; | |
89 | static char *mce_helper_argv[2] = { mce_helper, NULL }; | |
1da177e4 | 90 | |
93b62c3c HS |
91 | static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait); |
92 | ||
3c079792 AK |
93 | static DEFINE_PER_CPU(struct mce, mces_seen); |
94 | static int cpu_missing; | |
95 | ||
0644414e NR |
96 | /* |
97 | * MCA banks polled by the period polling timer for corrected events. | |
98 | * With Intel CMCI, this only has MCA banks which do not support CMCI (if any). | |
99 | */ | |
ee031c31 AK |
100 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { |
101 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
102 | }; | |
103 | ||
c3d1fb56 NR |
104 | /* |
105 | * MCA banks controlled through firmware first for corrected errors. | |
106 | * This is a global list of banks for which we won't enable CMCI and we | |
107 | * won't poll. Firmware controls these banks and is responsible for | |
108 | * reporting corrected errors through GHES. Uncorrected/recoverable | |
109 | * errors are still notified through a machine check. | |
110 | */ | |
111 | mce_banks_t mce_banks_ce_disabled; | |
112 | ||
061120ae CG |
113 | static struct work_struct mce_work; |
114 | static struct irq_work mce_irq_work; | |
9b1beaf2 | 115 | |
61b0fccd TL |
116 | static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs); |
117 | ||
3653ada5 BP |
118 | /* |
119 | * CPU/chipset specific EDAC code can register a notifier call here to print | |
120 | * MCE errors in a human-readable form. | |
121 | */ | |
648ed940 | 122 | ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain); |
3653ada5 | 123 | |
b5f2fa4e AK |
124 | /* Do initial initialization of a struct mce */ |
125 | void mce_setup(struct mce *m) | |
126 | { | |
127 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 128 | m->cpu = m->extcpu = smp_processor_id(); |
b5f2fa4e | 129 | rdtscll(m->tsc); |
8ee08347 AK |
130 | /* We hope get_seconds stays lockless */ |
131 | m->time = get_seconds(); | |
132 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
133 | m->cpuid = cpuid_eax(1); | |
8ee08347 | 134 | m->socketid = cpu_data(m->extcpu).phys_proc_id; |
8ee08347 AK |
135 | m->apicid = cpu_data(m->extcpu).initial_apicid; |
136 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
b5f2fa4e AK |
137 | } |
138 | ||
ea149b36 AK |
139 | DEFINE_PER_CPU(struct mce, injectm); |
140 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
141 | ||
1da177e4 LT |
142 | /* |
143 | * Lockless MCE logging infrastructure. | |
144 | * This avoids deadlocks on printk locks without having to break locks. Also | |
145 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
146 | */ | |
147 | ||
231fd906 | 148 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
149 | .signature = MCE_LOG_SIGNATURE, |
150 | .len = MCE_LOG_LEN, | |
151 | .recordlen = sizeof(struct mce), | |
d88203d1 | 152 | }; |
1da177e4 LT |
153 | |
154 | void mce_log(struct mce *mce) | |
155 | { | |
156 | unsigned next, entry; | |
e9eee03e | 157 | |
8968f9d3 HS |
158 | /* Emit the trace record: */ |
159 | trace_mce_record(mce); | |
160 | ||
a2413d8b | 161 | atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, mce); |
f0cb5452 | 162 | |
1da177e4 | 163 | mce->finished = 0; |
7644143c | 164 | wmb(); |
1da177e4 | 165 | for (;;) { |
f56e8a07 | 166 | entry = rcu_dereference_check_mce(mcelog.next); |
673242c1 | 167 | for (;;) { |
696e409d | 168 | |
e9eee03e IM |
169 | /* |
170 | * When the buffer fills up discard new entries. | |
171 | * Assume that the earlier errors are the more | |
172 | * interesting ones: | |
173 | */ | |
673242c1 | 174 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
175 | set_bit(MCE_OVERFLOW, |
176 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
177 | return; |
178 | } | |
e9eee03e | 179 | /* Old left over entry. Skip: */ |
673242c1 AK |
180 | if (mcelog.entry[entry].finished) { |
181 | entry++; | |
182 | continue; | |
183 | } | |
7644143c | 184 | break; |
1da177e4 | 185 | } |
1da177e4 LT |
186 | smp_rmb(); |
187 | next = entry + 1; | |
188 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
189 | break; | |
190 | } | |
191 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 192 | wmb(); |
1da177e4 | 193 | mcelog.entry[entry].finished = 1; |
7644143c | 194 | wmb(); |
1da177e4 | 195 | |
a0189c70 | 196 | mce->finished = 1; |
1020bcbc | 197 | set_bit(0, &mce_need_notify); |
1da177e4 LT |
198 | } |
199 | ||
09371957 BP |
200 | static void drain_mcelog_buffer(void) |
201 | { | |
202 | unsigned int next, i, prev = 0; | |
203 | ||
b11e3d78 | 204 | next = ACCESS_ONCE(mcelog.next); |
09371957 BP |
205 | |
206 | do { | |
207 | struct mce *m; | |
208 | ||
209 | /* drain what was logged during boot */ | |
210 | for (i = prev; i < next; i++) { | |
211 | unsigned long start = jiffies; | |
212 | unsigned retries = 1; | |
213 | ||
214 | m = &mcelog.entry[i]; | |
215 | ||
216 | while (!m->finished) { | |
217 | if (time_after_eq(jiffies, start + 2*retries)) | |
218 | retries++; | |
219 | ||
220 | cpu_relax(); | |
221 | ||
222 | if (!m->finished && retries >= 4) { | |
c767a54b | 223 | pr_err("skipping error being logged currently!\n"); |
09371957 BP |
224 | break; |
225 | } | |
226 | } | |
227 | smp_rmb(); | |
228 | atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); | |
229 | } | |
230 | ||
231 | memset(mcelog.entry + prev, 0, (next - prev) * sizeof(*m)); | |
232 | prev = next; | |
233 | next = cmpxchg(&mcelog.next, prev, 0); | |
234 | } while (next != prev); | |
235 | } | |
236 | ||
237 | ||
3653ada5 BP |
238 | void mce_register_decode_chain(struct notifier_block *nb) |
239 | { | |
240 | atomic_notifier_chain_register(&x86_mce_decoder_chain, nb); | |
09371957 | 241 | drain_mcelog_buffer(); |
3653ada5 BP |
242 | } |
243 | EXPORT_SYMBOL_GPL(mce_register_decode_chain); | |
244 | ||
245 | void mce_unregister_decode_chain(struct notifier_block *nb) | |
246 | { | |
247 | atomic_notifier_chain_unregister(&x86_mce_decoder_chain, nb); | |
248 | } | |
249 | EXPORT_SYMBOL_GPL(mce_unregister_decode_chain); | |
250 | ||
77e26cca | 251 | static void print_mce(struct mce *m) |
1da177e4 | 252 | { |
dffa4b2f BP |
253 | int ret = 0; |
254 | ||
a2d7b0d4 | 255 | pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n", |
d620c67f | 256 | m->extcpu, m->mcgstatus, m->bank, m->status); |
f436f8bb | 257 | |
65ea5b03 | 258 | if (m->ip) { |
a2d7b0d4 | 259 | pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", |
f436f8bb IM |
260 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
261 | m->cs, m->ip); | |
262 | ||
1da177e4 | 263 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 264 | print_symbol("{%s}", m->ip); |
f436f8bb | 265 | pr_cont("\n"); |
1da177e4 | 266 | } |
f436f8bb | 267 | |
a2d7b0d4 | 268 | pr_emerg(HW_ERR "TSC %llx ", m->tsc); |
1da177e4 | 269 | if (m->addr) |
f436f8bb | 270 | pr_cont("ADDR %llx ", m->addr); |
1da177e4 | 271 | if (m->misc) |
f436f8bb | 272 | pr_cont("MISC %llx ", m->misc); |
549d042d | 273 | |
f436f8bb | 274 | pr_cont("\n"); |
506ed6b5 AK |
275 | /* |
276 | * Note this output is parsed by external tools and old fields | |
277 | * should not be changed. | |
278 | */ | |
881e23e5 | 279 | pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n", |
506ed6b5 AK |
280 | m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, |
281 | cpu_data(m->extcpu).microcode); | |
f436f8bb IM |
282 | |
283 | /* | |
284 | * Print out human-readable details about the MCE error, | |
fb253195 | 285 | * (if the CPU has an implementation for that) |
f436f8bb | 286 | */ |
dffa4b2f BP |
287 | ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); |
288 | if (ret == NOTIFY_STOP) | |
289 | return; | |
290 | ||
291 | pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); | |
86503560 AK |
292 | } |
293 | ||
f94b61c2 AK |
294 | #define PANIC_TIMEOUT 5 /* 5 seconds */ |
295 | ||
c7c9b392 | 296 | static atomic_t mce_panicked; |
f94b61c2 | 297 | |
bf783f9f | 298 | static int fake_panic; |
c7c9b392 | 299 | static atomic_t mce_fake_panicked; |
bf783f9f | 300 | |
f94b61c2 AK |
301 | /* Panic in progress. Enable interrupts and wait for final IPI */ |
302 | static void wait_for_panic(void) | |
303 | { | |
304 | long timeout = PANIC_TIMEOUT*USEC_PER_SEC; | |
f436f8bb | 305 | |
f94b61c2 AK |
306 | preempt_disable(); |
307 | local_irq_enable(); | |
308 | while (timeout-- > 0) | |
309 | udelay(1); | |
29b0f591 | 310 | if (panic_timeout == 0) |
7af19e4a | 311 | panic_timeout = mca_cfg.panic_timeout; |
f94b61c2 AK |
312 | panic("Panicing machine check CPU died"); |
313 | } | |
314 | ||
6c80f87e | 315 | static void mce_panic(const char *msg, struct mce *final, char *exp) |
d88203d1 | 316 | { |
482908b4 | 317 | int i, apei_err = 0; |
e02e68d3 | 318 | |
bf783f9f HY |
319 | if (!fake_panic) { |
320 | /* | |
321 | * Make sure only one CPU runs in machine check panic | |
322 | */ | |
c7c9b392 | 323 | if (atomic_inc_return(&mce_panicked) > 1) |
bf783f9f HY |
324 | wait_for_panic(); |
325 | barrier(); | |
f94b61c2 | 326 | |
bf783f9f HY |
327 | bust_spinlocks(1); |
328 | console_verbose(); | |
329 | } else { | |
330 | /* Don't log too much for fake panic */ | |
c7c9b392 | 331 | if (atomic_inc_return(&mce_fake_panicked) > 1) |
bf783f9f HY |
332 | return; |
333 | } | |
a0189c70 | 334 | /* First print corrected ones that are still unlogged */ |
1da177e4 | 335 | for (i = 0; i < MCE_LOG_LEN; i++) { |
a0189c70 | 336 | struct mce *m = &mcelog.entry[i]; |
77e26cca HS |
337 | if (!(m->status & MCI_STATUS_VAL)) |
338 | continue; | |
482908b4 | 339 | if (!(m->status & MCI_STATUS_UC)) { |
77e26cca | 340 | print_mce(m); |
482908b4 HY |
341 | if (!apei_err) |
342 | apei_err = apei_write_mce(m); | |
343 | } | |
a0189c70 AK |
344 | } |
345 | /* Now print uncorrected but with the final one last */ | |
346 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
347 | struct mce *m = &mcelog.entry[i]; | |
348 | if (!(m->status & MCI_STATUS_VAL)) | |
1da177e4 | 349 | continue; |
77e26cca HS |
350 | if (!(m->status & MCI_STATUS_UC)) |
351 | continue; | |
482908b4 | 352 | if (!final || memcmp(m, final, sizeof(struct mce))) { |
77e26cca | 353 | print_mce(m); |
482908b4 HY |
354 | if (!apei_err) |
355 | apei_err = apei_write_mce(m); | |
356 | } | |
1da177e4 | 357 | } |
482908b4 | 358 | if (final) { |
77e26cca | 359 | print_mce(final); |
482908b4 HY |
360 | if (!apei_err) |
361 | apei_err = apei_write_mce(final); | |
362 | } | |
3c079792 | 363 | if (cpu_missing) |
a2d7b0d4 | 364 | pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n"); |
bd19a5e6 | 365 | if (exp) |
a2d7b0d4 | 366 | pr_emerg(HW_ERR "Machine check: %s\n", exp); |
bf783f9f HY |
367 | if (!fake_panic) { |
368 | if (panic_timeout == 0) | |
7af19e4a | 369 | panic_timeout = mca_cfg.panic_timeout; |
bf783f9f HY |
370 | panic(msg); |
371 | } else | |
a2d7b0d4 | 372 | pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); |
d88203d1 | 373 | } |
1da177e4 | 374 | |
ea149b36 AK |
375 | /* Support code for software error injection */ |
376 | ||
377 | static int msr_to_offset(u32 msr) | |
378 | { | |
0a3aee0d | 379 | unsigned bank = __this_cpu_read(injectm.bank); |
f436f8bb | 380 | |
84c2559d | 381 | if (msr == mca_cfg.rip_msr) |
ea149b36 | 382 | return offsetof(struct mce, ip); |
a2d32bcb | 383 | if (msr == MSR_IA32_MCx_STATUS(bank)) |
ea149b36 | 384 | return offsetof(struct mce, status); |
a2d32bcb | 385 | if (msr == MSR_IA32_MCx_ADDR(bank)) |
ea149b36 | 386 | return offsetof(struct mce, addr); |
a2d32bcb | 387 | if (msr == MSR_IA32_MCx_MISC(bank)) |
ea149b36 AK |
388 | return offsetof(struct mce, misc); |
389 | if (msr == MSR_IA32_MCG_STATUS) | |
390 | return offsetof(struct mce, mcgstatus); | |
391 | return -1; | |
392 | } | |
393 | ||
5f8c1a54 AK |
394 | /* MSR access wrappers used for error injection */ |
395 | static u64 mce_rdmsrl(u32 msr) | |
396 | { | |
397 | u64 v; | |
11868a2d | 398 | |
0a3aee0d | 399 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 400 | int offset = msr_to_offset(msr); |
11868a2d | 401 | |
ea149b36 AK |
402 | if (offset < 0) |
403 | return 0; | |
89cbc767 | 404 | return *(u64 *)((char *)this_cpu_ptr(&injectm) + offset); |
ea149b36 | 405 | } |
11868a2d IM |
406 | |
407 | if (rdmsrl_safe(msr, &v)) { | |
408 | WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr); | |
409 | /* | |
410 | * Return zero in case the access faulted. This should | |
411 | * not happen normally but can happen if the CPU does | |
412 | * something weird, or if the code is buggy. | |
413 | */ | |
414 | v = 0; | |
415 | } | |
416 | ||
5f8c1a54 AK |
417 | return v; |
418 | } | |
419 | ||
420 | static void mce_wrmsrl(u32 msr, u64 v) | |
421 | { | |
0a3aee0d | 422 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 423 | int offset = msr_to_offset(msr); |
11868a2d | 424 | |
ea149b36 | 425 | if (offset >= 0) |
89cbc767 | 426 | *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v; |
ea149b36 AK |
427 | return; |
428 | } | |
5f8c1a54 AK |
429 | wrmsrl(msr, v); |
430 | } | |
431 | ||
b8325c5b HS |
432 | /* |
433 | * Collect all global (w.r.t. this processor) status about this machine | |
434 | * check into our "mce" struct so that we can use it later to assess | |
435 | * the severity of the problem as we read per-bank specific details. | |
436 | */ | |
437 | static inline void mce_gather_info(struct mce *m, struct pt_regs *regs) | |
438 | { | |
439 | mce_setup(m); | |
440 | ||
441 | m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); | |
442 | if (regs) { | |
443 | /* | |
444 | * Get the address of the instruction at the time of | |
445 | * the machine check error. | |
446 | */ | |
447 | if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) { | |
448 | m->ip = regs->ip; | |
449 | m->cs = regs->cs; | |
a129a7c8 AK |
450 | |
451 | /* | |
452 | * When in VM86 mode make the cs look like ring 3 | |
453 | * always. This is a lie, but it's better than passing | |
454 | * the additional vm86 bit around everywhere. | |
455 | */ | |
456 | if (v8086_mode(regs)) | |
457 | m->cs |= 3; | |
b8325c5b HS |
458 | } |
459 | /* Use accurate RIP reporting if available. */ | |
84c2559d BP |
460 | if (mca_cfg.rip_msr) |
461 | m->ip = mce_rdmsrl(mca_cfg.rip_msr); | |
b8325c5b HS |
462 | } |
463 | } | |
464 | ||
9b1beaf2 AK |
465 | /* |
466 | * Simple lockless ring to communicate PFNs from the exception handler with the | |
467 | * process context work function. This is vastly simplified because there's | |
468 | * only a single reader and a single writer. | |
469 | */ | |
470 | #define MCE_RING_SIZE 16 /* we use one entry less */ | |
471 | ||
472 | struct mce_ring { | |
473 | unsigned short start; | |
474 | unsigned short end; | |
475 | unsigned long ring[MCE_RING_SIZE]; | |
476 | }; | |
477 | static DEFINE_PER_CPU(struct mce_ring, mce_ring); | |
478 | ||
479 | /* Runs with CPU affinity in workqueue */ | |
480 | static int mce_ring_empty(void) | |
481 | { | |
89cbc767 | 482 | struct mce_ring *r = this_cpu_ptr(&mce_ring); |
9b1beaf2 AK |
483 | |
484 | return r->start == r->end; | |
485 | } | |
486 | ||
487 | static int mce_ring_get(unsigned long *pfn) | |
488 | { | |
489 | struct mce_ring *r; | |
490 | int ret = 0; | |
491 | ||
492 | *pfn = 0; | |
493 | get_cpu(); | |
89cbc767 | 494 | r = this_cpu_ptr(&mce_ring); |
9b1beaf2 AK |
495 | if (r->start == r->end) |
496 | goto out; | |
497 | *pfn = r->ring[r->start]; | |
498 | r->start = (r->start + 1) % MCE_RING_SIZE; | |
499 | ret = 1; | |
500 | out: | |
501 | put_cpu(); | |
502 | return ret; | |
503 | } | |
504 | ||
505 | /* Always runs in MCE context with preempt off */ | |
506 | static int mce_ring_add(unsigned long pfn) | |
507 | { | |
89cbc767 | 508 | struct mce_ring *r = this_cpu_ptr(&mce_ring); |
9b1beaf2 AK |
509 | unsigned next; |
510 | ||
511 | next = (r->end + 1) % MCE_RING_SIZE; | |
512 | if (next == r->start) | |
513 | return -1; | |
514 | r->ring[r->end] = pfn; | |
515 | wmb(); | |
516 | r->end = next; | |
517 | return 0; | |
518 | } | |
519 | ||
88ccbedd | 520 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 521 | { |
1462594b | 522 | if (mca_cfg.disabled) |
5b4408fd | 523 | return 0; |
3d1712c9 | 524 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
525 | } |
526 | ||
9b1beaf2 AK |
527 | static void mce_schedule_work(void) |
528 | { | |
4d899be5 | 529 | if (!mce_ring_empty()) |
061120ae | 530 | schedule_work(&mce_work); |
9b1beaf2 AK |
531 | } |
532 | ||
b77e70bf | 533 | static void mce_irq_work_cb(struct irq_work *entry) |
ccc3c319 | 534 | { |
9ff36ee9 | 535 | mce_notify_irq(); |
9b1beaf2 | 536 | mce_schedule_work(); |
ccc3c319 | 537 | } |
ccc3c319 AK |
538 | |
539 | static void mce_report_event(struct pt_regs *regs) | |
540 | { | |
541 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { | |
9ff36ee9 | 542 | mce_notify_irq(); |
9b1beaf2 AK |
543 | /* |
544 | * Triggering the work queue here is just an insurance | |
545 | * policy in case the syscall exit notify handler | |
546 | * doesn't run soon enough or ends up running on the | |
547 | * wrong CPU (can happen when audit sleeps) | |
548 | */ | |
549 | mce_schedule_work(); | |
ccc3c319 AK |
550 | return; |
551 | } | |
552 | ||
061120ae | 553 | irq_work_queue(&mce_irq_work); |
ccc3c319 AK |
554 | } |
555 | ||
85f92694 TL |
556 | /* |
557 | * Read ADDR and MISC registers. | |
558 | */ | |
559 | static void mce_read_aux(struct mce *m, int i) | |
560 | { | |
561 | if (m->status & MCI_STATUS_MISCV) | |
562 | m->misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); | |
563 | if (m->status & MCI_STATUS_ADDRV) { | |
564 | m->addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); | |
565 | ||
566 | /* | |
567 | * Mask the reported address by the reported granularity. | |
568 | */ | |
1462594b | 569 | if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) { |
85f92694 TL |
570 | u8 shift = MCI_MISC_ADDR_LSB(m->misc); |
571 | m->addr >>= shift; | |
572 | m->addr <<= shift; | |
573 | } | |
574 | } | |
575 | } | |
576 | ||
fa92c586 CY |
577 | static bool memory_error(struct mce *m) |
578 | { | |
579 | struct cpuinfo_x86 *c = &boot_cpu_data; | |
580 | ||
581 | if (c->x86_vendor == X86_VENDOR_AMD) { | |
582 | /* | |
583 | * coming soon | |
584 | */ | |
585 | return false; | |
586 | } else if (c->x86_vendor == X86_VENDOR_INTEL) { | |
587 | /* | |
588 | * Intel SDM Volume 3B - 15.9.2 Compound Error Codes | |
589 | * | |
590 | * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for | |
591 | * indicating a memory error. Bit 8 is used for indicating a | |
592 | * cache hierarchy error. The combination of bit 2 and bit 3 | |
593 | * is used for indicating a `generic' cache hierarchy error | |
594 | * But we can't just blindly check the above bits, because if | |
595 | * bit 11 is set, then it is a bus/interconnect error - and | |
596 | * either way the above bits just gives more detail on what | |
597 | * bus/interconnect error happened. Note that bit 12 can be | |
598 | * ignored, as it's the "filter" bit. | |
599 | */ | |
600 | return (m->status & 0xef80) == BIT(7) || | |
601 | (m->status & 0xef00) == BIT(8) || | |
602 | (m->status & 0xeffc) == 0xc; | |
603 | } | |
604 | ||
605 | return false; | |
606 | } | |
607 | ||
ca84f696 AK |
608 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
609 | ||
d88203d1 | 610 | /* |
b79109c3 AK |
611 | * Poll for corrected events or events that happened before reset. |
612 | * Those are just logged through /dev/mcelog. | |
613 | * | |
614 | * This is executed in standard interrupt context. | |
ed7290d0 AK |
615 | * |
616 | * Note: spec recommends to panic for fatal unsignalled | |
617 | * errors here. However this would be quite problematic -- | |
618 | * we would need to reimplement the Monarch handling and | |
619 | * it would mess up the exclusion between exception handler | |
620 | * and poll hander -- * so we skip this for now. | |
621 | * These cases should not happen anyways, or only when the CPU | |
622 | * is already totally * confused. In this case it's likely it will | |
623 | * not fully execute the machine check handler either. | |
b79109c3 | 624 | */ |
3f2f0680 | 625 | bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 | 626 | { |
3f2f0680 | 627 | bool error_logged = false; |
b79109c3 | 628 | struct mce m; |
fa92c586 | 629 | int severity; |
b79109c3 AK |
630 | int i; |
631 | ||
c6ae41e7 | 632 | this_cpu_inc(mce_poll_count); |
ca84f696 | 633 | |
b8325c5b | 634 | mce_gather_info(&m, NULL); |
b79109c3 | 635 | |
d203f0b8 | 636 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 637 | if (!mce_banks[i].ctl || !test_bit(i, *b)) |
b79109c3 AK |
638 | continue; |
639 | ||
640 | m.misc = 0; | |
641 | m.addr = 0; | |
642 | m.bank = i; | |
643 | m.tsc = 0; | |
644 | ||
645 | barrier(); | |
a2d32bcb | 646 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
b79109c3 AK |
647 | if (!(m.status & MCI_STATUS_VAL)) |
648 | continue; | |
649 | ||
3f2f0680 | 650 | |
b79109c3 | 651 | /* |
ed7290d0 AK |
652 | * Uncorrected or signalled events are handled by the exception |
653 | * handler when it is enabled, so don't process those here. | |
b79109c3 AK |
654 | * |
655 | * TBD do the same check for MCI_STATUS_EN here? | |
656 | */ | |
ed7290d0 | 657 | if (!(flags & MCP_UC) && |
1462594b | 658 | (m.status & (mca_cfg.ser ? MCI_STATUS_S : MCI_STATUS_UC))) |
b79109c3 AK |
659 | continue; |
660 | ||
85f92694 | 661 | mce_read_aux(&m, i); |
b79109c3 AK |
662 | |
663 | if (!(flags & MCP_TIMESTAMP)) | |
664 | m.tsc = 0; | |
fa92c586 CY |
665 | |
666 | severity = mce_severity(&m, mca_cfg.tolerant, NULL, false); | |
667 | ||
668 | /* | |
669 | * In the cases where we don't have a valid address after all, | |
670 | * do not add it into the ring buffer. | |
671 | */ | |
672 | if (severity == MCE_DEFERRED_SEVERITY && memory_error(&m)) { | |
673 | if (m.status & MCI_STATUS_ADDRV) { | |
674 | mce_ring_add(m.addr >> PAGE_SHIFT); | |
675 | mce_schedule_work(); | |
676 | } | |
677 | } | |
678 | ||
b79109c3 AK |
679 | /* |
680 | * Don't get the IP here because it's unlikely to | |
681 | * have anything to do with the actual error location. | |
682 | */ | |
3f2f0680 BP |
683 | if (!(flags & MCP_DONTLOG) && !mca_cfg.dont_log_ce) { |
684 | error_logged = true; | |
5679af4c | 685 | mce_log(&m); |
3f2f0680 | 686 | } |
b79109c3 AK |
687 | |
688 | /* | |
689 | * Clear state for this bank. | |
690 | */ | |
a2d32bcb | 691 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
b79109c3 AK |
692 | } |
693 | ||
694 | /* | |
695 | * Don't clear MCG_STATUS here because it's only defined for | |
696 | * exceptions. | |
697 | */ | |
88921be3 AK |
698 | |
699 | sync_core(); | |
3f2f0680 BP |
700 | |
701 | return error_logged; | |
b79109c3 | 702 | } |
ea149b36 | 703 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 | 704 | |
bd19a5e6 AK |
705 | /* |
706 | * Do a quick check if any of the events requires a panic. | |
707 | * This decides if we keep the events around or clear them. | |
708 | */ | |
61b0fccd TL |
709 | static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp, |
710 | struct pt_regs *regs) | |
bd19a5e6 | 711 | { |
95022b8c | 712 | int i, ret = 0; |
17fea54b | 713 | char *tmp; |
bd19a5e6 | 714 | |
d203f0b8 | 715 | for (i = 0; i < mca_cfg.banks; i++) { |
a2d32bcb | 716 | m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
61b0fccd | 717 | if (m->status & MCI_STATUS_VAL) { |
95022b8c | 718 | __set_bit(i, validp); |
61b0fccd TL |
719 | if (quirk_no_way_out) |
720 | quirk_no_way_out(i, m, regs); | |
721 | } | |
17fea54b BP |
722 | |
723 | if (mce_severity(m, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) { | |
724 | *msg = tmp; | |
95022b8c | 725 | ret = 1; |
17fea54b | 726 | } |
bd19a5e6 | 727 | } |
95022b8c | 728 | return ret; |
bd19a5e6 AK |
729 | } |
730 | ||
3c079792 AK |
731 | /* |
732 | * Variable to establish order between CPUs while scanning. | |
733 | * Each CPU spins initially until executing is equal its number. | |
734 | */ | |
735 | static atomic_t mce_executing; | |
736 | ||
737 | /* | |
738 | * Defines order of CPUs on entry. First CPU becomes Monarch. | |
739 | */ | |
740 | static atomic_t mce_callin; | |
741 | ||
742 | /* | |
743 | * Check if a timeout waiting for other CPUs happened. | |
744 | */ | |
6c80f87e | 745 | static int mce_timed_out(u64 *t, const char *msg) |
3c079792 AK |
746 | { |
747 | /* | |
748 | * The others already did panic for some reason. | |
749 | * Bail out like in a timeout. | |
750 | * rmb() to tell the compiler that system_state | |
751 | * might have been modified by someone else. | |
752 | */ | |
753 | rmb(); | |
c7c9b392 | 754 | if (atomic_read(&mce_panicked)) |
3c079792 | 755 | wait_for_panic(); |
84c2559d | 756 | if (!mca_cfg.monarch_timeout) |
3c079792 AK |
757 | goto out; |
758 | if ((s64)*t < SPINUNIT) { | |
716079f6 | 759 | if (mca_cfg.tolerant <= 1) |
6c80f87e | 760 | mce_panic(msg, NULL, NULL); |
3c079792 AK |
761 | cpu_missing = 1; |
762 | return 1; | |
763 | } | |
764 | *t -= SPINUNIT; | |
765 | out: | |
766 | touch_nmi_watchdog(); | |
767 | return 0; | |
768 | } | |
769 | ||
770 | /* | |
771 | * The Monarch's reign. The Monarch is the CPU who entered | |
772 | * the machine check handler first. It waits for the others to | |
773 | * raise the exception too and then grades them. When any | |
774 | * error is fatal panic. Only then let the others continue. | |
775 | * | |
776 | * The other CPUs entering the MCE handler will be controlled by the | |
777 | * Monarch. They are called Subjects. | |
778 | * | |
779 | * This way we prevent any potential data corruption in a unrecoverable case | |
780 | * and also makes sure always all CPU's errors are examined. | |
781 | * | |
680b6cfd | 782 | * Also this detects the case of a machine check event coming from outer |
3c079792 AK |
783 | * space (not detected by any CPUs) In this case some external agent wants |
784 | * us to shut down, so panic too. | |
785 | * | |
786 | * The other CPUs might still decide to panic if the handler happens | |
787 | * in a unrecoverable place, but in this case the system is in a semi-stable | |
788 | * state and won't corrupt anything by itself. It's ok to let the others | |
789 | * continue for a bit first. | |
790 | * | |
791 | * All the spin loops have timeouts; when a timeout happens a CPU | |
792 | * typically elects itself to be Monarch. | |
793 | */ | |
794 | static void mce_reign(void) | |
795 | { | |
796 | int cpu; | |
797 | struct mce *m = NULL; | |
798 | int global_worst = 0; | |
799 | char *msg = NULL; | |
800 | char *nmsg = NULL; | |
801 | ||
802 | /* | |
803 | * This CPU is the Monarch and the other CPUs have run | |
804 | * through their handlers. | |
805 | * Grade the severity of the errors of all the CPUs. | |
806 | */ | |
807 | for_each_possible_cpu(cpu) { | |
d203f0b8 BP |
808 | int severity = mce_severity(&per_cpu(mces_seen, cpu), |
809 | mca_cfg.tolerant, | |
e3480271 | 810 | &nmsg, true); |
3c079792 AK |
811 | if (severity > global_worst) { |
812 | msg = nmsg; | |
813 | global_worst = severity; | |
814 | m = &per_cpu(mces_seen, cpu); | |
815 | } | |
816 | } | |
817 | ||
818 | /* | |
819 | * Cannot recover? Panic here then. | |
820 | * This dumps all the mces in the log buffer and stops the | |
821 | * other CPUs. | |
822 | */ | |
d203f0b8 | 823 | if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) |
8af7043a | 824 | mce_panic("Fatal machine check", m, msg); |
3c079792 AK |
825 | |
826 | /* | |
827 | * For UC somewhere we let the CPU who detects it handle it. | |
828 | * Also must let continue the others, otherwise the handling | |
829 | * CPU could deadlock on a lock. | |
830 | */ | |
831 | ||
832 | /* | |
833 | * No machine check event found. Must be some external | |
834 | * source or one CPU is hung. Panic. | |
835 | */ | |
d203f0b8 | 836 | if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3) |
8af7043a | 837 | mce_panic("Fatal machine check from unknown source", NULL, NULL); |
3c079792 AK |
838 | |
839 | /* | |
840 | * Now clear all the mces_seen so that they don't reappear on | |
841 | * the next mce. | |
842 | */ | |
843 | for_each_possible_cpu(cpu) | |
844 | memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); | |
845 | } | |
846 | ||
847 | static atomic_t global_nwo; | |
848 | ||
849 | /* | |
850 | * Start of Monarch synchronization. This waits until all CPUs have | |
851 | * entered the exception handler and then determines if any of them | |
852 | * saw a fatal event that requires panic. Then it executes them | |
853 | * in the entry order. | |
854 | * TBD double check parallel CPU hotunplug | |
855 | */ | |
7fb06fc9 | 856 | static int mce_start(int *no_way_out) |
3c079792 | 857 | { |
7fb06fc9 | 858 | int order; |
3c079792 | 859 | int cpus = num_online_cpus(); |
84c2559d | 860 | u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; |
3c079792 | 861 | |
7fb06fc9 HS |
862 | if (!timeout) |
863 | return -1; | |
3c079792 | 864 | |
7fb06fc9 | 865 | atomic_add(*no_way_out, &global_nwo); |
184e1fdf HY |
866 | /* |
867 | * global_nwo should be updated before mce_callin | |
868 | */ | |
869 | smp_wmb(); | |
a95436e4 | 870 | order = atomic_inc_return(&mce_callin); |
3c079792 AK |
871 | |
872 | /* | |
873 | * Wait for everyone. | |
874 | */ | |
875 | while (atomic_read(&mce_callin) != cpus) { | |
6c80f87e AL |
876 | if (mce_timed_out(&timeout, |
877 | "Timeout: Not all CPUs entered broadcast exception handler")) { | |
3c079792 | 878 | atomic_set(&global_nwo, 0); |
7fb06fc9 | 879 | return -1; |
3c079792 AK |
880 | } |
881 | ndelay(SPINUNIT); | |
882 | } | |
883 | ||
184e1fdf HY |
884 | /* |
885 | * mce_callin should be read before global_nwo | |
886 | */ | |
887 | smp_rmb(); | |
3c079792 | 888 | |
7fb06fc9 HS |
889 | if (order == 1) { |
890 | /* | |
891 | * Monarch: Starts executing now, the others wait. | |
892 | */ | |
3c079792 | 893 | atomic_set(&mce_executing, 1); |
7fb06fc9 HS |
894 | } else { |
895 | /* | |
896 | * Subject: Now start the scanning loop one by one in | |
897 | * the original callin order. | |
898 | * This way when there are any shared banks it will be | |
899 | * only seen by one CPU before cleared, avoiding duplicates. | |
900 | */ | |
901 | while (atomic_read(&mce_executing) < order) { | |
6c80f87e AL |
902 | if (mce_timed_out(&timeout, |
903 | "Timeout: Subject CPUs unable to finish machine check processing")) { | |
7fb06fc9 HS |
904 | atomic_set(&global_nwo, 0); |
905 | return -1; | |
906 | } | |
907 | ndelay(SPINUNIT); | |
908 | } | |
3c079792 AK |
909 | } |
910 | ||
911 | /* | |
7fb06fc9 | 912 | * Cache the global no_way_out state. |
3c079792 | 913 | */ |
7fb06fc9 HS |
914 | *no_way_out = atomic_read(&global_nwo); |
915 | ||
916 | return order; | |
3c079792 AK |
917 | } |
918 | ||
919 | /* | |
920 | * Synchronize between CPUs after main scanning loop. | |
921 | * This invokes the bulk of the Monarch processing. | |
922 | */ | |
923 | static int mce_end(int order) | |
924 | { | |
925 | int ret = -1; | |
84c2559d | 926 | u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; |
3c079792 AK |
927 | |
928 | if (!timeout) | |
929 | goto reset; | |
930 | if (order < 0) | |
931 | goto reset; | |
932 | ||
933 | /* | |
934 | * Allow others to run. | |
935 | */ | |
936 | atomic_inc(&mce_executing); | |
937 | ||
938 | if (order == 1) { | |
939 | /* CHECKME: Can this race with a parallel hotplug? */ | |
940 | int cpus = num_online_cpus(); | |
941 | ||
942 | /* | |
943 | * Monarch: Wait for everyone to go through their scanning | |
944 | * loops. | |
945 | */ | |
946 | while (atomic_read(&mce_executing) <= cpus) { | |
6c80f87e AL |
947 | if (mce_timed_out(&timeout, |
948 | "Timeout: Monarch CPU unable to finish machine check processing")) | |
3c079792 AK |
949 | goto reset; |
950 | ndelay(SPINUNIT); | |
951 | } | |
952 | ||
953 | mce_reign(); | |
954 | barrier(); | |
955 | ret = 0; | |
956 | } else { | |
957 | /* | |
958 | * Subject: Wait for Monarch to finish. | |
959 | */ | |
960 | while (atomic_read(&mce_executing) != 0) { | |
6c80f87e AL |
961 | if (mce_timed_out(&timeout, |
962 | "Timeout: Monarch CPU did not finish machine check processing")) | |
3c079792 AK |
963 | goto reset; |
964 | ndelay(SPINUNIT); | |
965 | } | |
966 | ||
967 | /* | |
968 | * Don't reset anything. That's done by the Monarch. | |
969 | */ | |
970 | return 0; | |
971 | } | |
972 | ||
973 | /* | |
974 | * Reset all global state. | |
975 | */ | |
976 | reset: | |
977 | atomic_set(&global_nwo, 0); | |
978 | atomic_set(&mce_callin, 0); | |
979 | barrier(); | |
980 | ||
981 | /* | |
982 | * Let others run again. | |
983 | */ | |
984 | atomic_set(&mce_executing, 0); | |
985 | return ret; | |
986 | } | |
987 | ||
9b1beaf2 AK |
988 | /* |
989 | * Check if the address reported by the CPU is in a format we can parse. | |
990 | * It would be possible to add code for most other cases, but all would | |
991 | * be somewhat complicated (e.g. segment offset would require an instruction | |
0d2eb44f | 992 | * parser). So only support physical addresses up to page granuality for now. |
9b1beaf2 AK |
993 | */ |
994 | static int mce_usable_address(struct mce *m) | |
995 | { | |
996 | if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) | |
997 | return 0; | |
2b90e77e | 998 | if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) |
9b1beaf2 | 999 | return 0; |
2b90e77e | 1000 | if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) |
9b1beaf2 AK |
1001 | return 0; |
1002 | return 1; | |
1003 | } | |
1004 | ||
3c079792 AK |
1005 | static void mce_clear_state(unsigned long *toclear) |
1006 | { | |
1007 | int i; | |
1008 | ||
d203f0b8 | 1009 | for (i = 0; i < mca_cfg.banks; i++) { |
3c079792 | 1010 | if (test_bit(i, toclear)) |
a2d32bcb | 1011 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
3c079792 AK |
1012 | } |
1013 | } | |
1014 | ||
b79109c3 AK |
1015 | /* |
1016 | * The actual machine check handler. This only handles real | |
1017 | * exceptions when something got corrupted coming in through int 18. | |
1018 | * | |
1019 | * This is executed in NMI context not subject to normal locking rules. This | |
1020 | * implies that most kernel services cannot be safely used. Don't even | |
1021 | * think about putting a printk in there! | |
3c079792 AK |
1022 | * |
1023 | * On Intel systems this is entered on all CPUs in parallel through | |
1024 | * MCE broadcast. However some CPUs might be broken beyond repair, | |
1025 | * so be always careful when synchronizing with others. | |
1da177e4 | 1026 | */ |
e9eee03e | 1027 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 | 1028 | { |
1462594b | 1029 | struct mca_config *cfg = &mca_cfg; |
3c079792 | 1030 | struct mce m, *final; |
95927475 | 1031 | enum ctx_state prev_state; |
1da177e4 | 1032 | int i; |
3c079792 AK |
1033 | int worst = 0; |
1034 | int severity; | |
1035 | /* | |
1036 | * Establish sequential order between the CPUs entering the machine | |
1037 | * check handler. | |
1038 | */ | |
7fb06fc9 | 1039 | int order; |
bd78432c TH |
1040 | /* |
1041 | * If no_way_out gets set, there is no safe way to recover from this | |
d203f0b8 | 1042 | * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway. |
bd78432c TH |
1043 | */ |
1044 | int no_way_out = 0; | |
1045 | /* | |
1046 | * If kill_it gets set, there might be a way to recover from this | |
1047 | * error. | |
1048 | */ | |
1049 | int kill_it = 0; | |
b79109c3 | 1050 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
95022b8c | 1051 | DECLARE_BITMAP(valid_banks, MAX_NR_BANKS); |
bd19a5e6 | 1052 | char *msg = "Unknown"; |
d4812e16 TL |
1053 | u64 recover_paddr = ~0ull; |
1054 | int flags = MF_ACTION_REQUIRED; | |
243d657e | 1055 | int lmce = 0; |
1da177e4 | 1056 | |
95927475 AL |
1057 | prev_state = ist_enter(regs); |
1058 | ||
c6ae41e7 | 1059 | this_cpu_inc(mce_exception_count); |
01ca79f1 | 1060 | |
1462594b | 1061 | if (!cfg->banks) |
32561696 | 1062 | goto out; |
1da177e4 | 1063 | |
b8325c5b | 1064 | mce_gather_info(&m, regs); |
b5f2fa4e | 1065 | |
89cbc767 | 1066 | final = this_cpu_ptr(&mces_seen); |
3c079792 AK |
1067 | *final = m; |
1068 | ||
95022b8c | 1069 | memset(valid_banks, 0, sizeof(valid_banks)); |
61b0fccd | 1070 | no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs); |
680b6cfd | 1071 | |
1da177e4 LT |
1072 | barrier(); |
1073 | ||
ed7290d0 | 1074 | /* |
a8c321fb TL |
1075 | * When no restart IP might need to kill or panic. |
1076 | * Assume the worst for now, but if we find the | |
1077 | * severity is MCE_AR_SEVERITY we have other options. | |
ed7290d0 AK |
1078 | */ |
1079 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
1080 | kill_it = 1; | |
1081 | ||
3c079792 | 1082 | /* |
243d657e | 1083 | * Check if this MCE is signaled to only this logical processor |
3c079792 | 1084 | */ |
243d657e AR |
1085 | if (m.mcgstatus & MCG_STATUS_LMCES) |
1086 | lmce = 1; | |
1087 | else { | |
1088 | /* | |
1089 | * Go through all the banks in exclusion of the other CPUs. | |
1090 | * This way we don't report duplicated events on shared banks | |
1091 | * because the first one to see it will clear it. | |
1092 | * If this is a Local MCE, then no need to perform rendezvous. | |
1093 | */ | |
1094 | order = mce_start(&no_way_out); | |
1095 | } | |
1096 | ||
1462594b | 1097 | for (i = 0; i < cfg->banks; i++) { |
b79109c3 | 1098 | __clear_bit(i, toclear); |
95022b8c TL |
1099 | if (!test_bit(i, valid_banks)) |
1100 | continue; | |
cebe1820 | 1101 | if (!mce_banks[i].ctl) |
1da177e4 | 1102 | continue; |
d88203d1 TG |
1103 | |
1104 | m.misc = 0; | |
1da177e4 LT |
1105 | m.addr = 0; |
1106 | m.bank = i; | |
1da177e4 | 1107 | |
a2d32bcb | 1108 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
1da177e4 LT |
1109 | if ((m.status & MCI_STATUS_VAL) == 0) |
1110 | continue; | |
1111 | ||
b79109c3 | 1112 | /* |
ed7290d0 AK |
1113 | * Non uncorrected or non signaled errors are handled by |
1114 | * machine_check_poll. Leave them alone, unless this panics. | |
b79109c3 | 1115 | */ |
1462594b | 1116 | if (!(m.status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) && |
ed7290d0 | 1117 | !no_way_out) |
b79109c3 AK |
1118 | continue; |
1119 | ||
1120 | /* | |
1121 | * Set taint even when machine check was not enabled. | |
1122 | */ | |
373d4d09 | 1123 | add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); |
b79109c3 | 1124 | |
e3480271 | 1125 | severity = mce_severity(&m, cfg->tolerant, NULL, true); |
b79109c3 | 1126 | |
ed7290d0 | 1127 | /* |
e3480271 CY |
1128 | * When machine check was for corrected/deferred handler don't |
1129 | * touch, unless we're panicing. | |
ed7290d0 | 1130 | */ |
e3480271 CY |
1131 | if ((severity == MCE_KEEP_SEVERITY || |
1132 | severity == MCE_UCNA_SEVERITY) && !no_way_out) | |
ed7290d0 AK |
1133 | continue; |
1134 | __set_bit(i, toclear); | |
1135 | if (severity == MCE_NO_SEVERITY) { | |
b79109c3 AK |
1136 | /* |
1137 | * Machine check event was not enabled. Clear, but | |
1138 | * ignore. | |
1139 | */ | |
1140 | continue; | |
1da177e4 LT |
1141 | } |
1142 | ||
85f92694 | 1143 | mce_read_aux(&m, i); |
1da177e4 | 1144 | |
9b1beaf2 AK |
1145 | /* |
1146 | * Action optional error. Queue address for later processing. | |
1147 | * When the ring overflows we just ignore the AO error. | |
1148 | * RED-PEN add some logging mechanism when | |
1149 | * usable_address or mce_add_ring fails. | |
d203f0b8 | 1150 | * RED-PEN don't ignore overflow for mca_cfg.tolerant == 0 |
9b1beaf2 AK |
1151 | */ |
1152 | if (severity == MCE_AO_SEVERITY && mce_usable_address(&m)) | |
1153 | mce_ring_add(m.addr >> PAGE_SHIFT); | |
1154 | ||
b79109c3 | 1155 | mce_log(&m); |
1da177e4 | 1156 | |
3c079792 AK |
1157 | if (severity > worst) { |
1158 | *final = m; | |
1159 | worst = severity; | |
1da177e4 | 1160 | } |
1da177e4 LT |
1161 | } |
1162 | ||
a8c321fb TL |
1163 | /* mce_clear_state will clear *final, save locally for use later */ |
1164 | m = *final; | |
1165 | ||
3c079792 AK |
1166 | if (!no_way_out) |
1167 | mce_clear_state(toclear); | |
1168 | ||
e9eee03e | 1169 | /* |
3c079792 AK |
1170 | * Do most of the synchronization with other CPUs. |
1171 | * When there's any problem use only local no_way_out state. | |
e9eee03e | 1172 | */ |
243d657e AR |
1173 | if (!lmce) { |
1174 | if (mce_end(order) < 0) | |
1175 | no_way_out = worst >= MCE_PANIC_SEVERITY; | |
1176 | } else { | |
1177 | /* | |
1178 | * Local MCE skipped calling mce_reign() | |
1179 | * If we found a fatal error, we need to panic here. | |
1180 | */ | |
1181 | if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) | |
1182 | mce_panic("Machine check from unknown source", | |
1183 | NULL, NULL); | |
1184 | } | |
bd78432c TH |
1185 | |
1186 | /* | |
a8c321fb TL |
1187 | * At insane "tolerant" levels we take no action. Otherwise |
1188 | * we only die if we have no other choice. For less serious | |
1189 | * issues we try to recover, or limit damage to the current | |
1190 | * process. | |
bd78432c | 1191 | */ |
1462594b | 1192 | if (cfg->tolerant < 3) { |
a8c321fb TL |
1193 | if (no_way_out) |
1194 | mce_panic("Fatal machine check on current CPU", &m, msg); | |
1195 | if (worst == MCE_AR_SEVERITY) { | |
d4812e16 TL |
1196 | recover_paddr = m.addr; |
1197 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
1198 | flags |= MF_MUST_KILL; | |
a8c321fb TL |
1199 | } else if (kill_it) { |
1200 | force_sig(SIGBUS, current); | |
1201 | } | |
1202 | } | |
e02e68d3 | 1203 | |
3c079792 AK |
1204 | if (worst > 0) |
1205 | mce_report_event(regs); | |
5f8c1a54 | 1206 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 1207 | out: |
88921be3 | 1208 | sync_core(); |
d4812e16 TL |
1209 | |
1210 | if (recover_paddr == ~0ull) | |
1211 | goto done; | |
1212 | ||
1213 | pr_err("Uncorrected hardware memory error in user-access at %llx", | |
1214 | recover_paddr); | |
1215 | /* | |
1216 | * We must call memory_failure() here even if the current process is | |
1217 | * doomed. We still need to mark the page as poisoned and alert any | |
1218 | * other users of the page. | |
1219 | */ | |
1220 | ist_begin_non_atomic(regs); | |
1221 | local_irq_enable(); | |
1222 | if (memory_failure(recover_paddr >> PAGE_SHIFT, MCE_VECTOR, flags) < 0) { | |
1223 | pr_err("Memory error not recovered"); | |
1224 | force_sig(SIGBUS, current); | |
1225 | } | |
1226 | local_irq_disable(); | |
1227 | ist_end_non_atomic(); | |
1228 | done: | |
95927475 | 1229 | ist_exit(regs, prev_state); |
1da177e4 | 1230 | } |
ea149b36 | 1231 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 1232 | |
cd42f4a3 TL |
1233 | #ifndef CONFIG_MEMORY_FAILURE |
1234 | int memory_failure(unsigned long pfn, int vector, int flags) | |
9b1beaf2 | 1235 | { |
a8c321fb TL |
1236 | /* mce_severity() should not hand us an ACTION_REQUIRED error */ |
1237 | BUG_ON(flags & MF_ACTION_REQUIRED); | |
c767a54b JP |
1238 | pr_err("Uncorrected memory error in page 0x%lx ignored\n" |
1239 | "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", | |
1240 | pfn); | |
cd42f4a3 TL |
1241 | |
1242 | return 0; | |
9b1beaf2 | 1243 | } |
cd42f4a3 | 1244 | #endif |
9b1beaf2 | 1245 | |
a8c321fb TL |
1246 | /* |
1247 | * Action optional processing happens here (picking up | |
1248 | * from the list of faulting pages that do_machine_check() | |
1249 | * placed into the "ring"). | |
1250 | */ | |
9b1beaf2 AK |
1251 | static void mce_process_work(struct work_struct *dummy) |
1252 | { | |
a8c321fb TL |
1253 | unsigned long pfn; |
1254 | ||
1255 | while (mce_ring_get(&pfn)) | |
1256 | memory_failure(pfn, MCE_VECTOR, 0); | |
9b1beaf2 AK |
1257 | } |
1258 | ||
15d5f839 DZ |
1259 | #ifdef CONFIG_X86_MCE_INTEL |
1260 | /*** | |
1261 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 1262 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
1263 | * @status: Event status information |
1264 | * | |
1265 | * This function should be called by the thermal interrupt after the | |
1266 | * event has been processed and the decision was made to log the event | |
1267 | * further. | |
1268 | * | |
1269 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
1270 | * and historically has been the register value of the | |
1271 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
1272 | */ | |
b5f2fa4e | 1273 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
1274 | { |
1275 | struct mce m; | |
1276 | ||
b5f2fa4e | 1277 | mce_setup(&m); |
15d5f839 DZ |
1278 | m.bank = MCE_THERMAL_BANK; |
1279 | m.status = status; | |
15d5f839 DZ |
1280 | mce_log(&m); |
1281 | } | |
1282 | #endif /* CONFIG_X86_MCE_INTEL */ | |
1283 | ||
1da177e4 | 1284 | /* |
8a336b0a TH |
1285 | * Periodic polling timer for "silent" machine check errors. If the |
1286 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
1287 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 1288 | */ |
3f2f0680 | 1289 | static unsigned long check_interval = INITIAL_CHECK_INTERVAL; |
e9eee03e | 1290 | |
82f7af09 | 1291 | static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */ |
52d168e2 | 1292 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 1293 | |
55babd8f CG |
1294 | static unsigned long mce_adjust_timer_default(unsigned long interval) |
1295 | { | |
1296 | return interval; | |
1297 | } | |
1298 | ||
3f2f0680 | 1299 | static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default; |
55babd8f | 1300 | |
3f2f0680 | 1301 | static void __restart_timer(struct timer_list *t, unsigned long interval) |
27f6c573 | 1302 | { |
3f2f0680 BP |
1303 | unsigned long when = jiffies + interval; |
1304 | unsigned long flags; | |
27f6c573 | 1305 | |
3f2f0680 | 1306 | local_irq_save(flags); |
27f6c573 | 1307 | |
3f2f0680 BP |
1308 | if (timer_pending(t)) { |
1309 | if (time_before(when, t->expires)) | |
1310 | mod_timer_pinned(t, when); | |
1311 | } else { | |
1312 | t->expires = round_jiffies(when); | |
1313 | add_timer_on(t, smp_processor_id()); | |
1314 | } | |
1315 | ||
1316 | local_irq_restore(flags); | |
27f6c573 CG |
1317 | } |
1318 | ||
82f7af09 | 1319 | static void mce_timer_fn(unsigned long data) |
1da177e4 | 1320 | { |
89cbc767 | 1321 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
3f2f0680 | 1322 | int cpu = smp_processor_id(); |
82f7af09 | 1323 | unsigned long iv; |
52d168e2 | 1324 | |
3f2f0680 BP |
1325 | WARN_ON(cpu != data); |
1326 | ||
1327 | iv = __this_cpu_read(mce_next_interval); | |
52d168e2 | 1328 | |
89cbc767 | 1329 | if (mce_available(this_cpu_ptr(&cpu_info))) { |
3f2f0680 BP |
1330 | machine_check_poll(MCP_TIMESTAMP, this_cpu_ptr(&mce_poll_banks)); |
1331 | ||
1332 | if (mce_intel_cmci_poll()) { | |
1333 | iv = mce_adjust_timer(iv); | |
1334 | goto done; | |
1335 | } | |
e9eee03e | 1336 | } |
1da177e4 LT |
1337 | |
1338 | /* | |
3f2f0680 BP |
1339 | * Alert userspace if needed. If we logged an MCE, reduce the polling |
1340 | * interval, otherwise increase the polling interval. | |
1da177e4 | 1341 | */ |
3f2f0680 | 1342 | if (mce_notify_irq()) |
958fb3c5 | 1343 | iv = max(iv / 2, (unsigned long) HZ/100); |
3f2f0680 | 1344 | else |
82f7af09 | 1345 | iv = min(iv * 2, round_jiffies_relative(check_interval * HZ)); |
3f2f0680 BP |
1346 | |
1347 | done: | |
82f7af09 | 1348 | __this_cpu_write(mce_next_interval, iv); |
3f2f0680 | 1349 | __restart_timer(t, iv); |
55babd8f | 1350 | } |
e02e68d3 | 1351 | |
55babd8f CG |
1352 | /* |
1353 | * Ensure that the timer is firing in @interval from now. | |
1354 | */ | |
1355 | void mce_timer_kick(unsigned long interval) | |
1356 | { | |
89cbc767 | 1357 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
55babd8f CG |
1358 | unsigned long iv = __this_cpu_read(mce_next_interval); |
1359 | ||
3f2f0680 BP |
1360 | __restart_timer(t, interval); |
1361 | ||
55babd8f CG |
1362 | if (interval < iv) |
1363 | __this_cpu_write(mce_next_interval, interval); | |
e02e68d3 TH |
1364 | } |
1365 | ||
9aaef96f HS |
1366 | /* Must not be called in IRQ context where del_timer_sync() can deadlock */ |
1367 | static void mce_timer_delete_all(void) | |
1368 | { | |
1369 | int cpu; | |
1370 | ||
1371 | for_each_online_cpu(cpu) | |
1372 | del_timer_sync(&per_cpu(mce_timer, cpu)); | |
1373 | } | |
1374 | ||
9bd98405 AK |
1375 | static void mce_do_trigger(struct work_struct *work) |
1376 | { | |
1020bcbc | 1377 | call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT); |
9bd98405 AK |
1378 | } |
1379 | ||
1380 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
1381 | ||
e02e68d3 | 1382 | /* |
9bd98405 AK |
1383 | * Notify the user(s) about new machine check events. |
1384 | * Can be called from interrupt context, but not from machine check/NMI | |
1385 | * context. | |
e02e68d3 | 1386 | */ |
9ff36ee9 | 1387 | int mce_notify_irq(void) |
e02e68d3 | 1388 | { |
8457c84d AK |
1389 | /* Not more than two messages every minute */ |
1390 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
1391 | ||
1020bcbc | 1392 | if (test_and_clear_bit(0, &mce_need_notify)) { |
93b62c3c HS |
1393 | /* wake processes polling /dev/mcelog */ |
1394 | wake_up_interruptible(&mce_chrdev_wait); | |
9bd98405 | 1395 | |
4d899be5 | 1396 | if (mce_helper[0]) |
9bd98405 | 1397 | schedule_work(&mce_trigger_work); |
e02e68d3 | 1398 | |
8457c84d | 1399 | if (__ratelimit(&ratelimit)) |
a2d7b0d4 | 1400 | pr_info(HW_ERR "Machine check events logged\n"); |
e02e68d3 TH |
1401 | |
1402 | return 1; | |
1da177e4 | 1403 | } |
e02e68d3 TH |
1404 | return 0; |
1405 | } | |
9ff36ee9 | 1406 | EXPORT_SYMBOL_GPL(mce_notify_irq); |
8a336b0a | 1407 | |
148f9bb8 | 1408 | static int __mcheck_cpu_mce_banks_init(void) |
cebe1820 AK |
1409 | { |
1410 | int i; | |
d203f0b8 | 1411 | u8 num_banks = mca_cfg.banks; |
cebe1820 | 1412 | |
d203f0b8 | 1413 | mce_banks = kzalloc(num_banks * sizeof(struct mce_bank), GFP_KERNEL); |
cebe1820 AK |
1414 | if (!mce_banks) |
1415 | return -ENOMEM; | |
d203f0b8 BP |
1416 | |
1417 | for (i = 0; i < num_banks; i++) { | |
cebe1820 | 1418 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1419 | |
cebe1820 AK |
1420 | b->ctl = -1ULL; |
1421 | b->init = 1; | |
1422 | } | |
1423 | return 0; | |
1424 | } | |
1425 | ||
d88203d1 | 1426 | /* |
1da177e4 LT |
1427 | * Initialize Machine Checks for a CPU. |
1428 | */ | |
148f9bb8 | 1429 | static int __mcheck_cpu_cap_init(void) |
1da177e4 | 1430 | { |
0d7482e3 | 1431 | unsigned b; |
e9eee03e | 1432 | u64 cap; |
1da177e4 LT |
1433 | |
1434 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
1435 | |
1436 | b = cap & MCG_BANKCNT_MASK; | |
d203f0b8 | 1437 | if (!mca_cfg.banks) |
c767a54b | 1438 | pr_info("CPU supports %d MCE banks\n", b); |
b659294b | 1439 | |
0d7482e3 | 1440 | if (b > MAX_NR_BANKS) { |
c767a54b | 1441 | pr_warn("Using only %u machine check banks out of %u\n", |
0d7482e3 AK |
1442 | MAX_NR_BANKS, b); |
1443 | b = MAX_NR_BANKS; | |
1444 | } | |
1445 | ||
1446 | /* Don't support asymmetric configurations today */ | |
d203f0b8 BP |
1447 | WARN_ON(mca_cfg.banks != 0 && b != mca_cfg.banks); |
1448 | mca_cfg.banks = b; | |
1449 | ||
cebe1820 | 1450 | if (!mce_banks) { |
cffd377e | 1451 | int err = __mcheck_cpu_mce_banks_init(); |
11868a2d | 1452 | |
cebe1820 AK |
1453 | if (err) |
1454 | return err; | |
1da177e4 | 1455 | } |
0d7482e3 | 1456 | |
94ad8474 | 1457 | /* Use accurate RIP reporting if available. */ |
01c6680a | 1458 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
84c2559d | 1459 | mca_cfg.rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 1460 | |
ed7290d0 | 1461 | if (cap & MCG_SER_P) |
1462594b | 1462 | mca_cfg.ser = true; |
ed7290d0 | 1463 | |
0d7482e3 AK |
1464 | return 0; |
1465 | } | |
1466 | ||
5e09954a | 1467 | static void __mcheck_cpu_init_generic(void) |
0d7482e3 | 1468 | { |
84c2559d | 1469 | enum mcp_flags m_fl = 0; |
e9eee03e | 1470 | mce_banks_t all_banks; |
0d7482e3 AK |
1471 | u64 cap; |
1472 | int i; | |
1473 | ||
84c2559d BP |
1474 | if (!mca_cfg.bootlog) |
1475 | m_fl = MCP_DONTLOG; | |
1476 | ||
b79109c3 AK |
1477 | /* |
1478 | * Log the machine checks left over from the previous reset. | |
1479 | */ | |
ee031c31 | 1480 | bitmap_fill(all_banks, MAX_NR_BANKS); |
84c2559d | 1481 | machine_check_poll(MCP_UC | m_fl, &all_banks); |
1da177e4 | 1482 | |
375074cc | 1483 | cr4_set_bits(X86_CR4_MCE); |
1da177e4 | 1484 | |
0d7482e3 | 1485 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
1486 | if (cap & MCG_CTL_P) |
1487 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
1488 | ||
d203f0b8 | 1489 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 1490 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1491 | |
cebe1820 | 1492 | if (!b->init) |
06b7a7a5 | 1493 | continue; |
a2d32bcb AK |
1494 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
1495 | wrmsrl(MSR_IA32_MCx_STATUS(i), 0); | |
d88203d1 | 1496 | } |
1da177e4 LT |
1497 | } |
1498 | ||
61b0fccd TL |
1499 | /* |
1500 | * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and | |
1501 | * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM | |
1502 | * Vol 3B Table 15-20). But this confuses both the code that determines | |
1503 | * whether the machine check occurred in kernel or user mode, and also | |
1504 | * the severity assessment code. Pretend that EIPV was set, and take the | |
1505 | * ip/cs values from the pt_regs that mce_gather_info() ignored earlier. | |
1506 | */ | |
1507 | static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs) | |
1508 | { | |
1509 | if (bank != 0) | |
1510 | return; | |
1511 | if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0) | |
1512 | return; | |
1513 | if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC| | |
1514 | MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV| | |
1515 | MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR| | |
1516 | MCACOD)) != | |
1517 | (MCI_STATUS_UC|MCI_STATUS_EN| | |
1518 | MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S| | |
1519 | MCI_STATUS_AR|MCACOD_INSTR)) | |
1520 | return; | |
1521 | ||
1522 | m->mcgstatus |= MCG_STATUS_EIPV; | |
1523 | m->ip = regs->ip; | |
1524 | m->cs = regs->cs; | |
1525 | } | |
1526 | ||
1da177e4 | 1527 | /* Add per CPU specific workarounds here */ |
148f9bb8 | 1528 | static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 1529 | { |
d203f0b8 BP |
1530 | struct mca_config *cfg = &mca_cfg; |
1531 | ||
e412cd25 | 1532 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { |
c767a54b | 1533 | pr_info("unknown CPU type - not enabling MCE support\n"); |
e412cd25 IM |
1534 | return -EOPNOTSUPP; |
1535 | } | |
1536 | ||
1da177e4 | 1537 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 1538 | if (c->x86_vendor == X86_VENDOR_AMD) { |
d203f0b8 | 1539 | if (c->x86 == 15 && cfg->banks > 4) { |
e9eee03e IM |
1540 | /* |
1541 | * disable GART TBL walk error reporting, which | |
1542 | * trips off incorrectly with the IOMMU & 3ware | |
1543 | * & Cerberus: | |
1544 | */ | |
cebe1820 | 1545 | clear_bit(10, (unsigned long *)&mce_banks[4].ctl); |
e9eee03e | 1546 | } |
84c2559d | 1547 | if (c->x86 <= 17 && cfg->bootlog < 0) { |
e9eee03e IM |
1548 | /* |
1549 | * Lots of broken BIOS around that don't clear them | |
1550 | * by default and leave crap in there. Don't log: | |
1551 | */ | |
84c2559d | 1552 | cfg->bootlog = 0; |
e9eee03e | 1553 | } |
2e6f694f AK |
1554 | /* |
1555 | * Various K7s with broken bank 0 around. Always disable | |
1556 | * by default. | |
1557 | */ | |
c9ce8712 | 1558 | if (c->x86 == 6 && cfg->banks > 0) |
cebe1820 | 1559 | mce_banks[0].ctl = 0; |
575203b4 | 1560 | |
bf80bbd7 AG |
1561 | /* |
1562 | * overflow_recov is supported for F15h Models 00h-0fh | |
1563 | * even though we don't have a CPUID bit for it. | |
1564 | */ | |
1565 | if (c->x86 == 0x15 && c->x86_model <= 0xf) | |
1566 | mce_flags.overflow_recov = 1; | |
1567 | ||
c9ce8712 BP |
1568 | /* |
1569 | * Turn off MC4_MISC thresholding banks on those models since | |
1570 | * they're not supported there. | |
1571 | */ | |
1572 | if (c->x86 == 0x15 && | |
1573 | (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) { | |
1574 | int i; | |
1575 | u64 hwcr; | |
1576 | bool need_toggle; | |
1577 | u32 msrs[] = { | |
575203b4 BP |
1578 | 0x00000413, /* MC4_MISC0 */ |
1579 | 0xc0000408, /* MC4_MISC1 */ | |
c9ce8712 | 1580 | }; |
575203b4 | 1581 | |
c9ce8712 | 1582 | rdmsrl(MSR_K7_HWCR, hwcr); |
575203b4 | 1583 | |
c9ce8712 BP |
1584 | /* McStatusWrEn has to be set */ |
1585 | need_toggle = !(hwcr & BIT(18)); | |
575203b4 | 1586 | |
c9ce8712 BP |
1587 | if (need_toggle) |
1588 | wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); | |
575203b4 | 1589 | |
c9ce8712 BP |
1590 | /* Clear CntP bit safely */ |
1591 | for (i = 0; i < ARRAY_SIZE(msrs); i++) | |
1592 | msr_clear_bit(msrs[i], 62); | |
575203b4 | 1593 | |
c9ce8712 BP |
1594 | /* restore old settings */ |
1595 | if (need_toggle) | |
1596 | wrmsrl(MSR_K7_HWCR, hwcr); | |
1597 | } | |
1da177e4 | 1598 | } |
e583538f | 1599 | |
06b7a7a5 AK |
1600 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
1601 | /* | |
1602 | * SDM documents that on family 6 bank 0 should not be written | |
1603 | * because it aliases to another special BIOS controlled | |
1604 | * register. | |
1605 | * But it's not aliased anymore on model 0x1a+ | |
1606 | * Don't ignore bank 0 completely because there could be a | |
1607 | * valid event later, merely don't write CTL0. | |
1608 | */ | |
1609 | ||
d203f0b8 | 1610 | if (c->x86 == 6 && c->x86_model < 0x1A && cfg->banks > 0) |
cebe1820 | 1611 | mce_banks[0].init = 0; |
3c079792 AK |
1612 | |
1613 | /* | |
1614 | * All newer Intel systems support MCE broadcasting. Enable | |
1615 | * synchronization with a one second timeout. | |
1616 | */ | |
1617 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && | |
84c2559d BP |
1618 | cfg->monarch_timeout < 0) |
1619 | cfg->monarch_timeout = USEC_PER_SEC; | |
c7f6fa44 | 1620 | |
e412cd25 IM |
1621 | /* |
1622 | * There are also broken BIOSes on some Pentium M and | |
1623 | * earlier systems: | |
1624 | */ | |
84c2559d BP |
1625 | if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0) |
1626 | cfg->bootlog = 0; | |
61b0fccd TL |
1627 | |
1628 | if (c->x86 == 6 && c->x86_model == 45) | |
1629 | quirk_no_way_out = quirk_sandybridge_ifu; | |
06b7a7a5 | 1630 | } |
84c2559d BP |
1631 | if (cfg->monarch_timeout < 0) |
1632 | cfg->monarch_timeout = 0; | |
1633 | if (cfg->bootlog != 0) | |
7af19e4a | 1634 | cfg->panic_timeout = 30; |
e412cd25 IM |
1635 | |
1636 | return 0; | |
d88203d1 | 1637 | } |
1da177e4 | 1638 | |
148f9bb8 | 1639 | static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) |
4efc0670 AK |
1640 | { |
1641 | if (c->x86 != 5) | |
3a97fc34 HS |
1642 | return 0; |
1643 | ||
4efc0670 AK |
1644 | switch (c->x86_vendor) { |
1645 | case X86_VENDOR_INTEL: | |
c6978369 | 1646 | intel_p5_mcheck_init(c); |
3a97fc34 | 1647 | return 1; |
4efc0670 AK |
1648 | break; |
1649 | case X86_VENDOR_CENTAUR: | |
1650 | winchip_mcheck_init(c); | |
3a97fc34 | 1651 | return 1; |
4efc0670 AK |
1652 | break; |
1653 | } | |
3a97fc34 HS |
1654 | |
1655 | return 0; | |
4efc0670 AK |
1656 | } |
1657 | ||
5e09954a | 1658 | static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
1659 | { |
1660 | switch (c->x86_vendor) { | |
1661 | case X86_VENDOR_INTEL: | |
1662 | mce_intel_feature_init(c); | |
3f2f0680 | 1663 | mce_adjust_timer = cmci_intel_adjust_timer; |
1da177e4 | 1664 | break; |
7559e13f AG |
1665 | |
1666 | case X86_VENDOR_AMD: { | |
1667 | u32 ebx = cpuid_ebx(0x80000007); | |
1668 | ||
89b831ef | 1669 | mce_amd_feature_init(c); |
7559e13f AG |
1670 | mce_flags.overflow_recov = !!(ebx & BIT(0)); |
1671 | mce_flags.succor = !!(ebx & BIT(1)); | |
89b831ef | 1672 | break; |
7559e13f AG |
1673 | } |
1674 | ||
1da177e4 LT |
1675 | default: |
1676 | break; | |
1677 | } | |
1678 | } | |
1679 | ||
26c3c283 | 1680 | static void mce_start_timer(unsigned int cpu, struct timer_list *t) |
52d168e2 | 1681 | { |
4f75d841 | 1682 | unsigned long iv = check_interval * HZ; |
bc09effa | 1683 | |
7af19e4a | 1684 | if (mca_cfg.ignore_ce || !iv) |
62fdac59 HS |
1685 | return; |
1686 | ||
4f75d841 BP |
1687 | per_cpu(mce_next_interval, cpu) = iv; |
1688 | ||
82f7af09 | 1689 | t->expires = round_jiffies(jiffies + iv); |
4f75d841 | 1690 | add_timer_on(t, cpu); |
52d168e2 AK |
1691 | } |
1692 | ||
26c3c283 TG |
1693 | static void __mcheck_cpu_init_timer(void) |
1694 | { | |
89cbc767 | 1695 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
26c3c283 TG |
1696 | unsigned int cpu = smp_processor_id(); |
1697 | ||
1698 | setup_timer(t, mce_timer_fn, cpu); | |
1699 | mce_start_timer(cpu, t); | |
1700 | } | |
1701 | ||
9eda8cb3 AK |
1702 | /* Handle unconfigured int18 (should never happen) */ |
1703 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
1704 | { | |
c767a54b | 1705 | pr_err("CPU#%d: Unexpected int18 (Machine Check)\n", |
9eda8cb3 AK |
1706 | smp_processor_id()); |
1707 | } | |
1708 | ||
1709 | /* Call the installed machine check handler for this CPU setup. */ | |
1710 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
1711 | unexpected_machine_check; | |
1712 | ||
d88203d1 | 1713 | /* |
1da177e4 | 1714 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 1715 | * Must be called with preempt off: |
1da177e4 | 1716 | */ |
148f9bb8 | 1717 | void mcheck_cpu_init(struct cpuinfo_x86 *c) |
1da177e4 | 1718 | { |
1462594b | 1719 | if (mca_cfg.disabled) |
4efc0670 AK |
1720 | return; |
1721 | ||
3a97fc34 HS |
1722 | if (__mcheck_cpu_ancient_init(c)) |
1723 | return; | |
4efc0670 | 1724 | |
5b4408fd | 1725 | if (!mce_available(c)) |
1da177e4 LT |
1726 | return; |
1727 | ||
5e09954a | 1728 | if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) { |
1462594b | 1729 | mca_cfg.disabled = true; |
0d7482e3 AK |
1730 | return; |
1731 | } | |
0d7482e3 | 1732 | |
648ed940 CG |
1733 | if (mce_gen_pool_init()) { |
1734 | mca_cfg.disabled = true; | |
1735 | pr_emerg("Couldn't allocate MCE records pool!\n"); | |
1736 | return; | |
1737 | } | |
1738 | ||
5d727926 AK |
1739 | machine_check_vector = do_machine_check; |
1740 | ||
5e09954a BP |
1741 | __mcheck_cpu_init_generic(); |
1742 | __mcheck_cpu_init_vendor(c); | |
1743 | __mcheck_cpu_init_timer(); | |
1da177e4 LT |
1744 | } |
1745 | ||
1746 | /* | |
93b62c3c | 1747 | * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log. |
1da177e4 LT |
1748 | */ |
1749 | ||
93b62c3c HS |
1750 | static DEFINE_SPINLOCK(mce_chrdev_state_lock); |
1751 | static int mce_chrdev_open_count; /* #times opened */ | |
1752 | static int mce_chrdev_open_exclu; /* already open exclusive? */ | |
f528e7ba | 1753 | |
93b62c3c | 1754 | static int mce_chrdev_open(struct inode *inode, struct file *file) |
f528e7ba | 1755 | { |
93b62c3c | 1756 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1757 | |
93b62c3c HS |
1758 | if (mce_chrdev_open_exclu || |
1759 | (mce_chrdev_open_count && (file->f_flags & O_EXCL))) { | |
1760 | spin_unlock(&mce_chrdev_state_lock); | |
e9eee03e | 1761 | |
f528e7ba TH |
1762 | return -EBUSY; |
1763 | } | |
1764 | ||
1765 | if (file->f_flags & O_EXCL) | |
93b62c3c HS |
1766 | mce_chrdev_open_exclu = 1; |
1767 | mce_chrdev_open_count++; | |
f528e7ba | 1768 | |
93b62c3c | 1769 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba | 1770 | |
bd78432c | 1771 | return nonseekable_open(inode, file); |
f528e7ba TH |
1772 | } |
1773 | ||
93b62c3c | 1774 | static int mce_chrdev_release(struct inode *inode, struct file *file) |
f528e7ba | 1775 | { |
93b62c3c | 1776 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1777 | |
93b62c3c HS |
1778 | mce_chrdev_open_count--; |
1779 | mce_chrdev_open_exclu = 0; | |
f528e7ba | 1780 | |
93b62c3c | 1781 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba TH |
1782 | |
1783 | return 0; | |
1784 | } | |
1785 | ||
d88203d1 TG |
1786 | static void collect_tscs(void *data) |
1787 | { | |
1da177e4 | 1788 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 1789 | |
1da177e4 | 1790 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 1791 | } |
1da177e4 | 1792 | |
482908b4 HY |
1793 | static int mce_apei_read_done; |
1794 | ||
1795 | /* Collect MCE record of previous boot in persistent storage via APEI ERST. */ | |
1796 | static int __mce_read_apei(char __user **ubuf, size_t usize) | |
1797 | { | |
1798 | int rc; | |
1799 | u64 record_id; | |
1800 | struct mce m; | |
1801 | ||
1802 | if (usize < sizeof(struct mce)) | |
1803 | return -EINVAL; | |
1804 | ||
1805 | rc = apei_read_mce(&m, &record_id); | |
1806 | /* Error or no more MCE record */ | |
1807 | if (rc <= 0) { | |
1808 | mce_apei_read_done = 1; | |
fadd85f1 NH |
1809 | /* |
1810 | * When ERST is disabled, mce_chrdev_read() should return | |
1811 | * "no record" instead of "no device." | |
1812 | */ | |
1813 | if (rc == -ENODEV) | |
1814 | return 0; | |
482908b4 HY |
1815 | return rc; |
1816 | } | |
1817 | rc = -EFAULT; | |
1818 | if (copy_to_user(*ubuf, &m, sizeof(struct mce))) | |
1819 | return rc; | |
1820 | /* | |
1821 | * In fact, we should have cleared the record after that has | |
1822 | * been flushed to the disk or sent to network in | |
1823 | * /sbin/mcelog, but we have no interface to support that now, | |
1824 | * so just clear it to avoid duplication. | |
1825 | */ | |
1826 | rc = apei_clear_mce(record_id); | |
1827 | if (rc) { | |
1828 | mce_apei_read_done = 1; | |
1829 | return rc; | |
1830 | } | |
1831 | *ubuf += sizeof(struct mce); | |
1832 | ||
1833 | return 0; | |
1834 | } | |
1835 | ||
93b62c3c HS |
1836 | static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf, |
1837 | size_t usize, loff_t *off) | |
1da177e4 | 1838 | { |
e9eee03e | 1839 | char __user *buf = ubuf; |
f0de53bb | 1840 | unsigned long *cpu_tsc; |
ef41df43 | 1841 | unsigned prev, next; |
1da177e4 LT |
1842 | int i, err; |
1843 | ||
6bca67f9 | 1844 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
1845 | if (!cpu_tsc) |
1846 | return -ENOMEM; | |
1847 | ||
93b62c3c | 1848 | mutex_lock(&mce_chrdev_read_mutex); |
482908b4 HY |
1849 | |
1850 | if (!mce_apei_read_done) { | |
1851 | err = __mce_read_apei(&buf, usize); | |
1852 | if (err || buf != ubuf) | |
1853 | goto out; | |
1854 | } | |
1855 | ||
f56e8a07 | 1856 | next = rcu_dereference_check_mce(mcelog.next); |
1da177e4 LT |
1857 | |
1858 | /* Only supports full reads right now */ | |
482908b4 HY |
1859 | err = -EINVAL; |
1860 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) | |
1861 | goto out; | |
1da177e4 LT |
1862 | |
1863 | err = 0; | |
ef41df43 HY |
1864 | prev = 0; |
1865 | do { | |
1866 | for (i = prev; i < next; i++) { | |
1867 | unsigned long start = jiffies; | |
559faa6b | 1868 | struct mce *m = &mcelog.entry[i]; |
ef41df43 | 1869 | |
559faa6b | 1870 | while (!m->finished) { |
ef41df43 | 1871 | if (time_after_eq(jiffies, start + 2)) { |
559faa6b | 1872 | memset(m, 0, sizeof(*m)); |
ef41df43 HY |
1873 | goto timeout; |
1874 | } | |
1875 | cpu_relax(); | |
673242c1 | 1876 | } |
ef41df43 | 1877 | smp_rmb(); |
559faa6b HS |
1878 | err |= copy_to_user(buf, m, sizeof(*m)); |
1879 | buf += sizeof(*m); | |
ef41df43 HY |
1880 | timeout: |
1881 | ; | |
673242c1 | 1882 | } |
1da177e4 | 1883 | |
ef41df43 HY |
1884 | memset(mcelog.entry + prev, 0, |
1885 | (next - prev) * sizeof(struct mce)); | |
1886 | prev = next; | |
1887 | next = cmpxchg(&mcelog.next, prev, 0); | |
1888 | } while (next != prev); | |
1da177e4 | 1889 | |
b2b18660 | 1890 | synchronize_sched(); |
1da177e4 | 1891 | |
d88203d1 TG |
1892 | /* |
1893 | * Collect entries that were still getting written before the | |
1894 | * synchronize. | |
1895 | */ | |
15c8b6c1 | 1896 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 1897 | |
d88203d1 | 1898 | for (i = next; i < MCE_LOG_LEN; i++) { |
559faa6b HS |
1899 | struct mce *m = &mcelog.entry[i]; |
1900 | ||
1901 | if (m->finished && m->tsc < cpu_tsc[m->cpu]) { | |
1902 | err |= copy_to_user(buf, m, sizeof(*m)); | |
1da177e4 | 1903 | smp_rmb(); |
559faa6b HS |
1904 | buf += sizeof(*m); |
1905 | memset(m, 0, sizeof(*m)); | |
1da177e4 | 1906 | } |
d88203d1 | 1907 | } |
482908b4 HY |
1908 | |
1909 | if (err) | |
1910 | err = -EFAULT; | |
1911 | ||
1912 | out: | |
93b62c3c | 1913 | mutex_unlock(&mce_chrdev_read_mutex); |
f0de53bb | 1914 | kfree(cpu_tsc); |
e9eee03e | 1915 | |
482908b4 | 1916 | return err ? err : buf - ubuf; |
1da177e4 LT |
1917 | } |
1918 | ||
93b62c3c | 1919 | static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait) |
e02e68d3 | 1920 | { |
93b62c3c | 1921 | poll_wait(file, &mce_chrdev_wait, wait); |
e90328b8 | 1922 | if (READ_ONCE(mcelog.next)) |
e02e68d3 | 1923 | return POLLIN | POLLRDNORM; |
482908b4 HY |
1924 | if (!mce_apei_read_done && apei_check_mce()) |
1925 | return POLLIN | POLLRDNORM; | |
e02e68d3 TH |
1926 | return 0; |
1927 | } | |
1928 | ||
93b62c3c HS |
1929 | static long mce_chrdev_ioctl(struct file *f, unsigned int cmd, |
1930 | unsigned long arg) | |
1da177e4 LT |
1931 | { |
1932 | int __user *p = (int __user *)arg; | |
d88203d1 | 1933 | |
1da177e4 | 1934 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 1935 | return -EPERM; |
e9eee03e | 1936 | |
1da177e4 | 1937 | switch (cmd) { |
d88203d1 | 1938 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
1939 | return put_user(sizeof(struct mce), p); |
1940 | case MCE_GET_LOG_LEN: | |
d88203d1 | 1941 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
1942 | case MCE_GETCLEAR_FLAGS: { |
1943 | unsigned flags; | |
d88203d1 TG |
1944 | |
1945 | do { | |
1da177e4 | 1946 | flags = mcelog.flags; |
d88203d1 | 1947 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 1948 | |
d88203d1 | 1949 | return put_user(flags, p); |
1da177e4 LT |
1950 | } |
1951 | default: | |
d88203d1 TG |
1952 | return -ENOTTY; |
1953 | } | |
1da177e4 LT |
1954 | } |
1955 | ||
66f5ddf3 TL |
1956 | static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf, |
1957 | size_t usize, loff_t *off); | |
1958 | ||
1959 | void register_mce_write_callback(ssize_t (*fn)(struct file *filp, | |
1960 | const char __user *ubuf, | |
1961 | size_t usize, loff_t *off)) | |
1962 | { | |
1963 | mce_write = fn; | |
1964 | } | |
1965 | EXPORT_SYMBOL_GPL(register_mce_write_callback); | |
1966 | ||
29c6820f PM |
1967 | static ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf, |
1968 | size_t usize, loff_t *off) | |
66f5ddf3 TL |
1969 | { |
1970 | if (mce_write) | |
1971 | return mce_write(filp, ubuf, usize, off); | |
1972 | else | |
1973 | return -EINVAL; | |
1974 | } | |
1975 | ||
1976 | static const struct file_operations mce_chrdev_ops = { | |
93b62c3c HS |
1977 | .open = mce_chrdev_open, |
1978 | .release = mce_chrdev_release, | |
1979 | .read = mce_chrdev_read, | |
66f5ddf3 | 1980 | .write = mce_chrdev_write, |
93b62c3c HS |
1981 | .poll = mce_chrdev_poll, |
1982 | .unlocked_ioctl = mce_chrdev_ioctl, | |
1983 | .llseek = no_llseek, | |
1da177e4 LT |
1984 | }; |
1985 | ||
93b62c3c | 1986 | static struct miscdevice mce_chrdev_device = { |
1da177e4 LT |
1987 | MISC_MCELOG_MINOR, |
1988 | "mcelog", | |
1989 | &mce_chrdev_ops, | |
1990 | }; | |
1991 | ||
c3d1fb56 NR |
1992 | static void __mce_disable_bank(void *arg) |
1993 | { | |
1994 | int bank = *((int *)arg); | |
89cbc767 | 1995 | __clear_bit(bank, this_cpu_ptr(mce_poll_banks)); |
c3d1fb56 NR |
1996 | cmci_disable_bank(bank); |
1997 | } | |
1998 | ||
1999 | void mce_disable_bank(int bank) | |
2000 | { | |
2001 | if (bank >= mca_cfg.banks) { | |
2002 | pr_warn(FW_BUG | |
2003 | "Ignoring request to disable invalid MCA bank %d.\n", | |
2004 | bank); | |
2005 | return; | |
2006 | } | |
2007 | set_bit(bank, mce_banks_ce_disabled); | |
2008 | on_each_cpu(__mce_disable_bank, &bank, 1); | |
2009 | } | |
2010 | ||
13503fa9 | 2011 | /* |
62fdac59 HS |
2012 | * mce=off Disables machine check |
2013 | * mce=no_cmci Disables CMCI | |
88d53867 | 2014 | * mce=no_lmce Disables LMCE |
62fdac59 HS |
2015 | * mce=dont_log_ce Clears corrected events silently, no log created for CEs. |
2016 | * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. | |
3c079792 AK |
2017 | * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) |
2018 | * monarchtimeout is how long to wait for other CPUs on machine | |
2019 | * check, or 0 to not wait | |
13503fa9 HS |
2020 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. |
2021 | * mce=nobootlog Don't log MCEs from before booting. | |
450cc201 | 2022 | * mce=bios_cmci_threshold Don't program the CMCI threshold |
13503fa9 | 2023 | */ |
1da177e4 LT |
2024 | static int __init mcheck_enable(char *str) |
2025 | { | |
d203f0b8 BP |
2026 | struct mca_config *cfg = &mca_cfg; |
2027 | ||
e3346fc4 | 2028 | if (*str == 0) { |
4efc0670 | 2029 | enable_p5_mce(); |
e3346fc4 BZ |
2030 | return 1; |
2031 | } | |
4efc0670 AK |
2032 | if (*str == '=') |
2033 | str++; | |
1da177e4 | 2034 | if (!strcmp(str, "off")) |
1462594b | 2035 | cfg->disabled = true; |
62fdac59 | 2036 | else if (!strcmp(str, "no_cmci")) |
7af19e4a | 2037 | cfg->cmci_disabled = true; |
88d53867 AR |
2038 | else if (!strcmp(str, "no_lmce")) |
2039 | cfg->lmce_disabled = true; | |
62fdac59 | 2040 | else if (!strcmp(str, "dont_log_ce")) |
d203f0b8 | 2041 | cfg->dont_log_ce = true; |
62fdac59 | 2042 | else if (!strcmp(str, "ignore_ce")) |
7af19e4a | 2043 | cfg->ignore_ce = true; |
13503fa9 | 2044 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
84c2559d | 2045 | cfg->bootlog = (str[0] == 'b'); |
450cc201 | 2046 | else if (!strcmp(str, "bios_cmci_threshold")) |
1462594b | 2047 | cfg->bios_cmci_threshold = true; |
3c079792 | 2048 | else if (isdigit(str[0])) { |
5c31b280 | 2049 | if (get_option(&str, &cfg->tolerant) == 2) |
84c2559d | 2050 | get_option(&str, &(cfg->monarch_timeout)); |
3c079792 | 2051 | } else { |
c767a54b | 2052 | pr_info("mce argument %s ignored. Please use /sys\n", str); |
13503fa9 HS |
2053 | return 0; |
2054 | } | |
9b41046c | 2055 | return 1; |
1da177e4 | 2056 | } |
4efc0670 | 2057 | __setup("mce", mcheck_enable); |
1da177e4 | 2058 | |
a2202aa2 | 2059 | int __init mcheck_init(void) |
b33a6363 | 2060 | { |
a2202aa2 | 2061 | mcheck_intel_therm_init(); |
43eaa2a1 | 2062 | mcheck_vendor_init_severity(); |
a2202aa2 | 2063 | |
061120ae CG |
2064 | INIT_WORK(&mce_work, mce_process_work); |
2065 | init_irq_work(&mce_irq_work, mce_irq_work_cb); | |
2066 | ||
b33a6363 BP |
2067 | return 0; |
2068 | } | |
b33a6363 | 2069 | |
d88203d1 | 2070 | /* |
c7cece89 | 2071 | * mce_syscore: PM support |
d88203d1 | 2072 | */ |
1da177e4 | 2073 | |
973a2dd1 AK |
2074 | /* |
2075 | * Disable machine checks on suspend and shutdown. We can't really handle | |
2076 | * them later. | |
2077 | */ | |
5e09954a | 2078 | static int mce_disable_error_reporting(void) |
973a2dd1 AK |
2079 | { |
2080 | int i; | |
2081 | ||
d203f0b8 | 2082 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2083 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2084 | |
cebe1820 | 2085 | if (b->init) |
a2d32bcb | 2086 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 2087 | } |
973a2dd1 AK |
2088 | return 0; |
2089 | } | |
2090 | ||
c7cece89 | 2091 | static int mce_syscore_suspend(void) |
973a2dd1 | 2092 | { |
5e09954a | 2093 | return mce_disable_error_reporting(); |
973a2dd1 AK |
2094 | } |
2095 | ||
c7cece89 | 2096 | static void mce_syscore_shutdown(void) |
973a2dd1 | 2097 | { |
f3c6ea1b | 2098 | mce_disable_error_reporting(); |
973a2dd1 AK |
2099 | } |
2100 | ||
e9eee03e IM |
2101 | /* |
2102 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
2103 | * Only one CPU is active at this time, the others get re-added later using | |
2104 | * CPU hotplug: | |
2105 | */ | |
c7cece89 | 2106 | static void mce_syscore_resume(void) |
1da177e4 | 2107 | { |
5e09954a | 2108 | __mcheck_cpu_init_generic(); |
89cbc767 | 2109 | __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info)); |
1da177e4 LT |
2110 | } |
2111 | ||
f3c6ea1b | 2112 | static struct syscore_ops mce_syscore_ops = { |
c7cece89 HS |
2113 | .suspend = mce_syscore_suspend, |
2114 | .shutdown = mce_syscore_shutdown, | |
2115 | .resume = mce_syscore_resume, | |
f3c6ea1b RW |
2116 | }; |
2117 | ||
c7cece89 | 2118 | /* |
8a25a2fd | 2119 | * mce_device: Sysfs support |
c7cece89 HS |
2120 | */ |
2121 | ||
52d168e2 AK |
2122 | static void mce_cpu_restart(void *data) |
2123 | { | |
89cbc767 | 2124 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
33edbf02 | 2125 | return; |
5e09954a BP |
2126 | __mcheck_cpu_init_generic(); |
2127 | __mcheck_cpu_init_timer(); | |
52d168e2 AK |
2128 | } |
2129 | ||
1da177e4 | 2130 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
2131 | static void mce_restart(void) |
2132 | { | |
9aaef96f | 2133 | mce_timer_delete_all(); |
52d168e2 | 2134 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
2135 | } |
2136 | ||
9af43b54 | 2137 | /* Toggle features for corrected errors */ |
9aaef96f | 2138 | static void mce_disable_cmci(void *data) |
9af43b54 | 2139 | { |
89cbc767 | 2140 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
9af43b54 | 2141 | return; |
9af43b54 HS |
2142 | cmci_clear(); |
2143 | } | |
2144 | ||
2145 | static void mce_enable_ce(void *all) | |
2146 | { | |
89cbc767 | 2147 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
9af43b54 HS |
2148 | return; |
2149 | cmci_reenable(); | |
2150 | cmci_recheck(); | |
2151 | if (all) | |
5e09954a | 2152 | __mcheck_cpu_init_timer(); |
9af43b54 HS |
2153 | } |
2154 | ||
8a25a2fd | 2155 | static struct bus_type mce_subsys = { |
e9eee03e | 2156 | .name = "machinecheck", |
8a25a2fd | 2157 | .dev_name = "machinecheck", |
1da177e4 LT |
2158 | }; |
2159 | ||
d6126ef5 | 2160 | DEFINE_PER_CPU(struct device *, mce_device); |
e9eee03e | 2161 | |
e9eee03e | 2162 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); |
1da177e4 | 2163 | |
8a25a2fd | 2164 | static inline struct mce_bank *attr_to_bank(struct device_attribute *attr) |
cebe1820 AK |
2165 | { |
2166 | return container_of(attr, struct mce_bank, attr); | |
2167 | } | |
0d7482e3 | 2168 | |
8a25a2fd | 2169 | static ssize_t show_bank(struct device *s, struct device_attribute *attr, |
0d7482e3 AK |
2170 | char *buf) |
2171 | { | |
cebe1820 | 2172 | return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl); |
0d7482e3 AK |
2173 | } |
2174 | ||
8a25a2fd | 2175 | static ssize_t set_bank(struct device *s, struct device_attribute *attr, |
9319cec8 | 2176 | const char *buf, size_t size) |
0d7482e3 | 2177 | { |
9319cec8 | 2178 | u64 new; |
e9eee03e | 2179 | |
164109e3 | 2180 | if (kstrtou64(buf, 0, &new) < 0) |
0d7482e3 | 2181 | return -EINVAL; |
e9eee03e | 2182 | |
cebe1820 | 2183 | attr_to_bank(attr)->ctl = new; |
0d7482e3 | 2184 | mce_restart(); |
e9eee03e | 2185 | |
9319cec8 | 2186 | return size; |
0d7482e3 | 2187 | } |
a98f0dd3 | 2188 | |
e9eee03e | 2189 | static ssize_t |
8a25a2fd | 2190 | show_trigger(struct device *s, struct device_attribute *attr, char *buf) |
a98f0dd3 | 2191 | { |
1020bcbc | 2192 | strcpy(buf, mce_helper); |
a98f0dd3 | 2193 | strcat(buf, "\n"); |
1020bcbc | 2194 | return strlen(mce_helper) + 1; |
a98f0dd3 AK |
2195 | } |
2196 | ||
8a25a2fd | 2197 | static ssize_t set_trigger(struct device *s, struct device_attribute *attr, |
e9eee03e | 2198 | const char *buf, size_t siz) |
a98f0dd3 AK |
2199 | { |
2200 | char *p; | |
e9eee03e | 2201 | |
1020bcbc HS |
2202 | strncpy(mce_helper, buf, sizeof(mce_helper)); |
2203 | mce_helper[sizeof(mce_helper)-1] = 0; | |
1020bcbc | 2204 | p = strchr(mce_helper, '\n'); |
e9eee03e | 2205 | |
e9084ec9 | 2206 | if (p) |
e9eee03e IM |
2207 | *p = 0; |
2208 | ||
e9084ec9 | 2209 | return strlen(mce_helper) + !!p; |
a98f0dd3 AK |
2210 | } |
2211 | ||
8a25a2fd KS |
2212 | static ssize_t set_ignore_ce(struct device *s, |
2213 | struct device_attribute *attr, | |
9af43b54 HS |
2214 | const char *buf, size_t size) |
2215 | { | |
2216 | u64 new; | |
2217 | ||
164109e3 | 2218 | if (kstrtou64(buf, 0, &new) < 0) |
9af43b54 HS |
2219 | return -EINVAL; |
2220 | ||
7af19e4a | 2221 | if (mca_cfg.ignore_ce ^ !!new) { |
9af43b54 HS |
2222 | if (new) { |
2223 | /* disable ce features */ | |
9aaef96f HS |
2224 | mce_timer_delete_all(); |
2225 | on_each_cpu(mce_disable_cmci, NULL, 1); | |
7af19e4a | 2226 | mca_cfg.ignore_ce = true; |
9af43b54 HS |
2227 | } else { |
2228 | /* enable ce features */ | |
7af19e4a | 2229 | mca_cfg.ignore_ce = false; |
9af43b54 HS |
2230 | on_each_cpu(mce_enable_ce, (void *)1, 1); |
2231 | } | |
2232 | } | |
2233 | return size; | |
2234 | } | |
2235 | ||
8a25a2fd KS |
2236 | static ssize_t set_cmci_disabled(struct device *s, |
2237 | struct device_attribute *attr, | |
9af43b54 HS |
2238 | const char *buf, size_t size) |
2239 | { | |
2240 | u64 new; | |
2241 | ||
164109e3 | 2242 | if (kstrtou64(buf, 0, &new) < 0) |
9af43b54 HS |
2243 | return -EINVAL; |
2244 | ||
7af19e4a | 2245 | if (mca_cfg.cmci_disabled ^ !!new) { |
9af43b54 HS |
2246 | if (new) { |
2247 | /* disable cmci */ | |
9aaef96f | 2248 | on_each_cpu(mce_disable_cmci, NULL, 1); |
7af19e4a | 2249 | mca_cfg.cmci_disabled = true; |
9af43b54 HS |
2250 | } else { |
2251 | /* enable cmci */ | |
7af19e4a | 2252 | mca_cfg.cmci_disabled = false; |
9af43b54 HS |
2253 | on_each_cpu(mce_enable_ce, NULL, 1); |
2254 | } | |
2255 | } | |
2256 | return size; | |
2257 | } | |
2258 | ||
8a25a2fd KS |
2259 | static ssize_t store_int_with_restart(struct device *s, |
2260 | struct device_attribute *attr, | |
b56f642d AK |
2261 | const char *buf, size_t size) |
2262 | { | |
8a25a2fd | 2263 | ssize_t ret = device_store_int(s, attr, buf, size); |
b56f642d AK |
2264 | mce_restart(); |
2265 | return ret; | |
2266 | } | |
2267 | ||
8a25a2fd | 2268 | static DEVICE_ATTR(trigger, 0644, show_trigger, set_trigger); |
d203f0b8 | 2269 | static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant); |
84c2559d | 2270 | static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout); |
d203f0b8 | 2271 | static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce); |
e9eee03e | 2272 | |
8a25a2fd KS |
2273 | static struct dev_ext_attribute dev_attr_check_interval = { |
2274 | __ATTR(check_interval, 0644, device_show_int, store_int_with_restart), | |
b56f642d AK |
2275 | &check_interval |
2276 | }; | |
e9eee03e | 2277 | |
8a25a2fd | 2278 | static struct dev_ext_attribute dev_attr_ignore_ce = { |
7af19e4a BP |
2279 | __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce), |
2280 | &mca_cfg.ignore_ce | |
9af43b54 HS |
2281 | }; |
2282 | ||
8a25a2fd | 2283 | static struct dev_ext_attribute dev_attr_cmci_disabled = { |
7af19e4a BP |
2284 | __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled), |
2285 | &mca_cfg.cmci_disabled | |
9af43b54 HS |
2286 | }; |
2287 | ||
8a25a2fd KS |
2288 | static struct device_attribute *mce_device_attrs[] = { |
2289 | &dev_attr_tolerant.attr, | |
2290 | &dev_attr_check_interval.attr, | |
2291 | &dev_attr_trigger, | |
2292 | &dev_attr_monarch_timeout.attr, | |
2293 | &dev_attr_dont_log_ce.attr, | |
2294 | &dev_attr_ignore_ce.attr, | |
2295 | &dev_attr_cmci_disabled.attr, | |
a98f0dd3 AK |
2296 | NULL |
2297 | }; | |
1da177e4 | 2298 | |
8a25a2fd | 2299 | static cpumask_var_t mce_device_initialized; |
bae19fe0 | 2300 | |
e032d807 GKH |
2301 | static void mce_device_release(struct device *dev) |
2302 | { | |
2303 | kfree(dev); | |
2304 | } | |
2305 | ||
8a25a2fd | 2306 | /* Per cpu device init. All of the cpus still share the same ctrl bank: */ |
148f9bb8 | 2307 | static int mce_device_create(unsigned int cpu) |
1da177e4 | 2308 | { |
e032d807 | 2309 | struct device *dev; |
1da177e4 | 2310 | int err; |
b1f49f95 | 2311 | int i, j; |
92cb7612 | 2312 | |
90367556 | 2313 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
2314 | return -EIO; |
2315 | ||
e032d807 GKH |
2316 | dev = kzalloc(sizeof *dev, GFP_KERNEL); |
2317 | if (!dev) | |
2318 | return -ENOMEM; | |
8a25a2fd KS |
2319 | dev->id = cpu; |
2320 | dev->bus = &mce_subsys; | |
e032d807 | 2321 | dev->release = &mce_device_release; |
91c6d400 | 2322 | |
8a25a2fd | 2323 | err = device_register(dev); |
853d9b18 LK |
2324 | if (err) { |
2325 | put_device(dev); | |
d435d862 | 2326 | return err; |
853d9b18 | 2327 | } |
d435d862 | 2328 | |
8a25a2fd KS |
2329 | for (i = 0; mce_device_attrs[i]; i++) { |
2330 | err = device_create_file(dev, mce_device_attrs[i]); | |
d435d862 AM |
2331 | if (err) |
2332 | goto error; | |
2333 | } | |
d203f0b8 | 2334 | for (j = 0; j < mca_cfg.banks; j++) { |
8a25a2fd | 2335 | err = device_create_file(dev, &mce_banks[j].attr); |
0d7482e3 AK |
2336 | if (err) |
2337 | goto error2; | |
2338 | } | |
8a25a2fd | 2339 | cpumask_set_cpu(cpu, mce_device_initialized); |
d6126ef5 | 2340 | per_cpu(mce_device, cpu) = dev; |
91c6d400 | 2341 | |
d435d862 | 2342 | return 0; |
0d7482e3 | 2343 | error2: |
b1f49f95 | 2344 | while (--j >= 0) |
8a25a2fd | 2345 | device_remove_file(dev, &mce_banks[j].attr); |
d435d862 | 2346 | error: |
cb491fca | 2347 | while (--i >= 0) |
8a25a2fd | 2348 | device_remove_file(dev, mce_device_attrs[i]); |
cb491fca | 2349 | |
8a25a2fd | 2350 | device_unregister(dev); |
d435d862 | 2351 | |
91c6d400 AK |
2352 | return err; |
2353 | } | |
2354 | ||
148f9bb8 | 2355 | static void mce_device_remove(unsigned int cpu) |
91c6d400 | 2356 | { |
d6126ef5 | 2357 | struct device *dev = per_cpu(mce_device, cpu); |
73ca5358 SL |
2358 | int i; |
2359 | ||
8a25a2fd | 2360 | if (!cpumask_test_cpu(cpu, mce_device_initialized)) |
bae19fe0 AH |
2361 | return; |
2362 | ||
8a25a2fd KS |
2363 | for (i = 0; mce_device_attrs[i]; i++) |
2364 | device_remove_file(dev, mce_device_attrs[i]); | |
cb491fca | 2365 | |
d203f0b8 | 2366 | for (i = 0; i < mca_cfg.banks; i++) |
8a25a2fd | 2367 | device_remove_file(dev, &mce_banks[i].attr); |
cb491fca | 2368 | |
8a25a2fd KS |
2369 | device_unregister(dev); |
2370 | cpumask_clear_cpu(cpu, mce_device_initialized); | |
d6126ef5 | 2371 | per_cpu(mce_device, cpu) = NULL; |
91c6d400 | 2372 | } |
91c6d400 | 2373 | |
d6b75584 | 2374 | /* Make sure there are no machine checks on offlined CPUs. */ |
148f9bb8 | 2375 | static void mce_disable_cpu(void *h) |
d6b75584 | 2376 | { |
88ccbedd | 2377 | unsigned long action = *(unsigned long *)h; |
cb491fca | 2378 | int i; |
d6b75584 | 2379 | |
89cbc767 | 2380 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
d6b75584 | 2381 | return; |
767df1bd | 2382 | |
88ccbedd AK |
2383 | if (!(action & CPU_TASKS_FROZEN)) |
2384 | cmci_clear(); | |
d203f0b8 | 2385 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2386 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2387 | |
cebe1820 | 2388 | if (b->init) |
a2d32bcb | 2389 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 2390 | } |
d6b75584 AK |
2391 | } |
2392 | ||
148f9bb8 | 2393 | static void mce_reenable_cpu(void *h) |
d6b75584 | 2394 | { |
88ccbedd | 2395 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 2396 | int i; |
d6b75584 | 2397 | |
89cbc767 | 2398 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
d6b75584 | 2399 | return; |
e9eee03e | 2400 | |
88ccbedd AK |
2401 | if (!(action & CPU_TASKS_FROZEN)) |
2402 | cmci_reenable(); | |
d203f0b8 | 2403 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2404 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2405 | |
cebe1820 | 2406 | if (b->init) |
a2d32bcb | 2407 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
06b7a7a5 | 2408 | } |
d6b75584 AK |
2409 | } |
2410 | ||
91c6d400 | 2411 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
148f9bb8 | 2412 | static int |
e9eee03e | 2413 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) |
91c6d400 AK |
2414 | { |
2415 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 2416 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 | 2417 | |
1a65f970 | 2418 | switch (action & ~CPU_TASKS_FROZEN) { |
bae19fe0 | 2419 | case CPU_ONLINE: |
8a25a2fd | 2420 | mce_device_create(cpu); |
8735728e RW |
2421 | if (threshold_cpu_callback) |
2422 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 2423 | break; |
91c6d400 | 2424 | case CPU_DEAD: |
8735728e RW |
2425 | if (threshold_cpu_callback) |
2426 | threshold_cpu_callback(action, cpu); | |
8a25a2fd | 2427 | mce_device_remove(cpu); |
55babd8f | 2428 | mce_intel_hcpu_update(cpu); |
38356c1f BP |
2429 | |
2430 | /* intentionally ignoring frozen here */ | |
2431 | if (!(action & CPU_TASKS_FROZEN)) | |
2432 | cmci_rediscover(); | |
91c6d400 | 2433 | break; |
52d168e2 | 2434 | case CPU_DOWN_PREPARE: |
88ccbedd | 2435 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
55babd8f | 2436 | del_timer_sync(t); |
52d168e2 AK |
2437 | break; |
2438 | case CPU_DOWN_FAILED: | |
88ccbedd | 2439 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
26c3c283 | 2440 | mce_start_timer(cpu, t); |
88ccbedd | 2441 | break; |
1a65f970 TG |
2442 | } |
2443 | ||
bae19fe0 | 2444 | return NOTIFY_OK; |
91c6d400 AK |
2445 | } |
2446 | ||
148f9bb8 | 2447 | static struct notifier_block mce_cpu_notifier = { |
91c6d400 AK |
2448 | .notifier_call = mce_cpu_callback, |
2449 | }; | |
2450 | ||
cebe1820 | 2451 | static __init void mce_init_banks(void) |
0d7482e3 AK |
2452 | { |
2453 | int i; | |
2454 | ||
d203f0b8 | 2455 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2456 | struct mce_bank *b = &mce_banks[i]; |
8a25a2fd | 2457 | struct device_attribute *a = &b->attr; |
e9eee03e | 2458 | |
a07e4156 | 2459 | sysfs_attr_init(&a->attr); |
cebe1820 AK |
2460 | a->attr.name = b->attrname; |
2461 | snprintf(b->attrname, ATTR_LEN, "bank%d", i); | |
e9eee03e IM |
2462 | |
2463 | a->attr.mode = 0644; | |
2464 | a->show = show_bank; | |
2465 | a->store = set_bank; | |
0d7482e3 | 2466 | } |
0d7482e3 AK |
2467 | } |
2468 | ||
5e09954a | 2469 | static __init int mcheck_init_device(void) |
91c6d400 AK |
2470 | { |
2471 | int err; | |
2472 | int i = 0; | |
2473 | ||
9c15a24b MS |
2474 | if (!mce_available(&boot_cpu_data)) { |
2475 | err = -EIO; | |
2476 | goto err_out; | |
2477 | } | |
0d7482e3 | 2478 | |
9c15a24b MS |
2479 | if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) { |
2480 | err = -ENOMEM; | |
2481 | goto err_out; | |
2482 | } | |
996867d0 | 2483 | |
cebe1820 | 2484 | mce_init_banks(); |
0d7482e3 | 2485 | |
8a25a2fd | 2486 | err = subsys_system_register(&mce_subsys, NULL); |
d435d862 | 2487 | if (err) |
9c15a24b | 2488 | goto err_out_mem; |
91c6d400 | 2489 | |
82a8f131 | 2490 | cpu_notifier_register_begin(); |
91c6d400 | 2491 | for_each_online_cpu(i) { |
8a25a2fd | 2492 | err = mce_device_create(i); |
82a8f131 | 2493 | if (err) { |
27c93415 BP |
2494 | /* |
2495 | * Register notifier anyway (and do not unreg it) so | |
2496 | * that we don't leave undeleted timers, see notifier | |
2497 | * callback above. | |
2498 | */ | |
2499 | __register_hotcpu_notifier(&mce_cpu_notifier); | |
82a8f131 | 2500 | cpu_notifier_register_done(); |
9c15a24b | 2501 | goto err_device_create; |
82a8f131 | 2502 | } |
91c6d400 AK |
2503 | } |
2504 | ||
82a8f131 SB |
2505 | __register_hotcpu_notifier(&mce_cpu_notifier); |
2506 | cpu_notifier_register_done(); | |
93b62c3c | 2507 | |
9c15a24b MS |
2508 | register_syscore_ops(&mce_syscore_ops); |
2509 | ||
93b62c3c | 2510 | /* register character device /dev/mcelog */ |
9c15a24b MS |
2511 | err = misc_register(&mce_chrdev_device); |
2512 | if (err) | |
2513 | goto err_register; | |
2514 | ||
2515 | return 0; | |
2516 | ||
2517 | err_register: | |
2518 | unregister_syscore_ops(&mce_syscore_ops); | |
2519 | ||
9c15a24b MS |
2520 | err_device_create: |
2521 | /* | |
2522 | * We didn't keep track of which devices were created above, but | |
2523 | * even if we had, the set of online cpus might have changed. | |
2524 | * Play safe and remove for every possible cpu, since | |
2525 | * mce_device_remove() will do the right thing. | |
2526 | */ | |
2527 | for_each_possible_cpu(i) | |
2528 | mce_device_remove(i); | |
2529 | ||
2530 | err_out_mem: | |
2531 | free_cpumask_var(mce_device_initialized); | |
2532 | ||
2533 | err_out: | |
2534 | pr_err("Unable to init device /dev/mcelog (rc: %d)\n", err); | |
e9eee03e | 2535 | |
1da177e4 | 2536 | return err; |
1da177e4 | 2537 | } |
cef12ee5 | 2538 | device_initcall_sync(mcheck_init_device); |
a988d334 | 2539 | |
d7c3c9a6 AK |
2540 | /* |
2541 | * Old style boot options parsing. Only for compatibility. | |
2542 | */ | |
2543 | static int __init mcheck_disable(char *str) | |
2544 | { | |
1462594b | 2545 | mca_cfg.disabled = true; |
d7c3c9a6 AK |
2546 | return 1; |
2547 | } | |
2548 | __setup("nomce", mcheck_disable); | |
a988d334 | 2549 | |
5be9ed25 HY |
2550 | #ifdef CONFIG_DEBUG_FS |
2551 | struct dentry *mce_get_debugfs_dir(void) | |
a988d334 | 2552 | { |
5be9ed25 | 2553 | static struct dentry *dmce; |
a988d334 | 2554 | |
5be9ed25 HY |
2555 | if (!dmce) |
2556 | dmce = debugfs_create_dir("mce", NULL); | |
a988d334 | 2557 | |
5be9ed25 HY |
2558 | return dmce; |
2559 | } | |
a988d334 | 2560 | |
bf783f9f HY |
2561 | static void mce_reset(void) |
2562 | { | |
2563 | cpu_missing = 0; | |
c7c9b392 | 2564 | atomic_set(&mce_fake_panicked, 0); |
bf783f9f HY |
2565 | atomic_set(&mce_executing, 0); |
2566 | atomic_set(&mce_callin, 0); | |
2567 | atomic_set(&global_nwo, 0); | |
2568 | } | |
a988d334 | 2569 | |
bf783f9f HY |
2570 | static int fake_panic_get(void *data, u64 *val) |
2571 | { | |
2572 | *val = fake_panic; | |
2573 | return 0; | |
a988d334 IM |
2574 | } |
2575 | ||
bf783f9f | 2576 | static int fake_panic_set(void *data, u64 val) |
a988d334 | 2577 | { |
bf783f9f HY |
2578 | mce_reset(); |
2579 | fake_panic = val; | |
2580 | return 0; | |
a988d334 | 2581 | } |
a988d334 | 2582 | |
bf783f9f HY |
2583 | DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get, |
2584 | fake_panic_set, "%llu\n"); | |
d7c3c9a6 | 2585 | |
5e09954a | 2586 | static int __init mcheck_debugfs_init(void) |
d7c3c9a6 | 2587 | { |
bf783f9f HY |
2588 | struct dentry *dmce, *ffake_panic; |
2589 | ||
2590 | dmce = mce_get_debugfs_dir(); | |
2591 | if (!dmce) | |
2592 | return -ENOMEM; | |
2593 | ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL, | |
2594 | &fake_panic_fops); | |
2595 | if (!ffake_panic) | |
2596 | return -ENOMEM; | |
2597 | ||
2598 | return 0; | |
d7c3c9a6 | 2599 | } |
5e09954a | 2600 | late_initcall(mcheck_debugfs_init); |
5be9ed25 | 2601 | #endif |