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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
e9eee03e IM |
10 | #include <linux/thread_info.h> |
11 | #include <linux/capability.h> | |
12 | #include <linux/miscdevice.h> | |
ccc3c319 | 13 | #include <linux/interrupt.h> |
e9eee03e IM |
14 | #include <linux/ratelimit.h> |
15 | #include <linux/kallsyms.h> | |
16 | #include <linux/rcupdate.h> | |
e9eee03e | 17 | #include <linux/kobject.h> |
14a02530 | 18 | #include <linux/uaccess.h> |
e9eee03e IM |
19 | #include <linux/kdebug.h> |
20 | #include <linux/kernel.h> | |
21 | #include <linux/percpu.h> | |
1da177e4 | 22 | #include <linux/string.h> |
1da177e4 | 23 | #include <linux/sysdev.h> |
3c079792 | 24 | #include <linux/delay.h> |
8c566ef5 | 25 | #include <linux/ctype.h> |
e9eee03e | 26 | #include <linux/sched.h> |
0d7482e3 | 27 | #include <linux/sysfs.h> |
e9eee03e | 28 | #include <linux/types.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
e9eee03e IM |
30 | #include <linux/init.h> |
31 | #include <linux/kmod.h> | |
32 | #include <linux/poll.h> | |
3c079792 | 33 | #include <linux/nmi.h> |
e9eee03e | 34 | #include <linux/cpu.h> |
14a02530 | 35 | #include <linux/smp.h> |
e9eee03e | 36 | #include <linux/fs.h> |
9b1beaf2 | 37 | #include <linux/mm.h> |
5be9ed25 | 38 | #include <linux/debugfs.h> |
696e409d | 39 | #include <linux/edac_mce.h> |
e9eee03e | 40 | |
d88203d1 | 41 | #include <asm/processor.h> |
ccc3c319 AK |
42 | #include <asm/hw_irq.h> |
43 | #include <asm/apic.h> | |
e02e68d3 | 44 | #include <asm/idle.h> |
ccc3c319 | 45 | #include <asm/ipi.h> |
e9eee03e IM |
46 | #include <asm/mce.h> |
47 | #include <asm/msr.h> | |
1da177e4 | 48 | |
bd19a5e6 | 49 | #include "mce-internal.h" |
711c2e48 | 50 | |
2aa2b50d IM |
51 | static DEFINE_MUTEX(mce_read_mutex); |
52 | ||
f56e8a07 | 53 | #define rcu_dereference_check_mce(p) \ |
ec8c27e0 | 54 | rcu_dereference_index_check((p), \ |
f56e8a07 PM |
55 | rcu_read_lock_sched_held() || \ |
56 | lockdep_is_held(&mce_read_mutex)) | |
57 | ||
8968f9d3 HS |
58 | #define CREATE_TRACE_POINTS |
59 | #include <trace/events/mce.h> | |
60 | ||
4e5b3e69 | 61 | int mce_disabled __read_mostly; |
04b2b1a4 | 62 | |
e9eee03e | 63 | #define MISC_MCELOG_MINOR 227 |
0d7482e3 | 64 | |
3c079792 AK |
65 | #define SPINUNIT 100 /* 100ns */ |
66 | ||
553f265f AK |
67 | atomic_t mce_entry; |
68 | ||
01ca79f1 AK |
69 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
70 | ||
bd78432c TH |
71 | /* |
72 | * Tolerant levels: | |
73 | * 0: always panic on uncorrected errors, log corrected errors | |
74 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
75 | * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors | |
76 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
77 | */ | |
4e5b3e69 HS |
78 | static int tolerant __read_mostly = 1; |
79 | static int banks __read_mostly; | |
4e5b3e69 HS |
80 | static int rip_msr __read_mostly; |
81 | static int mce_bootlog __read_mostly = -1; | |
82 | static int monarch_timeout __read_mostly = -1; | |
83 | static int mce_panic_timeout __read_mostly; | |
84 | static int mce_dont_log_ce __read_mostly; | |
85 | int mce_cmci_disabled __read_mostly; | |
86 | int mce_ignore_ce __read_mostly; | |
87 | int mce_ser __read_mostly; | |
a98f0dd3 | 88 | |
cebe1820 AK |
89 | struct mce_bank *mce_banks __read_mostly; |
90 | ||
1020bcbc HS |
91 | /* User mode helper program triggered by machine check event */ |
92 | static unsigned long mce_need_notify; | |
93 | static char mce_helper[128]; | |
94 | static char *mce_helper_argv[2] = { mce_helper, NULL }; | |
1da177e4 | 95 | |
e02e68d3 | 96 | static DECLARE_WAIT_QUEUE_HEAD(mce_wait); |
3c079792 AK |
97 | static DEFINE_PER_CPU(struct mce, mces_seen); |
98 | static int cpu_missing; | |
99 | ||
fb253195 BP |
100 | /* |
101 | * CPU/chipset specific EDAC code can register a notifier call here to print | |
102 | * MCE errors in a human-readable form. | |
103 | */ | |
104 | ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain); | |
105 | EXPORT_SYMBOL_GPL(x86_mce_decoder_chain); | |
106 | ||
107 | static int default_decode_mce(struct notifier_block *nb, unsigned long val, | |
108 | void *data) | |
f436f8bb | 109 | { |
a2d7b0d4 HY |
110 | pr_emerg(HW_ERR "No human readable MCE decoding support on this CPU type.\n"); |
111 | pr_emerg(HW_ERR "Run the message through 'mcelog --ascii' to decode.\n"); | |
fb253195 BP |
112 | |
113 | return NOTIFY_STOP; | |
f436f8bb IM |
114 | } |
115 | ||
fb253195 BP |
116 | static struct notifier_block mce_dec_nb = { |
117 | .notifier_call = default_decode_mce, | |
118 | .priority = -1, | |
119 | }; | |
e02e68d3 | 120 | |
ee031c31 AK |
121 | /* MCA banks polled by the period polling timer for corrected events */ |
122 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { | |
123 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
124 | }; | |
125 | ||
9b1beaf2 AK |
126 | static DEFINE_PER_CPU(struct work_struct, mce_work); |
127 | ||
b5f2fa4e AK |
128 | /* Do initial initialization of a struct mce */ |
129 | void mce_setup(struct mce *m) | |
130 | { | |
131 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 132 | m->cpu = m->extcpu = smp_processor_id(); |
b5f2fa4e | 133 | rdtscll(m->tsc); |
8ee08347 AK |
134 | /* We hope get_seconds stays lockless */ |
135 | m->time = get_seconds(); | |
136 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
137 | m->cpuid = cpuid_eax(1); | |
138 | #ifdef CONFIG_SMP | |
139 | m->socketid = cpu_data(m->extcpu).phys_proc_id; | |
140 | #endif | |
141 | m->apicid = cpu_data(m->extcpu).initial_apicid; | |
142 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
b5f2fa4e AK |
143 | } |
144 | ||
ea149b36 AK |
145 | DEFINE_PER_CPU(struct mce, injectm); |
146 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
147 | ||
1da177e4 LT |
148 | /* |
149 | * Lockless MCE logging infrastructure. | |
150 | * This avoids deadlocks on printk locks without having to break locks. Also | |
151 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
152 | */ | |
153 | ||
231fd906 | 154 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
155 | .signature = MCE_LOG_SIGNATURE, |
156 | .len = MCE_LOG_LEN, | |
157 | .recordlen = sizeof(struct mce), | |
d88203d1 | 158 | }; |
1da177e4 LT |
159 | |
160 | void mce_log(struct mce *mce) | |
161 | { | |
162 | unsigned next, entry; | |
e9eee03e | 163 | |
8968f9d3 HS |
164 | /* Emit the trace record: */ |
165 | trace_mce_record(mce); | |
166 | ||
1da177e4 | 167 | mce->finished = 0; |
7644143c | 168 | wmb(); |
1da177e4 | 169 | for (;;) { |
f56e8a07 | 170 | entry = rcu_dereference_check_mce(mcelog.next); |
673242c1 | 171 | for (;;) { |
696e409d MCC |
172 | /* |
173 | * If edac_mce is enabled, it will check the error type | |
174 | * and will process it, if it is a known error. | |
175 | * Otherwise, the error will be sent through mcelog | |
176 | * interface | |
177 | */ | |
178 | if (edac_mce_parse(mce)) | |
179 | return; | |
180 | ||
e9eee03e IM |
181 | /* |
182 | * When the buffer fills up discard new entries. | |
183 | * Assume that the earlier errors are the more | |
184 | * interesting ones: | |
185 | */ | |
673242c1 | 186 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
187 | set_bit(MCE_OVERFLOW, |
188 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
189 | return; |
190 | } | |
e9eee03e | 191 | /* Old left over entry. Skip: */ |
673242c1 AK |
192 | if (mcelog.entry[entry].finished) { |
193 | entry++; | |
194 | continue; | |
195 | } | |
7644143c | 196 | break; |
1da177e4 | 197 | } |
1da177e4 LT |
198 | smp_rmb(); |
199 | next = entry + 1; | |
200 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
201 | break; | |
202 | } | |
203 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 204 | wmb(); |
1da177e4 | 205 | mcelog.entry[entry].finished = 1; |
7644143c | 206 | wmb(); |
1da177e4 | 207 | |
a0189c70 | 208 | mce->finished = 1; |
1020bcbc | 209 | set_bit(0, &mce_need_notify); |
1da177e4 LT |
210 | } |
211 | ||
77e26cca | 212 | static void print_mce(struct mce *m) |
1da177e4 | 213 | { |
a2d7b0d4 | 214 | pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n", |
d620c67f | 215 | m->extcpu, m->mcgstatus, m->bank, m->status); |
f436f8bb | 216 | |
65ea5b03 | 217 | if (m->ip) { |
a2d7b0d4 | 218 | pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", |
f436f8bb IM |
219 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
220 | m->cs, m->ip); | |
221 | ||
1da177e4 | 222 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 223 | print_symbol("{%s}", m->ip); |
f436f8bb | 224 | pr_cont("\n"); |
1da177e4 | 225 | } |
f436f8bb | 226 | |
a2d7b0d4 | 227 | pr_emerg(HW_ERR "TSC %llx ", m->tsc); |
1da177e4 | 228 | if (m->addr) |
f436f8bb | 229 | pr_cont("ADDR %llx ", m->addr); |
1da177e4 | 230 | if (m->misc) |
f436f8bb | 231 | pr_cont("MISC %llx ", m->misc); |
549d042d | 232 | |
f436f8bb | 233 | pr_cont("\n"); |
a2d7b0d4 | 234 | pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n", |
f436f8bb IM |
235 | m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid); |
236 | ||
237 | /* | |
238 | * Print out human-readable details about the MCE error, | |
fb253195 | 239 | * (if the CPU has an implementation for that) |
f436f8bb | 240 | */ |
fb253195 | 241 | atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); |
86503560 AK |
242 | } |
243 | ||
f94b61c2 AK |
244 | #define PANIC_TIMEOUT 5 /* 5 seconds */ |
245 | ||
246 | static atomic_t mce_paniced; | |
247 | ||
bf783f9f HY |
248 | static int fake_panic; |
249 | static atomic_t mce_fake_paniced; | |
250 | ||
f94b61c2 AK |
251 | /* Panic in progress. Enable interrupts and wait for final IPI */ |
252 | static void wait_for_panic(void) | |
253 | { | |
254 | long timeout = PANIC_TIMEOUT*USEC_PER_SEC; | |
f436f8bb | 255 | |
f94b61c2 AK |
256 | preempt_disable(); |
257 | local_irq_enable(); | |
258 | while (timeout-- > 0) | |
259 | udelay(1); | |
29b0f591 AK |
260 | if (panic_timeout == 0) |
261 | panic_timeout = mce_panic_timeout; | |
f94b61c2 AK |
262 | panic("Panicing machine check CPU died"); |
263 | } | |
264 | ||
bd19a5e6 | 265 | static void mce_panic(char *msg, struct mce *final, char *exp) |
d88203d1 | 266 | { |
482908b4 | 267 | int i, apei_err = 0; |
e02e68d3 | 268 | |
bf783f9f HY |
269 | if (!fake_panic) { |
270 | /* | |
271 | * Make sure only one CPU runs in machine check panic | |
272 | */ | |
273 | if (atomic_inc_return(&mce_paniced) > 1) | |
274 | wait_for_panic(); | |
275 | barrier(); | |
f94b61c2 | 276 | |
bf783f9f HY |
277 | bust_spinlocks(1); |
278 | console_verbose(); | |
279 | } else { | |
280 | /* Don't log too much for fake panic */ | |
281 | if (atomic_inc_return(&mce_fake_paniced) > 1) | |
282 | return; | |
283 | } | |
a0189c70 | 284 | /* First print corrected ones that are still unlogged */ |
1da177e4 | 285 | for (i = 0; i < MCE_LOG_LEN; i++) { |
a0189c70 | 286 | struct mce *m = &mcelog.entry[i]; |
77e26cca HS |
287 | if (!(m->status & MCI_STATUS_VAL)) |
288 | continue; | |
482908b4 | 289 | if (!(m->status & MCI_STATUS_UC)) { |
77e26cca | 290 | print_mce(m); |
482908b4 HY |
291 | if (!apei_err) |
292 | apei_err = apei_write_mce(m); | |
293 | } | |
a0189c70 AK |
294 | } |
295 | /* Now print uncorrected but with the final one last */ | |
296 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
297 | struct mce *m = &mcelog.entry[i]; | |
298 | if (!(m->status & MCI_STATUS_VAL)) | |
1da177e4 | 299 | continue; |
77e26cca HS |
300 | if (!(m->status & MCI_STATUS_UC)) |
301 | continue; | |
482908b4 | 302 | if (!final || memcmp(m, final, sizeof(struct mce))) { |
77e26cca | 303 | print_mce(m); |
482908b4 HY |
304 | if (!apei_err) |
305 | apei_err = apei_write_mce(m); | |
306 | } | |
1da177e4 | 307 | } |
482908b4 | 308 | if (final) { |
77e26cca | 309 | print_mce(final); |
482908b4 HY |
310 | if (!apei_err) |
311 | apei_err = apei_write_mce(final); | |
312 | } | |
3c079792 | 313 | if (cpu_missing) |
a2d7b0d4 | 314 | pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n"); |
bd19a5e6 | 315 | if (exp) |
a2d7b0d4 | 316 | pr_emerg(HW_ERR "Machine check: %s\n", exp); |
bf783f9f HY |
317 | if (!fake_panic) { |
318 | if (panic_timeout == 0) | |
319 | panic_timeout = mce_panic_timeout; | |
320 | panic(msg); | |
321 | } else | |
a2d7b0d4 | 322 | pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); |
d88203d1 | 323 | } |
1da177e4 | 324 | |
ea149b36 AK |
325 | /* Support code for software error injection */ |
326 | ||
327 | static int msr_to_offset(u32 msr) | |
328 | { | |
329 | unsigned bank = __get_cpu_var(injectm.bank); | |
f436f8bb | 330 | |
ea149b36 AK |
331 | if (msr == rip_msr) |
332 | return offsetof(struct mce, ip); | |
a2d32bcb | 333 | if (msr == MSR_IA32_MCx_STATUS(bank)) |
ea149b36 | 334 | return offsetof(struct mce, status); |
a2d32bcb | 335 | if (msr == MSR_IA32_MCx_ADDR(bank)) |
ea149b36 | 336 | return offsetof(struct mce, addr); |
a2d32bcb | 337 | if (msr == MSR_IA32_MCx_MISC(bank)) |
ea149b36 AK |
338 | return offsetof(struct mce, misc); |
339 | if (msr == MSR_IA32_MCG_STATUS) | |
340 | return offsetof(struct mce, mcgstatus); | |
341 | return -1; | |
342 | } | |
343 | ||
5f8c1a54 AK |
344 | /* MSR access wrappers used for error injection */ |
345 | static u64 mce_rdmsrl(u32 msr) | |
346 | { | |
347 | u64 v; | |
11868a2d | 348 | |
ea149b36 AK |
349 | if (__get_cpu_var(injectm).finished) { |
350 | int offset = msr_to_offset(msr); | |
11868a2d | 351 | |
ea149b36 AK |
352 | if (offset < 0) |
353 | return 0; | |
354 | return *(u64 *)((char *)&__get_cpu_var(injectm) + offset); | |
355 | } | |
11868a2d IM |
356 | |
357 | if (rdmsrl_safe(msr, &v)) { | |
358 | WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr); | |
359 | /* | |
360 | * Return zero in case the access faulted. This should | |
361 | * not happen normally but can happen if the CPU does | |
362 | * something weird, or if the code is buggy. | |
363 | */ | |
364 | v = 0; | |
365 | } | |
366 | ||
5f8c1a54 AK |
367 | return v; |
368 | } | |
369 | ||
370 | static void mce_wrmsrl(u32 msr, u64 v) | |
371 | { | |
ea149b36 AK |
372 | if (__get_cpu_var(injectm).finished) { |
373 | int offset = msr_to_offset(msr); | |
11868a2d | 374 | |
ea149b36 AK |
375 | if (offset >= 0) |
376 | *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v; | |
377 | return; | |
378 | } | |
5f8c1a54 AK |
379 | wrmsrl(msr, v); |
380 | } | |
381 | ||
9b1beaf2 AK |
382 | /* |
383 | * Simple lockless ring to communicate PFNs from the exception handler with the | |
384 | * process context work function. This is vastly simplified because there's | |
385 | * only a single reader and a single writer. | |
386 | */ | |
387 | #define MCE_RING_SIZE 16 /* we use one entry less */ | |
388 | ||
389 | struct mce_ring { | |
390 | unsigned short start; | |
391 | unsigned short end; | |
392 | unsigned long ring[MCE_RING_SIZE]; | |
393 | }; | |
394 | static DEFINE_PER_CPU(struct mce_ring, mce_ring); | |
395 | ||
396 | /* Runs with CPU affinity in workqueue */ | |
397 | static int mce_ring_empty(void) | |
398 | { | |
399 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
400 | ||
401 | return r->start == r->end; | |
402 | } | |
403 | ||
404 | static int mce_ring_get(unsigned long *pfn) | |
405 | { | |
406 | struct mce_ring *r; | |
407 | int ret = 0; | |
408 | ||
409 | *pfn = 0; | |
410 | get_cpu(); | |
411 | r = &__get_cpu_var(mce_ring); | |
412 | if (r->start == r->end) | |
413 | goto out; | |
414 | *pfn = r->ring[r->start]; | |
415 | r->start = (r->start + 1) % MCE_RING_SIZE; | |
416 | ret = 1; | |
417 | out: | |
418 | put_cpu(); | |
419 | return ret; | |
420 | } | |
421 | ||
422 | /* Always runs in MCE context with preempt off */ | |
423 | static int mce_ring_add(unsigned long pfn) | |
424 | { | |
425 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
426 | unsigned next; | |
427 | ||
428 | next = (r->end + 1) % MCE_RING_SIZE; | |
429 | if (next == r->start) | |
430 | return -1; | |
431 | r->ring[r->end] = pfn; | |
432 | wmb(); | |
433 | r->end = next; | |
434 | return 0; | |
435 | } | |
436 | ||
88ccbedd | 437 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 438 | { |
04b2b1a4 | 439 | if (mce_disabled) |
5b4408fd | 440 | return 0; |
3d1712c9 | 441 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
442 | } |
443 | ||
9b1beaf2 AK |
444 | static void mce_schedule_work(void) |
445 | { | |
446 | if (!mce_ring_empty()) { | |
447 | struct work_struct *work = &__get_cpu_var(mce_work); | |
448 | if (!work_pending(work)) | |
449 | schedule_work(work); | |
450 | } | |
451 | } | |
452 | ||
1b2797dc HY |
453 | /* |
454 | * Get the address of the instruction at the time of the machine check | |
455 | * error. | |
456 | */ | |
94ad8474 AK |
457 | static inline void mce_get_rip(struct mce *m, struct pt_regs *regs) |
458 | { | |
1b2797dc HY |
459 | |
460 | if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) { | |
65ea5b03 | 461 | m->ip = regs->ip; |
94ad8474 AK |
462 | m->cs = regs->cs; |
463 | } else { | |
65ea5b03 | 464 | m->ip = 0; |
94ad8474 AK |
465 | m->cs = 0; |
466 | } | |
1b2797dc | 467 | if (rip_msr) |
5f8c1a54 | 468 | m->ip = mce_rdmsrl(rip_msr); |
94ad8474 AK |
469 | } |
470 | ||
11868a2d | 471 | #ifdef CONFIG_X86_LOCAL_APIC |
ccc3c319 AK |
472 | /* |
473 | * Called after interrupts have been reenabled again | |
474 | * when a MCE happened during an interrupts off region | |
475 | * in the kernel. | |
476 | */ | |
477 | asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs) | |
478 | { | |
479 | ack_APIC_irq(); | |
480 | exit_idle(); | |
481 | irq_enter(); | |
9ff36ee9 | 482 | mce_notify_irq(); |
9b1beaf2 | 483 | mce_schedule_work(); |
ccc3c319 AK |
484 | irq_exit(); |
485 | } | |
486 | #endif | |
487 | ||
488 | static void mce_report_event(struct pt_regs *regs) | |
489 | { | |
490 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { | |
9ff36ee9 | 491 | mce_notify_irq(); |
9b1beaf2 AK |
492 | /* |
493 | * Triggering the work queue here is just an insurance | |
494 | * policy in case the syscall exit notify handler | |
495 | * doesn't run soon enough or ends up running on the | |
496 | * wrong CPU (can happen when audit sleeps) | |
497 | */ | |
498 | mce_schedule_work(); | |
ccc3c319 AK |
499 | return; |
500 | } | |
501 | ||
502 | #ifdef CONFIG_X86_LOCAL_APIC | |
503 | /* | |
504 | * Without APIC do not notify. The event will be picked | |
505 | * up eventually. | |
506 | */ | |
507 | if (!cpu_has_apic) | |
508 | return; | |
509 | ||
510 | /* | |
511 | * When interrupts are disabled we cannot use | |
512 | * kernel services safely. Trigger an self interrupt | |
513 | * through the APIC to instead do the notification | |
514 | * after interrupts are reenabled again. | |
515 | */ | |
516 | apic->send_IPI_self(MCE_SELF_VECTOR); | |
517 | ||
518 | /* | |
519 | * Wait for idle afterwards again so that we don't leave the | |
520 | * APIC in a non idle state because the normal APIC writes | |
521 | * cannot exclude us. | |
522 | */ | |
523 | apic_wait_icr_idle(); | |
524 | #endif | |
525 | } | |
526 | ||
ca84f696 AK |
527 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
528 | ||
d88203d1 | 529 | /* |
b79109c3 AK |
530 | * Poll for corrected events or events that happened before reset. |
531 | * Those are just logged through /dev/mcelog. | |
532 | * | |
533 | * This is executed in standard interrupt context. | |
ed7290d0 AK |
534 | * |
535 | * Note: spec recommends to panic for fatal unsignalled | |
536 | * errors here. However this would be quite problematic -- | |
537 | * we would need to reimplement the Monarch handling and | |
538 | * it would mess up the exclusion between exception handler | |
539 | * and poll hander -- * so we skip this for now. | |
540 | * These cases should not happen anyways, or only when the CPU | |
541 | * is already totally * confused. In this case it's likely it will | |
542 | * not fully execute the machine check handler either. | |
b79109c3 | 543 | */ |
ee031c31 | 544 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 AK |
545 | { |
546 | struct mce m; | |
547 | int i; | |
548 | ||
402af0d7 | 549 | percpu_inc(mce_poll_count); |
ca84f696 | 550 | |
b79109c3 AK |
551 | mce_setup(&m); |
552 | ||
5f8c1a54 | 553 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
b79109c3 | 554 | for (i = 0; i < banks; i++) { |
cebe1820 | 555 | if (!mce_banks[i].ctl || !test_bit(i, *b)) |
b79109c3 AK |
556 | continue; |
557 | ||
558 | m.misc = 0; | |
559 | m.addr = 0; | |
560 | m.bank = i; | |
561 | m.tsc = 0; | |
562 | ||
563 | barrier(); | |
a2d32bcb | 564 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
b79109c3 AK |
565 | if (!(m.status & MCI_STATUS_VAL)) |
566 | continue; | |
567 | ||
568 | /* | |
ed7290d0 AK |
569 | * Uncorrected or signalled events are handled by the exception |
570 | * handler when it is enabled, so don't process those here. | |
b79109c3 AK |
571 | * |
572 | * TBD do the same check for MCI_STATUS_EN here? | |
573 | */ | |
ed7290d0 AK |
574 | if (!(flags & MCP_UC) && |
575 | (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC))) | |
b79109c3 AK |
576 | continue; |
577 | ||
578 | if (m.status & MCI_STATUS_MISCV) | |
a2d32bcb | 579 | m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); |
b79109c3 | 580 | if (m.status & MCI_STATUS_ADDRV) |
a2d32bcb | 581 | m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); |
b79109c3 AK |
582 | |
583 | if (!(flags & MCP_TIMESTAMP)) | |
584 | m.tsc = 0; | |
585 | /* | |
586 | * Don't get the IP here because it's unlikely to | |
587 | * have anything to do with the actual error location. | |
588 | */ | |
62fdac59 | 589 | if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) { |
5679af4c | 590 | mce_log(&m); |
98a5ae2d | 591 | atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, &m); |
5679af4c AK |
592 | add_taint(TAINT_MACHINE_CHECK); |
593 | } | |
b79109c3 AK |
594 | |
595 | /* | |
596 | * Clear state for this bank. | |
597 | */ | |
a2d32bcb | 598 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
b79109c3 AK |
599 | } |
600 | ||
601 | /* | |
602 | * Don't clear MCG_STATUS here because it's only defined for | |
603 | * exceptions. | |
604 | */ | |
88921be3 AK |
605 | |
606 | sync_core(); | |
b79109c3 | 607 | } |
ea149b36 | 608 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 | 609 | |
bd19a5e6 AK |
610 | /* |
611 | * Do a quick check if any of the events requires a panic. | |
612 | * This decides if we keep the events around or clear them. | |
613 | */ | |
614 | static int mce_no_way_out(struct mce *m, char **msg) | |
615 | { | |
616 | int i; | |
617 | ||
618 | for (i = 0; i < banks; i++) { | |
a2d32bcb | 619 | m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
bd19a5e6 AK |
620 | if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY) |
621 | return 1; | |
622 | } | |
623 | return 0; | |
624 | } | |
625 | ||
3c079792 AK |
626 | /* |
627 | * Variable to establish order between CPUs while scanning. | |
628 | * Each CPU spins initially until executing is equal its number. | |
629 | */ | |
630 | static atomic_t mce_executing; | |
631 | ||
632 | /* | |
633 | * Defines order of CPUs on entry. First CPU becomes Monarch. | |
634 | */ | |
635 | static atomic_t mce_callin; | |
636 | ||
637 | /* | |
638 | * Check if a timeout waiting for other CPUs happened. | |
639 | */ | |
640 | static int mce_timed_out(u64 *t) | |
641 | { | |
642 | /* | |
643 | * The others already did panic for some reason. | |
644 | * Bail out like in a timeout. | |
645 | * rmb() to tell the compiler that system_state | |
646 | * might have been modified by someone else. | |
647 | */ | |
648 | rmb(); | |
649 | if (atomic_read(&mce_paniced)) | |
650 | wait_for_panic(); | |
651 | if (!monarch_timeout) | |
652 | goto out; | |
653 | if ((s64)*t < SPINUNIT) { | |
654 | /* CHECKME: Make panic default for 1 too? */ | |
655 | if (tolerant < 1) | |
656 | mce_panic("Timeout synchronizing machine check over CPUs", | |
657 | NULL, NULL); | |
658 | cpu_missing = 1; | |
659 | return 1; | |
660 | } | |
661 | *t -= SPINUNIT; | |
662 | out: | |
663 | touch_nmi_watchdog(); | |
664 | return 0; | |
665 | } | |
666 | ||
667 | /* | |
668 | * The Monarch's reign. The Monarch is the CPU who entered | |
669 | * the machine check handler first. It waits for the others to | |
670 | * raise the exception too and then grades them. When any | |
671 | * error is fatal panic. Only then let the others continue. | |
672 | * | |
673 | * The other CPUs entering the MCE handler will be controlled by the | |
674 | * Monarch. They are called Subjects. | |
675 | * | |
676 | * This way we prevent any potential data corruption in a unrecoverable case | |
677 | * and also makes sure always all CPU's errors are examined. | |
678 | * | |
680b6cfd | 679 | * Also this detects the case of a machine check event coming from outer |
3c079792 AK |
680 | * space (not detected by any CPUs) In this case some external agent wants |
681 | * us to shut down, so panic too. | |
682 | * | |
683 | * The other CPUs might still decide to panic if the handler happens | |
684 | * in a unrecoverable place, but in this case the system is in a semi-stable | |
685 | * state and won't corrupt anything by itself. It's ok to let the others | |
686 | * continue for a bit first. | |
687 | * | |
688 | * All the spin loops have timeouts; when a timeout happens a CPU | |
689 | * typically elects itself to be Monarch. | |
690 | */ | |
691 | static void mce_reign(void) | |
692 | { | |
693 | int cpu; | |
694 | struct mce *m = NULL; | |
695 | int global_worst = 0; | |
696 | char *msg = NULL; | |
697 | char *nmsg = NULL; | |
698 | ||
699 | /* | |
700 | * This CPU is the Monarch and the other CPUs have run | |
701 | * through their handlers. | |
702 | * Grade the severity of the errors of all the CPUs. | |
703 | */ | |
704 | for_each_possible_cpu(cpu) { | |
705 | int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant, | |
706 | &nmsg); | |
707 | if (severity > global_worst) { | |
708 | msg = nmsg; | |
709 | global_worst = severity; | |
710 | m = &per_cpu(mces_seen, cpu); | |
711 | } | |
712 | } | |
713 | ||
714 | /* | |
715 | * Cannot recover? Panic here then. | |
716 | * This dumps all the mces in the log buffer and stops the | |
717 | * other CPUs. | |
718 | */ | |
719 | if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3) | |
ac960375 | 720 | mce_panic("Fatal Machine check", m, msg); |
3c079792 AK |
721 | |
722 | /* | |
723 | * For UC somewhere we let the CPU who detects it handle it. | |
724 | * Also must let continue the others, otherwise the handling | |
725 | * CPU could deadlock on a lock. | |
726 | */ | |
727 | ||
728 | /* | |
729 | * No machine check event found. Must be some external | |
730 | * source or one CPU is hung. Panic. | |
731 | */ | |
680b6cfd | 732 | if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3) |
3c079792 AK |
733 | mce_panic("Machine check from unknown source", NULL, NULL); |
734 | ||
735 | /* | |
736 | * Now clear all the mces_seen so that they don't reappear on | |
737 | * the next mce. | |
738 | */ | |
739 | for_each_possible_cpu(cpu) | |
740 | memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); | |
741 | } | |
742 | ||
743 | static atomic_t global_nwo; | |
744 | ||
745 | /* | |
746 | * Start of Monarch synchronization. This waits until all CPUs have | |
747 | * entered the exception handler and then determines if any of them | |
748 | * saw a fatal event that requires panic. Then it executes them | |
749 | * in the entry order. | |
750 | * TBD double check parallel CPU hotunplug | |
751 | */ | |
7fb06fc9 | 752 | static int mce_start(int *no_way_out) |
3c079792 | 753 | { |
7fb06fc9 | 754 | int order; |
3c079792 AK |
755 | int cpus = num_online_cpus(); |
756 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
757 | ||
7fb06fc9 HS |
758 | if (!timeout) |
759 | return -1; | |
3c079792 | 760 | |
7fb06fc9 | 761 | atomic_add(*no_way_out, &global_nwo); |
184e1fdf HY |
762 | /* |
763 | * global_nwo should be updated before mce_callin | |
764 | */ | |
765 | smp_wmb(); | |
a95436e4 | 766 | order = atomic_inc_return(&mce_callin); |
3c079792 AK |
767 | |
768 | /* | |
769 | * Wait for everyone. | |
770 | */ | |
771 | while (atomic_read(&mce_callin) != cpus) { | |
772 | if (mce_timed_out(&timeout)) { | |
773 | atomic_set(&global_nwo, 0); | |
7fb06fc9 | 774 | return -1; |
3c079792 AK |
775 | } |
776 | ndelay(SPINUNIT); | |
777 | } | |
778 | ||
184e1fdf HY |
779 | /* |
780 | * mce_callin should be read before global_nwo | |
781 | */ | |
782 | smp_rmb(); | |
3c079792 | 783 | |
7fb06fc9 HS |
784 | if (order == 1) { |
785 | /* | |
786 | * Monarch: Starts executing now, the others wait. | |
787 | */ | |
3c079792 | 788 | atomic_set(&mce_executing, 1); |
7fb06fc9 HS |
789 | } else { |
790 | /* | |
791 | * Subject: Now start the scanning loop one by one in | |
792 | * the original callin order. | |
793 | * This way when there are any shared banks it will be | |
794 | * only seen by one CPU before cleared, avoiding duplicates. | |
795 | */ | |
796 | while (atomic_read(&mce_executing) < order) { | |
797 | if (mce_timed_out(&timeout)) { | |
798 | atomic_set(&global_nwo, 0); | |
799 | return -1; | |
800 | } | |
801 | ndelay(SPINUNIT); | |
802 | } | |
3c079792 AK |
803 | } |
804 | ||
805 | /* | |
7fb06fc9 | 806 | * Cache the global no_way_out state. |
3c079792 | 807 | */ |
7fb06fc9 HS |
808 | *no_way_out = atomic_read(&global_nwo); |
809 | ||
810 | return order; | |
3c079792 AK |
811 | } |
812 | ||
813 | /* | |
814 | * Synchronize between CPUs after main scanning loop. | |
815 | * This invokes the bulk of the Monarch processing. | |
816 | */ | |
817 | static int mce_end(int order) | |
818 | { | |
819 | int ret = -1; | |
820 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
821 | ||
822 | if (!timeout) | |
823 | goto reset; | |
824 | if (order < 0) | |
825 | goto reset; | |
826 | ||
827 | /* | |
828 | * Allow others to run. | |
829 | */ | |
830 | atomic_inc(&mce_executing); | |
831 | ||
832 | if (order == 1) { | |
833 | /* CHECKME: Can this race with a parallel hotplug? */ | |
834 | int cpus = num_online_cpus(); | |
835 | ||
836 | /* | |
837 | * Monarch: Wait for everyone to go through their scanning | |
838 | * loops. | |
839 | */ | |
840 | while (atomic_read(&mce_executing) <= cpus) { | |
841 | if (mce_timed_out(&timeout)) | |
842 | goto reset; | |
843 | ndelay(SPINUNIT); | |
844 | } | |
845 | ||
846 | mce_reign(); | |
847 | barrier(); | |
848 | ret = 0; | |
849 | } else { | |
850 | /* | |
851 | * Subject: Wait for Monarch to finish. | |
852 | */ | |
853 | while (atomic_read(&mce_executing) != 0) { | |
854 | if (mce_timed_out(&timeout)) | |
855 | goto reset; | |
856 | ndelay(SPINUNIT); | |
857 | } | |
858 | ||
859 | /* | |
860 | * Don't reset anything. That's done by the Monarch. | |
861 | */ | |
862 | return 0; | |
863 | } | |
864 | ||
865 | /* | |
866 | * Reset all global state. | |
867 | */ | |
868 | reset: | |
869 | atomic_set(&global_nwo, 0); | |
870 | atomic_set(&mce_callin, 0); | |
871 | barrier(); | |
872 | ||
873 | /* | |
874 | * Let others run again. | |
875 | */ | |
876 | atomic_set(&mce_executing, 0); | |
877 | return ret; | |
878 | } | |
879 | ||
9b1beaf2 AK |
880 | /* |
881 | * Check if the address reported by the CPU is in a format we can parse. | |
882 | * It would be possible to add code for most other cases, but all would | |
883 | * be somewhat complicated (e.g. segment offset would require an instruction | |
884 | * parser). So only support physical addresses upto page granuality for now. | |
885 | */ | |
886 | static int mce_usable_address(struct mce *m) | |
887 | { | |
888 | if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) | |
889 | return 0; | |
890 | if ((m->misc & 0x3f) > PAGE_SHIFT) | |
891 | return 0; | |
892 | if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS) | |
893 | return 0; | |
894 | return 1; | |
895 | } | |
896 | ||
3c079792 AK |
897 | static void mce_clear_state(unsigned long *toclear) |
898 | { | |
899 | int i; | |
900 | ||
901 | for (i = 0; i < banks; i++) { | |
902 | if (test_bit(i, toclear)) | |
a2d32bcb | 903 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
3c079792 AK |
904 | } |
905 | } | |
906 | ||
b79109c3 AK |
907 | /* |
908 | * The actual machine check handler. This only handles real | |
909 | * exceptions when something got corrupted coming in through int 18. | |
910 | * | |
911 | * This is executed in NMI context not subject to normal locking rules. This | |
912 | * implies that most kernel services cannot be safely used. Don't even | |
913 | * think about putting a printk in there! | |
3c079792 AK |
914 | * |
915 | * On Intel systems this is entered on all CPUs in parallel through | |
916 | * MCE broadcast. However some CPUs might be broken beyond repair, | |
917 | * so be always careful when synchronizing with others. | |
1da177e4 | 918 | */ |
e9eee03e | 919 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 | 920 | { |
3c079792 | 921 | struct mce m, *final; |
1da177e4 | 922 | int i; |
3c079792 AK |
923 | int worst = 0; |
924 | int severity; | |
925 | /* | |
926 | * Establish sequential order between the CPUs entering the machine | |
927 | * check handler. | |
928 | */ | |
7fb06fc9 | 929 | int order; |
bd78432c TH |
930 | /* |
931 | * If no_way_out gets set, there is no safe way to recover from this | |
932 | * MCE. If tolerant is cranked up, we'll try anyway. | |
933 | */ | |
934 | int no_way_out = 0; | |
935 | /* | |
936 | * If kill_it gets set, there might be a way to recover from this | |
937 | * error. | |
938 | */ | |
939 | int kill_it = 0; | |
b79109c3 | 940 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
bd19a5e6 | 941 | char *msg = "Unknown"; |
1da177e4 | 942 | |
553f265f AK |
943 | atomic_inc(&mce_entry); |
944 | ||
402af0d7 | 945 | percpu_inc(mce_exception_count); |
01ca79f1 | 946 | |
b79109c3 | 947 | if (notify_die(DIE_NMI, "machine check", regs, error_code, |
22f5991c | 948 | 18, SIGKILL) == NOTIFY_STOP) |
32561696 | 949 | goto out; |
b79109c3 | 950 | if (!banks) |
32561696 | 951 | goto out; |
1da177e4 | 952 | |
b5f2fa4e AK |
953 | mce_setup(&m); |
954 | ||
5f8c1a54 | 955 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
3c079792 AK |
956 | final = &__get_cpu_var(mces_seen); |
957 | *final = m; | |
958 | ||
680b6cfd HS |
959 | no_way_out = mce_no_way_out(&m, &msg); |
960 | ||
1da177e4 LT |
961 | barrier(); |
962 | ||
ed7290d0 AK |
963 | /* |
964 | * When no restart IP must always kill or panic. | |
965 | */ | |
966 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
967 | kill_it = 1; | |
968 | ||
3c079792 AK |
969 | /* |
970 | * Go through all the banks in exclusion of the other CPUs. | |
971 | * This way we don't report duplicated events on shared banks | |
972 | * because the first one to see it will clear it. | |
973 | */ | |
7fb06fc9 | 974 | order = mce_start(&no_way_out); |
1da177e4 | 975 | for (i = 0; i < banks; i++) { |
b79109c3 | 976 | __clear_bit(i, toclear); |
cebe1820 | 977 | if (!mce_banks[i].ctl) |
1da177e4 | 978 | continue; |
d88203d1 TG |
979 | |
980 | m.misc = 0; | |
1da177e4 LT |
981 | m.addr = 0; |
982 | m.bank = i; | |
1da177e4 | 983 | |
a2d32bcb | 984 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
1da177e4 LT |
985 | if ((m.status & MCI_STATUS_VAL) == 0) |
986 | continue; | |
987 | ||
b79109c3 | 988 | /* |
ed7290d0 AK |
989 | * Non uncorrected or non signaled errors are handled by |
990 | * machine_check_poll. Leave them alone, unless this panics. | |
b79109c3 | 991 | */ |
ed7290d0 AK |
992 | if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) && |
993 | !no_way_out) | |
b79109c3 AK |
994 | continue; |
995 | ||
996 | /* | |
997 | * Set taint even when machine check was not enabled. | |
998 | */ | |
999 | add_taint(TAINT_MACHINE_CHECK); | |
1000 | ||
ed7290d0 | 1001 | severity = mce_severity(&m, tolerant, NULL); |
b79109c3 | 1002 | |
ed7290d0 AK |
1003 | /* |
1004 | * When machine check was for corrected handler don't touch, | |
1005 | * unless we're panicing. | |
1006 | */ | |
1007 | if (severity == MCE_KEEP_SEVERITY && !no_way_out) | |
1008 | continue; | |
1009 | __set_bit(i, toclear); | |
1010 | if (severity == MCE_NO_SEVERITY) { | |
b79109c3 AK |
1011 | /* |
1012 | * Machine check event was not enabled. Clear, but | |
1013 | * ignore. | |
1014 | */ | |
1015 | continue; | |
1da177e4 LT |
1016 | } |
1017 | ||
ed7290d0 AK |
1018 | /* |
1019 | * Kill on action required. | |
1020 | */ | |
1021 | if (severity == MCE_AR_SEVERITY) | |
1022 | kill_it = 1; | |
1023 | ||
1da177e4 | 1024 | if (m.status & MCI_STATUS_MISCV) |
a2d32bcb | 1025 | m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); |
1da177e4 | 1026 | if (m.status & MCI_STATUS_ADDRV) |
a2d32bcb | 1027 | m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); |
1da177e4 | 1028 | |
9b1beaf2 AK |
1029 | /* |
1030 | * Action optional error. Queue address for later processing. | |
1031 | * When the ring overflows we just ignore the AO error. | |
1032 | * RED-PEN add some logging mechanism when | |
1033 | * usable_address or mce_add_ring fails. | |
1034 | * RED-PEN don't ignore overflow for tolerant == 0 | |
1035 | */ | |
1036 | if (severity == MCE_AO_SEVERITY && mce_usable_address(&m)) | |
1037 | mce_ring_add(m.addr >> PAGE_SHIFT); | |
1038 | ||
94ad8474 | 1039 | mce_get_rip(&m, regs); |
b79109c3 | 1040 | mce_log(&m); |
1da177e4 | 1041 | |
3c079792 AK |
1042 | if (severity > worst) { |
1043 | *final = m; | |
1044 | worst = severity; | |
1da177e4 | 1045 | } |
1da177e4 LT |
1046 | } |
1047 | ||
3c079792 AK |
1048 | if (!no_way_out) |
1049 | mce_clear_state(toclear); | |
1050 | ||
e9eee03e | 1051 | /* |
3c079792 AK |
1052 | * Do most of the synchronization with other CPUs. |
1053 | * When there's any problem use only local no_way_out state. | |
e9eee03e | 1054 | */ |
3c079792 AK |
1055 | if (mce_end(order) < 0) |
1056 | no_way_out = worst >= MCE_PANIC_SEVERITY; | |
bd78432c TH |
1057 | |
1058 | /* | |
1059 | * If we have decided that we just CAN'T continue, and the user | |
e9eee03e | 1060 | * has not set tolerant to an insane level, give up and die. |
3c079792 AK |
1061 | * |
1062 | * This is mainly used in the case when the system doesn't | |
1063 | * support MCE broadcasting or it has been disabled. | |
bd78432c TH |
1064 | */ |
1065 | if (no_way_out && tolerant < 3) | |
ac960375 | 1066 | mce_panic("Fatal machine check on current CPU", final, msg); |
bd78432c TH |
1067 | |
1068 | /* | |
1069 | * If the error seems to be unrecoverable, something should be | |
1070 | * done. Try to kill as little as possible. If we can kill just | |
1071 | * one task, do that. If the user has set the tolerance very | |
1072 | * high, don't try to do anything at all. | |
1073 | */ | |
bd78432c | 1074 | |
ed7290d0 AK |
1075 | if (kill_it && tolerant < 3) |
1076 | force_sig(SIGBUS, current); | |
1da177e4 | 1077 | |
e02e68d3 TH |
1078 | /* notify userspace ASAP */ |
1079 | set_thread_flag(TIF_MCE_NOTIFY); | |
1080 | ||
3c079792 AK |
1081 | if (worst > 0) |
1082 | mce_report_event(regs); | |
5f8c1a54 | 1083 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 1084 | out: |
553f265f | 1085 | atomic_dec(&mce_entry); |
88921be3 | 1086 | sync_core(); |
1da177e4 | 1087 | } |
ea149b36 | 1088 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 1089 | |
9b1beaf2 AK |
1090 | /* dummy to break dependency. actual code is in mm/memory-failure.c */ |
1091 | void __attribute__((weak)) memory_failure(unsigned long pfn, int vector) | |
1092 | { | |
1093 | printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn); | |
1094 | } | |
1095 | ||
1096 | /* | |
1097 | * Called after mce notification in process context. This code | |
1098 | * is allowed to sleep. Call the high level VM handler to process | |
1099 | * any corrupted pages. | |
1100 | * Assume that the work queue code only calls this one at a time | |
1101 | * per CPU. | |
1102 | * Note we don't disable preemption, so this code might run on the wrong | |
1103 | * CPU. In this case the event is picked up by the scheduled work queue. | |
1104 | * This is merely a fast path to expedite processing in some common | |
1105 | * cases. | |
1106 | */ | |
1107 | void mce_notify_process(void) | |
1108 | { | |
1109 | unsigned long pfn; | |
1110 | mce_notify_irq(); | |
1111 | while (mce_ring_get(&pfn)) | |
1112 | memory_failure(pfn, MCE_VECTOR); | |
1113 | } | |
1114 | ||
1115 | static void mce_process_work(struct work_struct *dummy) | |
1116 | { | |
1117 | mce_notify_process(); | |
1118 | } | |
1119 | ||
15d5f839 DZ |
1120 | #ifdef CONFIG_X86_MCE_INTEL |
1121 | /*** | |
1122 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 1123 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
1124 | * @status: Event status information |
1125 | * | |
1126 | * This function should be called by the thermal interrupt after the | |
1127 | * event has been processed and the decision was made to log the event | |
1128 | * further. | |
1129 | * | |
1130 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
1131 | * and historically has been the register value of the | |
1132 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
1133 | */ | |
b5f2fa4e | 1134 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
1135 | { |
1136 | struct mce m; | |
1137 | ||
b5f2fa4e | 1138 | mce_setup(&m); |
15d5f839 DZ |
1139 | m.bank = MCE_THERMAL_BANK; |
1140 | m.status = status; | |
15d5f839 DZ |
1141 | mce_log(&m); |
1142 | } | |
1143 | #endif /* CONFIG_X86_MCE_INTEL */ | |
1144 | ||
1da177e4 | 1145 | /* |
8a336b0a TH |
1146 | * Periodic polling timer for "silent" machine check errors. If the |
1147 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
1148 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 1149 | */ |
1da177e4 | 1150 | static int check_interval = 5 * 60; /* 5 minutes */ |
e9eee03e | 1151 | |
245b2e70 | 1152 | static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */ |
52d168e2 | 1153 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 1154 | |
5e09954a | 1155 | static void mce_start_timer(unsigned long data) |
1da177e4 | 1156 | { |
52d168e2 | 1157 | struct timer_list *t = &per_cpu(mce_timer, data); |
6298c512 | 1158 | int *n; |
52d168e2 AK |
1159 | |
1160 | WARN_ON(smp_processor_id() != data); | |
1161 | ||
e9eee03e | 1162 | if (mce_available(¤t_cpu_data)) { |
ee031c31 AK |
1163 | machine_check_poll(MCP_TIMESTAMP, |
1164 | &__get_cpu_var(mce_poll_banks)); | |
e9eee03e | 1165 | } |
1da177e4 LT |
1166 | |
1167 | /* | |
e02e68d3 TH |
1168 | * Alert userspace if needed. If we logged an MCE, reduce the |
1169 | * polling interval, otherwise increase the polling interval. | |
1da177e4 | 1170 | */ |
245b2e70 | 1171 | n = &__get_cpu_var(mce_next_interval); |
9ff36ee9 | 1172 | if (mce_notify_irq()) |
6298c512 | 1173 | *n = max(*n/2, HZ/100); |
14a02530 | 1174 | else |
6298c512 | 1175 | *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ)); |
e02e68d3 | 1176 | |
6298c512 | 1177 | t->expires = jiffies + *n; |
5be6066a | 1178 | add_timer_on(t, smp_processor_id()); |
e02e68d3 TH |
1179 | } |
1180 | ||
9bd98405 AK |
1181 | static void mce_do_trigger(struct work_struct *work) |
1182 | { | |
1020bcbc | 1183 | call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT); |
9bd98405 AK |
1184 | } |
1185 | ||
1186 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
1187 | ||
e02e68d3 | 1188 | /* |
9bd98405 AK |
1189 | * Notify the user(s) about new machine check events. |
1190 | * Can be called from interrupt context, but not from machine check/NMI | |
1191 | * context. | |
e02e68d3 | 1192 | */ |
9ff36ee9 | 1193 | int mce_notify_irq(void) |
e02e68d3 | 1194 | { |
8457c84d AK |
1195 | /* Not more than two messages every minute */ |
1196 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
1197 | ||
e02e68d3 | 1198 | clear_thread_flag(TIF_MCE_NOTIFY); |
e9eee03e | 1199 | |
1020bcbc | 1200 | if (test_and_clear_bit(0, &mce_need_notify)) { |
e02e68d3 | 1201 | wake_up_interruptible(&mce_wait); |
9bd98405 AK |
1202 | |
1203 | /* | |
1204 | * There is no risk of missing notifications because | |
1205 | * work_pending is always cleared before the function is | |
1206 | * executed. | |
1207 | */ | |
1020bcbc | 1208 | if (mce_helper[0] && !work_pending(&mce_trigger_work)) |
9bd98405 | 1209 | schedule_work(&mce_trigger_work); |
e02e68d3 | 1210 | |
8457c84d | 1211 | if (__ratelimit(&ratelimit)) |
a2d7b0d4 | 1212 | pr_info(HW_ERR "Machine check events logged\n"); |
e02e68d3 TH |
1213 | |
1214 | return 1; | |
1da177e4 | 1215 | } |
e02e68d3 TH |
1216 | return 0; |
1217 | } | |
9ff36ee9 | 1218 | EXPORT_SYMBOL_GPL(mce_notify_irq); |
8a336b0a | 1219 | |
cffd377e | 1220 | static int __cpuinit __mcheck_cpu_mce_banks_init(void) |
cebe1820 AK |
1221 | { |
1222 | int i; | |
1223 | ||
1224 | mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL); | |
1225 | if (!mce_banks) | |
1226 | return -ENOMEM; | |
1227 | for (i = 0; i < banks; i++) { | |
1228 | struct mce_bank *b = &mce_banks[i]; | |
11868a2d | 1229 | |
cebe1820 AK |
1230 | b->ctl = -1ULL; |
1231 | b->init = 1; | |
1232 | } | |
1233 | return 0; | |
1234 | } | |
1235 | ||
d88203d1 | 1236 | /* |
1da177e4 LT |
1237 | * Initialize Machine Checks for a CPU. |
1238 | */ | |
5e09954a | 1239 | static int __cpuinit __mcheck_cpu_cap_init(void) |
1da177e4 | 1240 | { |
0d7482e3 | 1241 | unsigned b; |
e9eee03e | 1242 | u64 cap; |
1da177e4 LT |
1243 | |
1244 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
1245 | |
1246 | b = cap & MCG_BANKCNT_MASK; | |
93ae5012 RD |
1247 | if (!banks) |
1248 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b); | |
b659294b | 1249 | |
0d7482e3 AK |
1250 | if (b > MAX_NR_BANKS) { |
1251 | printk(KERN_WARNING | |
1252 | "MCE: Using only %u machine check banks out of %u\n", | |
1253 | MAX_NR_BANKS, b); | |
1254 | b = MAX_NR_BANKS; | |
1255 | } | |
1256 | ||
1257 | /* Don't support asymmetric configurations today */ | |
1258 | WARN_ON(banks != 0 && b != banks); | |
1259 | banks = b; | |
cebe1820 | 1260 | if (!mce_banks) { |
cffd377e | 1261 | int err = __mcheck_cpu_mce_banks_init(); |
11868a2d | 1262 | |
cebe1820 AK |
1263 | if (err) |
1264 | return err; | |
1da177e4 | 1265 | } |
0d7482e3 | 1266 | |
94ad8474 | 1267 | /* Use accurate RIP reporting if available. */ |
01c6680a | 1268 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
94ad8474 | 1269 | rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 1270 | |
ed7290d0 AK |
1271 | if (cap & MCG_SER_P) |
1272 | mce_ser = 1; | |
1273 | ||
0d7482e3 AK |
1274 | return 0; |
1275 | } | |
1276 | ||
5e09954a | 1277 | static void __mcheck_cpu_init_generic(void) |
0d7482e3 | 1278 | { |
e9eee03e | 1279 | mce_banks_t all_banks; |
0d7482e3 AK |
1280 | u64 cap; |
1281 | int i; | |
1282 | ||
b79109c3 AK |
1283 | /* |
1284 | * Log the machine checks left over from the previous reset. | |
1285 | */ | |
ee031c31 | 1286 | bitmap_fill(all_banks, MAX_NR_BANKS); |
5679af4c | 1287 | machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks); |
1da177e4 LT |
1288 | |
1289 | set_in_cr4(X86_CR4_MCE); | |
1290 | ||
0d7482e3 | 1291 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
1292 | if (cap & MCG_CTL_P) |
1293 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
1294 | ||
1295 | for (i = 0; i < banks; i++) { | |
cebe1820 | 1296 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1297 | |
cebe1820 | 1298 | if (!b->init) |
06b7a7a5 | 1299 | continue; |
a2d32bcb AK |
1300 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
1301 | wrmsrl(MSR_IA32_MCx_STATUS(i), 0); | |
d88203d1 | 1302 | } |
1da177e4 LT |
1303 | } |
1304 | ||
1305 | /* Add per CPU specific workarounds here */ | |
5e09954a | 1306 | static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 1307 | { |
e412cd25 IM |
1308 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { |
1309 | pr_info("MCE: unknown CPU type - not enabling MCE support.\n"); | |
1310 | return -EOPNOTSUPP; | |
1311 | } | |
1312 | ||
1da177e4 | 1313 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 1314 | if (c->x86_vendor == X86_VENDOR_AMD) { |
e9eee03e IM |
1315 | if (c->x86 == 15 && banks > 4) { |
1316 | /* | |
1317 | * disable GART TBL walk error reporting, which | |
1318 | * trips off incorrectly with the IOMMU & 3ware | |
1319 | * & Cerberus: | |
1320 | */ | |
cebe1820 | 1321 | clear_bit(10, (unsigned long *)&mce_banks[4].ctl); |
e9eee03e IM |
1322 | } |
1323 | if (c->x86 <= 17 && mce_bootlog < 0) { | |
1324 | /* | |
1325 | * Lots of broken BIOS around that don't clear them | |
1326 | * by default and leave crap in there. Don't log: | |
1327 | */ | |
911f6a7b | 1328 | mce_bootlog = 0; |
e9eee03e | 1329 | } |
2e6f694f AK |
1330 | /* |
1331 | * Various K7s with broken bank 0 around. Always disable | |
1332 | * by default. | |
1333 | */ | |
203abd67 | 1334 | if (c->x86 == 6 && banks > 0) |
cebe1820 | 1335 | mce_banks[0].ctl = 0; |
1da177e4 | 1336 | } |
e583538f | 1337 | |
06b7a7a5 AK |
1338 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
1339 | /* | |
1340 | * SDM documents that on family 6 bank 0 should not be written | |
1341 | * because it aliases to another special BIOS controlled | |
1342 | * register. | |
1343 | * But it's not aliased anymore on model 0x1a+ | |
1344 | * Don't ignore bank 0 completely because there could be a | |
1345 | * valid event later, merely don't write CTL0. | |
1346 | */ | |
1347 | ||
cebe1820 AK |
1348 | if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0) |
1349 | mce_banks[0].init = 0; | |
3c079792 AK |
1350 | |
1351 | /* | |
1352 | * All newer Intel systems support MCE broadcasting. Enable | |
1353 | * synchronization with a one second timeout. | |
1354 | */ | |
1355 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && | |
1356 | monarch_timeout < 0) | |
1357 | monarch_timeout = USEC_PER_SEC; | |
c7f6fa44 | 1358 | |
e412cd25 IM |
1359 | /* |
1360 | * There are also broken BIOSes on some Pentium M and | |
1361 | * earlier systems: | |
1362 | */ | |
1363 | if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0) | |
c7f6fa44 | 1364 | mce_bootlog = 0; |
06b7a7a5 | 1365 | } |
3c079792 AK |
1366 | if (monarch_timeout < 0) |
1367 | monarch_timeout = 0; | |
29b0f591 AK |
1368 | if (mce_bootlog != 0) |
1369 | mce_panic_timeout = 30; | |
e412cd25 IM |
1370 | |
1371 | return 0; | |
d88203d1 | 1372 | } |
1da177e4 | 1373 | |
5e09954a | 1374 | static void __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) |
4efc0670 AK |
1375 | { |
1376 | if (c->x86 != 5) | |
1377 | return; | |
1378 | switch (c->x86_vendor) { | |
1379 | case X86_VENDOR_INTEL: | |
c6978369 | 1380 | intel_p5_mcheck_init(c); |
4efc0670 AK |
1381 | break; |
1382 | case X86_VENDOR_CENTAUR: | |
1383 | winchip_mcheck_init(c); | |
1384 | break; | |
1385 | } | |
1386 | } | |
1387 | ||
5e09954a | 1388 | static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
1389 | { |
1390 | switch (c->x86_vendor) { | |
1391 | case X86_VENDOR_INTEL: | |
1392 | mce_intel_feature_init(c); | |
1393 | break; | |
89b831ef JS |
1394 | case X86_VENDOR_AMD: |
1395 | mce_amd_feature_init(c); | |
1396 | break; | |
1da177e4 LT |
1397 | default: |
1398 | break; | |
1399 | } | |
1400 | } | |
1401 | ||
5e09954a | 1402 | static void __mcheck_cpu_init_timer(void) |
52d168e2 AK |
1403 | { |
1404 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
245b2e70 | 1405 | int *n = &__get_cpu_var(mce_next_interval); |
52d168e2 | 1406 | |
bc09effa JB |
1407 | setup_timer(t, mce_start_timer, smp_processor_id()); |
1408 | ||
62fdac59 HS |
1409 | if (mce_ignore_ce) |
1410 | return; | |
1411 | ||
6298c512 AK |
1412 | *n = check_interval * HZ; |
1413 | if (!*n) | |
52d168e2 | 1414 | return; |
6298c512 | 1415 | t->expires = round_jiffies(jiffies + *n); |
5be6066a | 1416 | add_timer_on(t, smp_processor_id()); |
52d168e2 AK |
1417 | } |
1418 | ||
9eda8cb3 AK |
1419 | /* Handle unconfigured int18 (should never happen) */ |
1420 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
1421 | { | |
1422 | printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n", | |
1423 | smp_processor_id()); | |
1424 | } | |
1425 | ||
1426 | /* Call the installed machine check handler for this CPU setup. */ | |
1427 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
1428 | unexpected_machine_check; | |
1429 | ||
d88203d1 | 1430 | /* |
1da177e4 | 1431 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 1432 | * Must be called with preempt off: |
1da177e4 | 1433 | */ |
5e09954a | 1434 | void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c) |
1da177e4 | 1435 | { |
4efc0670 AK |
1436 | if (mce_disabled) |
1437 | return; | |
1438 | ||
5e09954a | 1439 | __mcheck_cpu_ancient_init(c); |
4efc0670 | 1440 | |
5b4408fd | 1441 | if (!mce_available(c)) |
1da177e4 LT |
1442 | return; |
1443 | ||
5e09954a | 1444 | if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) { |
04b2b1a4 | 1445 | mce_disabled = 1; |
0d7482e3 AK |
1446 | return; |
1447 | } | |
0d7482e3 | 1448 | |
5d727926 AK |
1449 | machine_check_vector = do_machine_check; |
1450 | ||
5e09954a BP |
1451 | __mcheck_cpu_init_generic(); |
1452 | __mcheck_cpu_init_vendor(c); | |
1453 | __mcheck_cpu_init_timer(); | |
9b1beaf2 | 1454 | INIT_WORK(&__get_cpu_var(mce_work), mce_process_work); |
fb253195 | 1455 | |
1da177e4 LT |
1456 | } |
1457 | ||
1458 | /* | |
1459 | * Character device to read and clear the MCE log. | |
1460 | */ | |
1461 | ||
f528e7ba | 1462 | static DEFINE_SPINLOCK(mce_state_lock); |
e9eee03e IM |
1463 | static int open_count; /* #times opened */ |
1464 | static int open_exclu; /* already open exclusive? */ | |
f528e7ba TH |
1465 | |
1466 | static int mce_open(struct inode *inode, struct file *file) | |
1467 | { | |
1468 | spin_lock(&mce_state_lock); | |
1469 | ||
1470 | if (open_exclu || (open_count && (file->f_flags & O_EXCL))) { | |
1471 | spin_unlock(&mce_state_lock); | |
e9eee03e | 1472 | |
f528e7ba TH |
1473 | return -EBUSY; |
1474 | } | |
1475 | ||
1476 | if (file->f_flags & O_EXCL) | |
1477 | open_exclu = 1; | |
1478 | open_count++; | |
1479 | ||
1480 | spin_unlock(&mce_state_lock); | |
1481 | ||
bd78432c | 1482 | return nonseekable_open(inode, file); |
f528e7ba TH |
1483 | } |
1484 | ||
1485 | static int mce_release(struct inode *inode, struct file *file) | |
1486 | { | |
1487 | spin_lock(&mce_state_lock); | |
1488 | ||
1489 | open_count--; | |
1490 | open_exclu = 0; | |
1491 | ||
1492 | spin_unlock(&mce_state_lock); | |
1493 | ||
1494 | return 0; | |
1495 | } | |
1496 | ||
d88203d1 TG |
1497 | static void collect_tscs(void *data) |
1498 | { | |
1da177e4 | 1499 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 1500 | |
1da177e4 | 1501 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 1502 | } |
1da177e4 | 1503 | |
482908b4 HY |
1504 | static int mce_apei_read_done; |
1505 | ||
1506 | /* Collect MCE record of previous boot in persistent storage via APEI ERST. */ | |
1507 | static int __mce_read_apei(char __user **ubuf, size_t usize) | |
1508 | { | |
1509 | int rc; | |
1510 | u64 record_id; | |
1511 | struct mce m; | |
1512 | ||
1513 | if (usize < sizeof(struct mce)) | |
1514 | return -EINVAL; | |
1515 | ||
1516 | rc = apei_read_mce(&m, &record_id); | |
1517 | /* Error or no more MCE record */ | |
1518 | if (rc <= 0) { | |
1519 | mce_apei_read_done = 1; | |
1520 | return rc; | |
1521 | } | |
1522 | rc = -EFAULT; | |
1523 | if (copy_to_user(*ubuf, &m, sizeof(struct mce))) | |
1524 | return rc; | |
1525 | /* | |
1526 | * In fact, we should have cleared the record after that has | |
1527 | * been flushed to the disk or sent to network in | |
1528 | * /sbin/mcelog, but we have no interface to support that now, | |
1529 | * so just clear it to avoid duplication. | |
1530 | */ | |
1531 | rc = apei_clear_mce(record_id); | |
1532 | if (rc) { | |
1533 | mce_apei_read_done = 1; | |
1534 | return rc; | |
1535 | } | |
1536 | *ubuf += sizeof(struct mce); | |
1537 | ||
1538 | return 0; | |
1539 | } | |
1540 | ||
d88203d1 TG |
1541 | static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize, |
1542 | loff_t *off) | |
1da177e4 | 1543 | { |
e9eee03e | 1544 | char __user *buf = ubuf; |
f0de53bb | 1545 | unsigned long *cpu_tsc; |
ef41df43 | 1546 | unsigned prev, next; |
1da177e4 LT |
1547 | int i, err; |
1548 | ||
6bca67f9 | 1549 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
1550 | if (!cpu_tsc) |
1551 | return -ENOMEM; | |
1552 | ||
8c8b8859 | 1553 | mutex_lock(&mce_read_mutex); |
482908b4 HY |
1554 | |
1555 | if (!mce_apei_read_done) { | |
1556 | err = __mce_read_apei(&buf, usize); | |
1557 | if (err || buf != ubuf) | |
1558 | goto out; | |
1559 | } | |
1560 | ||
f56e8a07 | 1561 | next = rcu_dereference_check_mce(mcelog.next); |
1da177e4 LT |
1562 | |
1563 | /* Only supports full reads right now */ | |
482908b4 HY |
1564 | err = -EINVAL; |
1565 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) | |
1566 | goto out; | |
1da177e4 LT |
1567 | |
1568 | err = 0; | |
ef41df43 HY |
1569 | prev = 0; |
1570 | do { | |
1571 | for (i = prev; i < next; i++) { | |
1572 | unsigned long start = jiffies; | |
1573 | ||
1574 | while (!mcelog.entry[i].finished) { | |
1575 | if (time_after_eq(jiffies, start + 2)) { | |
1576 | memset(mcelog.entry + i, 0, | |
1577 | sizeof(struct mce)); | |
1578 | goto timeout; | |
1579 | } | |
1580 | cpu_relax(); | |
673242c1 | 1581 | } |
ef41df43 HY |
1582 | smp_rmb(); |
1583 | err |= copy_to_user(buf, mcelog.entry + i, | |
1584 | sizeof(struct mce)); | |
1585 | buf += sizeof(struct mce); | |
1586 | timeout: | |
1587 | ; | |
673242c1 | 1588 | } |
1da177e4 | 1589 | |
ef41df43 HY |
1590 | memset(mcelog.entry + prev, 0, |
1591 | (next - prev) * sizeof(struct mce)); | |
1592 | prev = next; | |
1593 | next = cmpxchg(&mcelog.next, prev, 0); | |
1594 | } while (next != prev); | |
1da177e4 | 1595 | |
b2b18660 | 1596 | synchronize_sched(); |
1da177e4 | 1597 | |
d88203d1 TG |
1598 | /* |
1599 | * Collect entries that were still getting written before the | |
1600 | * synchronize. | |
1601 | */ | |
15c8b6c1 | 1602 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 1603 | |
d88203d1 TG |
1604 | for (i = next; i < MCE_LOG_LEN; i++) { |
1605 | if (mcelog.entry[i].finished && | |
1606 | mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) { | |
1607 | err |= copy_to_user(buf, mcelog.entry+i, | |
1608 | sizeof(struct mce)); | |
1da177e4 LT |
1609 | smp_rmb(); |
1610 | buf += sizeof(struct mce); | |
1611 | memset(&mcelog.entry[i], 0, sizeof(struct mce)); | |
1612 | } | |
d88203d1 | 1613 | } |
482908b4 HY |
1614 | |
1615 | if (err) | |
1616 | err = -EFAULT; | |
1617 | ||
1618 | out: | |
8c8b8859 | 1619 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 1620 | kfree(cpu_tsc); |
e9eee03e | 1621 | |
482908b4 | 1622 | return err ? err : buf - ubuf; |
1da177e4 LT |
1623 | } |
1624 | ||
e02e68d3 TH |
1625 | static unsigned int mce_poll(struct file *file, poll_table *wait) |
1626 | { | |
1627 | poll_wait(file, &mce_wait, wait); | |
f56e8a07 | 1628 | if (rcu_dereference_check_mce(mcelog.next)) |
e02e68d3 | 1629 | return POLLIN | POLLRDNORM; |
482908b4 HY |
1630 | if (!mce_apei_read_done && apei_check_mce()) |
1631 | return POLLIN | POLLRDNORM; | |
e02e68d3 TH |
1632 | return 0; |
1633 | } | |
1634 | ||
c68461b6 | 1635 | static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg) |
1da177e4 LT |
1636 | { |
1637 | int __user *p = (int __user *)arg; | |
d88203d1 | 1638 | |
1da177e4 | 1639 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 1640 | return -EPERM; |
e9eee03e | 1641 | |
1da177e4 | 1642 | switch (cmd) { |
d88203d1 | 1643 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
1644 | return put_user(sizeof(struct mce), p); |
1645 | case MCE_GET_LOG_LEN: | |
d88203d1 | 1646 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
1647 | case MCE_GETCLEAR_FLAGS: { |
1648 | unsigned flags; | |
d88203d1 TG |
1649 | |
1650 | do { | |
1da177e4 | 1651 | flags = mcelog.flags; |
d88203d1 | 1652 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 1653 | |
d88203d1 | 1654 | return put_user(flags, p); |
1da177e4 LT |
1655 | } |
1656 | default: | |
d88203d1 TG |
1657 | return -ENOTTY; |
1658 | } | |
1da177e4 LT |
1659 | } |
1660 | ||
a1ff41bf | 1661 | /* Modified in mce-inject.c, so not static or const */ |
ea149b36 | 1662 | struct file_operations mce_chrdev_ops = { |
e9eee03e IM |
1663 | .open = mce_open, |
1664 | .release = mce_release, | |
1665 | .read = mce_read, | |
1666 | .poll = mce_poll, | |
1667 | .unlocked_ioctl = mce_ioctl, | |
6038f373 | 1668 | .llseek = no_llseek, |
1da177e4 | 1669 | }; |
ea149b36 | 1670 | EXPORT_SYMBOL_GPL(mce_chrdev_ops); |
1da177e4 LT |
1671 | |
1672 | static struct miscdevice mce_log_device = { | |
1673 | MISC_MCELOG_MINOR, | |
1674 | "mcelog", | |
1675 | &mce_chrdev_ops, | |
1676 | }; | |
1677 | ||
13503fa9 | 1678 | /* |
62fdac59 HS |
1679 | * mce=off Disables machine check |
1680 | * mce=no_cmci Disables CMCI | |
1681 | * mce=dont_log_ce Clears corrected events silently, no log created for CEs. | |
1682 | * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. | |
3c079792 AK |
1683 | * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) |
1684 | * monarchtimeout is how long to wait for other CPUs on machine | |
1685 | * check, or 0 to not wait | |
13503fa9 HS |
1686 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. |
1687 | * mce=nobootlog Don't log MCEs from before booting. | |
1688 | */ | |
1da177e4 LT |
1689 | static int __init mcheck_enable(char *str) |
1690 | { | |
e3346fc4 | 1691 | if (*str == 0) { |
4efc0670 | 1692 | enable_p5_mce(); |
e3346fc4 BZ |
1693 | return 1; |
1694 | } | |
4efc0670 AK |
1695 | if (*str == '=') |
1696 | str++; | |
1da177e4 | 1697 | if (!strcmp(str, "off")) |
04b2b1a4 | 1698 | mce_disabled = 1; |
62fdac59 HS |
1699 | else if (!strcmp(str, "no_cmci")) |
1700 | mce_cmci_disabled = 1; | |
1701 | else if (!strcmp(str, "dont_log_ce")) | |
1702 | mce_dont_log_ce = 1; | |
1703 | else if (!strcmp(str, "ignore_ce")) | |
1704 | mce_ignore_ce = 1; | |
13503fa9 HS |
1705 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
1706 | mce_bootlog = (str[0] == 'b'); | |
3c079792 | 1707 | else if (isdigit(str[0])) { |
8c566ef5 | 1708 | get_option(&str, &tolerant); |
3c079792 AK |
1709 | if (*str == ',') { |
1710 | ++str; | |
1711 | get_option(&str, &monarch_timeout); | |
1712 | } | |
1713 | } else { | |
4efc0670 | 1714 | printk(KERN_INFO "mce argument %s ignored. Please use /sys\n", |
13503fa9 HS |
1715 | str); |
1716 | return 0; | |
1717 | } | |
9b41046c | 1718 | return 1; |
1da177e4 | 1719 | } |
4efc0670 | 1720 | __setup("mce", mcheck_enable); |
1da177e4 | 1721 | |
a2202aa2 | 1722 | int __init mcheck_init(void) |
b33a6363 BP |
1723 | { |
1724 | atomic_notifier_chain_register(&x86_mce_decoder_chain, &mce_dec_nb); | |
1725 | ||
a2202aa2 YW |
1726 | mcheck_intel_therm_init(); |
1727 | ||
b33a6363 BP |
1728 | return 0; |
1729 | } | |
b33a6363 | 1730 | |
d88203d1 | 1731 | /* |
1da177e4 | 1732 | * Sysfs support |
d88203d1 | 1733 | */ |
1da177e4 | 1734 | |
973a2dd1 AK |
1735 | /* |
1736 | * Disable machine checks on suspend and shutdown. We can't really handle | |
1737 | * them later. | |
1738 | */ | |
5e09954a | 1739 | static int mce_disable_error_reporting(void) |
973a2dd1 AK |
1740 | { |
1741 | int i; | |
1742 | ||
06b7a7a5 | 1743 | for (i = 0; i < banks; i++) { |
cebe1820 | 1744 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1745 | |
cebe1820 | 1746 | if (b->init) |
a2d32bcb | 1747 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 1748 | } |
973a2dd1 AK |
1749 | return 0; |
1750 | } | |
1751 | ||
1752 | static int mce_suspend(struct sys_device *dev, pm_message_t state) | |
1753 | { | |
5e09954a | 1754 | return mce_disable_error_reporting(); |
973a2dd1 AK |
1755 | } |
1756 | ||
1757 | static int mce_shutdown(struct sys_device *dev) | |
1758 | { | |
5e09954a | 1759 | return mce_disable_error_reporting(); |
973a2dd1 AK |
1760 | } |
1761 | ||
e9eee03e IM |
1762 | /* |
1763 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
1764 | * Only one CPU is active at this time, the others get re-added later using | |
1765 | * CPU hotplug: | |
1766 | */ | |
1da177e4 LT |
1767 | static int mce_resume(struct sys_device *dev) |
1768 | { | |
5e09954a BP |
1769 | __mcheck_cpu_init_generic(); |
1770 | __mcheck_cpu_init_vendor(¤t_cpu_data); | |
e9eee03e | 1771 | |
1da177e4 LT |
1772 | return 0; |
1773 | } | |
1774 | ||
52d168e2 AK |
1775 | static void mce_cpu_restart(void *data) |
1776 | { | |
1777 | del_timer_sync(&__get_cpu_var(mce_timer)); | |
33edbf02 HS |
1778 | if (!mce_available(¤t_cpu_data)) |
1779 | return; | |
5e09954a BP |
1780 | __mcheck_cpu_init_generic(); |
1781 | __mcheck_cpu_init_timer(); | |
52d168e2 AK |
1782 | } |
1783 | ||
1da177e4 | 1784 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
1785 | static void mce_restart(void) |
1786 | { | |
52d168e2 | 1787 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
1788 | } |
1789 | ||
9af43b54 HS |
1790 | /* Toggle features for corrected errors */ |
1791 | static void mce_disable_ce(void *all) | |
1792 | { | |
1793 | if (!mce_available(¤t_cpu_data)) | |
1794 | return; | |
1795 | if (all) | |
1796 | del_timer_sync(&__get_cpu_var(mce_timer)); | |
1797 | cmci_clear(); | |
1798 | } | |
1799 | ||
1800 | static void mce_enable_ce(void *all) | |
1801 | { | |
1802 | if (!mce_available(¤t_cpu_data)) | |
1803 | return; | |
1804 | cmci_reenable(); | |
1805 | cmci_recheck(); | |
1806 | if (all) | |
5e09954a | 1807 | __mcheck_cpu_init_timer(); |
9af43b54 HS |
1808 | } |
1809 | ||
1da177e4 | 1810 | static struct sysdev_class mce_sysclass = { |
e9eee03e IM |
1811 | .suspend = mce_suspend, |
1812 | .shutdown = mce_shutdown, | |
1813 | .resume = mce_resume, | |
1814 | .name = "machinecheck", | |
1da177e4 LT |
1815 | }; |
1816 | ||
cb491fca | 1817 | DEFINE_PER_CPU(struct sys_device, mce_dev); |
e9eee03e IM |
1818 | |
1819 | __cpuinitdata | |
1820 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); | |
1da177e4 | 1821 | |
cebe1820 AK |
1822 | static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr) |
1823 | { | |
1824 | return container_of(attr, struct mce_bank, attr); | |
1825 | } | |
0d7482e3 AK |
1826 | |
1827 | static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
1828 | char *buf) | |
1829 | { | |
cebe1820 | 1830 | return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl); |
0d7482e3 AK |
1831 | } |
1832 | ||
1833 | static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
9319cec8 | 1834 | const char *buf, size_t size) |
0d7482e3 | 1835 | { |
9319cec8 | 1836 | u64 new; |
e9eee03e | 1837 | |
9319cec8 | 1838 | if (strict_strtoull(buf, 0, &new) < 0) |
0d7482e3 | 1839 | return -EINVAL; |
e9eee03e | 1840 | |
cebe1820 | 1841 | attr_to_bank(attr)->ctl = new; |
0d7482e3 | 1842 | mce_restart(); |
e9eee03e | 1843 | |
9319cec8 | 1844 | return size; |
0d7482e3 | 1845 | } |
a98f0dd3 | 1846 | |
e9eee03e IM |
1847 | static ssize_t |
1848 | show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf) | |
a98f0dd3 | 1849 | { |
1020bcbc | 1850 | strcpy(buf, mce_helper); |
a98f0dd3 | 1851 | strcat(buf, "\n"); |
1020bcbc | 1852 | return strlen(mce_helper) + 1; |
a98f0dd3 AK |
1853 | } |
1854 | ||
4a0b2b4d | 1855 | static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr, |
e9eee03e | 1856 | const char *buf, size_t siz) |
a98f0dd3 AK |
1857 | { |
1858 | char *p; | |
e9eee03e | 1859 | |
1020bcbc HS |
1860 | strncpy(mce_helper, buf, sizeof(mce_helper)); |
1861 | mce_helper[sizeof(mce_helper)-1] = 0; | |
1020bcbc | 1862 | p = strchr(mce_helper, '\n'); |
e9eee03e | 1863 | |
e9084ec9 | 1864 | if (p) |
e9eee03e IM |
1865 | *p = 0; |
1866 | ||
e9084ec9 | 1867 | return strlen(mce_helper) + !!p; |
a98f0dd3 AK |
1868 | } |
1869 | ||
9af43b54 HS |
1870 | static ssize_t set_ignore_ce(struct sys_device *s, |
1871 | struct sysdev_attribute *attr, | |
1872 | const char *buf, size_t size) | |
1873 | { | |
1874 | u64 new; | |
1875 | ||
1876 | if (strict_strtoull(buf, 0, &new) < 0) | |
1877 | return -EINVAL; | |
1878 | ||
1879 | if (mce_ignore_ce ^ !!new) { | |
1880 | if (new) { | |
1881 | /* disable ce features */ | |
1882 | on_each_cpu(mce_disable_ce, (void *)1, 1); | |
1883 | mce_ignore_ce = 1; | |
1884 | } else { | |
1885 | /* enable ce features */ | |
1886 | mce_ignore_ce = 0; | |
1887 | on_each_cpu(mce_enable_ce, (void *)1, 1); | |
1888 | } | |
1889 | } | |
1890 | return size; | |
1891 | } | |
1892 | ||
1893 | static ssize_t set_cmci_disabled(struct sys_device *s, | |
1894 | struct sysdev_attribute *attr, | |
1895 | const char *buf, size_t size) | |
1896 | { | |
1897 | u64 new; | |
1898 | ||
1899 | if (strict_strtoull(buf, 0, &new) < 0) | |
1900 | return -EINVAL; | |
1901 | ||
1902 | if (mce_cmci_disabled ^ !!new) { | |
1903 | if (new) { | |
1904 | /* disable cmci */ | |
1905 | on_each_cpu(mce_disable_ce, NULL, 1); | |
1906 | mce_cmci_disabled = 1; | |
1907 | } else { | |
1908 | /* enable cmci */ | |
1909 | mce_cmci_disabled = 0; | |
1910 | on_each_cpu(mce_enable_ce, NULL, 1); | |
1911 | } | |
1912 | } | |
1913 | return size; | |
1914 | } | |
1915 | ||
b56f642d AK |
1916 | static ssize_t store_int_with_restart(struct sys_device *s, |
1917 | struct sysdev_attribute *attr, | |
1918 | const char *buf, size_t size) | |
1919 | { | |
1920 | ssize_t ret = sysdev_store_int(s, attr, buf, size); | |
1921 | mce_restart(); | |
1922 | return ret; | |
1923 | } | |
1924 | ||
a98f0dd3 | 1925 | static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger); |
d95d62c0 | 1926 | static SYSDEV_INT_ATTR(tolerant, 0644, tolerant); |
3c079792 | 1927 | static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout); |
9af43b54 | 1928 | static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce); |
e9eee03e | 1929 | |
b56f642d AK |
1930 | static struct sysdev_ext_attribute attr_check_interval = { |
1931 | _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int, | |
1932 | store_int_with_restart), | |
1933 | &check_interval | |
1934 | }; | |
e9eee03e | 1935 | |
9af43b54 HS |
1936 | static struct sysdev_ext_attribute attr_ignore_ce = { |
1937 | _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce), | |
1938 | &mce_ignore_ce | |
1939 | }; | |
1940 | ||
1941 | static struct sysdev_ext_attribute attr_cmci_disabled = { | |
74b602c7 | 1942 | _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled), |
9af43b54 HS |
1943 | &mce_cmci_disabled |
1944 | }; | |
1945 | ||
cb491fca | 1946 | static struct sysdev_attribute *mce_attrs[] = { |
9af43b54 HS |
1947 | &attr_tolerant.attr, |
1948 | &attr_check_interval.attr, | |
1949 | &attr_trigger, | |
3c079792 | 1950 | &attr_monarch_timeout.attr, |
9af43b54 HS |
1951 | &attr_dont_log_ce.attr, |
1952 | &attr_ignore_ce.attr, | |
1953 | &attr_cmci_disabled.attr, | |
a98f0dd3 AK |
1954 | NULL |
1955 | }; | |
1da177e4 | 1956 | |
cb491fca | 1957 | static cpumask_var_t mce_dev_initialized; |
bae19fe0 | 1958 | |
e9eee03e | 1959 | /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */ |
91c6d400 | 1960 | static __cpuinit int mce_create_device(unsigned int cpu) |
1da177e4 LT |
1961 | { |
1962 | int err; | |
b1f49f95 | 1963 | int i, j; |
92cb7612 | 1964 | |
90367556 | 1965 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
1966 | return -EIO; |
1967 | ||
cb491fca IM |
1968 | memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject)); |
1969 | per_cpu(mce_dev, cpu).id = cpu; | |
1970 | per_cpu(mce_dev, cpu).cls = &mce_sysclass; | |
91c6d400 | 1971 | |
cb491fca | 1972 | err = sysdev_register(&per_cpu(mce_dev, cpu)); |
d435d862 AM |
1973 | if (err) |
1974 | return err; | |
1975 | ||
cb491fca IM |
1976 | for (i = 0; mce_attrs[i]; i++) { |
1977 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
d435d862 AM |
1978 | if (err) |
1979 | goto error; | |
1980 | } | |
b1f49f95 | 1981 | for (j = 0; j < banks; j++) { |
cb491fca | 1982 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), |
cebe1820 | 1983 | &mce_banks[j].attr); |
0d7482e3 AK |
1984 | if (err) |
1985 | goto error2; | |
1986 | } | |
cb491fca | 1987 | cpumask_set_cpu(cpu, mce_dev_initialized); |
91c6d400 | 1988 | |
d435d862 | 1989 | return 0; |
0d7482e3 | 1990 | error2: |
b1f49f95 | 1991 | while (--j >= 0) |
cebe1820 | 1992 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr); |
d435d862 | 1993 | error: |
cb491fca | 1994 | while (--i >= 0) |
5c0e9f28 | 1995 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); |
cb491fca IM |
1996 | |
1997 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
d435d862 | 1998 | |
91c6d400 AK |
1999 | return err; |
2000 | } | |
2001 | ||
2d9cd6c2 | 2002 | static __cpuinit void mce_remove_device(unsigned int cpu) |
91c6d400 | 2003 | { |
73ca5358 SL |
2004 | int i; |
2005 | ||
cb491fca | 2006 | if (!cpumask_test_cpu(cpu, mce_dev_initialized)) |
bae19fe0 AH |
2007 | return; |
2008 | ||
cb491fca IM |
2009 | for (i = 0; mce_attrs[i]; i++) |
2010 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
2011 | ||
0d7482e3 | 2012 | for (i = 0; i < banks; i++) |
cebe1820 | 2013 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr); |
cb491fca IM |
2014 | |
2015 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
2016 | cpumask_clear_cpu(cpu, mce_dev_initialized); | |
91c6d400 | 2017 | } |
91c6d400 | 2018 | |
d6b75584 | 2019 | /* Make sure there are no machine checks on offlined CPUs. */ |
767df1bd | 2020 | static void __cpuinit mce_disable_cpu(void *h) |
d6b75584 | 2021 | { |
88ccbedd | 2022 | unsigned long action = *(unsigned long *)h; |
cb491fca | 2023 | int i; |
d6b75584 AK |
2024 | |
2025 | if (!mce_available(¤t_cpu_data)) | |
2026 | return; | |
767df1bd | 2027 | |
88ccbedd AK |
2028 | if (!(action & CPU_TASKS_FROZEN)) |
2029 | cmci_clear(); | |
06b7a7a5 | 2030 | for (i = 0; i < banks; i++) { |
cebe1820 | 2031 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2032 | |
cebe1820 | 2033 | if (b->init) |
a2d32bcb | 2034 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 2035 | } |
d6b75584 AK |
2036 | } |
2037 | ||
767df1bd | 2038 | static void __cpuinit mce_reenable_cpu(void *h) |
d6b75584 | 2039 | { |
88ccbedd | 2040 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 2041 | int i; |
d6b75584 AK |
2042 | |
2043 | if (!mce_available(¤t_cpu_data)) | |
2044 | return; | |
e9eee03e | 2045 | |
88ccbedd AK |
2046 | if (!(action & CPU_TASKS_FROZEN)) |
2047 | cmci_reenable(); | |
06b7a7a5 | 2048 | for (i = 0; i < banks; i++) { |
cebe1820 | 2049 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2050 | |
cebe1820 | 2051 | if (b->init) |
a2d32bcb | 2052 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
06b7a7a5 | 2053 | } |
d6b75584 AK |
2054 | } |
2055 | ||
91c6d400 | 2056 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
e9eee03e IM |
2057 | static int __cpuinit |
2058 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) | |
91c6d400 AK |
2059 | { |
2060 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 2061 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 AK |
2062 | |
2063 | switch (action) { | |
bae19fe0 AH |
2064 | case CPU_ONLINE: |
2065 | case CPU_ONLINE_FROZEN: | |
2066 | mce_create_device(cpu); | |
8735728e RW |
2067 | if (threshold_cpu_callback) |
2068 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 2069 | break; |
91c6d400 | 2070 | case CPU_DEAD: |
8bb78442 | 2071 | case CPU_DEAD_FROZEN: |
8735728e RW |
2072 | if (threshold_cpu_callback) |
2073 | threshold_cpu_callback(action, cpu); | |
91c6d400 AK |
2074 | mce_remove_device(cpu); |
2075 | break; | |
52d168e2 AK |
2076 | case CPU_DOWN_PREPARE: |
2077 | case CPU_DOWN_PREPARE_FROZEN: | |
2078 | del_timer_sync(t); | |
88ccbedd | 2079 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
52d168e2 AK |
2080 | break; |
2081 | case CPU_DOWN_FAILED: | |
2082 | case CPU_DOWN_FAILED_FROZEN: | |
fe5ed91d HS |
2083 | if (!mce_ignore_ce && check_interval) { |
2084 | t->expires = round_jiffies(jiffies + | |
245b2e70 | 2085 | __get_cpu_var(mce_next_interval)); |
fe5ed91d HS |
2086 | add_timer_on(t, cpu); |
2087 | } | |
88ccbedd AK |
2088 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
2089 | break; | |
2090 | case CPU_POST_DEAD: | |
2091 | /* intentionally ignoring frozen here */ | |
2092 | cmci_rediscover(cpu); | |
52d168e2 | 2093 | break; |
91c6d400 | 2094 | } |
bae19fe0 | 2095 | return NOTIFY_OK; |
91c6d400 AK |
2096 | } |
2097 | ||
1e35669d | 2098 | static struct notifier_block mce_cpu_notifier __cpuinitdata = { |
91c6d400 AK |
2099 | .notifier_call = mce_cpu_callback, |
2100 | }; | |
2101 | ||
cebe1820 | 2102 | static __init void mce_init_banks(void) |
0d7482e3 AK |
2103 | { |
2104 | int i; | |
2105 | ||
0d7482e3 | 2106 | for (i = 0; i < banks; i++) { |
cebe1820 AK |
2107 | struct mce_bank *b = &mce_banks[i]; |
2108 | struct sysdev_attribute *a = &b->attr; | |
e9eee03e | 2109 | |
a07e4156 | 2110 | sysfs_attr_init(&a->attr); |
cebe1820 AK |
2111 | a->attr.name = b->attrname; |
2112 | snprintf(b->attrname, ATTR_LEN, "bank%d", i); | |
e9eee03e IM |
2113 | |
2114 | a->attr.mode = 0644; | |
2115 | a->show = show_bank; | |
2116 | a->store = set_bank; | |
0d7482e3 | 2117 | } |
0d7482e3 AK |
2118 | } |
2119 | ||
5e09954a | 2120 | static __init int mcheck_init_device(void) |
91c6d400 AK |
2121 | { |
2122 | int err; | |
2123 | int i = 0; | |
2124 | ||
1da177e4 LT |
2125 | if (!mce_available(&boot_cpu_data)) |
2126 | return -EIO; | |
0d7482e3 | 2127 | |
e92fae06 | 2128 | zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL); |
996867d0 | 2129 | |
cebe1820 | 2130 | mce_init_banks(); |
0d7482e3 | 2131 | |
1da177e4 | 2132 | err = sysdev_class_register(&mce_sysclass); |
d435d862 AM |
2133 | if (err) |
2134 | return err; | |
91c6d400 AK |
2135 | |
2136 | for_each_online_cpu(i) { | |
d435d862 AM |
2137 | err = mce_create_device(i); |
2138 | if (err) | |
2139 | return err; | |
91c6d400 AK |
2140 | } |
2141 | ||
be6b5a35 | 2142 | register_hotcpu_notifier(&mce_cpu_notifier); |
1da177e4 | 2143 | misc_register(&mce_log_device); |
e9eee03e | 2144 | |
1da177e4 | 2145 | return err; |
1da177e4 | 2146 | } |
91c6d400 | 2147 | |
5e09954a | 2148 | device_initcall(mcheck_init_device); |
a988d334 | 2149 | |
d7c3c9a6 AK |
2150 | /* |
2151 | * Old style boot options parsing. Only for compatibility. | |
2152 | */ | |
2153 | static int __init mcheck_disable(char *str) | |
2154 | { | |
2155 | mce_disabled = 1; | |
2156 | return 1; | |
2157 | } | |
2158 | __setup("nomce", mcheck_disable); | |
a988d334 | 2159 | |
5be9ed25 HY |
2160 | #ifdef CONFIG_DEBUG_FS |
2161 | struct dentry *mce_get_debugfs_dir(void) | |
a988d334 | 2162 | { |
5be9ed25 | 2163 | static struct dentry *dmce; |
a988d334 | 2164 | |
5be9ed25 HY |
2165 | if (!dmce) |
2166 | dmce = debugfs_create_dir("mce", NULL); | |
a988d334 | 2167 | |
5be9ed25 HY |
2168 | return dmce; |
2169 | } | |
a988d334 | 2170 | |
bf783f9f HY |
2171 | static void mce_reset(void) |
2172 | { | |
2173 | cpu_missing = 0; | |
2174 | atomic_set(&mce_fake_paniced, 0); | |
2175 | atomic_set(&mce_executing, 0); | |
2176 | atomic_set(&mce_callin, 0); | |
2177 | atomic_set(&global_nwo, 0); | |
2178 | } | |
a988d334 | 2179 | |
bf783f9f HY |
2180 | static int fake_panic_get(void *data, u64 *val) |
2181 | { | |
2182 | *val = fake_panic; | |
2183 | return 0; | |
a988d334 IM |
2184 | } |
2185 | ||
bf783f9f | 2186 | static int fake_panic_set(void *data, u64 val) |
a988d334 | 2187 | { |
bf783f9f HY |
2188 | mce_reset(); |
2189 | fake_panic = val; | |
2190 | return 0; | |
a988d334 | 2191 | } |
a988d334 | 2192 | |
bf783f9f HY |
2193 | DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get, |
2194 | fake_panic_set, "%llu\n"); | |
d7c3c9a6 | 2195 | |
5e09954a | 2196 | static int __init mcheck_debugfs_init(void) |
d7c3c9a6 | 2197 | { |
bf783f9f HY |
2198 | struct dentry *dmce, *ffake_panic; |
2199 | ||
2200 | dmce = mce_get_debugfs_dir(); | |
2201 | if (!dmce) | |
2202 | return -ENOMEM; | |
2203 | ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL, | |
2204 | &fake_panic_fops); | |
2205 | if (!ffake_panic) | |
2206 | return -ENOMEM; | |
2207 | ||
2208 | return 0; | |
d7c3c9a6 | 2209 | } |
5e09954a | 2210 | late_initcall(mcheck_debugfs_init); |
5be9ed25 | 2211 | #endif |