]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
e9eee03e IM |
10 | #include <linux/thread_info.h> |
11 | #include <linux/capability.h> | |
12 | #include <linux/miscdevice.h> | |
ccc3c319 | 13 | #include <linux/interrupt.h> |
e9eee03e IM |
14 | #include <linux/ratelimit.h> |
15 | #include <linux/kallsyms.h> | |
16 | #include <linux/rcupdate.h> | |
e9eee03e | 17 | #include <linux/kobject.h> |
14a02530 | 18 | #include <linux/uaccess.h> |
e9eee03e IM |
19 | #include <linux/kdebug.h> |
20 | #include <linux/kernel.h> | |
21 | #include <linux/percpu.h> | |
1da177e4 | 22 | #include <linux/string.h> |
1da177e4 | 23 | #include <linux/sysdev.h> |
3c079792 | 24 | #include <linux/delay.h> |
8c566ef5 | 25 | #include <linux/ctype.h> |
e9eee03e | 26 | #include <linux/sched.h> |
0d7482e3 | 27 | #include <linux/sysfs.h> |
e9eee03e IM |
28 | #include <linux/types.h> |
29 | #include <linux/init.h> | |
30 | #include <linux/kmod.h> | |
31 | #include <linux/poll.h> | |
3c079792 | 32 | #include <linux/nmi.h> |
e9eee03e | 33 | #include <linux/cpu.h> |
14a02530 | 34 | #include <linux/smp.h> |
e9eee03e IM |
35 | #include <linux/fs.h> |
36 | ||
d88203d1 | 37 | #include <asm/processor.h> |
ccc3c319 AK |
38 | #include <asm/hw_irq.h> |
39 | #include <asm/apic.h> | |
e02e68d3 | 40 | #include <asm/idle.h> |
ccc3c319 | 41 | #include <asm/ipi.h> |
e9eee03e IM |
42 | #include <asm/mce.h> |
43 | #include <asm/msr.h> | |
1da177e4 | 44 | |
bd19a5e6 | 45 | #include "mce-internal.h" |
711c2e48 IM |
46 | #include "mce.h" |
47 | ||
5d727926 AK |
48 | /* Handle unconfigured int18 (should never happen) */ |
49 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
50 | { | |
51 | printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n", | |
52 | smp_processor_id()); | |
53 | } | |
54 | ||
55 | /* Call the installed machine check handler for this CPU setup. */ | |
56 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
57 | unexpected_machine_check; | |
04b2b1a4 AK |
58 | |
59 | int mce_disabled; | |
60 | ||
4efc0670 | 61 | #ifdef CONFIG_X86_NEW_MCE |
711c2e48 | 62 | |
e9eee03e | 63 | #define MISC_MCELOG_MINOR 227 |
0d7482e3 | 64 | |
3c079792 AK |
65 | #define SPINUNIT 100 /* 100ns */ |
66 | ||
553f265f AK |
67 | atomic_t mce_entry; |
68 | ||
01ca79f1 AK |
69 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
70 | ||
bd78432c TH |
71 | /* |
72 | * Tolerant levels: | |
73 | * 0: always panic on uncorrected errors, log corrected errors | |
74 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
75 | * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors | |
76 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
77 | */ | |
e9eee03e IM |
78 | static int tolerant = 1; |
79 | static int banks; | |
80 | static u64 *bank; | |
81 | static unsigned long notify_user; | |
82 | static int rip_msr; | |
83 | static int mce_bootlog = -1; | |
3c079792 | 84 | static int monarch_timeout = -1; |
29b0f591 | 85 | static int mce_panic_timeout; |
a98f0dd3 | 86 | |
e9eee03e IM |
87 | static char trigger[128]; |
88 | static char *trigger_argv[2] = { trigger, NULL }; | |
1da177e4 | 89 | |
06b7a7a5 AK |
90 | static unsigned long dont_init_banks; |
91 | ||
e02e68d3 | 92 | static DECLARE_WAIT_QUEUE_HEAD(mce_wait); |
3c079792 AK |
93 | static DEFINE_PER_CPU(struct mce, mces_seen); |
94 | static int cpu_missing; | |
95 | ||
e02e68d3 | 96 | |
ee031c31 AK |
97 | /* MCA banks polled by the period polling timer for corrected events */ |
98 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { | |
99 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
100 | }; | |
101 | ||
06b7a7a5 AK |
102 | static inline int skip_bank_init(int i) |
103 | { | |
104 | return i < BITS_PER_LONG && test_bit(i, &dont_init_banks); | |
105 | } | |
106 | ||
b5f2fa4e AK |
107 | /* Do initial initialization of a struct mce */ |
108 | void mce_setup(struct mce *m) | |
109 | { | |
110 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 111 | m->cpu = m->extcpu = smp_processor_id(); |
b5f2fa4e | 112 | rdtscll(m->tsc); |
8ee08347 AK |
113 | /* We hope get_seconds stays lockless */ |
114 | m->time = get_seconds(); | |
115 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
116 | m->cpuid = cpuid_eax(1); | |
117 | #ifdef CONFIG_SMP | |
118 | m->socketid = cpu_data(m->extcpu).phys_proc_id; | |
119 | #endif | |
120 | m->apicid = cpu_data(m->extcpu).initial_apicid; | |
121 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
b5f2fa4e AK |
122 | } |
123 | ||
ea149b36 AK |
124 | DEFINE_PER_CPU(struct mce, injectm); |
125 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
126 | ||
1da177e4 LT |
127 | /* |
128 | * Lockless MCE logging infrastructure. | |
129 | * This avoids deadlocks on printk locks without having to break locks. Also | |
130 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
131 | */ | |
132 | ||
231fd906 | 133 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
134 | .signature = MCE_LOG_SIGNATURE, |
135 | .len = MCE_LOG_LEN, | |
136 | .recordlen = sizeof(struct mce), | |
d88203d1 | 137 | }; |
1da177e4 LT |
138 | |
139 | void mce_log(struct mce *mce) | |
140 | { | |
141 | unsigned next, entry; | |
e9eee03e | 142 | |
1da177e4 | 143 | mce->finished = 0; |
7644143c | 144 | wmb(); |
1da177e4 LT |
145 | for (;;) { |
146 | entry = rcu_dereference(mcelog.next); | |
673242c1 | 147 | for (;;) { |
e9eee03e IM |
148 | /* |
149 | * When the buffer fills up discard new entries. | |
150 | * Assume that the earlier errors are the more | |
151 | * interesting ones: | |
152 | */ | |
673242c1 | 153 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
154 | set_bit(MCE_OVERFLOW, |
155 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
156 | return; |
157 | } | |
e9eee03e | 158 | /* Old left over entry. Skip: */ |
673242c1 AK |
159 | if (mcelog.entry[entry].finished) { |
160 | entry++; | |
161 | continue; | |
162 | } | |
7644143c | 163 | break; |
1da177e4 | 164 | } |
1da177e4 LT |
165 | smp_rmb(); |
166 | next = entry + 1; | |
167 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
168 | break; | |
169 | } | |
170 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 171 | wmb(); |
1da177e4 | 172 | mcelog.entry[entry].finished = 1; |
7644143c | 173 | wmb(); |
1da177e4 | 174 | |
a0189c70 | 175 | mce->finished = 1; |
e02e68d3 | 176 | set_bit(0, ¬ify_user); |
1da177e4 LT |
177 | } |
178 | ||
86503560 | 179 | static void print_mce(struct mce *m, int *first) |
1da177e4 | 180 | { |
86503560 AK |
181 | if (*first) { |
182 | printk(KERN_EMERG "\n" KERN_EMERG "HARDWARE ERROR\n"); | |
183 | *first = 0; | |
184 | } | |
185 | printk(KERN_EMERG | |
1da177e4 | 186 | "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n", |
d620c67f | 187 | m->extcpu, m->mcgstatus, m->bank, m->status); |
65ea5b03 | 188 | if (m->ip) { |
d88203d1 | 189 | printk(KERN_EMERG "RIP%s %02x:<%016Lx> ", |
1da177e4 | 190 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
65ea5b03 | 191 | m->cs, m->ip); |
1da177e4 | 192 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 193 | print_symbol("{%s}", m->ip); |
1da177e4 LT |
194 | printk("\n"); |
195 | } | |
f6d1826d | 196 | printk(KERN_EMERG "TSC %llx ", m->tsc); |
1da177e4 | 197 | if (m->addr) |
f6d1826d | 198 | printk("ADDR %llx ", m->addr); |
1da177e4 | 199 | if (m->misc) |
f6d1826d | 200 | printk("MISC %llx ", m->misc); |
1da177e4 | 201 | printk("\n"); |
8ee08347 AK |
202 | printk(KERN_EMERG "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n", |
203 | m->cpuvendor, m->cpuid, m->time, m->socketid, | |
204 | m->apicid); | |
86503560 AK |
205 | } |
206 | ||
207 | static void print_mce_tail(void) | |
208 | { | |
209 | printk(KERN_EMERG "This is not a software problem!\n" | |
210 | KERN_EMERG "Run through mcelog --ascii to decode and contact your hardware vendor\n"); | |
1da177e4 LT |
211 | } |
212 | ||
f94b61c2 AK |
213 | #define PANIC_TIMEOUT 5 /* 5 seconds */ |
214 | ||
215 | static atomic_t mce_paniced; | |
216 | ||
217 | /* Panic in progress. Enable interrupts and wait for final IPI */ | |
218 | static void wait_for_panic(void) | |
219 | { | |
220 | long timeout = PANIC_TIMEOUT*USEC_PER_SEC; | |
221 | preempt_disable(); | |
222 | local_irq_enable(); | |
223 | while (timeout-- > 0) | |
224 | udelay(1); | |
29b0f591 AK |
225 | if (panic_timeout == 0) |
226 | panic_timeout = mce_panic_timeout; | |
f94b61c2 AK |
227 | panic("Panicing machine check CPU died"); |
228 | } | |
229 | ||
bd19a5e6 | 230 | static void mce_panic(char *msg, struct mce *final, char *exp) |
d88203d1 | 231 | { |
1da177e4 | 232 | int i; |
86503560 | 233 | int first = 1; |
e02e68d3 | 234 | |
f94b61c2 AK |
235 | /* |
236 | * Make sure only one CPU runs in machine check panic | |
237 | */ | |
238 | if (atomic_add_return(1, &mce_paniced) > 1) | |
239 | wait_for_panic(); | |
240 | barrier(); | |
241 | ||
d896a940 AK |
242 | bust_spinlocks(1); |
243 | console_verbose(); | |
a0189c70 | 244 | /* First print corrected ones that are still unlogged */ |
1da177e4 | 245 | for (i = 0; i < MCE_LOG_LEN; i++) { |
a0189c70 AK |
246 | struct mce *m = &mcelog.entry[i]; |
247 | if ((m->status & MCI_STATUS_VAL) && | |
248 | !(m->status & MCI_STATUS_UC)) | |
86503560 | 249 | print_mce(m, &first); |
a0189c70 AK |
250 | } |
251 | /* Now print uncorrected but with the final one last */ | |
252 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
253 | struct mce *m = &mcelog.entry[i]; | |
254 | if (!(m->status & MCI_STATUS_VAL)) | |
1da177e4 | 255 | continue; |
a0189c70 | 256 | if (!final || memcmp(m, final, sizeof(struct mce))) |
86503560 | 257 | print_mce(m, &first); |
1da177e4 | 258 | } |
a0189c70 | 259 | if (final) |
86503560 | 260 | print_mce(final, &first); |
3c079792 AK |
261 | if (cpu_missing) |
262 | printk(KERN_EMERG "Some CPUs didn't answer in synchronization\n"); | |
86503560 | 263 | print_mce_tail(); |
bd19a5e6 AK |
264 | if (exp) |
265 | printk(KERN_EMERG "Machine check: %s\n", exp); | |
29b0f591 AK |
266 | if (panic_timeout == 0) |
267 | panic_timeout = mce_panic_timeout; | |
e02e68d3 | 268 | panic(msg); |
d88203d1 | 269 | } |
1da177e4 | 270 | |
ea149b36 AK |
271 | /* Support code for software error injection */ |
272 | ||
273 | static int msr_to_offset(u32 msr) | |
274 | { | |
275 | unsigned bank = __get_cpu_var(injectm.bank); | |
276 | if (msr == rip_msr) | |
277 | return offsetof(struct mce, ip); | |
278 | if (msr == MSR_IA32_MC0_STATUS + bank*4) | |
279 | return offsetof(struct mce, status); | |
280 | if (msr == MSR_IA32_MC0_ADDR + bank*4) | |
281 | return offsetof(struct mce, addr); | |
282 | if (msr == MSR_IA32_MC0_MISC + bank*4) | |
283 | return offsetof(struct mce, misc); | |
284 | if (msr == MSR_IA32_MCG_STATUS) | |
285 | return offsetof(struct mce, mcgstatus); | |
286 | return -1; | |
287 | } | |
288 | ||
5f8c1a54 AK |
289 | /* MSR access wrappers used for error injection */ |
290 | static u64 mce_rdmsrl(u32 msr) | |
291 | { | |
292 | u64 v; | |
ea149b36 AK |
293 | if (__get_cpu_var(injectm).finished) { |
294 | int offset = msr_to_offset(msr); | |
295 | if (offset < 0) | |
296 | return 0; | |
297 | return *(u64 *)((char *)&__get_cpu_var(injectm) + offset); | |
298 | } | |
5f8c1a54 AK |
299 | rdmsrl(msr, v); |
300 | return v; | |
301 | } | |
302 | ||
303 | static void mce_wrmsrl(u32 msr, u64 v) | |
304 | { | |
ea149b36 AK |
305 | if (__get_cpu_var(injectm).finished) { |
306 | int offset = msr_to_offset(msr); | |
307 | if (offset >= 0) | |
308 | *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v; | |
309 | return; | |
310 | } | |
5f8c1a54 AK |
311 | wrmsrl(msr, v); |
312 | } | |
313 | ||
88ccbedd | 314 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 315 | { |
04b2b1a4 | 316 | if (mce_disabled) |
5b4408fd | 317 | return 0; |
3d1712c9 | 318 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
319 | } |
320 | ||
1b2797dc HY |
321 | /* |
322 | * Get the address of the instruction at the time of the machine check | |
323 | * error. | |
324 | */ | |
94ad8474 AK |
325 | static inline void mce_get_rip(struct mce *m, struct pt_regs *regs) |
326 | { | |
1b2797dc HY |
327 | |
328 | if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) { | |
65ea5b03 | 329 | m->ip = regs->ip; |
94ad8474 AK |
330 | m->cs = regs->cs; |
331 | } else { | |
65ea5b03 | 332 | m->ip = 0; |
94ad8474 AK |
333 | m->cs = 0; |
334 | } | |
1b2797dc | 335 | if (rip_msr) |
5f8c1a54 | 336 | m->ip = mce_rdmsrl(rip_msr); |
94ad8474 AK |
337 | } |
338 | ||
ccc3c319 AK |
339 | #ifdef CONFIG_X86_LOCAL_APIC |
340 | /* | |
341 | * Called after interrupts have been reenabled again | |
342 | * when a MCE happened during an interrupts off region | |
343 | * in the kernel. | |
344 | */ | |
345 | asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs) | |
346 | { | |
347 | ack_APIC_irq(); | |
348 | exit_idle(); | |
349 | irq_enter(); | |
350 | mce_notify_user(); | |
351 | irq_exit(); | |
352 | } | |
353 | #endif | |
354 | ||
355 | static void mce_report_event(struct pt_regs *regs) | |
356 | { | |
357 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { | |
358 | mce_notify_user(); | |
359 | return; | |
360 | } | |
361 | ||
362 | #ifdef CONFIG_X86_LOCAL_APIC | |
363 | /* | |
364 | * Without APIC do not notify. The event will be picked | |
365 | * up eventually. | |
366 | */ | |
367 | if (!cpu_has_apic) | |
368 | return; | |
369 | ||
370 | /* | |
371 | * When interrupts are disabled we cannot use | |
372 | * kernel services safely. Trigger an self interrupt | |
373 | * through the APIC to instead do the notification | |
374 | * after interrupts are reenabled again. | |
375 | */ | |
376 | apic->send_IPI_self(MCE_SELF_VECTOR); | |
377 | ||
378 | /* | |
379 | * Wait for idle afterwards again so that we don't leave the | |
380 | * APIC in a non idle state because the normal APIC writes | |
381 | * cannot exclude us. | |
382 | */ | |
383 | apic_wait_icr_idle(); | |
384 | #endif | |
385 | } | |
386 | ||
ca84f696 AK |
387 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
388 | ||
d88203d1 | 389 | /* |
b79109c3 AK |
390 | * Poll for corrected events or events that happened before reset. |
391 | * Those are just logged through /dev/mcelog. | |
392 | * | |
393 | * This is executed in standard interrupt context. | |
394 | */ | |
ee031c31 | 395 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 AK |
396 | { |
397 | struct mce m; | |
398 | int i; | |
399 | ||
ca84f696 AK |
400 | __get_cpu_var(mce_poll_count)++; |
401 | ||
b79109c3 AK |
402 | mce_setup(&m); |
403 | ||
5f8c1a54 | 404 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
b79109c3 | 405 | for (i = 0; i < banks; i++) { |
ee031c31 | 406 | if (!bank[i] || !test_bit(i, *b)) |
b79109c3 AK |
407 | continue; |
408 | ||
409 | m.misc = 0; | |
410 | m.addr = 0; | |
411 | m.bank = i; | |
412 | m.tsc = 0; | |
413 | ||
414 | barrier(); | |
5f8c1a54 | 415 | m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4); |
b79109c3 AK |
416 | if (!(m.status & MCI_STATUS_VAL)) |
417 | continue; | |
418 | ||
419 | /* | |
420 | * Uncorrected events are handled by the exception handler | |
421 | * when it is enabled. But when the exception is disabled log | |
422 | * everything. | |
423 | * | |
424 | * TBD do the same check for MCI_STATUS_EN here? | |
425 | */ | |
426 | if ((m.status & MCI_STATUS_UC) && !(flags & MCP_UC)) | |
427 | continue; | |
428 | ||
429 | if (m.status & MCI_STATUS_MISCV) | |
5f8c1a54 | 430 | m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4); |
b79109c3 | 431 | if (m.status & MCI_STATUS_ADDRV) |
5f8c1a54 | 432 | m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4); |
b79109c3 AK |
433 | |
434 | if (!(flags & MCP_TIMESTAMP)) | |
435 | m.tsc = 0; | |
436 | /* | |
437 | * Don't get the IP here because it's unlikely to | |
438 | * have anything to do with the actual error location. | |
439 | */ | |
5679af4c AK |
440 | if (!(flags & MCP_DONTLOG)) { |
441 | mce_log(&m); | |
442 | add_taint(TAINT_MACHINE_CHECK); | |
443 | } | |
b79109c3 AK |
444 | |
445 | /* | |
446 | * Clear state for this bank. | |
447 | */ | |
5f8c1a54 | 448 | mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); |
b79109c3 AK |
449 | } |
450 | ||
451 | /* | |
452 | * Don't clear MCG_STATUS here because it's only defined for | |
453 | * exceptions. | |
454 | */ | |
88921be3 AK |
455 | |
456 | sync_core(); | |
b79109c3 | 457 | } |
ea149b36 | 458 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 | 459 | |
bd19a5e6 AK |
460 | /* |
461 | * Do a quick check if any of the events requires a panic. | |
462 | * This decides if we keep the events around or clear them. | |
463 | */ | |
464 | static int mce_no_way_out(struct mce *m, char **msg) | |
465 | { | |
466 | int i; | |
467 | ||
468 | for (i = 0; i < banks; i++) { | |
469 | m->status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4); | |
470 | if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY) | |
471 | return 1; | |
472 | } | |
473 | return 0; | |
474 | } | |
475 | ||
3c079792 AK |
476 | /* |
477 | * Variable to establish order between CPUs while scanning. | |
478 | * Each CPU spins initially until executing is equal its number. | |
479 | */ | |
480 | static atomic_t mce_executing; | |
481 | ||
482 | /* | |
483 | * Defines order of CPUs on entry. First CPU becomes Monarch. | |
484 | */ | |
485 | static atomic_t mce_callin; | |
486 | ||
487 | /* | |
488 | * Check if a timeout waiting for other CPUs happened. | |
489 | */ | |
490 | static int mce_timed_out(u64 *t) | |
491 | { | |
492 | /* | |
493 | * The others already did panic for some reason. | |
494 | * Bail out like in a timeout. | |
495 | * rmb() to tell the compiler that system_state | |
496 | * might have been modified by someone else. | |
497 | */ | |
498 | rmb(); | |
499 | if (atomic_read(&mce_paniced)) | |
500 | wait_for_panic(); | |
501 | if (!monarch_timeout) | |
502 | goto out; | |
503 | if ((s64)*t < SPINUNIT) { | |
504 | /* CHECKME: Make panic default for 1 too? */ | |
505 | if (tolerant < 1) | |
506 | mce_panic("Timeout synchronizing machine check over CPUs", | |
507 | NULL, NULL); | |
508 | cpu_missing = 1; | |
509 | return 1; | |
510 | } | |
511 | *t -= SPINUNIT; | |
512 | out: | |
513 | touch_nmi_watchdog(); | |
514 | return 0; | |
515 | } | |
516 | ||
517 | /* | |
518 | * The Monarch's reign. The Monarch is the CPU who entered | |
519 | * the machine check handler first. It waits for the others to | |
520 | * raise the exception too and then grades them. When any | |
521 | * error is fatal panic. Only then let the others continue. | |
522 | * | |
523 | * The other CPUs entering the MCE handler will be controlled by the | |
524 | * Monarch. They are called Subjects. | |
525 | * | |
526 | * This way we prevent any potential data corruption in a unrecoverable case | |
527 | * and also makes sure always all CPU's errors are examined. | |
528 | * | |
529 | * Also this detects the case of an machine check event coming from outer | |
530 | * space (not detected by any CPUs) In this case some external agent wants | |
531 | * us to shut down, so panic too. | |
532 | * | |
533 | * The other CPUs might still decide to panic if the handler happens | |
534 | * in a unrecoverable place, but in this case the system is in a semi-stable | |
535 | * state and won't corrupt anything by itself. It's ok to let the others | |
536 | * continue for a bit first. | |
537 | * | |
538 | * All the spin loops have timeouts; when a timeout happens a CPU | |
539 | * typically elects itself to be Monarch. | |
540 | */ | |
541 | static void mce_reign(void) | |
542 | { | |
543 | int cpu; | |
544 | struct mce *m = NULL; | |
545 | int global_worst = 0; | |
546 | char *msg = NULL; | |
547 | char *nmsg = NULL; | |
548 | ||
549 | /* | |
550 | * This CPU is the Monarch and the other CPUs have run | |
551 | * through their handlers. | |
552 | * Grade the severity of the errors of all the CPUs. | |
553 | */ | |
554 | for_each_possible_cpu(cpu) { | |
555 | int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant, | |
556 | &nmsg); | |
557 | if (severity > global_worst) { | |
558 | msg = nmsg; | |
559 | global_worst = severity; | |
560 | m = &per_cpu(mces_seen, cpu); | |
561 | } | |
562 | } | |
563 | ||
564 | /* | |
565 | * Cannot recover? Panic here then. | |
566 | * This dumps all the mces in the log buffer and stops the | |
567 | * other CPUs. | |
568 | */ | |
569 | if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3) | |
ac960375 | 570 | mce_panic("Fatal Machine check", m, msg); |
3c079792 AK |
571 | |
572 | /* | |
573 | * For UC somewhere we let the CPU who detects it handle it. | |
574 | * Also must let continue the others, otherwise the handling | |
575 | * CPU could deadlock on a lock. | |
576 | */ | |
577 | ||
578 | /* | |
579 | * No machine check event found. Must be some external | |
580 | * source or one CPU is hung. Panic. | |
581 | */ | |
582 | if (!m && tolerant < 3) | |
583 | mce_panic("Machine check from unknown source", NULL, NULL); | |
584 | ||
585 | /* | |
586 | * Now clear all the mces_seen so that they don't reappear on | |
587 | * the next mce. | |
588 | */ | |
589 | for_each_possible_cpu(cpu) | |
590 | memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); | |
591 | } | |
592 | ||
593 | static atomic_t global_nwo; | |
594 | ||
595 | /* | |
596 | * Start of Monarch synchronization. This waits until all CPUs have | |
597 | * entered the exception handler and then determines if any of them | |
598 | * saw a fatal event that requires panic. Then it executes them | |
599 | * in the entry order. | |
600 | * TBD double check parallel CPU hotunplug | |
601 | */ | |
602 | static int mce_start(int no_way_out, int *order) | |
603 | { | |
604 | int nwo; | |
605 | int cpus = num_online_cpus(); | |
606 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
607 | ||
608 | if (!timeout) { | |
609 | *order = -1; | |
610 | return no_way_out; | |
611 | } | |
612 | ||
613 | atomic_add(no_way_out, &global_nwo); | |
614 | ||
615 | /* | |
616 | * Wait for everyone. | |
617 | */ | |
618 | while (atomic_read(&mce_callin) != cpus) { | |
619 | if (mce_timed_out(&timeout)) { | |
620 | atomic_set(&global_nwo, 0); | |
621 | *order = -1; | |
622 | return no_way_out; | |
623 | } | |
624 | ndelay(SPINUNIT); | |
625 | } | |
626 | ||
627 | /* | |
628 | * Cache the global no_way_out state. | |
629 | */ | |
630 | nwo = atomic_read(&global_nwo); | |
631 | ||
632 | /* | |
633 | * Monarch starts executing now, the others wait. | |
634 | */ | |
635 | if (*order == 1) { | |
636 | atomic_set(&mce_executing, 1); | |
637 | return nwo; | |
638 | } | |
639 | ||
640 | /* | |
641 | * Now start the scanning loop one by one | |
642 | * in the original callin order. | |
643 | * This way when there are any shared banks it will | |
644 | * be only seen by one CPU before cleared, avoiding duplicates. | |
645 | */ | |
646 | while (atomic_read(&mce_executing) < *order) { | |
647 | if (mce_timed_out(&timeout)) { | |
648 | atomic_set(&global_nwo, 0); | |
649 | *order = -1; | |
650 | return no_way_out; | |
651 | } | |
652 | ndelay(SPINUNIT); | |
653 | } | |
654 | return nwo; | |
655 | } | |
656 | ||
657 | /* | |
658 | * Synchronize between CPUs after main scanning loop. | |
659 | * This invokes the bulk of the Monarch processing. | |
660 | */ | |
661 | static int mce_end(int order) | |
662 | { | |
663 | int ret = -1; | |
664 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
665 | ||
666 | if (!timeout) | |
667 | goto reset; | |
668 | if (order < 0) | |
669 | goto reset; | |
670 | ||
671 | /* | |
672 | * Allow others to run. | |
673 | */ | |
674 | atomic_inc(&mce_executing); | |
675 | ||
676 | if (order == 1) { | |
677 | /* CHECKME: Can this race with a parallel hotplug? */ | |
678 | int cpus = num_online_cpus(); | |
679 | ||
680 | /* | |
681 | * Monarch: Wait for everyone to go through their scanning | |
682 | * loops. | |
683 | */ | |
684 | while (atomic_read(&mce_executing) <= cpus) { | |
685 | if (mce_timed_out(&timeout)) | |
686 | goto reset; | |
687 | ndelay(SPINUNIT); | |
688 | } | |
689 | ||
690 | mce_reign(); | |
691 | barrier(); | |
692 | ret = 0; | |
693 | } else { | |
694 | /* | |
695 | * Subject: Wait for Monarch to finish. | |
696 | */ | |
697 | while (atomic_read(&mce_executing) != 0) { | |
698 | if (mce_timed_out(&timeout)) | |
699 | goto reset; | |
700 | ndelay(SPINUNIT); | |
701 | } | |
702 | ||
703 | /* | |
704 | * Don't reset anything. That's done by the Monarch. | |
705 | */ | |
706 | return 0; | |
707 | } | |
708 | ||
709 | /* | |
710 | * Reset all global state. | |
711 | */ | |
712 | reset: | |
713 | atomic_set(&global_nwo, 0); | |
714 | atomic_set(&mce_callin, 0); | |
715 | barrier(); | |
716 | ||
717 | /* | |
718 | * Let others run again. | |
719 | */ | |
720 | atomic_set(&mce_executing, 0); | |
721 | return ret; | |
722 | } | |
723 | ||
724 | static void mce_clear_state(unsigned long *toclear) | |
725 | { | |
726 | int i; | |
727 | ||
728 | for (i = 0; i < banks; i++) { | |
729 | if (test_bit(i, toclear)) | |
730 | mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); | |
731 | } | |
732 | } | |
733 | ||
b79109c3 AK |
734 | /* |
735 | * The actual machine check handler. This only handles real | |
736 | * exceptions when something got corrupted coming in through int 18. | |
737 | * | |
738 | * This is executed in NMI context not subject to normal locking rules. This | |
739 | * implies that most kernel services cannot be safely used. Don't even | |
740 | * think about putting a printk in there! | |
3c079792 AK |
741 | * |
742 | * On Intel systems this is entered on all CPUs in parallel through | |
743 | * MCE broadcast. However some CPUs might be broken beyond repair, | |
744 | * so be always careful when synchronizing with others. | |
1da177e4 | 745 | */ |
e9eee03e | 746 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 | 747 | { |
3c079792 | 748 | struct mce m, *final; |
1da177e4 | 749 | int i; |
3c079792 AK |
750 | int worst = 0; |
751 | int severity; | |
752 | /* | |
753 | * Establish sequential order between the CPUs entering the machine | |
754 | * check handler. | |
755 | */ | |
756 | int order; | |
757 | ||
bd78432c TH |
758 | /* |
759 | * If no_way_out gets set, there is no safe way to recover from this | |
760 | * MCE. If tolerant is cranked up, we'll try anyway. | |
761 | */ | |
762 | int no_way_out = 0; | |
763 | /* | |
764 | * If kill_it gets set, there might be a way to recover from this | |
765 | * error. | |
766 | */ | |
767 | int kill_it = 0; | |
b79109c3 | 768 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
bd19a5e6 | 769 | char *msg = "Unknown"; |
1da177e4 | 770 | |
553f265f AK |
771 | atomic_inc(&mce_entry); |
772 | ||
01ca79f1 AK |
773 | __get_cpu_var(mce_exception_count)++; |
774 | ||
b79109c3 | 775 | if (notify_die(DIE_NMI, "machine check", regs, error_code, |
22f5991c | 776 | 18, SIGKILL) == NOTIFY_STOP) |
32561696 | 777 | goto out; |
b79109c3 | 778 | if (!banks) |
32561696 | 779 | goto out; |
1da177e4 | 780 | |
3c079792 | 781 | order = atomic_add_return(1, &mce_callin); |
b5f2fa4e AK |
782 | mce_setup(&m); |
783 | ||
5f8c1a54 | 784 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
bd19a5e6 | 785 | no_way_out = mce_no_way_out(&m, &msg); |
d88203d1 | 786 | |
3c079792 AK |
787 | final = &__get_cpu_var(mces_seen); |
788 | *final = m; | |
789 | ||
1da177e4 LT |
790 | barrier(); |
791 | ||
3c079792 AK |
792 | /* |
793 | * Go through all the banks in exclusion of the other CPUs. | |
794 | * This way we don't report duplicated events on shared banks | |
795 | * because the first one to see it will clear it. | |
796 | */ | |
797 | no_way_out = mce_start(no_way_out, &order); | |
1da177e4 | 798 | for (i = 0; i < banks; i++) { |
b79109c3 | 799 | __clear_bit(i, toclear); |
0d7482e3 | 800 | if (!bank[i]) |
1da177e4 | 801 | continue; |
d88203d1 TG |
802 | |
803 | m.misc = 0; | |
1da177e4 LT |
804 | m.addr = 0; |
805 | m.bank = i; | |
1da177e4 | 806 | |
5f8c1a54 | 807 | m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4); |
1da177e4 LT |
808 | if ((m.status & MCI_STATUS_VAL) == 0) |
809 | continue; | |
810 | ||
b79109c3 AK |
811 | /* |
812 | * Non uncorrected errors are handled by machine_check_poll | |
de8a84d8 | 813 | * Leave them alone, unless this panics. |
b79109c3 | 814 | */ |
de8a84d8 | 815 | if ((m.status & MCI_STATUS_UC) == 0 && !no_way_out) |
b79109c3 AK |
816 | continue; |
817 | ||
818 | /* | |
819 | * Set taint even when machine check was not enabled. | |
820 | */ | |
821 | add_taint(TAINT_MACHINE_CHECK); | |
822 | ||
823 | __set_bit(i, toclear); | |
824 | ||
1da177e4 | 825 | if (m.status & MCI_STATUS_EN) { |
bd78432c TH |
826 | /* |
827 | * If this error was uncorrectable and there was | |
828 | * an overflow, we're in trouble. If no overflow, | |
829 | * we might get away with just killing a task. | |
830 | */ | |
bd19a5e6 | 831 | if (m.status & MCI_STATUS_UC) |
bd78432c | 832 | kill_it = 1; |
b79109c3 AK |
833 | } else { |
834 | /* | |
835 | * Machine check event was not enabled. Clear, but | |
836 | * ignore. | |
837 | */ | |
838 | continue; | |
1da177e4 LT |
839 | } |
840 | ||
841 | if (m.status & MCI_STATUS_MISCV) | |
5f8c1a54 | 842 | m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4); |
1da177e4 | 843 | if (m.status & MCI_STATUS_ADDRV) |
5f8c1a54 | 844 | m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4); |
1da177e4 | 845 | |
94ad8474 | 846 | mce_get_rip(&m, regs); |
b79109c3 | 847 | mce_log(&m); |
1da177e4 | 848 | |
3c079792 AK |
849 | severity = mce_severity(&m, tolerant, NULL); |
850 | if (severity > worst) { | |
851 | *final = m; | |
852 | worst = severity; | |
1da177e4 | 853 | } |
1da177e4 LT |
854 | } |
855 | ||
3c079792 AK |
856 | if (!no_way_out) |
857 | mce_clear_state(toclear); | |
858 | ||
e9eee03e | 859 | /* |
3c079792 AK |
860 | * Do most of the synchronization with other CPUs. |
861 | * When there's any problem use only local no_way_out state. | |
e9eee03e | 862 | */ |
3c079792 AK |
863 | if (mce_end(order) < 0) |
864 | no_way_out = worst >= MCE_PANIC_SEVERITY; | |
bd78432c TH |
865 | |
866 | /* | |
867 | * If we have decided that we just CAN'T continue, and the user | |
e9eee03e | 868 | * has not set tolerant to an insane level, give up and die. |
3c079792 AK |
869 | * |
870 | * This is mainly used in the case when the system doesn't | |
871 | * support MCE broadcasting or it has been disabled. | |
bd78432c TH |
872 | */ |
873 | if (no_way_out && tolerant < 3) | |
ac960375 | 874 | mce_panic("Fatal machine check on current CPU", final, msg); |
bd78432c TH |
875 | |
876 | /* | |
877 | * If the error seems to be unrecoverable, something should be | |
878 | * done. Try to kill as little as possible. If we can kill just | |
879 | * one task, do that. If the user has set the tolerance very | |
880 | * high, don't try to do anything at all. | |
881 | */ | |
882 | if (kill_it && tolerant < 3) { | |
1da177e4 LT |
883 | int user_space = 0; |
884 | ||
bd78432c TH |
885 | /* |
886 | * If the EIPV bit is set, it means the saved IP is the | |
887 | * instruction which caused the MCE. | |
888 | */ | |
889 | if (m.mcgstatus & MCG_STATUS_EIPV) | |
3c079792 | 890 | user_space = final->ip && (final->cs & 3); |
bd78432c TH |
891 | |
892 | /* | |
893 | * If we know that the error was in user space, send a | |
894 | * SIGBUS. Otherwise, panic if tolerance is low. | |
895 | * | |
380851bc | 896 | * force_sig() takes an awful lot of locks and has a slight |
bd78432c TH |
897 | * risk of deadlocking. |
898 | */ | |
899 | if (user_space) { | |
380851bc | 900 | force_sig(SIGBUS, current); |
bd78432c | 901 | } else if (panic_on_oops || tolerant < 2) { |
3c079792 | 902 | mce_panic("Uncorrected machine check", final, msg); |
bd78432c | 903 | } |
1da177e4 LT |
904 | } |
905 | ||
e02e68d3 TH |
906 | /* notify userspace ASAP */ |
907 | set_thread_flag(TIF_MCE_NOTIFY); | |
908 | ||
3c079792 AK |
909 | if (worst > 0) |
910 | mce_report_event(regs); | |
5f8c1a54 | 911 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 912 | out: |
553f265f | 913 | atomic_dec(&mce_entry); |
88921be3 | 914 | sync_core(); |
1da177e4 | 915 | } |
ea149b36 | 916 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 917 | |
15d5f839 DZ |
918 | #ifdef CONFIG_X86_MCE_INTEL |
919 | /*** | |
920 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 921 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
922 | * @status: Event status information |
923 | * | |
924 | * This function should be called by the thermal interrupt after the | |
925 | * event has been processed and the decision was made to log the event | |
926 | * further. | |
927 | * | |
928 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
929 | * and historically has been the register value of the | |
930 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
931 | */ | |
b5f2fa4e | 932 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
933 | { |
934 | struct mce m; | |
935 | ||
b5f2fa4e | 936 | mce_setup(&m); |
15d5f839 DZ |
937 | m.bank = MCE_THERMAL_BANK; |
938 | m.status = status; | |
15d5f839 DZ |
939 | mce_log(&m); |
940 | } | |
941 | #endif /* CONFIG_X86_MCE_INTEL */ | |
942 | ||
1da177e4 | 943 | /* |
8a336b0a TH |
944 | * Periodic polling timer for "silent" machine check errors. If the |
945 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
946 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 947 | */ |
1da177e4 | 948 | static int check_interval = 5 * 60; /* 5 minutes */ |
e9eee03e | 949 | |
6298c512 | 950 | static DEFINE_PER_CPU(int, next_interval); /* in jiffies */ |
52d168e2 | 951 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 952 | |
52d168e2 | 953 | static void mcheck_timer(unsigned long data) |
1da177e4 | 954 | { |
52d168e2 | 955 | struct timer_list *t = &per_cpu(mce_timer, data); |
6298c512 | 956 | int *n; |
52d168e2 AK |
957 | |
958 | WARN_ON(smp_processor_id() != data); | |
959 | ||
e9eee03e | 960 | if (mce_available(¤t_cpu_data)) { |
ee031c31 AK |
961 | machine_check_poll(MCP_TIMESTAMP, |
962 | &__get_cpu_var(mce_poll_banks)); | |
e9eee03e | 963 | } |
1da177e4 LT |
964 | |
965 | /* | |
e02e68d3 TH |
966 | * Alert userspace if needed. If we logged an MCE, reduce the |
967 | * polling interval, otherwise increase the polling interval. | |
1da177e4 | 968 | */ |
6298c512 | 969 | n = &__get_cpu_var(next_interval); |
14a02530 | 970 | if (mce_notify_user()) |
6298c512 | 971 | *n = max(*n/2, HZ/100); |
14a02530 | 972 | else |
6298c512 | 973 | *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ)); |
e02e68d3 | 974 | |
6298c512 | 975 | t->expires = jiffies + *n; |
52d168e2 | 976 | add_timer(t); |
e02e68d3 TH |
977 | } |
978 | ||
9bd98405 AK |
979 | static void mce_do_trigger(struct work_struct *work) |
980 | { | |
981 | call_usermodehelper(trigger, trigger_argv, NULL, UMH_NO_WAIT); | |
982 | } | |
983 | ||
984 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
985 | ||
e02e68d3 | 986 | /* |
9bd98405 AK |
987 | * Notify the user(s) about new machine check events. |
988 | * Can be called from interrupt context, but not from machine check/NMI | |
989 | * context. | |
e02e68d3 TH |
990 | */ |
991 | int mce_notify_user(void) | |
992 | { | |
8457c84d AK |
993 | /* Not more than two messages every minute */ |
994 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
995 | ||
e02e68d3 | 996 | clear_thread_flag(TIF_MCE_NOTIFY); |
e9eee03e | 997 | |
e02e68d3 | 998 | if (test_and_clear_bit(0, ¬ify_user)) { |
e02e68d3 | 999 | wake_up_interruptible(&mce_wait); |
9bd98405 AK |
1000 | |
1001 | /* | |
1002 | * There is no risk of missing notifications because | |
1003 | * work_pending is always cleared before the function is | |
1004 | * executed. | |
1005 | */ | |
1006 | if (trigger[0] && !work_pending(&mce_trigger_work)) | |
1007 | schedule_work(&mce_trigger_work); | |
e02e68d3 | 1008 | |
8457c84d | 1009 | if (__ratelimit(&ratelimit)) |
8a336b0a | 1010 | printk(KERN_INFO "Machine check events logged\n"); |
e02e68d3 TH |
1011 | |
1012 | return 1; | |
1da177e4 | 1013 | } |
e02e68d3 TH |
1014 | return 0; |
1015 | } | |
ea149b36 | 1016 | EXPORT_SYMBOL_GPL(mce_notify_user); |
8a336b0a | 1017 | |
d88203d1 | 1018 | /* |
1da177e4 LT |
1019 | * Initialize Machine Checks for a CPU. |
1020 | */ | |
0d7482e3 | 1021 | static int mce_cap_init(void) |
1da177e4 | 1022 | { |
0d7482e3 | 1023 | unsigned b; |
e9eee03e | 1024 | u64 cap; |
1da177e4 LT |
1025 | |
1026 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
1027 | |
1028 | b = cap & MCG_BANKCNT_MASK; | |
b659294b IM |
1029 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b); |
1030 | ||
0d7482e3 AK |
1031 | if (b > MAX_NR_BANKS) { |
1032 | printk(KERN_WARNING | |
1033 | "MCE: Using only %u machine check banks out of %u\n", | |
1034 | MAX_NR_BANKS, b); | |
1035 | b = MAX_NR_BANKS; | |
1036 | } | |
1037 | ||
1038 | /* Don't support asymmetric configurations today */ | |
1039 | WARN_ON(banks != 0 && b != banks); | |
1040 | banks = b; | |
1041 | if (!bank) { | |
1042 | bank = kmalloc(banks * sizeof(u64), GFP_KERNEL); | |
1043 | if (!bank) | |
1044 | return -ENOMEM; | |
1045 | memset(bank, 0xff, banks * sizeof(u64)); | |
1da177e4 | 1046 | } |
0d7482e3 | 1047 | |
94ad8474 | 1048 | /* Use accurate RIP reporting if available. */ |
01c6680a | 1049 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
94ad8474 | 1050 | rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 1051 | |
0d7482e3 AK |
1052 | return 0; |
1053 | } | |
1054 | ||
8be91105 | 1055 | static void mce_init(void) |
0d7482e3 | 1056 | { |
e9eee03e | 1057 | mce_banks_t all_banks; |
0d7482e3 AK |
1058 | u64 cap; |
1059 | int i; | |
1060 | ||
b79109c3 AK |
1061 | /* |
1062 | * Log the machine checks left over from the previous reset. | |
1063 | */ | |
ee031c31 | 1064 | bitmap_fill(all_banks, MAX_NR_BANKS); |
5679af4c | 1065 | machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks); |
1da177e4 LT |
1066 | |
1067 | set_in_cr4(X86_CR4_MCE); | |
1068 | ||
0d7482e3 | 1069 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
1070 | if (cap & MCG_CTL_P) |
1071 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
1072 | ||
1073 | for (i = 0; i < banks; i++) { | |
06b7a7a5 AK |
1074 | if (skip_bank_init(i)) |
1075 | continue; | |
0d7482e3 | 1076 | wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]); |
1da177e4 | 1077 | wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); |
d88203d1 | 1078 | } |
1da177e4 LT |
1079 | } |
1080 | ||
1081 | /* Add per CPU specific workarounds here */ | |
ec5b3d32 | 1082 | static void mce_cpu_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 1083 | { |
1da177e4 | 1084 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 1085 | if (c->x86_vendor == X86_VENDOR_AMD) { |
e9eee03e IM |
1086 | if (c->x86 == 15 && banks > 4) { |
1087 | /* | |
1088 | * disable GART TBL walk error reporting, which | |
1089 | * trips off incorrectly with the IOMMU & 3ware | |
1090 | * & Cerberus: | |
1091 | */ | |
0d7482e3 | 1092 | clear_bit(10, (unsigned long *)&bank[4]); |
e9eee03e IM |
1093 | } |
1094 | if (c->x86 <= 17 && mce_bootlog < 0) { | |
1095 | /* | |
1096 | * Lots of broken BIOS around that don't clear them | |
1097 | * by default and leave crap in there. Don't log: | |
1098 | */ | |
911f6a7b | 1099 | mce_bootlog = 0; |
e9eee03e | 1100 | } |
2e6f694f AK |
1101 | /* |
1102 | * Various K7s with broken bank 0 around. Always disable | |
1103 | * by default. | |
1104 | */ | |
1105 | if (c->x86 == 6) | |
1106 | bank[0] = 0; | |
1da177e4 | 1107 | } |
e583538f | 1108 | |
06b7a7a5 AK |
1109 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
1110 | /* | |
1111 | * SDM documents that on family 6 bank 0 should not be written | |
1112 | * because it aliases to another special BIOS controlled | |
1113 | * register. | |
1114 | * But it's not aliased anymore on model 0x1a+ | |
1115 | * Don't ignore bank 0 completely because there could be a | |
1116 | * valid event later, merely don't write CTL0. | |
1117 | */ | |
1118 | ||
1119 | if (c->x86 == 6 && c->x86_model < 0x1A) | |
1120 | __set_bit(0, &dont_init_banks); | |
3c079792 AK |
1121 | |
1122 | /* | |
1123 | * All newer Intel systems support MCE broadcasting. Enable | |
1124 | * synchronization with a one second timeout. | |
1125 | */ | |
1126 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && | |
1127 | monarch_timeout < 0) | |
1128 | monarch_timeout = USEC_PER_SEC; | |
06b7a7a5 | 1129 | } |
3c079792 AK |
1130 | if (monarch_timeout < 0) |
1131 | monarch_timeout = 0; | |
29b0f591 AK |
1132 | if (mce_bootlog != 0) |
1133 | mce_panic_timeout = 30; | |
d88203d1 | 1134 | } |
1da177e4 | 1135 | |
4efc0670 AK |
1136 | static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c) |
1137 | { | |
1138 | if (c->x86 != 5) | |
1139 | return; | |
1140 | switch (c->x86_vendor) { | |
1141 | case X86_VENDOR_INTEL: | |
1142 | if (mce_p5_enabled()) | |
1143 | intel_p5_mcheck_init(c); | |
1144 | break; | |
1145 | case X86_VENDOR_CENTAUR: | |
1146 | winchip_mcheck_init(c); | |
1147 | break; | |
1148 | } | |
1149 | } | |
1150 | ||
cc3ca220 | 1151 | static void mce_cpu_features(struct cpuinfo_x86 *c) |
1da177e4 LT |
1152 | { |
1153 | switch (c->x86_vendor) { | |
1154 | case X86_VENDOR_INTEL: | |
1155 | mce_intel_feature_init(c); | |
1156 | break; | |
89b831ef JS |
1157 | case X86_VENDOR_AMD: |
1158 | mce_amd_feature_init(c); | |
1159 | break; | |
1da177e4 LT |
1160 | default: |
1161 | break; | |
1162 | } | |
1163 | } | |
1164 | ||
52d168e2 AK |
1165 | static void mce_init_timer(void) |
1166 | { | |
1167 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
6298c512 | 1168 | int *n = &__get_cpu_var(next_interval); |
52d168e2 | 1169 | |
6298c512 AK |
1170 | *n = check_interval * HZ; |
1171 | if (!*n) | |
52d168e2 AK |
1172 | return; |
1173 | setup_timer(t, mcheck_timer, smp_processor_id()); | |
6298c512 | 1174 | t->expires = round_jiffies(jiffies + *n); |
52d168e2 AK |
1175 | add_timer(t); |
1176 | } | |
1177 | ||
d88203d1 | 1178 | /* |
1da177e4 | 1179 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 1180 | * Must be called with preempt off: |
1da177e4 | 1181 | */ |
e6982c67 | 1182 | void __cpuinit mcheck_init(struct cpuinfo_x86 *c) |
1da177e4 | 1183 | { |
4efc0670 AK |
1184 | if (mce_disabled) |
1185 | return; | |
1186 | ||
1187 | mce_ancient_init(c); | |
1188 | ||
5b4408fd | 1189 | if (!mce_available(c)) |
1da177e4 LT |
1190 | return; |
1191 | ||
0d7482e3 | 1192 | if (mce_cap_init() < 0) { |
04b2b1a4 | 1193 | mce_disabled = 1; |
0d7482e3 AK |
1194 | return; |
1195 | } | |
1196 | mce_cpu_quirks(c); | |
1197 | ||
5d727926 AK |
1198 | machine_check_vector = do_machine_check; |
1199 | ||
8be91105 | 1200 | mce_init(); |
1da177e4 | 1201 | mce_cpu_features(c); |
52d168e2 | 1202 | mce_init_timer(); |
1da177e4 LT |
1203 | } |
1204 | ||
1205 | /* | |
1206 | * Character device to read and clear the MCE log. | |
1207 | */ | |
1208 | ||
f528e7ba | 1209 | static DEFINE_SPINLOCK(mce_state_lock); |
e9eee03e IM |
1210 | static int open_count; /* #times opened */ |
1211 | static int open_exclu; /* already open exclusive? */ | |
f528e7ba TH |
1212 | |
1213 | static int mce_open(struct inode *inode, struct file *file) | |
1214 | { | |
1215 | spin_lock(&mce_state_lock); | |
1216 | ||
1217 | if (open_exclu || (open_count && (file->f_flags & O_EXCL))) { | |
1218 | spin_unlock(&mce_state_lock); | |
e9eee03e | 1219 | |
f528e7ba TH |
1220 | return -EBUSY; |
1221 | } | |
1222 | ||
1223 | if (file->f_flags & O_EXCL) | |
1224 | open_exclu = 1; | |
1225 | open_count++; | |
1226 | ||
1227 | spin_unlock(&mce_state_lock); | |
1228 | ||
bd78432c | 1229 | return nonseekable_open(inode, file); |
f528e7ba TH |
1230 | } |
1231 | ||
1232 | static int mce_release(struct inode *inode, struct file *file) | |
1233 | { | |
1234 | spin_lock(&mce_state_lock); | |
1235 | ||
1236 | open_count--; | |
1237 | open_exclu = 0; | |
1238 | ||
1239 | spin_unlock(&mce_state_lock); | |
1240 | ||
1241 | return 0; | |
1242 | } | |
1243 | ||
d88203d1 TG |
1244 | static void collect_tscs(void *data) |
1245 | { | |
1da177e4 | 1246 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 1247 | |
1da177e4 | 1248 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 1249 | } |
1da177e4 | 1250 | |
e9eee03e IM |
1251 | static DEFINE_MUTEX(mce_read_mutex); |
1252 | ||
d88203d1 TG |
1253 | static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize, |
1254 | loff_t *off) | |
1da177e4 | 1255 | { |
e9eee03e | 1256 | char __user *buf = ubuf; |
f0de53bb | 1257 | unsigned long *cpu_tsc; |
ef41df43 | 1258 | unsigned prev, next; |
1da177e4 LT |
1259 | int i, err; |
1260 | ||
6bca67f9 | 1261 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
1262 | if (!cpu_tsc) |
1263 | return -ENOMEM; | |
1264 | ||
8c8b8859 | 1265 | mutex_lock(&mce_read_mutex); |
1da177e4 LT |
1266 | next = rcu_dereference(mcelog.next); |
1267 | ||
1268 | /* Only supports full reads right now */ | |
d88203d1 | 1269 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) { |
8c8b8859 | 1270 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 1271 | kfree(cpu_tsc); |
e9eee03e | 1272 | |
1da177e4 LT |
1273 | return -EINVAL; |
1274 | } | |
1275 | ||
1276 | err = 0; | |
ef41df43 HY |
1277 | prev = 0; |
1278 | do { | |
1279 | for (i = prev; i < next; i++) { | |
1280 | unsigned long start = jiffies; | |
1281 | ||
1282 | while (!mcelog.entry[i].finished) { | |
1283 | if (time_after_eq(jiffies, start + 2)) { | |
1284 | memset(mcelog.entry + i, 0, | |
1285 | sizeof(struct mce)); | |
1286 | goto timeout; | |
1287 | } | |
1288 | cpu_relax(); | |
673242c1 | 1289 | } |
ef41df43 HY |
1290 | smp_rmb(); |
1291 | err |= copy_to_user(buf, mcelog.entry + i, | |
1292 | sizeof(struct mce)); | |
1293 | buf += sizeof(struct mce); | |
1294 | timeout: | |
1295 | ; | |
673242c1 | 1296 | } |
1da177e4 | 1297 | |
ef41df43 HY |
1298 | memset(mcelog.entry + prev, 0, |
1299 | (next - prev) * sizeof(struct mce)); | |
1300 | prev = next; | |
1301 | next = cmpxchg(&mcelog.next, prev, 0); | |
1302 | } while (next != prev); | |
1da177e4 | 1303 | |
b2b18660 | 1304 | synchronize_sched(); |
1da177e4 | 1305 | |
d88203d1 TG |
1306 | /* |
1307 | * Collect entries that were still getting written before the | |
1308 | * synchronize. | |
1309 | */ | |
15c8b6c1 | 1310 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 1311 | |
d88203d1 TG |
1312 | for (i = next; i < MCE_LOG_LEN; i++) { |
1313 | if (mcelog.entry[i].finished && | |
1314 | mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) { | |
1315 | err |= copy_to_user(buf, mcelog.entry+i, | |
1316 | sizeof(struct mce)); | |
1da177e4 LT |
1317 | smp_rmb(); |
1318 | buf += sizeof(struct mce); | |
1319 | memset(&mcelog.entry[i], 0, sizeof(struct mce)); | |
1320 | } | |
d88203d1 | 1321 | } |
8c8b8859 | 1322 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 1323 | kfree(cpu_tsc); |
e9eee03e | 1324 | |
d88203d1 | 1325 | return err ? -EFAULT : buf - ubuf; |
1da177e4 LT |
1326 | } |
1327 | ||
e02e68d3 TH |
1328 | static unsigned int mce_poll(struct file *file, poll_table *wait) |
1329 | { | |
1330 | poll_wait(file, &mce_wait, wait); | |
1331 | if (rcu_dereference(mcelog.next)) | |
1332 | return POLLIN | POLLRDNORM; | |
1333 | return 0; | |
1334 | } | |
1335 | ||
c68461b6 | 1336 | static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg) |
1da177e4 LT |
1337 | { |
1338 | int __user *p = (int __user *)arg; | |
d88203d1 | 1339 | |
1da177e4 | 1340 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 1341 | return -EPERM; |
e9eee03e | 1342 | |
1da177e4 | 1343 | switch (cmd) { |
d88203d1 | 1344 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
1345 | return put_user(sizeof(struct mce), p); |
1346 | case MCE_GET_LOG_LEN: | |
d88203d1 | 1347 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
1348 | case MCE_GETCLEAR_FLAGS: { |
1349 | unsigned flags; | |
d88203d1 TG |
1350 | |
1351 | do { | |
1da177e4 | 1352 | flags = mcelog.flags; |
d88203d1 | 1353 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 1354 | |
d88203d1 | 1355 | return put_user(flags, p); |
1da177e4 LT |
1356 | } |
1357 | default: | |
d88203d1 TG |
1358 | return -ENOTTY; |
1359 | } | |
1da177e4 LT |
1360 | } |
1361 | ||
a1ff41bf | 1362 | /* Modified in mce-inject.c, so not static or const */ |
ea149b36 | 1363 | struct file_operations mce_chrdev_ops = { |
e9eee03e IM |
1364 | .open = mce_open, |
1365 | .release = mce_release, | |
1366 | .read = mce_read, | |
1367 | .poll = mce_poll, | |
1368 | .unlocked_ioctl = mce_ioctl, | |
1da177e4 | 1369 | }; |
ea149b36 | 1370 | EXPORT_SYMBOL_GPL(mce_chrdev_ops); |
1da177e4 LT |
1371 | |
1372 | static struct miscdevice mce_log_device = { | |
1373 | MISC_MCELOG_MINOR, | |
1374 | "mcelog", | |
1375 | &mce_chrdev_ops, | |
1376 | }; | |
1377 | ||
13503fa9 HS |
1378 | /* |
1379 | * mce=off disables machine check | |
3c079792 AK |
1380 | * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) |
1381 | * monarchtimeout is how long to wait for other CPUs on machine | |
1382 | * check, or 0 to not wait | |
13503fa9 HS |
1383 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. |
1384 | * mce=nobootlog Don't log MCEs from before booting. | |
1385 | */ | |
1da177e4 LT |
1386 | static int __init mcheck_enable(char *str) |
1387 | { | |
4efc0670 AK |
1388 | if (*str == 0) |
1389 | enable_p5_mce(); | |
1390 | if (*str == '=') | |
1391 | str++; | |
1da177e4 | 1392 | if (!strcmp(str, "off")) |
04b2b1a4 | 1393 | mce_disabled = 1; |
13503fa9 HS |
1394 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
1395 | mce_bootlog = (str[0] == 'b'); | |
3c079792 | 1396 | else if (isdigit(str[0])) { |
8c566ef5 | 1397 | get_option(&str, &tolerant); |
3c079792 AK |
1398 | if (*str == ',') { |
1399 | ++str; | |
1400 | get_option(&str, &monarch_timeout); | |
1401 | } | |
1402 | } else { | |
4efc0670 | 1403 | printk(KERN_INFO "mce argument %s ignored. Please use /sys\n", |
13503fa9 HS |
1404 | str); |
1405 | return 0; | |
1406 | } | |
9b41046c | 1407 | return 1; |
1da177e4 | 1408 | } |
4efc0670 | 1409 | __setup("mce", mcheck_enable); |
1da177e4 | 1410 | |
d88203d1 | 1411 | /* |
1da177e4 | 1412 | * Sysfs support |
d88203d1 | 1413 | */ |
1da177e4 | 1414 | |
973a2dd1 AK |
1415 | /* |
1416 | * Disable machine checks on suspend and shutdown. We can't really handle | |
1417 | * them later. | |
1418 | */ | |
1419 | static int mce_disable(void) | |
1420 | { | |
1421 | int i; | |
1422 | ||
06b7a7a5 AK |
1423 | for (i = 0; i < banks; i++) { |
1424 | if (!skip_bank_init(i)) | |
1425 | wrmsrl(MSR_IA32_MC0_CTL + i*4, 0); | |
1426 | } | |
973a2dd1 AK |
1427 | return 0; |
1428 | } | |
1429 | ||
1430 | static int mce_suspend(struct sys_device *dev, pm_message_t state) | |
1431 | { | |
1432 | return mce_disable(); | |
1433 | } | |
1434 | ||
1435 | static int mce_shutdown(struct sys_device *dev) | |
1436 | { | |
1437 | return mce_disable(); | |
1438 | } | |
1439 | ||
e9eee03e IM |
1440 | /* |
1441 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
1442 | * Only one CPU is active at this time, the others get re-added later using | |
1443 | * CPU hotplug: | |
1444 | */ | |
1da177e4 LT |
1445 | static int mce_resume(struct sys_device *dev) |
1446 | { | |
8be91105 | 1447 | mce_init(); |
6ec68bff | 1448 | mce_cpu_features(¤t_cpu_data); |
e9eee03e | 1449 | |
1da177e4 LT |
1450 | return 0; |
1451 | } | |
1452 | ||
52d168e2 AK |
1453 | static void mce_cpu_restart(void *data) |
1454 | { | |
1455 | del_timer_sync(&__get_cpu_var(mce_timer)); | |
1456 | if (mce_available(¤t_cpu_data)) | |
8be91105 | 1457 | mce_init(); |
52d168e2 AK |
1458 | mce_init_timer(); |
1459 | } | |
1460 | ||
1da177e4 | 1461 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
1462 | static void mce_restart(void) |
1463 | { | |
52d168e2 | 1464 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
1465 | } |
1466 | ||
1467 | static struct sysdev_class mce_sysclass = { | |
e9eee03e IM |
1468 | .suspend = mce_suspend, |
1469 | .shutdown = mce_shutdown, | |
1470 | .resume = mce_resume, | |
1471 | .name = "machinecheck", | |
1da177e4 LT |
1472 | }; |
1473 | ||
cb491fca | 1474 | DEFINE_PER_CPU(struct sys_device, mce_dev); |
e9eee03e IM |
1475 | |
1476 | __cpuinitdata | |
1477 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); | |
1da177e4 | 1478 | |
0d7482e3 AK |
1479 | static struct sysdev_attribute *bank_attrs; |
1480 | ||
1481 | static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
1482 | char *buf) | |
1483 | { | |
1484 | u64 b = bank[attr - bank_attrs]; | |
e9eee03e | 1485 | |
f6d1826d | 1486 | return sprintf(buf, "%llx\n", b); |
0d7482e3 AK |
1487 | } |
1488 | ||
1489 | static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
9319cec8 | 1490 | const char *buf, size_t size) |
0d7482e3 | 1491 | { |
9319cec8 | 1492 | u64 new; |
e9eee03e | 1493 | |
9319cec8 | 1494 | if (strict_strtoull(buf, 0, &new) < 0) |
0d7482e3 | 1495 | return -EINVAL; |
e9eee03e | 1496 | |
0d7482e3 AK |
1497 | bank[attr - bank_attrs] = new; |
1498 | mce_restart(); | |
e9eee03e | 1499 | |
9319cec8 | 1500 | return size; |
0d7482e3 | 1501 | } |
a98f0dd3 | 1502 | |
e9eee03e IM |
1503 | static ssize_t |
1504 | show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf) | |
a98f0dd3 AK |
1505 | { |
1506 | strcpy(buf, trigger); | |
1507 | strcat(buf, "\n"); | |
1508 | return strlen(trigger) + 1; | |
1509 | } | |
1510 | ||
4a0b2b4d | 1511 | static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr, |
e9eee03e | 1512 | const char *buf, size_t siz) |
a98f0dd3 AK |
1513 | { |
1514 | char *p; | |
1515 | int len; | |
e9eee03e | 1516 | |
a98f0dd3 AK |
1517 | strncpy(trigger, buf, sizeof(trigger)); |
1518 | trigger[sizeof(trigger)-1] = 0; | |
1519 | len = strlen(trigger); | |
1520 | p = strchr(trigger, '\n'); | |
e9eee03e IM |
1521 | |
1522 | if (*p) | |
1523 | *p = 0; | |
1524 | ||
a98f0dd3 AK |
1525 | return len; |
1526 | } | |
1527 | ||
b56f642d AK |
1528 | static ssize_t store_int_with_restart(struct sys_device *s, |
1529 | struct sysdev_attribute *attr, | |
1530 | const char *buf, size_t size) | |
1531 | { | |
1532 | ssize_t ret = sysdev_store_int(s, attr, buf, size); | |
1533 | mce_restart(); | |
1534 | return ret; | |
1535 | } | |
1536 | ||
a98f0dd3 | 1537 | static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger); |
d95d62c0 | 1538 | static SYSDEV_INT_ATTR(tolerant, 0644, tolerant); |
3c079792 | 1539 | static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout); |
e9eee03e | 1540 | |
b56f642d AK |
1541 | static struct sysdev_ext_attribute attr_check_interval = { |
1542 | _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int, | |
1543 | store_int_with_restart), | |
1544 | &check_interval | |
1545 | }; | |
e9eee03e | 1546 | |
cb491fca | 1547 | static struct sysdev_attribute *mce_attrs[] = { |
b56f642d | 1548 | &attr_tolerant.attr, &attr_check_interval.attr, &attr_trigger, |
3c079792 | 1549 | &attr_monarch_timeout.attr, |
a98f0dd3 AK |
1550 | NULL |
1551 | }; | |
1da177e4 | 1552 | |
cb491fca | 1553 | static cpumask_var_t mce_dev_initialized; |
bae19fe0 | 1554 | |
e9eee03e | 1555 | /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */ |
91c6d400 | 1556 | static __cpuinit int mce_create_device(unsigned int cpu) |
1da177e4 LT |
1557 | { |
1558 | int err; | |
73ca5358 | 1559 | int i; |
92cb7612 | 1560 | |
90367556 | 1561 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
1562 | return -EIO; |
1563 | ||
cb491fca IM |
1564 | memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject)); |
1565 | per_cpu(mce_dev, cpu).id = cpu; | |
1566 | per_cpu(mce_dev, cpu).cls = &mce_sysclass; | |
91c6d400 | 1567 | |
cb491fca | 1568 | err = sysdev_register(&per_cpu(mce_dev, cpu)); |
d435d862 AM |
1569 | if (err) |
1570 | return err; | |
1571 | ||
cb491fca IM |
1572 | for (i = 0; mce_attrs[i]; i++) { |
1573 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
d435d862 AM |
1574 | if (err) |
1575 | goto error; | |
1576 | } | |
0d7482e3 | 1577 | for (i = 0; i < banks; i++) { |
cb491fca | 1578 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), |
0d7482e3 AK |
1579 | &bank_attrs[i]); |
1580 | if (err) | |
1581 | goto error2; | |
1582 | } | |
cb491fca | 1583 | cpumask_set_cpu(cpu, mce_dev_initialized); |
91c6d400 | 1584 | |
d435d862 | 1585 | return 0; |
0d7482e3 | 1586 | error2: |
cb491fca IM |
1587 | while (--i >= 0) |
1588 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]); | |
d435d862 | 1589 | error: |
cb491fca IM |
1590 | while (--i >= 0) |
1591 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
1592 | ||
1593 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
d435d862 | 1594 | |
91c6d400 AK |
1595 | return err; |
1596 | } | |
1597 | ||
2d9cd6c2 | 1598 | static __cpuinit void mce_remove_device(unsigned int cpu) |
91c6d400 | 1599 | { |
73ca5358 SL |
1600 | int i; |
1601 | ||
cb491fca | 1602 | if (!cpumask_test_cpu(cpu, mce_dev_initialized)) |
bae19fe0 AH |
1603 | return; |
1604 | ||
cb491fca IM |
1605 | for (i = 0; mce_attrs[i]; i++) |
1606 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
1607 | ||
0d7482e3 | 1608 | for (i = 0; i < banks; i++) |
cb491fca IM |
1609 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]); |
1610 | ||
1611 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
1612 | cpumask_clear_cpu(cpu, mce_dev_initialized); | |
91c6d400 | 1613 | } |
91c6d400 | 1614 | |
d6b75584 | 1615 | /* Make sure there are no machine checks on offlined CPUs. */ |
ec5b3d32 | 1616 | static void mce_disable_cpu(void *h) |
d6b75584 | 1617 | { |
88ccbedd | 1618 | unsigned long action = *(unsigned long *)h; |
cb491fca | 1619 | int i; |
d6b75584 AK |
1620 | |
1621 | if (!mce_available(¤t_cpu_data)) | |
1622 | return; | |
88ccbedd AK |
1623 | if (!(action & CPU_TASKS_FROZEN)) |
1624 | cmci_clear(); | |
06b7a7a5 AK |
1625 | for (i = 0; i < banks; i++) { |
1626 | if (!skip_bank_init(i)) | |
1627 | wrmsrl(MSR_IA32_MC0_CTL + i*4, 0); | |
1628 | } | |
d6b75584 AK |
1629 | } |
1630 | ||
ec5b3d32 | 1631 | static void mce_reenable_cpu(void *h) |
d6b75584 | 1632 | { |
88ccbedd | 1633 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 1634 | int i; |
d6b75584 AK |
1635 | |
1636 | if (!mce_available(¤t_cpu_data)) | |
1637 | return; | |
e9eee03e | 1638 | |
88ccbedd AK |
1639 | if (!(action & CPU_TASKS_FROZEN)) |
1640 | cmci_reenable(); | |
06b7a7a5 AK |
1641 | for (i = 0; i < banks; i++) { |
1642 | if (!skip_bank_init(i)) | |
1643 | wrmsrl(MSR_IA32_MC0_CTL + i*4, bank[i]); | |
1644 | } | |
d6b75584 AK |
1645 | } |
1646 | ||
91c6d400 | 1647 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
e9eee03e IM |
1648 | static int __cpuinit |
1649 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) | |
91c6d400 AK |
1650 | { |
1651 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 1652 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 AK |
1653 | |
1654 | switch (action) { | |
bae19fe0 AH |
1655 | case CPU_ONLINE: |
1656 | case CPU_ONLINE_FROZEN: | |
1657 | mce_create_device(cpu); | |
8735728e RW |
1658 | if (threshold_cpu_callback) |
1659 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 1660 | break; |
91c6d400 | 1661 | case CPU_DEAD: |
8bb78442 | 1662 | case CPU_DEAD_FROZEN: |
8735728e RW |
1663 | if (threshold_cpu_callback) |
1664 | threshold_cpu_callback(action, cpu); | |
91c6d400 AK |
1665 | mce_remove_device(cpu); |
1666 | break; | |
52d168e2 AK |
1667 | case CPU_DOWN_PREPARE: |
1668 | case CPU_DOWN_PREPARE_FROZEN: | |
1669 | del_timer_sync(t); | |
88ccbedd | 1670 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
52d168e2 AK |
1671 | break; |
1672 | case CPU_DOWN_FAILED: | |
1673 | case CPU_DOWN_FAILED_FROZEN: | |
6298c512 AK |
1674 | t->expires = round_jiffies(jiffies + |
1675 | __get_cpu_var(next_interval)); | |
52d168e2 | 1676 | add_timer_on(t, cpu); |
88ccbedd AK |
1677 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
1678 | break; | |
1679 | case CPU_POST_DEAD: | |
1680 | /* intentionally ignoring frozen here */ | |
1681 | cmci_rediscover(cpu); | |
52d168e2 | 1682 | break; |
91c6d400 | 1683 | } |
bae19fe0 | 1684 | return NOTIFY_OK; |
91c6d400 AK |
1685 | } |
1686 | ||
1e35669d | 1687 | static struct notifier_block mce_cpu_notifier __cpuinitdata = { |
91c6d400 AK |
1688 | .notifier_call = mce_cpu_callback, |
1689 | }; | |
1690 | ||
0d7482e3 AK |
1691 | static __init int mce_init_banks(void) |
1692 | { | |
1693 | int i; | |
1694 | ||
1695 | bank_attrs = kzalloc(sizeof(struct sysdev_attribute) * banks, | |
1696 | GFP_KERNEL); | |
1697 | if (!bank_attrs) | |
1698 | return -ENOMEM; | |
1699 | ||
1700 | for (i = 0; i < banks; i++) { | |
1701 | struct sysdev_attribute *a = &bank_attrs[i]; | |
e9eee03e IM |
1702 | |
1703 | a->attr.name = kasprintf(GFP_KERNEL, "bank%d", i); | |
0d7482e3 AK |
1704 | if (!a->attr.name) |
1705 | goto nomem; | |
e9eee03e IM |
1706 | |
1707 | a->attr.mode = 0644; | |
1708 | a->show = show_bank; | |
1709 | a->store = set_bank; | |
0d7482e3 AK |
1710 | } |
1711 | return 0; | |
1712 | ||
1713 | nomem: | |
1714 | while (--i >= 0) | |
1715 | kfree(bank_attrs[i].attr.name); | |
1716 | kfree(bank_attrs); | |
1717 | bank_attrs = NULL; | |
e9eee03e | 1718 | |
0d7482e3 AK |
1719 | return -ENOMEM; |
1720 | } | |
1721 | ||
91c6d400 AK |
1722 | static __init int mce_init_device(void) |
1723 | { | |
1724 | int err; | |
1725 | int i = 0; | |
1726 | ||
1da177e4 LT |
1727 | if (!mce_available(&boot_cpu_data)) |
1728 | return -EIO; | |
0d7482e3 | 1729 | |
cb491fca | 1730 | alloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL); |
996867d0 | 1731 | |
0d7482e3 AK |
1732 | err = mce_init_banks(); |
1733 | if (err) | |
1734 | return err; | |
1735 | ||
1da177e4 | 1736 | err = sysdev_class_register(&mce_sysclass); |
d435d862 AM |
1737 | if (err) |
1738 | return err; | |
91c6d400 AK |
1739 | |
1740 | for_each_online_cpu(i) { | |
d435d862 AM |
1741 | err = mce_create_device(i); |
1742 | if (err) | |
1743 | return err; | |
91c6d400 AK |
1744 | } |
1745 | ||
be6b5a35 | 1746 | register_hotcpu_notifier(&mce_cpu_notifier); |
1da177e4 | 1747 | misc_register(&mce_log_device); |
e9eee03e | 1748 | |
1da177e4 | 1749 | return err; |
1da177e4 | 1750 | } |
91c6d400 | 1751 | |
1da177e4 | 1752 | device_initcall(mce_init_device); |
a988d334 | 1753 | |
4efc0670 | 1754 | #else /* CONFIG_X86_OLD_MCE: */ |
a988d334 | 1755 | |
a988d334 IM |
1756 | int nr_mce_banks; |
1757 | EXPORT_SYMBOL_GPL(nr_mce_banks); /* non-fatal.o */ | |
1758 | ||
a988d334 IM |
1759 | /* This has to be run for each processor */ |
1760 | void mcheck_init(struct cpuinfo_x86 *c) | |
1761 | { | |
1762 | if (mce_disabled == 1) | |
1763 | return; | |
1764 | ||
1765 | switch (c->x86_vendor) { | |
1766 | case X86_VENDOR_AMD: | |
1767 | amd_mcheck_init(c); | |
1768 | break; | |
1769 | ||
1770 | case X86_VENDOR_INTEL: | |
1771 | if (c->x86 == 5) | |
1772 | intel_p5_mcheck_init(c); | |
1773 | if (c->x86 == 6) | |
1774 | intel_p6_mcheck_init(c); | |
1775 | if (c->x86 == 15) | |
1776 | intel_p4_mcheck_init(c); | |
1777 | break; | |
1778 | ||
1779 | case X86_VENDOR_CENTAUR: | |
1780 | if (c->x86 == 5) | |
1781 | winchip_mcheck_init(c); | |
1782 | break; | |
1783 | ||
1784 | default: | |
1785 | break; | |
1786 | } | |
b659294b | 1787 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", nr_mce_banks); |
a988d334 IM |
1788 | } |
1789 | ||
a988d334 IM |
1790 | static int __init mcheck_enable(char *str) |
1791 | { | |
1792 | mce_disabled = -1; | |
1793 | return 1; | |
1794 | } | |
1795 | ||
a988d334 IM |
1796 | __setup("mce", mcheck_enable); |
1797 | ||
d7c3c9a6 AK |
1798 | #endif /* CONFIG_X86_OLD_MCE */ |
1799 | ||
1800 | /* | |
1801 | * Old style boot options parsing. Only for compatibility. | |
1802 | */ | |
1803 | static int __init mcheck_disable(char *str) | |
1804 | { | |
1805 | mce_disabled = 1; | |
1806 | return 1; | |
1807 | } | |
1808 | __setup("nomce", mcheck_disable); |