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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
e9eee03e IM |
10 | #include <linux/thread_info.h> |
11 | #include <linux/capability.h> | |
12 | #include <linux/miscdevice.h> | |
13 | #include <linux/ratelimit.h> | |
14 | #include <linux/kallsyms.h> | |
15 | #include <linux/rcupdate.h> | |
38c4c97c | 16 | #include <linux/smp_lock.h> |
e9eee03e IM |
17 | #include <linux/kobject.h> |
18 | #include <linux/kdebug.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/percpu.h> | |
1da177e4 | 21 | #include <linux/string.h> |
1da177e4 | 22 | #include <linux/sysdev.h> |
8c566ef5 | 23 | #include <linux/ctype.h> |
e9eee03e | 24 | #include <linux/sched.h> |
0d7482e3 | 25 | #include <linux/sysfs.h> |
e9eee03e IM |
26 | #include <linux/types.h> |
27 | #include <linux/init.h> | |
28 | #include <linux/kmod.h> | |
29 | #include <linux/poll.h> | |
30 | #include <linux/cpu.h> | |
31 | #include <linux/fs.h> | |
32 | ||
d88203d1 | 33 | #include <asm/processor.h> |
1da177e4 | 34 | #include <asm/uaccess.h> |
e02e68d3 | 35 | #include <asm/idle.h> |
e9eee03e IM |
36 | #include <asm/mce.h> |
37 | #include <asm/msr.h> | |
38 | #include <asm/smp.h> | |
1da177e4 | 39 | |
711c2e48 IM |
40 | #include "mce.h" |
41 | ||
42 | #ifdef CONFIG_X86_64 | |
43 | ||
e9eee03e | 44 | #define MISC_MCELOG_MINOR 227 |
0d7482e3 | 45 | |
553f265f AK |
46 | atomic_t mce_entry; |
47 | ||
e9eee03e | 48 | static int mce_dont_init; |
1da177e4 | 49 | |
bd78432c TH |
50 | /* |
51 | * Tolerant levels: | |
52 | * 0: always panic on uncorrected errors, log corrected errors | |
53 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
54 | * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors | |
55 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
56 | */ | |
e9eee03e IM |
57 | static int tolerant = 1; |
58 | static int banks; | |
59 | static u64 *bank; | |
60 | static unsigned long notify_user; | |
61 | static int rip_msr; | |
62 | static int mce_bootlog = -1; | |
63 | static atomic_t mce_events; | |
a98f0dd3 | 64 | |
e9eee03e IM |
65 | static char trigger[128]; |
66 | static char *trigger_argv[2] = { trigger, NULL }; | |
1da177e4 | 67 | |
e02e68d3 TH |
68 | static DECLARE_WAIT_QUEUE_HEAD(mce_wait); |
69 | ||
ee031c31 AK |
70 | /* MCA banks polled by the period polling timer for corrected events */ |
71 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { | |
72 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
73 | }; | |
74 | ||
b5f2fa4e AK |
75 | /* Do initial initialization of a struct mce */ |
76 | void mce_setup(struct mce *m) | |
77 | { | |
78 | memset(m, 0, sizeof(struct mce)); | |
79 | m->cpu = smp_processor_id(); | |
80 | rdtscll(m->tsc); | |
81 | } | |
82 | ||
1da177e4 LT |
83 | /* |
84 | * Lockless MCE logging infrastructure. | |
85 | * This avoids deadlocks on printk locks without having to break locks. Also | |
86 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
87 | */ | |
88 | ||
231fd906 | 89 | static struct mce_log mcelog = { |
1da177e4 LT |
90 | MCE_LOG_SIGNATURE, |
91 | MCE_LOG_LEN, | |
d88203d1 | 92 | }; |
1da177e4 LT |
93 | |
94 | void mce_log(struct mce *mce) | |
95 | { | |
96 | unsigned next, entry; | |
e9eee03e | 97 | |
a98f0dd3 | 98 | atomic_inc(&mce_events); |
1da177e4 | 99 | mce->finished = 0; |
7644143c | 100 | wmb(); |
1da177e4 LT |
101 | for (;;) { |
102 | entry = rcu_dereference(mcelog.next); | |
673242c1 | 103 | for (;;) { |
e9eee03e IM |
104 | /* |
105 | * When the buffer fills up discard new entries. | |
106 | * Assume that the earlier errors are the more | |
107 | * interesting ones: | |
108 | */ | |
673242c1 | 109 | if (entry >= MCE_LOG_LEN) { |
53756d37 | 110 | set_bit(MCE_OVERFLOW, (unsigned long *)&mcelog.flags); |
673242c1 AK |
111 | return; |
112 | } | |
e9eee03e | 113 | /* Old left over entry. Skip: */ |
673242c1 AK |
114 | if (mcelog.entry[entry].finished) { |
115 | entry++; | |
116 | continue; | |
117 | } | |
7644143c | 118 | break; |
1da177e4 | 119 | } |
1da177e4 LT |
120 | smp_rmb(); |
121 | next = entry + 1; | |
122 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
123 | break; | |
124 | } | |
125 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 126 | wmb(); |
1da177e4 | 127 | mcelog.entry[entry].finished = 1; |
7644143c | 128 | wmb(); |
1da177e4 | 129 | |
e02e68d3 | 130 | set_bit(0, ¬ify_user); |
1da177e4 LT |
131 | } |
132 | ||
133 | static void print_mce(struct mce *m) | |
134 | { | |
135 | printk(KERN_EMERG "\n" | |
4855170f | 136 | KERN_EMERG "HARDWARE ERROR\n" |
1da177e4 LT |
137 | KERN_EMERG |
138 | "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n", | |
139 | m->cpu, m->mcgstatus, m->bank, m->status); | |
65ea5b03 | 140 | if (m->ip) { |
d88203d1 | 141 | printk(KERN_EMERG "RIP%s %02x:<%016Lx> ", |
1da177e4 | 142 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
65ea5b03 | 143 | m->cs, m->ip); |
1da177e4 | 144 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 145 | print_symbol("{%s}", m->ip); |
1da177e4 LT |
146 | printk("\n"); |
147 | } | |
f6d1826d | 148 | printk(KERN_EMERG "TSC %llx ", m->tsc); |
1da177e4 | 149 | if (m->addr) |
f6d1826d | 150 | printk("ADDR %llx ", m->addr); |
1da177e4 | 151 | if (m->misc) |
f6d1826d | 152 | printk("MISC %llx ", m->misc); |
1da177e4 | 153 | printk("\n"); |
4855170f | 154 | printk(KERN_EMERG "This is not a software problem!\n"); |
d88203d1 TG |
155 | printk(KERN_EMERG "Run through mcelog --ascii to decode " |
156 | "and contact your hardware vendor\n"); | |
1da177e4 LT |
157 | } |
158 | ||
159 | static void mce_panic(char *msg, struct mce *backup, unsigned long start) | |
d88203d1 | 160 | { |
1da177e4 | 161 | int i; |
e02e68d3 | 162 | |
1da177e4 LT |
163 | oops_begin(); |
164 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
165 | unsigned long tsc = mcelog.entry[i].tsc; | |
d88203d1 | 166 | |
1da177e4 LT |
167 | if (time_before(tsc, start)) |
168 | continue; | |
d88203d1 | 169 | print_mce(&mcelog.entry[i]); |
1da177e4 LT |
170 | if (backup && mcelog.entry[i].tsc == backup->tsc) |
171 | backup = NULL; | |
172 | } | |
173 | if (backup) | |
174 | print_mce(backup); | |
e02e68d3 | 175 | panic(msg); |
d88203d1 | 176 | } |
1da177e4 | 177 | |
88ccbedd | 178 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 179 | { |
5b4408fd AK |
180 | if (mce_dont_init) |
181 | return 0; | |
3d1712c9 | 182 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
183 | } |
184 | ||
94ad8474 AK |
185 | static inline void mce_get_rip(struct mce *m, struct pt_regs *regs) |
186 | { | |
187 | if (regs && (m->mcgstatus & MCG_STATUS_RIPV)) { | |
65ea5b03 | 188 | m->ip = regs->ip; |
94ad8474 AK |
189 | m->cs = regs->cs; |
190 | } else { | |
65ea5b03 | 191 | m->ip = 0; |
94ad8474 AK |
192 | m->cs = 0; |
193 | } | |
194 | if (rip_msr) { | |
195 | /* Assume the RIP in the MSR is exact. Is this true? */ | |
196 | m->mcgstatus |= MCG_STATUS_EIPV; | |
65ea5b03 | 197 | rdmsrl(rip_msr, m->ip); |
94ad8474 AK |
198 | m->cs = 0; |
199 | } | |
200 | } | |
201 | ||
d88203d1 | 202 | /* |
b79109c3 AK |
203 | * Poll for corrected events or events that happened before reset. |
204 | * Those are just logged through /dev/mcelog. | |
205 | * | |
206 | * This is executed in standard interrupt context. | |
207 | */ | |
ee031c31 | 208 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 AK |
209 | { |
210 | struct mce m; | |
211 | int i; | |
212 | ||
213 | mce_setup(&m); | |
214 | ||
215 | rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); | |
216 | for (i = 0; i < banks; i++) { | |
ee031c31 | 217 | if (!bank[i] || !test_bit(i, *b)) |
b79109c3 AK |
218 | continue; |
219 | ||
220 | m.misc = 0; | |
221 | m.addr = 0; | |
222 | m.bank = i; | |
223 | m.tsc = 0; | |
224 | ||
225 | barrier(); | |
226 | rdmsrl(MSR_IA32_MC0_STATUS + i*4, m.status); | |
227 | if (!(m.status & MCI_STATUS_VAL)) | |
228 | continue; | |
229 | ||
230 | /* | |
231 | * Uncorrected events are handled by the exception handler | |
232 | * when it is enabled. But when the exception is disabled log | |
233 | * everything. | |
234 | * | |
235 | * TBD do the same check for MCI_STATUS_EN here? | |
236 | */ | |
237 | if ((m.status & MCI_STATUS_UC) && !(flags & MCP_UC)) | |
238 | continue; | |
239 | ||
240 | if (m.status & MCI_STATUS_MISCV) | |
241 | rdmsrl(MSR_IA32_MC0_MISC + i*4, m.misc); | |
242 | if (m.status & MCI_STATUS_ADDRV) | |
243 | rdmsrl(MSR_IA32_MC0_ADDR + i*4, m.addr); | |
244 | ||
245 | if (!(flags & MCP_TIMESTAMP)) | |
246 | m.tsc = 0; | |
247 | /* | |
248 | * Don't get the IP here because it's unlikely to | |
249 | * have anything to do with the actual error location. | |
250 | */ | |
5679af4c AK |
251 | if (!(flags & MCP_DONTLOG)) { |
252 | mce_log(&m); | |
253 | add_taint(TAINT_MACHINE_CHECK); | |
254 | } | |
b79109c3 AK |
255 | |
256 | /* | |
257 | * Clear state for this bank. | |
258 | */ | |
259 | wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); | |
260 | } | |
261 | ||
262 | /* | |
263 | * Don't clear MCG_STATUS here because it's only defined for | |
264 | * exceptions. | |
265 | */ | |
266 | } | |
267 | ||
268 | /* | |
269 | * The actual machine check handler. This only handles real | |
270 | * exceptions when something got corrupted coming in through int 18. | |
271 | * | |
272 | * This is executed in NMI context not subject to normal locking rules. This | |
273 | * implies that most kernel services cannot be safely used. Don't even | |
274 | * think about putting a printk in there! | |
1da177e4 | 275 | */ |
e9eee03e | 276 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 LT |
277 | { |
278 | struct mce m, panicm; | |
e9eee03e | 279 | int panicm_found = 0; |
1da177e4 LT |
280 | u64 mcestart = 0; |
281 | int i; | |
bd78432c TH |
282 | /* |
283 | * If no_way_out gets set, there is no safe way to recover from this | |
284 | * MCE. If tolerant is cranked up, we'll try anyway. | |
285 | */ | |
286 | int no_way_out = 0; | |
287 | /* | |
288 | * If kill_it gets set, there might be a way to recover from this | |
289 | * error. | |
290 | */ | |
291 | int kill_it = 0; | |
b79109c3 | 292 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
1da177e4 | 293 | |
553f265f AK |
294 | atomic_inc(&mce_entry); |
295 | ||
b79109c3 | 296 | if (notify_die(DIE_NMI, "machine check", regs, error_code, |
22f5991c | 297 | 18, SIGKILL) == NOTIFY_STOP) |
b79109c3 AK |
298 | goto out2; |
299 | if (!banks) | |
553f265f | 300 | goto out2; |
1da177e4 | 301 | |
b5f2fa4e AK |
302 | mce_setup(&m); |
303 | ||
1da177e4 | 304 | rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); |
e9eee03e | 305 | |
bd78432c | 306 | /* if the restart IP is not valid, we're done for */ |
1da177e4 | 307 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) |
bd78432c | 308 | no_way_out = 1; |
d88203d1 | 309 | |
1da177e4 LT |
310 | rdtscll(mcestart); |
311 | barrier(); | |
312 | ||
313 | for (i = 0; i < banks; i++) { | |
b79109c3 | 314 | __clear_bit(i, toclear); |
0d7482e3 | 315 | if (!bank[i]) |
1da177e4 | 316 | continue; |
d88203d1 TG |
317 | |
318 | m.misc = 0; | |
1da177e4 LT |
319 | m.addr = 0; |
320 | m.bank = i; | |
1da177e4 LT |
321 | |
322 | rdmsrl(MSR_IA32_MC0_STATUS + i*4, m.status); | |
323 | if ((m.status & MCI_STATUS_VAL) == 0) | |
324 | continue; | |
325 | ||
b79109c3 AK |
326 | /* |
327 | * Non uncorrected errors are handled by machine_check_poll | |
328 | * Leave them alone. | |
329 | */ | |
330 | if ((m.status & MCI_STATUS_UC) == 0) | |
331 | continue; | |
332 | ||
333 | /* | |
334 | * Set taint even when machine check was not enabled. | |
335 | */ | |
336 | add_taint(TAINT_MACHINE_CHECK); | |
337 | ||
338 | __set_bit(i, toclear); | |
339 | ||
1da177e4 | 340 | if (m.status & MCI_STATUS_EN) { |
bd78432c TH |
341 | /* if PCC was set, there's no way out */ |
342 | no_way_out |= !!(m.status & MCI_STATUS_PCC); | |
343 | /* | |
344 | * If this error was uncorrectable and there was | |
345 | * an overflow, we're in trouble. If no overflow, | |
346 | * we might get away with just killing a task. | |
347 | */ | |
348 | if (m.status & MCI_STATUS_UC) { | |
349 | if (tolerant < 1 || m.status & MCI_STATUS_OVER) | |
350 | no_way_out = 1; | |
351 | kill_it = 1; | |
352 | } | |
b79109c3 AK |
353 | } else { |
354 | /* | |
355 | * Machine check event was not enabled. Clear, but | |
356 | * ignore. | |
357 | */ | |
358 | continue; | |
1da177e4 LT |
359 | } |
360 | ||
361 | if (m.status & MCI_STATUS_MISCV) | |
362 | rdmsrl(MSR_IA32_MC0_MISC + i*4, m.misc); | |
363 | if (m.status & MCI_STATUS_ADDRV) | |
364 | rdmsrl(MSR_IA32_MC0_ADDR + i*4, m.addr); | |
365 | ||
94ad8474 | 366 | mce_get_rip(&m, regs); |
b79109c3 | 367 | mce_log(&m); |
1da177e4 | 368 | |
e9eee03e IM |
369 | /* |
370 | * Did this bank cause the exception? | |
371 | * | |
372 | * Assume that the bank with uncorrectable errors did it, | |
373 | * and that there is only a single one: | |
374 | */ | |
375 | if ((m.status & MCI_STATUS_UC) && | |
376 | (m.status & MCI_STATUS_EN)) { | |
1da177e4 LT |
377 | panicm = m; |
378 | panicm_found = 1; | |
379 | } | |
1da177e4 LT |
380 | } |
381 | ||
e9eee03e IM |
382 | /* |
383 | * If we didn't find an uncorrectable error, pick | |
384 | * the last one (shouldn't happen, just being safe). | |
385 | */ | |
1da177e4 LT |
386 | if (!panicm_found) |
387 | panicm = m; | |
bd78432c TH |
388 | |
389 | /* | |
390 | * If we have decided that we just CAN'T continue, and the user | |
e9eee03e | 391 | * has not set tolerant to an insane level, give up and die. |
bd78432c TH |
392 | */ |
393 | if (no_way_out && tolerant < 3) | |
1da177e4 | 394 | mce_panic("Machine check", &panicm, mcestart); |
bd78432c TH |
395 | |
396 | /* | |
397 | * If the error seems to be unrecoverable, something should be | |
398 | * done. Try to kill as little as possible. If we can kill just | |
399 | * one task, do that. If the user has set the tolerance very | |
400 | * high, don't try to do anything at all. | |
401 | */ | |
402 | if (kill_it && tolerant < 3) { | |
1da177e4 LT |
403 | int user_space = 0; |
404 | ||
bd78432c TH |
405 | /* |
406 | * If the EIPV bit is set, it means the saved IP is the | |
407 | * instruction which caused the MCE. | |
408 | */ | |
409 | if (m.mcgstatus & MCG_STATUS_EIPV) | |
65ea5b03 | 410 | user_space = panicm.ip && (panicm.cs & 3); |
bd78432c TH |
411 | |
412 | /* | |
413 | * If we know that the error was in user space, send a | |
414 | * SIGBUS. Otherwise, panic if tolerance is low. | |
415 | * | |
380851bc | 416 | * force_sig() takes an awful lot of locks and has a slight |
bd78432c TH |
417 | * risk of deadlocking. |
418 | */ | |
419 | if (user_space) { | |
380851bc | 420 | force_sig(SIGBUS, current); |
bd78432c TH |
421 | } else if (panic_on_oops || tolerant < 2) { |
422 | mce_panic("Uncorrected machine check", | |
423 | &panicm, mcestart); | |
424 | } | |
1da177e4 LT |
425 | } |
426 | ||
e02e68d3 TH |
427 | /* notify userspace ASAP */ |
428 | set_thread_flag(TIF_MCE_NOTIFY); | |
429 | ||
bd78432c | 430 | /* the last thing we do is clear state */ |
b79109c3 AK |
431 | for (i = 0; i < banks; i++) { |
432 | if (test_bit(i, toclear)) | |
433 | wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); | |
434 | } | |
1da177e4 | 435 | wrmsrl(MSR_IA32_MCG_STATUS, 0); |
553f265f AK |
436 | out2: |
437 | atomic_dec(&mce_entry); | |
1da177e4 LT |
438 | } |
439 | ||
15d5f839 DZ |
440 | #ifdef CONFIG_X86_MCE_INTEL |
441 | /*** | |
442 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 443 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
444 | * @status: Event status information |
445 | * | |
446 | * This function should be called by the thermal interrupt after the | |
447 | * event has been processed and the decision was made to log the event | |
448 | * further. | |
449 | * | |
450 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
451 | * and historically has been the register value of the | |
452 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
453 | */ | |
b5f2fa4e | 454 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
455 | { |
456 | struct mce m; | |
457 | ||
b5f2fa4e | 458 | mce_setup(&m); |
15d5f839 DZ |
459 | m.bank = MCE_THERMAL_BANK; |
460 | m.status = status; | |
15d5f839 DZ |
461 | mce_log(&m); |
462 | } | |
463 | #endif /* CONFIG_X86_MCE_INTEL */ | |
464 | ||
1da177e4 | 465 | /* |
8a336b0a TH |
466 | * Periodic polling timer for "silent" machine check errors. If the |
467 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
468 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 469 | */ |
1da177e4 | 470 | static int check_interval = 5 * 60; /* 5 minutes */ |
e9eee03e | 471 | |
6298c512 | 472 | static DEFINE_PER_CPU(int, next_interval); /* in jiffies */ |
52d168e2 | 473 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 474 | |
52d168e2 | 475 | static void mcheck_timer(unsigned long data) |
1da177e4 | 476 | { |
52d168e2 | 477 | struct timer_list *t = &per_cpu(mce_timer, data); |
6298c512 | 478 | int *n; |
52d168e2 AK |
479 | |
480 | WARN_ON(smp_processor_id() != data); | |
481 | ||
e9eee03e | 482 | if (mce_available(¤t_cpu_data)) { |
ee031c31 AK |
483 | machine_check_poll(MCP_TIMESTAMP, |
484 | &__get_cpu_var(mce_poll_banks)); | |
e9eee03e | 485 | } |
1da177e4 LT |
486 | |
487 | /* | |
e02e68d3 TH |
488 | * Alert userspace if needed. If we logged an MCE, reduce the |
489 | * polling interval, otherwise increase the polling interval. | |
1da177e4 | 490 | */ |
6298c512 | 491 | n = &__get_cpu_var(next_interval); |
e02e68d3 | 492 | if (mce_notify_user()) { |
6298c512 | 493 | *n = max(*n/2, HZ/100); |
e02e68d3 | 494 | } else { |
6298c512 | 495 | *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ)); |
e02e68d3 TH |
496 | } |
497 | ||
6298c512 | 498 | t->expires = jiffies + *n; |
52d168e2 | 499 | add_timer(t); |
e02e68d3 TH |
500 | } |
501 | ||
9bd98405 AK |
502 | static void mce_do_trigger(struct work_struct *work) |
503 | { | |
504 | call_usermodehelper(trigger, trigger_argv, NULL, UMH_NO_WAIT); | |
505 | } | |
506 | ||
507 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
508 | ||
e02e68d3 | 509 | /* |
9bd98405 AK |
510 | * Notify the user(s) about new machine check events. |
511 | * Can be called from interrupt context, but not from machine check/NMI | |
512 | * context. | |
e02e68d3 TH |
513 | */ |
514 | int mce_notify_user(void) | |
515 | { | |
8457c84d AK |
516 | /* Not more than two messages every minute */ |
517 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
518 | ||
e02e68d3 | 519 | clear_thread_flag(TIF_MCE_NOTIFY); |
e9eee03e | 520 | |
e02e68d3 | 521 | if (test_and_clear_bit(0, ¬ify_user)) { |
e02e68d3 | 522 | wake_up_interruptible(&mce_wait); |
9bd98405 AK |
523 | |
524 | /* | |
525 | * There is no risk of missing notifications because | |
526 | * work_pending is always cleared before the function is | |
527 | * executed. | |
528 | */ | |
529 | if (trigger[0] && !work_pending(&mce_trigger_work)) | |
530 | schedule_work(&mce_trigger_work); | |
e02e68d3 | 531 | |
8457c84d | 532 | if (__ratelimit(&ratelimit)) |
8a336b0a | 533 | printk(KERN_INFO "Machine check events logged\n"); |
e02e68d3 TH |
534 | |
535 | return 1; | |
1da177e4 | 536 | } |
e02e68d3 TH |
537 | return 0; |
538 | } | |
8a336b0a | 539 | |
e9eee03e | 540 | /* see if the idle task needs to notify userspace: */ |
e02e68d3 | 541 | static int |
e9eee03e IM |
542 | mce_idle_callback(struct notifier_block *nfb, unsigned long action, |
543 | void *unused) | |
e02e68d3 TH |
544 | { |
545 | /* IDLE_END should be safe - interrupts are back on */ | |
546 | if (action == IDLE_END && test_thread_flag(TIF_MCE_NOTIFY)) | |
547 | mce_notify_user(); | |
548 | ||
549 | return NOTIFY_OK; | |
1da177e4 LT |
550 | } |
551 | ||
e02e68d3 | 552 | static struct notifier_block mce_idle_notifier = { |
e9eee03e | 553 | .notifier_call = mce_idle_callback, |
e02e68d3 | 554 | }; |
1da177e4 LT |
555 | |
556 | static __init int periodic_mcheck_init(void) | |
d88203d1 | 557 | { |
52d168e2 AK |
558 | idle_notifier_register(&mce_idle_notifier); |
559 | return 0; | |
d88203d1 | 560 | } |
1da177e4 LT |
561 | __initcall(periodic_mcheck_init); |
562 | ||
d88203d1 | 563 | /* |
1da177e4 LT |
564 | * Initialize Machine Checks for a CPU. |
565 | */ | |
0d7482e3 | 566 | static int mce_cap_init(void) |
1da177e4 | 567 | { |
0d7482e3 | 568 | unsigned b; |
e9eee03e | 569 | u64 cap; |
1da177e4 LT |
570 | |
571 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
0d7482e3 | 572 | b = cap & 0xff; |
b659294b IM |
573 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b); |
574 | ||
0d7482e3 AK |
575 | if (b > MAX_NR_BANKS) { |
576 | printk(KERN_WARNING | |
577 | "MCE: Using only %u machine check banks out of %u\n", | |
578 | MAX_NR_BANKS, b); | |
579 | b = MAX_NR_BANKS; | |
580 | } | |
581 | ||
582 | /* Don't support asymmetric configurations today */ | |
583 | WARN_ON(banks != 0 && b != banks); | |
584 | banks = b; | |
585 | if (!bank) { | |
586 | bank = kmalloc(banks * sizeof(u64), GFP_KERNEL); | |
587 | if (!bank) | |
588 | return -ENOMEM; | |
589 | memset(bank, 0xff, banks * sizeof(u64)); | |
1da177e4 | 590 | } |
0d7482e3 | 591 | |
94ad8474 AK |
592 | /* Use accurate RIP reporting if available. */ |
593 | if ((cap & (1<<9)) && ((cap >> 16) & 0xff) >= 9) | |
594 | rip_msr = MSR_IA32_MCG_EIP; | |
1da177e4 | 595 | |
0d7482e3 AK |
596 | return 0; |
597 | } | |
598 | ||
599 | static void mce_init(void *dummy) | |
600 | { | |
e9eee03e | 601 | mce_banks_t all_banks; |
0d7482e3 AK |
602 | u64 cap; |
603 | int i; | |
604 | ||
b79109c3 AK |
605 | /* |
606 | * Log the machine checks left over from the previous reset. | |
607 | */ | |
ee031c31 | 608 | bitmap_fill(all_banks, MAX_NR_BANKS); |
5679af4c | 609 | machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks); |
1da177e4 LT |
610 | |
611 | set_in_cr4(X86_CR4_MCE); | |
612 | ||
0d7482e3 | 613 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
614 | if (cap & MCG_CTL_P) |
615 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
616 | ||
617 | for (i = 0; i < banks; i++) { | |
0d7482e3 | 618 | wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]); |
1da177e4 | 619 | wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); |
d88203d1 | 620 | } |
1da177e4 LT |
621 | } |
622 | ||
623 | /* Add per CPU specific workarounds here */ | |
ec5b3d32 | 624 | static void mce_cpu_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 625 | { |
1da177e4 | 626 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 627 | if (c->x86_vendor == X86_VENDOR_AMD) { |
e9eee03e IM |
628 | if (c->x86 == 15 && banks > 4) { |
629 | /* | |
630 | * disable GART TBL walk error reporting, which | |
631 | * trips off incorrectly with the IOMMU & 3ware | |
632 | * & Cerberus: | |
633 | */ | |
0d7482e3 | 634 | clear_bit(10, (unsigned long *)&bank[4]); |
e9eee03e IM |
635 | } |
636 | if (c->x86 <= 17 && mce_bootlog < 0) { | |
637 | /* | |
638 | * Lots of broken BIOS around that don't clear them | |
639 | * by default and leave crap in there. Don't log: | |
640 | */ | |
911f6a7b | 641 | mce_bootlog = 0; |
e9eee03e | 642 | } |
1da177e4 | 643 | } |
e583538f | 644 | |
d88203d1 | 645 | } |
1da177e4 | 646 | |
cc3ca220 | 647 | static void mce_cpu_features(struct cpuinfo_x86 *c) |
1da177e4 LT |
648 | { |
649 | switch (c->x86_vendor) { | |
650 | case X86_VENDOR_INTEL: | |
651 | mce_intel_feature_init(c); | |
652 | break; | |
89b831ef JS |
653 | case X86_VENDOR_AMD: |
654 | mce_amd_feature_init(c); | |
655 | break; | |
1da177e4 LT |
656 | default: |
657 | break; | |
658 | } | |
659 | } | |
660 | ||
52d168e2 AK |
661 | static void mce_init_timer(void) |
662 | { | |
663 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
6298c512 | 664 | int *n = &__get_cpu_var(next_interval); |
52d168e2 | 665 | |
6298c512 AK |
666 | *n = check_interval * HZ; |
667 | if (!*n) | |
52d168e2 AK |
668 | return; |
669 | setup_timer(t, mcheck_timer, smp_processor_id()); | |
6298c512 | 670 | t->expires = round_jiffies(jiffies + *n); |
52d168e2 AK |
671 | add_timer(t); |
672 | } | |
673 | ||
d88203d1 | 674 | /* |
1da177e4 | 675 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 676 | * Must be called with preempt off: |
1da177e4 | 677 | */ |
e6982c67 | 678 | void __cpuinit mcheck_init(struct cpuinfo_x86 *c) |
1da177e4 | 679 | { |
5b4408fd | 680 | if (!mce_available(c)) |
1da177e4 LT |
681 | return; |
682 | ||
0d7482e3 AK |
683 | if (mce_cap_init() < 0) { |
684 | mce_dont_init = 1; | |
685 | return; | |
686 | } | |
687 | mce_cpu_quirks(c); | |
688 | ||
1da177e4 LT |
689 | mce_init(NULL); |
690 | mce_cpu_features(c); | |
52d168e2 | 691 | mce_init_timer(); |
1da177e4 LT |
692 | } |
693 | ||
694 | /* | |
695 | * Character device to read and clear the MCE log. | |
696 | */ | |
697 | ||
f528e7ba | 698 | static DEFINE_SPINLOCK(mce_state_lock); |
e9eee03e IM |
699 | static int open_count; /* #times opened */ |
700 | static int open_exclu; /* already open exclusive? */ | |
f528e7ba TH |
701 | |
702 | static int mce_open(struct inode *inode, struct file *file) | |
703 | { | |
38c4c97c | 704 | lock_kernel(); |
f528e7ba TH |
705 | spin_lock(&mce_state_lock); |
706 | ||
707 | if (open_exclu || (open_count && (file->f_flags & O_EXCL))) { | |
708 | spin_unlock(&mce_state_lock); | |
38c4c97c | 709 | unlock_kernel(); |
e9eee03e | 710 | |
f528e7ba TH |
711 | return -EBUSY; |
712 | } | |
713 | ||
714 | if (file->f_flags & O_EXCL) | |
715 | open_exclu = 1; | |
716 | open_count++; | |
717 | ||
718 | spin_unlock(&mce_state_lock); | |
38c4c97c | 719 | unlock_kernel(); |
f528e7ba | 720 | |
bd78432c | 721 | return nonseekable_open(inode, file); |
f528e7ba TH |
722 | } |
723 | ||
724 | static int mce_release(struct inode *inode, struct file *file) | |
725 | { | |
726 | spin_lock(&mce_state_lock); | |
727 | ||
728 | open_count--; | |
729 | open_exclu = 0; | |
730 | ||
731 | spin_unlock(&mce_state_lock); | |
732 | ||
733 | return 0; | |
734 | } | |
735 | ||
d88203d1 TG |
736 | static void collect_tscs(void *data) |
737 | { | |
1da177e4 | 738 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 739 | |
1da177e4 | 740 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 741 | } |
1da177e4 | 742 | |
e9eee03e IM |
743 | static DEFINE_MUTEX(mce_read_mutex); |
744 | ||
d88203d1 TG |
745 | static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize, |
746 | loff_t *off) | |
1da177e4 | 747 | { |
e9eee03e | 748 | char __user *buf = ubuf; |
f0de53bb | 749 | unsigned long *cpu_tsc; |
ef41df43 | 750 | unsigned prev, next; |
1da177e4 LT |
751 | int i, err; |
752 | ||
6bca67f9 | 753 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
754 | if (!cpu_tsc) |
755 | return -ENOMEM; | |
756 | ||
8c8b8859 | 757 | mutex_lock(&mce_read_mutex); |
1da177e4 LT |
758 | next = rcu_dereference(mcelog.next); |
759 | ||
760 | /* Only supports full reads right now */ | |
d88203d1 | 761 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) { |
8c8b8859 | 762 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 763 | kfree(cpu_tsc); |
e9eee03e | 764 | |
1da177e4 LT |
765 | return -EINVAL; |
766 | } | |
767 | ||
768 | err = 0; | |
ef41df43 HY |
769 | prev = 0; |
770 | do { | |
771 | for (i = prev; i < next; i++) { | |
772 | unsigned long start = jiffies; | |
773 | ||
774 | while (!mcelog.entry[i].finished) { | |
775 | if (time_after_eq(jiffies, start + 2)) { | |
776 | memset(mcelog.entry + i, 0, | |
777 | sizeof(struct mce)); | |
778 | goto timeout; | |
779 | } | |
780 | cpu_relax(); | |
673242c1 | 781 | } |
ef41df43 HY |
782 | smp_rmb(); |
783 | err |= copy_to_user(buf, mcelog.entry + i, | |
784 | sizeof(struct mce)); | |
785 | buf += sizeof(struct mce); | |
786 | timeout: | |
787 | ; | |
673242c1 | 788 | } |
1da177e4 | 789 | |
ef41df43 HY |
790 | memset(mcelog.entry + prev, 0, |
791 | (next - prev) * sizeof(struct mce)); | |
792 | prev = next; | |
793 | next = cmpxchg(&mcelog.next, prev, 0); | |
794 | } while (next != prev); | |
1da177e4 | 795 | |
b2b18660 | 796 | synchronize_sched(); |
1da177e4 | 797 | |
d88203d1 TG |
798 | /* |
799 | * Collect entries that were still getting written before the | |
800 | * synchronize. | |
801 | */ | |
15c8b6c1 | 802 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 803 | |
d88203d1 TG |
804 | for (i = next; i < MCE_LOG_LEN; i++) { |
805 | if (mcelog.entry[i].finished && | |
806 | mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) { | |
807 | err |= copy_to_user(buf, mcelog.entry+i, | |
808 | sizeof(struct mce)); | |
1da177e4 LT |
809 | smp_rmb(); |
810 | buf += sizeof(struct mce); | |
811 | memset(&mcelog.entry[i], 0, sizeof(struct mce)); | |
812 | } | |
d88203d1 | 813 | } |
8c8b8859 | 814 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 815 | kfree(cpu_tsc); |
e9eee03e | 816 | |
d88203d1 | 817 | return err ? -EFAULT : buf - ubuf; |
1da177e4 LT |
818 | } |
819 | ||
e02e68d3 TH |
820 | static unsigned int mce_poll(struct file *file, poll_table *wait) |
821 | { | |
822 | poll_wait(file, &mce_wait, wait); | |
823 | if (rcu_dereference(mcelog.next)) | |
824 | return POLLIN | POLLRDNORM; | |
825 | return 0; | |
826 | } | |
827 | ||
c68461b6 | 828 | static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg) |
1da177e4 LT |
829 | { |
830 | int __user *p = (int __user *)arg; | |
d88203d1 | 831 | |
1da177e4 | 832 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 833 | return -EPERM; |
e9eee03e | 834 | |
1da177e4 | 835 | switch (cmd) { |
d88203d1 | 836 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
837 | return put_user(sizeof(struct mce), p); |
838 | case MCE_GET_LOG_LEN: | |
d88203d1 | 839 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
840 | case MCE_GETCLEAR_FLAGS: { |
841 | unsigned flags; | |
d88203d1 TG |
842 | |
843 | do { | |
1da177e4 | 844 | flags = mcelog.flags; |
d88203d1 | 845 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 846 | |
d88203d1 | 847 | return put_user(flags, p); |
1da177e4 LT |
848 | } |
849 | default: | |
d88203d1 TG |
850 | return -ENOTTY; |
851 | } | |
1da177e4 LT |
852 | } |
853 | ||
5dfe4c96 | 854 | static const struct file_operations mce_chrdev_ops = { |
e9eee03e IM |
855 | .open = mce_open, |
856 | .release = mce_release, | |
857 | .read = mce_read, | |
858 | .poll = mce_poll, | |
859 | .unlocked_ioctl = mce_ioctl, | |
1da177e4 LT |
860 | }; |
861 | ||
862 | static struct miscdevice mce_log_device = { | |
863 | MISC_MCELOG_MINOR, | |
864 | "mcelog", | |
865 | &mce_chrdev_ops, | |
866 | }; | |
867 | ||
d88203d1 TG |
868 | /* |
869 | * Old style boot options parsing. Only for compatibility. | |
1da177e4 | 870 | */ |
1da177e4 LT |
871 | static int __init mcheck_disable(char *str) |
872 | { | |
873 | mce_dont_init = 1; | |
9b41046c | 874 | return 1; |
1da177e4 | 875 | } |
13503fa9 | 876 | __setup("nomce", mcheck_disable); |
1da177e4 | 877 | |
13503fa9 HS |
878 | /* |
879 | * mce=off disables machine check | |
880 | * mce=TOLERANCELEVEL (number, see above) | |
881 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. | |
882 | * mce=nobootlog Don't log MCEs from before booting. | |
883 | */ | |
1da177e4 LT |
884 | static int __init mcheck_enable(char *str) |
885 | { | |
886 | if (!strcmp(str, "off")) | |
887 | mce_dont_init = 1; | |
13503fa9 HS |
888 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
889 | mce_bootlog = (str[0] == 'b'); | |
8c566ef5 AK |
890 | else if (isdigit(str[0])) |
891 | get_option(&str, &tolerant); | |
13503fa9 HS |
892 | else { |
893 | printk(KERN_INFO "mce= argument %s ignored. Please use /sys\n", | |
894 | str); | |
895 | return 0; | |
896 | } | |
9b41046c | 897 | return 1; |
1da177e4 | 898 | } |
909dd324 | 899 | __setup("mce=", mcheck_enable); |
1da177e4 | 900 | |
d88203d1 | 901 | /* |
1da177e4 | 902 | * Sysfs support |
d88203d1 | 903 | */ |
1da177e4 | 904 | |
973a2dd1 AK |
905 | /* |
906 | * Disable machine checks on suspend and shutdown. We can't really handle | |
907 | * them later. | |
908 | */ | |
909 | static int mce_disable(void) | |
910 | { | |
911 | int i; | |
912 | ||
913 | for (i = 0; i < banks; i++) | |
914 | wrmsrl(MSR_IA32_MC0_CTL + i*4, 0); | |
915 | return 0; | |
916 | } | |
917 | ||
918 | static int mce_suspend(struct sys_device *dev, pm_message_t state) | |
919 | { | |
920 | return mce_disable(); | |
921 | } | |
922 | ||
923 | static int mce_shutdown(struct sys_device *dev) | |
924 | { | |
925 | return mce_disable(); | |
926 | } | |
927 | ||
e9eee03e IM |
928 | /* |
929 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
930 | * Only one CPU is active at this time, the others get re-added later using | |
931 | * CPU hotplug: | |
932 | */ | |
1da177e4 LT |
933 | static int mce_resume(struct sys_device *dev) |
934 | { | |
413588c7 | 935 | mce_init(NULL); |
6ec68bff | 936 | mce_cpu_features(¤t_cpu_data); |
e9eee03e | 937 | |
1da177e4 LT |
938 | return 0; |
939 | } | |
940 | ||
52d168e2 AK |
941 | static void mce_cpu_restart(void *data) |
942 | { | |
943 | del_timer_sync(&__get_cpu_var(mce_timer)); | |
944 | if (mce_available(¤t_cpu_data)) | |
945 | mce_init(NULL); | |
946 | mce_init_timer(); | |
947 | } | |
948 | ||
1da177e4 | 949 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
950 | static void mce_restart(void) |
951 | { | |
52d168e2 | 952 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
953 | } |
954 | ||
955 | static struct sysdev_class mce_sysclass = { | |
e9eee03e IM |
956 | .suspend = mce_suspend, |
957 | .shutdown = mce_shutdown, | |
958 | .resume = mce_resume, | |
959 | .name = "machinecheck", | |
1da177e4 LT |
960 | }; |
961 | ||
cb491fca | 962 | DEFINE_PER_CPU(struct sys_device, mce_dev); |
e9eee03e IM |
963 | |
964 | __cpuinitdata | |
965 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); | |
1da177e4 LT |
966 | |
967 | /* Why are there no generic functions for this? */ | |
968 | #define ACCESSOR(name, var, start) \ | |
4a0b2b4d AK |
969 | static ssize_t show_ ## name(struct sys_device *s, \ |
970 | struct sysdev_attribute *attr, \ | |
971 | char *buf) { \ | |
d88203d1 TG |
972 | return sprintf(buf, "%lx\n", (unsigned long)var); \ |
973 | } \ | |
4a0b2b4d AK |
974 | static ssize_t set_ ## name(struct sys_device *s, \ |
975 | struct sysdev_attribute *attr, \ | |
976 | const char *buf, size_t siz) { \ | |
d88203d1 TG |
977 | char *end; \ |
978 | unsigned long new = simple_strtoul(buf, &end, 0); \ | |
e9eee03e IM |
979 | \ |
980 | if (end == buf) \ | |
981 | return -EINVAL; \ | |
d88203d1 TG |
982 | var = new; \ |
983 | start; \ | |
e9eee03e | 984 | \ |
d88203d1 TG |
985 | return end-buf; \ |
986 | } \ | |
1da177e4 LT |
987 | static SYSDEV_ATTR(name, 0644, show_ ## name, set_ ## name); |
988 | ||
0d7482e3 AK |
989 | static struct sysdev_attribute *bank_attrs; |
990 | ||
991 | static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
992 | char *buf) | |
993 | { | |
994 | u64 b = bank[attr - bank_attrs]; | |
e9eee03e | 995 | |
f6d1826d | 996 | return sprintf(buf, "%llx\n", b); |
0d7482e3 AK |
997 | } |
998 | ||
999 | static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
1000 | const char *buf, size_t siz) | |
1001 | { | |
1002 | char *end; | |
1003 | u64 new = simple_strtoull(buf, &end, 0); | |
e9eee03e | 1004 | |
0d7482e3 AK |
1005 | if (end == buf) |
1006 | return -EINVAL; | |
e9eee03e | 1007 | |
0d7482e3 AK |
1008 | bank[attr - bank_attrs] = new; |
1009 | mce_restart(); | |
e9eee03e | 1010 | |
0d7482e3 AK |
1011 | return end-buf; |
1012 | } | |
a98f0dd3 | 1013 | |
e9eee03e IM |
1014 | static ssize_t |
1015 | show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf) | |
a98f0dd3 AK |
1016 | { |
1017 | strcpy(buf, trigger); | |
1018 | strcat(buf, "\n"); | |
1019 | return strlen(trigger) + 1; | |
1020 | } | |
1021 | ||
4a0b2b4d | 1022 | static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr, |
e9eee03e | 1023 | const char *buf, size_t siz) |
a98f0dd3 AK |
1024 | { |
1025 | char *p; | |
1026 | int len; | |
e9eee03e | 1027 | |
a98f0dd3 AK |
1028 | strncpy(trigger, buf, sizeof(trigger)); |
1029 | trigger[sizeof(trigger)-1] = 0; | |
1030 | len = strlen(trigger); | |
1031 | p = strchr(trigger, '\n'); | |
e9eee03e IM |
1032 | |
1033 | if (*p) | |
1034 | *p = 0; | |
1035 | ||
a98f0dd3 AK |
1036 | return len; |
1037 | } | |
1038 | ||
1039 | static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger); | |
d95d62c0 | 1040 | static SYSDEV_INT_ATTR(tolerant, 0644, tolerant); |
e9eee03e IM |
1041 | |
1042 | ACCESSOR(check_interval, check_interval, mce_restart()) | |
1043 | ||
cb491fca | 1044 | static struct sysdev_attribute *mce_attrs[] = { |
d95d62c0 | 1045 | &attr_tolerant.attr, &attr_check_interval, &attr_trigger, |
a98f0dd3 AK |
1046 | NULL |
1047 | }; | |
1da177e4 | 1048 | |
cb491fca | 1049 | static cpumask_var_t mce_dev_initialized; |
bae19fe0 | 1050 | |
e9eee03e | 1051 | /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */ |
91c6d400 | 1052 | static __cpuinit int mce_create_device(unsigned int cpu) |
1da177e4 LT |
1053 | { |
1054 | int err; | |
73ca5358 | 1055 | int i; |
92cb7612 | 1056 | |
90367556 | 1057 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
1058 | return -EIO; |
1059 | ||
cb491fca IM |
1060 | memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject)); |
1061 | per_cpu(mce_dev, cpu).id = cpu; | |
1062 | per_cpu(mce_dev, cpu).cls = &mce_sysclass; | |
91c6d400 | 1063 | |
cb491fca | 1064 | err = sysdev_register(&per_cpu(mce_dev, cpu)); |
d435d862 AM |
1065 | if (err) |
1066 | return err; | |
1067 | ||
cb491fca IM |
1068 | for (i = 0; mce_attrs[i]; i++) { |
1069 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
d435d862 AM |
1070 | if (err) |
1071 | goto error; | |
1072 | } | |
0d7482e3 | 1073 | for (i = 0; i < banks; i++) { |
cb491fca | 1074 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), |
0d7482e3 AK |
1075 | &bank_attrs[i]); |
1076 | if (err) | |
1077 | goto error2; | |
1078 | } | |
cb491fca | 1079 | cpumask_set_cpu(cpu, mce_dev_initialized); |
91c6d400 | 1080 | |
d435d862 | 1081 | return 0; |
0d7482e3 | 1082 | error2: |
cb491fca IM |
1083 | while (--i >= 0) |
1084 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]); | |
d435d862 | 1085 | error: |
cb491fca IM |
1086 | while (--i >= 0) |
1087 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
1088 | ||
1089 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
d435d862 | 1090 | |
91c6d400 AK |
1091 | return err; |
1092 | } | |
1093 | ||
2d9cd6c2 | 1094 | static __cpuinit void mce_remove_device(unsigned int cpu) |
91c6d400 | 1095 | { |
73ca5358 SL |
1096 | int i; |
1097 | ||
cb491fca | 1098 | if (!cpumask_test_cpu(cpu, mce_dev_initialized)) |
bae19fe0 AH |
1099 | return; |
1100 | ||
cb491fca IM |
1101 | for (i = 0; mce_attrs[i]; i++) |
1102 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
1103 | ||
0d7482e3 | 1104 | for (i = 0; i < banks; i++) |
cb491fca IM |
1105 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]); |
1106 | ||
1107 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
1108 | cpumask_clear_cpu(cpu, mce_dev_initialized); | |
91c6d400 | 1109 | } |
91c6d400 | 1110 | |
d6b75584 | 1111 | /* Make sure there are no machine checks on offlined CPUs. */ |
ec5b3d32 | 1112 | static void mce_disable_cpu(void *h) |
d6b75584 | 1113 | { |
88ccbedd | 1114 | unsigned long action = *(unsigned long *)h; |
cb491fca | 1115 | int i; |
d6b75584 AK |
1116 | |
1117 | if (!mce_available(¤t_cpu_data)) | |
1118 | return; | |
88ccbedd AK |
1119 | if (!(action & CPU_TASKS_FROZEN)) |
1120 | cmci_clear(); | |
d6b75584 AK |
1121 | for (i = 0; i < banks; i++) |
1122 | wrmsrl(MSR_IA32_MC0_CTL + i*4, 0); | |
1123 | } | |
1124 | ||
ec5b3d32 | 1125 | static void mce_reenable_cpu(void *h) |
d6b75584 | 1126 | { |
88ccbedd | 1127 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 1128 | int i; |
d6b75584 AK |
1129 | |
1130 | if (!mce_available(¤t_cpu_data)) | |
1131 | return; | |
e9eee03e | 1132 | |
88ccbedd AK |
1133 | if (!(action & CPU_TASKS_FROZEN)) |
1134 | cmci_reenable(); | |
d6b75584 AK |
1135 | for (i = 0; i < banks; i++) |
1136 | wrmsrl(MSR_IA32_MC0_CTL + i*4, bank[i]); | |
1137 | } | |
1138 | ||
91c6d400 | 1139 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
e9eee03e IM |
1140 | static int __cpuinit |
1141 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) | |
91c6d400 AK |
1142 | { |
1143 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 1144 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 AK |
1145 | |
1146 | switch (action) { | |
bae19fe0 AH |
1147 | case CPU_ONLINE: |
1148 | case CPU_ONLINE_FROZEN: | |
1149 | mce_create_device(cpu); | |
8735728e RW |
1150 | if (threshold_cpu_callback) |
1151 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 1152 | break; |
91c6d400 | 1153 | case CPU_DEAD: |
8bb78442 | 1154 | case CPU_DEAD_FROZEN: |
8735728e RW |
1155 | if (threshold_cpu_callback) |
1156 | threshold_cpu_callback(action, cpu); | |
91c6d400 AK |
1157 | mce_remove_device(cpu); |
1158 | break; | |
52d168e2 AK |
1159 | case CPU_DOWN_PREPARE: |
1160 | case CPU_DOWN_PREPARE_FROZEN: | |
1161 | del_timer_sync(t); | |
88ccbedd | 1162 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
52d168e2 AK |
1163 | break; |
1164 | case CPU_DOWN_FAILED: | |
1165 | case CPU_DOWN_FAILED_FROZEN: | |
6298c512 AK |
1166 | t->expires = round_jiffies(jiffies + |
1167 | __get_cpu_var(next_interval)); | |
52d168e2 | 1168 | add_timer_on(t, cpu); |
88ccbedd AK |
1169 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
1170 | break; | |
1171 | case CPU_POST_DEAD: | |
1172 | /* intentionally ignoring frozen here */ | |
1173 | cmci_rediscover(cpu); | |
52d168e2 | 1174 | break; |
91c6d400 | 1175 | } |
bae19fe0 | 1176 | return NOTIFY_OK; |
91c6d400 AK |
1177 | } |
1178 | ||
1e35669d | 1179 | static struct notifier_block mce_cpu_notifier __cpuinitdata = { |
91c6d400 AK |
1180 | .notifier_call = mce_cpu_callback, |
1181 | }; | |
1182 | ||
0d7482e3 AK |
1183 | static __init int mce_init_banks(void) |
1184 | { | |
1185 | int i; | |
1186 | ||
1187 | bank_attrs = kzalloc(sizeof(struct sysdev_attribute) * banks, | |
1188 | GFP_KERNEL); | |
1189 | if (!bank_attrs) | |
1190 | return -ENOMEM; | |
1191 | ||
1192 | for (i = 0; i < banks; i++) { | |
1193 | struct sysdev_attribute *a = &bank_attrs[i]; | |
e9eee03e IM |
1194 | |
1195 | a->attr.name = kasprintf(GFP_KERNEL, "bank%d", i); | |
0d7482e3 AK |
1196 | if (!a->attr.name) |
1197 | goto nomem; | |
e9eee03e IM |
1198 | |
1199 | a->attr.mode = 0644; | |
1200 | a->show = show_bank; | |
1201 | a->store = set_bank; | |
0d7482e3 AK |
1202 | } |
1203 | return 0; | |
1204 | ||
1205 | nomem: | |
1206 | while (--i >= 0) | |
1207 | kfree(bank_attrs[i].attr.name); | |
1208 | kfree(bank_attrs); | |
1209 | bank_attrs = NULL; | |
e9eee03e | 1210 | |
0d7482e3 AK |
1211 | return -ENOMEM; |
1212 | } | |
1213 | ||
91c6d400 AK |
1214 | static __init int mce_init_device(void) |
1215 | { | |
1216 | int err; | |
1217 | int i = 0; | |
1218 | ||
1da177e4 LT |
1219 | if (!mce_available(&boot_cpu_data)) |
1220 | return -EIO; | |
0d7482e3 | 1221 | |
cb491fca | 1222 | alloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL); |
996867d0 | 1223 | |
0d7482e3 AK |
1224 | err = mce_init_banks(); |
1225 | if (err) | |
1226 | return err; | |
1227 | ||
1da177e4 | 1228 | err = sysdev_class_register(&mce_sysclass); |
d435d862 AM |
1229 | if (err) |
1230 | return err; | |
91c6d400 AK |
1231 | |
1232 | for_each_online_cpu(i) { | |
d435d862 AM |
1233 | err = mce_create_device(i); |
1234 | if (err) | |
1235 | return err; | |
91c6d400 AK |
1236 | } |
1237 | ||
be6b5a35 | 1238 | register_hotcpu_notifier(&mce_cpu_notifier); |
1da177e4 | 1239 | misc_register(&mce_log_device); |
e9eee03e | 1240 | |
1da177e4 | 1241 | return err; |
1da177e4 | 1242 | } |
91c6d400 | 1243 | |
1da177e4 | 1244 | device_initcall(mce_init_device); |
a988d334 | 1245 | |
711c2e48 | 1246 | #else /* CONFIG_X86_32: */ |
a988d334 IM |
1247 | |
1248 | int mce_disabled; | |
1249 | ||
1250 | int nr_mce_banks; | |
1251 | EXPORT_SYMBOL_GPL(nr_mce_banks); /* non-fatal.o */ | |
1252 | ||
1253 | /* Handle unconfigured int18 (should never happen) */ | |
1254 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
1255 | { | |
1256 | printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n", | |
1257 | smp_processor_id()); | |
1258 | } | |
1259 | ||
1260 | /* Call the installed machine check handler for this CPU setup. */ | |
1261 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
1262 | unexpected_machine_check; | |
1263 | ||
1264 | /* This has to be run for each processor */ | |
1265 | void mcheck_init(struct cpuinfo_x86 *c) | |
1266 | { | |
1267 | if (mce_disabled == 1) | |
1268 | return; | |
1269 | ||
1270 | switch (c->x86_vendor) { | |
1271 | case X86_VENDOR_AMD: | |
1272 | amd_mcheck_init(c); | |
1273 | break; | |
1274 | ||
1275 | case X86_VENDOR_INTEL: | |
1276 | if (c->x86 == 5) | |
1277 | intel_p5_mcheck_init(c); | |
1278 | if (c->x86 == 6) | |
1279 | intel_p6_mcheck_init(c); | |
1280 | if (c->x86 == 15) | |
1281 | intel_p4_mcheck_init(c); | |
1282 | break; | |
1283 | ||
1284 | case X86_VENDOR_CENTAUR: | |
1285 | if (c->x86 == 5) | |
1286 | winchip_mcheck_init(c); | |
1287 | break; | |
1288 | ||
1289 | default: | |
1290 | break; | |
1291 | } | |
b659294b | 1292 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", nr_mce_banks); |
a988d334 IM |
1293 | } |
1294 | ||
1295 | static int __init mcheck_disable(char *str) | |
1296 | { | |
1297 | mce_disabled = 1; | |
1298 | return 1; | |
1299 | } | |
1300 | ||
1301 | static int __init mcheck_enable(char *str) | |
1302 | { | |
1303 | mce_disabled = -1; | |
1304 | return 1; | |
1305 | } | |
1306 | ||
1307 | __setup("nomce", mcheck_disable); | |
1308 | __setup("mce", mcheck_enable); | |
1309 | ||
1310 | #endif /* CONFIG_X86_32 */ |