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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
c767a54b JP |
10 | |
11 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
12 | ||
e9eee03e IM |
13 | #include <linux/thread_info.h> |
14 | #include <linux/capability.h> | |
15 | #include <linux/miscdevice.h> | |
16 | #include <linux/ratelimit.h> | |
17 | #include <linux/kallsyms.h> | |
18 | #include <linux/rcupdate.h> | |
e9eee03e | 19 | #include <linux/kobject.h> |
14a02530 | 20 | #include <linux/uaccess.h> |
e9eee03e IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/kernel.h> | |
23 | #include <linux/percpu.h> | |
1da177e4 | 24 | #include <linux/string.h> |
8a25a2fd | 25 | #include <linux/device.h> |
f3c6ea1b | 26 | #include <linux/syscore_ops.h> |
3c079792 | 27 | #include <linux/delay.h> |
8c566ef5 | 28 | #include <linux/ctype.h> |
e9eee03e | 29 | #include <linux/sched.h> |
0d7482e3 | 30 | #include <linux/sysfs.h> |
e9eee03e | 31 | #include <linux/types.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
e9eee03e IM |
33 | #include <linux/init.h> |
34 | #include <linux/kmod.h> | |
35 | #include <linux/poll.h> | |
3c079792 | 36 | #include <linux/nmi.h> |
e9eee03e | 37 | #include <linux/cpu.h> |
14a02530 | 38 | #include <linux/smp.h> |
e9eee03e | 39 | #include <linux/fs.h> |
9b1beaf2 | 40 | #include <linux/mm.h> |
5be9ed25 | 41 | #include <linux/debugfs.h> |
b77e70bf | 42 | #include <linux/irq_work.h> |
69c60c88 | 43 | #include <linux/export.h> |
e9eee03e | 44 | |
d88203d1 | 45 | #include <asm/processor.h> |
95927475 | 46 | #include <asm/traps.h> |
e9eee03e IM |
47 | #include <asm/mce.h> |
48 | #include <asm/msr.h> | |
1da177e4 | 49 | |
bd19a5e6 | 50 | #include "mce-internal.h" |
711c2e48 | 51 | |
93b62c3c | 52 | static DEFINE_MUTEX(mce_chrdev_read_mutex); |
2aa2b50d | 53 | |
f56e8a07 | 54 | #define rcu_dereference_check_mce(p) \ |
ec8c27e0 | 55 | rcu_dereference_index_check((p), \ |
f56e8a07 | 56 | rcu_read_lock_sched_held() || \ |
93b62c3c | 57 | lockdep_is_held(&mce_chrdev_read_mutex)) |
f56e8a07 | 58 | |
8968f9d3 HS |
59 | #define CREATE_TRACE_POINTS |
60 | #include <trace/events/mce.h> | |
61 | ||
3f2f0680 | 62 | #define SPINUNIT 100 /* 100ns */ |
3c079792 | 63 | |
01ca79f1 AK |
64 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
65 | ||
1462594b | 66 | struct mce_bank *mce_banks __read_mostly; |
bf80bbd7 | 67 | struct mce_vendor_flags mce_flags __read_mostly; |
cebe1820 | 68 | |
d203f0b8 | 69 | struct mca_config mca_cfg __read_mostly = { |
84c2559d | 70 | .bootlog = -1, |
d203f0b8 BP |
71 | /* |
72 | * Tolerant levels: | |
73 | * 0: always panic on uncorrected errors, log corrected errors | |
74 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
75 | * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors | |
76 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
77 | */ | |
84c2559d BP |
78 | .tolerant = 1, |
79 | .monarch_timeout = -1 | |
d203f0b8 BP |
80 | }; |
81 | ||
1020bcbc HS |
82 | /* User mode helper program triggered by machine check event */ |
83 | static unsigned long mce_need_notify; | |
84 | static char mce_helper[128]; | |
85 | static char *mce_helper_argv[2] = { mce_helper, NULL }; | |
1da177e4 | 86 | |
93b62c3c HS |
87 | static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait); |
88 | ||
3c079792 AK |
89 | static DEFINE_PER_CPU(struct mce, mces_seen); |
90 | static int cpu_missing; | |
91 | ||
0644414e NR |
92 | /* |
93 | * MCA banks polled by the period polling timer for corrected events. | |
94 | * With Intel CMCI, this only has MCA banks which do not support CMCI (if any). | |
95 | */ | |
ee031c31 AK |
96 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { |
97 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
98 | }; | |
99 | ||
c3d1fb56 NR |
100 | /* |
101 | * MCA banks controlled through firmware first for corrected errors. | |
102 | * This is a global list of banks for which we won't enable CMCI and we | |
103 | * won't poll. Firmware controls these banks and is responsible for | |
104 | * reporting corrected errors through GHES. Uncorrected/recoverable | |
105 | * errors are still notified through a machine check. | |
106 | */ | |
107 | mce_banks_t mce_banks_ce_disabled; | |
108 | ||
9b1beaf2 AK |
109 | static DEFINE_PER_CPU(struct work_struct, mce_work); |
110 | ||
61b0fccd TL |
111 | static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs); |
112 | ||
3653ada5 BP |
113 | /* |
114 | * CPU/chipset specific EDAC code can register a notifier call here to print | |
115 | * MCE errors in a human-readable form. | |
116 | */ | |
83737691 | 117 | static ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain); |
3653ada5 | 118 | |
b5f2fa4e AK |
119 | /* Do initial initialization of a struct mce */ |
120 | void mce_setup(struct mce *m) | |
121 | { | |
122 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 123 | m->cpu = m->extcpu = smp_processor_id(); |
b5f2fa4e | 124 | rdtscll(m->tsc); |
8ee08347 AK |
125 | /* We hope get_seconds stays lockless */ |
126 | m->time = get_seconds(); | |
127 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
128 | m->cpuid = cpuid_eax(1); | |
8ee08347 | 129 | m->socketid = cpu_data(m->extcpu).phys_proc_id; |
8ee08347 AK |
130 | m->apicid = cpu_data(m->extcpu).initial_apicid; |
131 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
b5f2fa4e AK |
132 | } |
133 | ||
ea149b36 AK |
134 | DEFINE_PER_CPU(struct mce, injectm); |
135 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
136 | ||
1da177e4 LT |
137 | /* |
138 | * Lockless MCE logging infrastructure. | |
139 | * This avoids deadlocks on printk locks without having to break locks. Also | |
140 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
141 | */ | |
142 | ||
231fd906 | 143 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
144 | .signature = MCE_LOG_SIGNATURE, |
145 | .len = MCE_LOG_LEN, | |
146 | .recordlen = sizeof(struct mce), | |
d88203d1 | 147 | }; |
1da177e4 LT |
148 | |
149 | void mce_log(struct mce *mce) | |
150 | { | |
151 | unsigned next, entry; | |
f0cb5452 | 152 | int ret = 0; |
e9eee03e | 153 | |
8968f9d3 HS |
154 | /* Emit the trace record: */ |
155 | trace_mce_record(mce); | |
156 | ||
f0cb5452 BP |
157 | ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, mce); |
158 | if (ret == NOTIFY_STOP) | |
159 | return; | |
160 | ||
1da177e4 | 161 | mce->finished = 0; |
7644143c | 162 | wmb(); |
1da177e4 | 163 | for (;;) { |
f56e8a07 | 164 | entry = rcu_dereference_check_mce(mcelog.next); |
673242c1 | 165 | for (;;) { |
696e409d | 166 | |
e9eee03e IM |
167 | /* |
168 | * When the buffer fills up discard new entries. | |
169 | * Assume that the earlier errors are the more | |
170 | * interesting ones: | |
171 | */ | |
673242c1 | 172 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
173 | set_bit(MCE_OVERFLOW, |
174 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
175 | return; |
176 | } | |
e9eee03e | 177 | /* Old left over entry. Skip: */ |
673242c1 AK |
178 | if (mcelog.entry[entry].finished) { |
179 | entry++; | |
180 | continue; | |
181 | } | |
7644143c | 182 | break; |
1da177e4 | 183 | } |
1da177e4 LT |
184 | smp_rmb(); |
185 | next = entry + 1; | |
186 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
187 | break; | |
188 | } | |
189 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 190 | wmb(); |
1da177e4 | 191 | mcelog.entry[entry].finished = 1; |
7644143c | 192 | wmb(); |
1da177e4 | 193 | |
a0189c70 | 194 | mce->finished = 1; |
1020bcbc | 195 | set_bit(0, &mce_need_notify); |
1da177e4 LT |
196 | } |
197 | ||
09371957 BP |
198 | static void drain_mcelog_buffer(void) |
199 | { | |
200 | unsigned int next, i, prev = 0; | |
201 | ||
b11e3d78 | 202 | next = ACCESS_ONCE(mcelog.next); |
09371957 BP |
203 | |
204 | do { | |
205 | struct mce *m; | |
206 | ||
207 | /* drain what was logged during boot */ | |
208 | for (i = prev; i < next; i++) { | |
209 | unsigned long start = jiffies; | |
210 | unsigned retries = 1; | |
211 | ||
212 | m = &mcelog.entry[i]; | |
213 | ||
214 | while (!m->finished) { | |
215 | if (time_after_eq(jiffies, start + 2*retries)) | |
216 | retries++; | |
217 | ||
218 | cpu_relax(); | |
219 | ||
220 | if (!m->finished && retries >= 4) { | |
c767a54b | 221 | pr_err("skipping error being logged currently!\n"); |
09371957 BP |
222 | break; |
223 | } | |
224 | } | |
225 | smp_rmb(); | |
226 | atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); | |
227 | } | |
228 | ||
229 | memset(mcelog.entry + prev, 0, (next - prev) * sizeof(*m)); | |
230 | prev = next; | |
231 | next = cmpxchg(&mcelog.next, prev, 0); | |
232 | } while (next != prev); | |
233 | } | |
234 | ||
235 | ||
3653ada5 BP |
236 | void mce_register_decode_chain(struct notifier_block *nb) |
237 | { | |
238 | atomic_notifier_chain_register(&x86_mce_decoder_chain, nb); | |
09371957 | 239 | drain_mcelog_buffer(); |
3653ada5 BP |
240 | } |
241 | EXPORT_SYMBOL_GPL(mce_register_decode_chain); | |
242 | ||
243 | void mce_unregister_decode_chain(struct notifier_block *nb) | |
244 | { | |
245 | atomic_notifier_chain_unregister(&x86_mce_decoder_chain, nb); | |
246 | } | |
247 | EXPORT_SYMBOL_GPL(mce_unregister_decode_chain); | |
248 | ||
77e26cca | 249 | static void print_mce(struct mce *m) |
1da177e4 | 250 | { |
dffa4b2f BP |
251 | int ret = 0; |
252 | ||
a2d7b0d4 | 253 | pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n", |
d620c67f | 254 | m->extcpu, m->mcgstatus, m->bank, m->status); |
f436f8bb | 255 | |
65ea5b03 | 256 | if (m->ip) { |
a2d7b0d4 | 257 | pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", |
f436f8bb IM |
258 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
259 | m->cs, m->ip); | |
260 | ||
1da177e4 | 261 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 262 | print_symbol("{%s}", m->ip); |
f436f8bb | 263 | pr_cont("\n"); |
1da177e4 | 264 | } |
f436f8bb | 265 | |
a2d7b0d4 | 266 | pr_emerg(HW_ERR "TSC %llx ", m->tsc); |
1da177e4 | 267 | if (m->addr) |
f436f8bb | 268 | pr_cont("ADDR %llx ", m->addr); |
1da177e4 | 269 | if (m->misc) |
f436f8bb | 270 | pr_cont("MISC %llx ", m->misc); |
549d042d | 271 | |
f436f8bb | 272 | pr_cont("\n"); |
506ed6b5 AK |
273 | /* |
274 | * Note this output is parsed by external tools and old fields | |
275 | * should not be changed. | |
276 | */ | |
881e23e5 | 277 | pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n", |
506ed6b5 AK |
278 | m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, |
279 | cpu_data(m->extcpu).microcode); | |
f436f8bb IM |
280 | |
281 | /* | |
282 | * Print out human-readable details about the MCE error, | |
fb253195 | 283 | * (if the CPU has an implementation for that) |
f436f8bb | 284 | */ |
dffa4b2f BP |
285 | ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); |
286 | if (ret == NOTIFY_STOP) | |
287 | return; | |
288 | ||
289 | pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); | |
86503560 AK |
290 | } |
291 | ||
f94b61c2 AK |
292 | #define PANIC_TIMEOUT 5 /* 5 seconds */ |
293 | ||
c7c9b392 | 294 | static atomic_t mce_panicked; |
f94b61c2 | 295 | |
bf783f9f | 296 | static int fake_panic; |
c7c9b392 | 297 | static atomic_t mce_fake_panicked; |
bf783f9f | 298 | |
f94b61c2 AK |
299 | /* Panic in progress. Enable interrupts and wait for final IPI */ |
300 | static void wait_for_panic(void) | |
301 | { | |
302 | long timeout = PANIC_TIMEOUT*USEC_PER_SEC; | |
f436f8bb | 303 | |
f94b61c2 AK |
304 | preempt_disable(); |
305 | local_irq_enable(); | |
306 | while (timeout-- > 0) | |
307 | udelay(1); | |
29b0f591 | 308 | if (panic_timeout == 0) |
7af19e4a | 309 | panic_timeout = mca_cfg.panic_timeout; |
f94b61c2 AK |
310 | panic("Panicing machine check CPU died"); |
311 | } | |
312 | ||
6c80f87e | 313 | static void mce_panic(const char *msg, struct mce *final, char *exp) |
d88203d1 | 314 | { |
482908b4 | 315 | int i, apei_err = 0; |
e02e68d3 | 316 | |
bf783f9f HY |
317 | if (!fake_panic) { |
318 | /* | |
319 | * Make sure only one CPU runs in machine check panic | |
320 | */ | |
c7c9b392 | 321 | if (atomic_inc_return(&mce_panicked) > 1) |
bf783f9f HY |
322 | wait_for_panic(); |
323 | barrier(); | |
f94b61c2 | 324 | |
bf783f9f HY |
325 | bust_spinlocks(1); |
326 | console_verbose(); | |
327 | } else { | |
328 | /* Don't log too much for fake panic */ | |
c7c9b392 | 329 | if (atomic_inc_return(&mce_fake_panicked) > 1) |
bf783f9f HY |
330 | return; |
331 | } | |
a0189c70 | 332 | /* First print corrected ones that are still unlogged */ |
1da177e4 | 333 | for (i = 0; i < MCE_LOG_LEN; i++) { |
a0189c70 | 334 | struct mce *m = &mcelog.entry[i]; |
77e26cca HS |
335 | if (!(m->status & MCI_STATUS_VAL)) |
336 | continue; | |
482908b4 | 337 | if (!(m->status & MCI_STATUS_UC)) { |
77e26cca | 338 | print_mce(m); |
482908b4 HY |
339 | if (!apei_err) |
340 | apei_err = apei_write_mce(m); | |
341 | } | |
a0189c70 AK |
342 | } |
343 | /* Now print uncorrected but with the final one last */ | |
344 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
345 | struct mce *m = &mcelog.entry[i]; | |
346 | if (!(m->status & MCI_STATUS_VAL)) | |
1da177e4 | 347 | continue; |
77e26cca HS |
348 | if (!(m->status & MCI_STATUS_UC)) |
349 | continue; | |
482908b4 | 350 | if (!final || memcmp(m, final, sizeof(struct mce))) { |
77e26cca | 351 | print_mce(m); |
482908b4 HY |
352 | if (!apei_err) |
353 | apei_err = apei_write_mce(m); | |
354 | } | |
1da177e4 | 355 | } |
482908b4 | 356 | if (final) { |
77e26cca | 357 | print_mce(final); |
482908b4 HY |
358 | if (!apei_err) |
359 | apei_err = apei_write_mce(final); | |
360 | } | |
3c079792 | 361 | if (cpu_missing) |
a2d7b0d4 | 362 | pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n"); |
bd19a5e6 | 363 | if (exp) |
a2d7b0d4 | 364 | pr_emerg(HW_ERR "Machine check: %s\n", exp); |
bf783f9f HY |
365 | if (!fake_panic) { |
366 | if (panic_timeout == 0) | |
7af19e4a | 367 | panic_timeout = mca_cfg.panic_timeout; |
bf783f9f HY |
368 | panic(msg); |
369 | } else | |
a2d7b0d4 | 370 | pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); |
d88203d1 | 371 | } |
1da177e4 | 372 | |
ea149b36 AK |
373 | /* Support code for software error injection */ |
374 | ||
375 | static int msr_to_offset(u32 msr) | |
376 | { | |
0a3aee0d | 377 | unsigned bank = __this_cpu_read(injectm.bank); |
f436f8bb | 378 | |
84c2559d | 379 | if (msr == mca_cfg.rip_msr) |
ea149b36 | 380 | return offsetof(struct mce, ip); |
a2d32bcb | 381 | if (msr == MSR_IA32_MCx_STATUS(bank)) |
ea149b36 | 382 | return offsetof(struct mce, status); |
a2d32bcb | 383 | if (msr == MSR_IA32_MCx_ADDR(bank)) |
ea149b36 | 384 | return offsetof(struct mce, addr); |
a2d32bcb | 385 | if (msr == MSR_IA32_MCx_MISC(bank)) |
ea149b36 AK |
386 | return offsetof(struct mce, misc); |
387 | if (msr == MSR_IA32_MCG_STATUS) | |
388 | return offsetof(struct mce, mcgstatus); | |
389 | return -1; | |
390 | } | |
391 | ||
5f8c1a54 AK |
392 | /* MSR access wrappers used for error injection */ |
393 | static u64 mce_rdmsrl(u32 msr) | |
394 | { | |
395 | u64 v; | |
11868a2d | 396 | |
0a3aee0d | 397 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 398 | int offset = msr_to_offset(msr); |
11868a2d | 399 | |
ea149b36 AK |
400 | if (offset < 0) |
401 | return 0; | |
89cbc767 | 402 | return *(u64 *)((char *)this_cpu_ptr(&injectm) + offset); |
ea149b36 | 403 | } |
11868a2d IM |
404 | |
405 | if (rdmsrl_safe(msr, &v)) { | |
406 | WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr); | |
407 | /* | |
408 | * Return zero in case the access faulted. This should | |
409 | * not happen normally but can happen if the CPU does | |
410 | * something weird, or if the code is buggy. | |
411 | */ | |
412 | v = 0; | |
413 | } | |
414 | ||
5f8c1a54 AK |
415 | return v; |
416 | } | |
417 | ||
418 | static void mce_wrmsrl(u32 msr, u64 v) | |
419 | { | |
0a3aee0d | 420 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 421 | int offset = msr_to_offset(msr); |
11868a2d | 422 | |
ea149b36 | 423 | if (offset >= 0) |
89cbc767 | 424 | *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v; |
ea149b36 AK |
425 | return; |
426 | } | |
5f8c1a54 AK |
427 | wrmsrl(msr, v); |
428 | } | |
429 | ||
b8325c5b HS |
430 | /* |
431 | * Collect all global (w.r.t. this processor) status about this machine | |
432 | * check into our "mce" struct so that we can use it later to assess | |
433 | * the severity of the problem as we read per-bank specific details. | |
434 | */ | |
435 | static inline void mce_gather_info(struct mce *m, struct pt_regs *regs) | |
436 | { | |
437 | mce_setup(m); | |
438 | ||
439 | m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); | |
440 | if (regs) { | |
441 | /* | |
442 | * Get the address of the instruction at the time of | |
443 | * the machine check error. | |
444 | */ | |
445 | if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) { | |
446 | m->ip = regs->ip; | |
447 | m->cs = regs->cs; | |
a129a7c8 AK |
448 | |
449 | /* | |
450 | * When in VM86 mode make the cs look like ring 3 | |
451 | * always. This is a lie, but it's better than passing | |
452 | * the additional vm86 bit around everywhere. | |
453 | */ | |
454 | if (v8086_mode(regs)) | |
455 | m->cs |= 3; | |
b8325c5b HS |
456 | } |
457 | /* Use accurate RIP reporting if available. */ | |
84c2559d BP |
458 | if (mca_cfg.rip_msr) |
459 | m->ip = mce_rdmsrl(mca_cfg.rip_msr); | |
b8325c5b HS |
460 | } |
461 | } | |
462 | ||
9b1beaf2 AK |
463 | /* |
464 | * Simple lockless ring to communicate PFNs from the exception handler with the | |
465 | * process context work function. This is vastly simplified because there's | |
466 | * only a single reader and a single writer. | |
467 | */ | |
468 | #define MCE_RING_SIZE 16 /* we use one entry less */ | |
469 | ||
470 | struct mce_ring { | |
471 | unsigned short start; | |
472 | unsigned short end; | |
473 | unsigned long ring[MCE_RING_SIZE]; | |
474 | }; | |
475 | static DEFINE_PER_CPU(struct mce_ring, mce_ring); | |
476 | ||
477 | /* Runs with CPU affinity in workqueue */ | |
478 | static int mce_ring_empty(void) | |
479 | { | |
89cbc767 | 480 | struct mce_ring *r = this_cpu_ptr(&mce_ring); |
9b1beaf2 AK |
481 | |
482 | return r->start == r->end; | |
483 | } | |
484 | ||
485 | static int mce_ring_get(unsigned long *pfn) | |
486 | { | |
487 | struct mce_ring *r; | |
488 | int ret = 0; | |
489 | ||
490 | *pfn = 0; | |
491 | get_cpu(); | |
89cbc767 | 492 | r = this_cpu_ptr(&mce_ring); |
9b1beaf2 AK |
493 | if (r->start == r->end) |
494 | goto out; | |
495 | *pfn = r->ring[r->start]; | |
496 | r->start = (r->start + 1) % MCE_RING_SIZE; | |
497 | ret = 1; | |
498 | out: | |
499 | put_cpu(); | |
500 | return ret; | |
501 | } | |
502 | ||
503 | /* Always runs in MCE context with preempt off */ | |
504 | static int mce_ring_add(unsigned long pfn) | |
505 | { | |
89cbc767 | 506 | struct mce_ring *r = this_cpu_ptr(&mce_ring); |
9b1beaf2 AK |
507 | unsigned next; |
508 | ||
509 | next = (r->end + 1) % MCE_RING_SIZE; | |
510 | if (next == r->start) | |
511 | return -1; | |
512 | r->ring[r->end] = pfn; | |
513 | wmb(); | |
514 | r->end = next; | |
515 | return 0; | |
516 | } | |
517 | ||
88ccbedd | 518 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 519 | { |
1462594b | 520 | if (mca_cfg.disabled) |
5b4408fd | 521 | return 0; |
3d1712c9 | 522 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
523 | } |
524 | ||
9b1beaf2 AK |
525 | static void mce_schedule_work(void) |
526 | { | |
4d899be5 | 527 | if (!mce_ring_empty()) |
89cbc767 | 528 | schedule_work(this_cpu_ptr(&mce_work)); |
9b1beaf2 AK |
529 | } |
530 | ||
83737691 | 531 | static DEFINE_PER_CPU(struct irq_work, mce_irq_work); |
b77e70bf HS |
532 | |
533 | static void mce_irq_work_cb(struct irq_work *entry) | |
ccc3c319 | 534 | { |
9ff36ee9 | 535 | mce_notify_irq(); |
9b1beaf2 | 536 | mce_schedule_work(); |
ccc3c319 | 537 | } |
ccc3c319 AK |
538 | |
539 | static void mce_report_event(struct pt_regs *regs) | |
540 | { | |
541 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { | |
9ff36ee9 | 542 | mce_notify_irq(); |
9b1beaf2 AK |
543 | /* |
544 | * Triggering the work queue here is just an insurance | |
545 | * policy in case the syscall exit notify handler | |
546 | * doesn't run soon enough or ends up running on the | |
547 | * wrong CPU (can happen when audit sleeps) | |
548 | */ | |
549 | mce_schedule_work(); | |
ccc3c319 AK |
550 | return; |
551 | } | |
552 | ||
89cbc767 | 553 | irq_work_queue(this_cpu_ptr(&mce_irq_work)); |
ccc3c319 AK |
554 | } |
555 | ||
85f92694 TL |
556 | /* |
557 | * Read ADDR and MISC registers. | |
558 | */ | |
559 | static void mce_read_aux(struct mce *m, int i) | |
560 | { | |
561 | if (m->status & MCI_STATUS_MISCV) | |
562 | m->misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); | |
563 | if (m->status & MCI_STATUS_ADDRV) { | |
564 | m->addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); | |
565 | ||
566 | /* | |
567 | * Mask the reported address by the reported granularity. | |
568 | */ | |
1462594b | 569 | if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) { |
85f92694 TL |
570 | u8 shift = MCI_MISC_ADDR_LSB(m->misc); |
571 | m->addr >>= shift; | |
572 | m->addr <<= shift; | |
573 | } | |
574 | } | |
575 | } | |
576 | ||
fa92c586 CY |
577 | static bool memory_error(struct mce *m) |
578 | { | |
579 | struct cpuinfo_x86 *c = &boot_cpu_data; | |
580 | ||
581 | if (c->x86_vendor == X86_VENDOR_AMD) { | |
582 | /* | |
583 | * coming soon | |
584 | */ | |
585 | return false; | |
586 | } else if (c->x86_vendor == X86_VENDOR_INTEL) { | |
587 | /* | |
588 | * Intel SDM Volume 3B - 15.9.2 Compound Error Codes | |
589 | * | |
590 | * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for | |
591 | * indicating a memory error. Bit 8 is used for indicating a | |
592 | * cache hierarchy error. The combination of bit 2 and bit 3 | |
593 | * is used for indicating a `generic' cache hierarchy error | |
594 | * But we can't just blindly check the above bits, because if | |
595 | * bit 11 is set, then it is a bus/interconnect error - and | |
596 | * either way the above bits just gives more detail on what | |
597 | * bus/interconnect error happened. Note that bit 12 can be | |
598 | * ignored, as it's the "filter" bit. | |
599 | */ | |
600 | return (m->status & 0xef80) == BIT(7) || | |
601 | (m->status & 0xef00) == BIT(8) || | |
602 | (m->status & 0xeffc) == 0xc; | |
603 | } | |
604 | ||
605 | return false; | |
606 | } | |
607 | ||
ca84f696 AK |
608 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
609 | ||
d88203d1 | 610 | /* |
b79109c3 AK |
611 | * Poll for corrected events or events that happened before reset. |
612 | * Those are just logged through /dev/mcelog. | |
613 | * | |
614 | * This is executed in standard interrupt context. | |
ed7290d0 AK |
615 | * |
616 | * Note: spec recommends to panic for fatal unsignalled | |
617 | * errors here. However this would be quite problematic -- | |
618 | * we would need to reimplement the Monarch handling and | |
619 | * it would mess up the exclusion between exception handler | |
620 | * and poll hander -- * so we skip this for now. | |
621 | * These cases should not happen anyways, or only when the CPU | |
622 | * is already totally * confused. In this case it's likely it will | |
623 | * not fully execute the machine check handler either. | |
b79109c3 | 624 | */ |
3f2f0680 | 625 | bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 | 626 | { |
3f2f0680 | 627 | bool error_logged = false; |
b79109c3 | 628 | struct mce m; |
fa92c586 | 629 | int severity; |
b79109c3 AK |
630 | int i; |
631 | ||
c6ae41e7 | 632 | this_cpu_inc(mce_poll_count); |
ca84f696 | 633 | |
b8325c5b | 634 | mce_gather_info(&m, NULL); |
b79109c3 | 635 | |
d203f0b8 | 636 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 637 | if (!mce_banks[i].ctl || !test_bit(i, *b)) |
b79109c3 AK |
638 | continue; |
639 | ||
640 | m.misc = 0; | |
641 | m.addr = 0; | |
642 | m.bank = i; | |
643 | m.tsc = 0; | |
644 | ||
645 | barrier(); | |
a2d32bcb | 646 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
b79109c3 AK |
647 | if (!(m.status & MCI_STATUS_VAL)) |
648 | continue; | |
649 | ||
3f2f0680 | 650 | |
b79109c3 | 651 | /* |
ed7290d0 AK |
652 | * Uncorrected or signalled events are handled by the exception |
653 | * handler when it is enabled, so don't process those here. | |
b79109c3 AK |
654 | * |
655 | * TBD do the same check for MCI_STATUS_EN here? | |
656 | */ | |
ed7290d0 | 657 | if (!(flags & MCP_UC) && |
1462594b | 658 | (m.status & (mca_cfg.ser ? MCI_STATUS_S : MCI_STATUS_UC))) |
b79109c3 AK |
659 | continue; |
660 | ||
85f92694 | 661 | mce_read_aux(&m, i); |
b79109c3 AK |
662 | |
663 | if (!(flags & MCP_TIMESTAMP)) | |
664 | m.tsc = 0; | |
fa92c586 CY |
665 | |
666 | severity = mce_severity(&m, mca_cfg.tolerant, NULL, false); | |
667 | ||
668 | /* | |
669 | * In the cases where we don't have a valid address after all, | |
670 | * do not add it into the ring buffer. | |
671 | */ | |
672 | if (severity == MCE_DEFERRED_SEVERITY && memory_error(&m)) { | |
673 | if (m.status & MCI_STATUS_ADDRV) { | |
674 | mce_ring_add(m.addr >> PAGE_SHIFT); | |
675 | mce_schedule_work(); | |
676 | } | |
677 | } | |
678 | ||
b79109c3 AK |
679 | /* |
680 | * Don't get the IP here because it's unlikely to | |
681 | * have anything to do with the actual error location. | |
682 | */ | |
3f2f0680 BP |
683 | if (!(flags & MCP_DONTLOG) && !mca_cfg.dont_log_ce) { |
684 | error_logged = true; | |
5679af4c | 685 | mce_log(&m); |
3f2f0680 | 686 | } |
b79109c3 AK |
687 | |
688 | /* | |
689 | * Clear state for this bank. | |
690 | */ | |
a2d32bcb | 691 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
b79109c3 AK |
692 | } |
693 | ||
694 | /* | |
695 | * Don't clear MCG_STATUS here because it's only defined for | |
696 | * exceptions. | |
697 | */ | |
88921be3 AK |
698 | |
699 | sync_core(); | |
3f2f0680 BP |
700 | |
701 | return error_logged; | |
b79109c3 | 702 | } |
ea149b36 | 703 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 | 704 | |
bd19a5e6 AK |
705 | /* |
706 | * Do a quick check if any of the events requires a panic. | |
707 | * This decides if we keep the events around or clear them. | |
708 | */ | |
61b0fccd TL |
709 | static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp, |
710 | struct pt_regs *regs) | |
bd19a5e6 | 711 | { |
95022b8c | 712 | int i, ret = 0; |
bd19a5e6 | 713 | |
d203f0b8 | 714 | for (i = 0; i < mca_cfg.banks; i++) { |
a2d32bcb | 715 | m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
61b0fccd | 716 | if (m->status & MCI_STATUS_VAL) { |
95022b8c | 717 | __set_bit(i, validp); |
61b0fccd TL |
718 | if (quirk_no_way_out) |
719 | quirk_no_way_out(i, m, regs); | |
720 | } | |
e3480271 CY |
721 | if (mce_severity(m, mca_cfg.tolerant, msg, true) >= |
722 | MCE_PANIC_SEVERITY) | |
95022b8c | 723 | ret = 1; |
bd19a5e6 | 724 | } |
95022b8c | 725 | return ret; |
bd19a5e6 AK |
726 | } |
727 | ||
3c079792 AK |
728 | /* |
729 | * Variable to establish order between CPUs while scanning. | |
730 | * Each CPU spins initially until executing is equal its number. | |
731 | */ | |
732 | static atomic_t mce_executing; | |
733 | ||
734 | /* | |
735 | * Defines order of CPUs on entry. First CPU becomes Monarch. | |
736 | */ | |
737 | static atomic_t mce_callin; | |
738 | ||
739 | /* | |
740 | * Check if a timeout waiting for other CPUs happened. | |
741 | */ | |
6c80f87e | 742 | static int mce_timed_out(u64 *t, const char *msg) |
3c079792 AK |
743 | { |
744 | /* | |
745 | * The others already did panic for some reason. | |
746 | * Bail out like in a timeout. | |
747 | * rmb() to tell the compiler that system_state | |
748 | * might have been modified by someone else. | |
749 | */ | |
750 | rmb(); | |
c7c9b392 | 751 | if (atomic_read(&mce_panicked)) |
3c079792 | 752 | wait_for_panic(); |
84c2559d | 753 | if (!mca_cfg.monarch_timeout) |
3c079792 AK |
754 | goto out; |
755 | if ((s64)*t < SPINUNIT) { | |
716079f6 | 756 | if (mca_cfg.tolerant <= 1) |
6c80f87e | 757 | mce_panic(msg, NULL, NULL); |
3c079792 AK |
758 | cpu_missing = 1; |
759 | return 1; | |
760 | } | |
761 | *t -= SPINUNIT; | |
762 | out: | |
763 | touch_nmi_watchdog(); | |
764 | return 0; | |
765 | } | |
766 | ||
767 | /* | |
768 | * The Monarch's reign. The Monarch is the CPU who entered | |
769 | * the machine check handler first. It waits for the others to | |
770 | * raise the exception too and then grades them. When any | |
771 | * error is fatal panic. Only then let the others continue. | |
772 | * | |
773 | * The other CPUs entering the MCE handler will be controlled by the | |
774 | * Monarch. They are called Subjects. | |
775 | * | |
776 | * This way we prevent any potential data corruption in a unrecoverable case | |
777 | * and also makes sure always all CPU's errors are examined. | |
778 | * | |
680b6cfd | 779 | * Also this detects the case of a machine check event coming from outer |
3c079792 AK |
780 | * space (not detected by any CPUs) In this case some external agent wants |
781 | * us to shut down, so panic too. | |
782 | * | |
783 | * The other CPUs might still decide to panic if the handler happens | |
784 | * in a unrecoverable place, but in this case the system is in a semi-stable | |
785 | * state and won't corrupt anything by itself. It's ok to let the others | |
786 | * continue for a bit first. | |
787 | * | |
788 | * All the spin loops have timeouts; when a timeout happens a CPU | |
789 | * typically elects itself to be Monarch. | |
790 | */ | |
791 | static void mce_reign(void) | |
792 | { | |
793 | int cpu; | |
794 | struct mce *m = NULL; | |
795 | int global_worst = 0; | |
796 | char *msg = NULL; | |
797 | char *nmsg = NULL; | |
798 | ||
799 | /* | |
800 | * This CPU is the Monarch and the other CPUs have run | |
801 | * through their handlers. | |
802 | * Grade the severity of the errors of all the CPUs. | |
803 | */ | |
804 | for_each_possible_cpu(cpu) { | |
d203f0b8 BP |
805 | int severity = mce_severity(&per_cpu(mces_seen, cpu), |
806 | mca_cfg.tolerant, | |
e3480271 | 807 | &nmsg, true); |
3c079792 AK |
808 | if (severity > global_worst) { |
809 | msg = nmsg; | |
810 | global_worst = severity; | |
811 | m = &per_cpu(mces_seen, cpu); | |
812 | } | |
813 | } | |
814 | ||
815 | /* | |
816 | * Cannot recover? Panic here then. | |
817 | * This dumps all the mces in the log buffer and stops the | |
818 | * other CPUs. | |
819 | */ | |
d203f0b8 | 820 | if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) |
8af7043a | 821 | mce_panic("Fatal machine check", m, msg); |
3c079792 AK |
822 | |
823 | /* | |
824 | * For UC somewhere we let the CPU who detects it handle it. | |
825 | * Also must let continue the others, otherwise the handling | |
826 | * CPU could deadlock on a lock. | |
827 | */ | |
828 | ||
829 | /* | |
830 | * No machine check event found. Must be some external | |
831 | * source or one CPU is hung. Panic. | |
832 | */ | |
d203f0b8 | 833 | if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3) |
8af7043a | 834 | mce_panic("Fatal machine check from unknown source", NULL, NULL); |
3c079792 AK |
835 | |
836 | /* | |
837 | * Now clear all the mces_seen so that they don't reappear on | |
838 | * the next mce. | |
839 | */ | |
840 | for_each_possible_cpu(cpu) | |
841 | memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); | |
842 | } | |
843 | ||
844 | static atomic_t global_nwo; | |
845 | ||
846 | /* | |
847 | * Start of Monarch synchronization. This waits until all CPUs have | |
848 | * entered the exception handler and then determines if any of them | |
849 | * saw a fatal event that requires panic. Then it executes them | |
850 | * in the entry order. | |
851 | * TBD double check parallel CPU hotunplug | |
852 | */ | |
7fb06fc9 | 853 | static int mce_start(int *no_way_out) |
3c079792 | 854 | { |
7fb06fc9 | 855 | int order; |
3c079792 | 856 | int cpus = num_online_cpus(); |
84c2559d | 857 | u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; |
3c079792 | 858 | |
7fb06fc9 HS |
859 | if (!timeout) |
860 | return -1; | |
3c079792 | 861 | |
7fb06fc9 | 862 | atomic_add(*no_way_out, &global_nwo); |
184e1fdf HY |
863 | /* |
864 | * global_nwo should be updated before mce_callin | |
865 | */ | |
866 | smp_wmb(); | |
a95436e4 | 867 | order = atomic_inc_return(&mce_callin); |
3c079792 AK |
868 | |
869 | /* | |
870 | * Wait for everyone. | |
871 | */ | |
872 | while (atomic_read(&mce_callin) != cpus) { | |
6c80f87e AL |
873 | if (mce_timed_out(&timeout, |
874 | "Timeout: Not all CPUs entered broadcast exception handler")) { | |
3c079792 | 875 | atomic_set(&global_nwo, 0); |
7fb06fc9 | 876 | return -1; |
3c079792 AK |
877 | } |
878 | ndelay(SPINUNIT); | |
879 | } | |
880 | ||
184e1fdf HY |
881 | /* |
882 | * mce_callin should be read before global_nwo | |
883 | */ | |
884 | smp_rmb(); | |
3c079792 | 885 | |
7fb06fc9 HS |
886 | if (order == 1) { |
887 | /* | |
888 | * Monarch: Starts executing now, the others wait. | |
889 | */ | |
3c079792 | 890 | atomic_set(&mce_executing, 1); |
7fb06fc9 HS |
891 | } else { |
892 | /* | |
893 | * Subject: Now start the scanning loop one by one in | |
894 | * the original callin order. | |
895 | * This way when there are any shared banks it will be | |
896 | * only seen by one CPU before cleared, avoiding duplicates. | |
897 | */ | |
898 | while (atomic_read(&mce_executing) < order) { | |
6c80f87e AL |
899 | if (mce_timed_out(&timeout, |
900 | "Timeout: Subject CPUs unable to finish machine check processing")) { | |
7fb06fc9 HS |
901 | atomic_set(&global_nwo, 0); |
902 | return -1; | |
903 | } | |
904 | ndelay(SPINUNIT); | |
905 | } | |
3c079792 AK |
906 | } |
907 | ||
908 | /* | |
7fb06fc9 | 909 | * Cache the global no_way_out state. |
3c079792 | 910 | */ |
7fb06fc9 HS |
911 | *no_way_out = atomic_read(&global_nwo); |
912 | ||
913 | return order; | |
3c079792 AK |
914 | } |
915 | ||
916 | /* | |
917 | * Synchronize between CPUs after main scanning loop. | |
918 | * This invokes the bulk of the Monarch processing. | |
919 | */ | |
920 | static int mce_end(int order) | |
921 | { | |
922 | int ret = -1; | |
84c2559d | 923 | u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; |
3c079792 AK |
924 | |
925 | if (!timeout) | |
926 | goto reset; | |
927 | if (order < 0) | |
928 | goto reset; | |
929 | ||
930 | /* | |
931 | * Allow others to run. | |
932 | */ | |
933 | atomic_inc(&mce_executing); | |
934 | ||
935 | if (order == 1) { | |
936 | /* CHECKME: Can this race with a parallel hotplug? */ | |
937 | int cpus = num_online_cpus(); | |
938 | ||
939 | /* | |
940 | * Monarch: Wait for everyone to go through their scanning | |
941 | * loops. | |
942 | */ | |
943 | while (atomic_read(&mce_executing) <= cpus) { | |
6c80f87e AL |
944 | if (mce_timed_out(&timeout, |
945 | "Timeout: Monarch CPU unable to finish machine check processing")) | |
3c079792 AK |
946 | goto reset; |
947 | ndelay(SPINUNIT); | |
948 | } | |
949 | ||
950 | mce_reign(); | |
951 | barrier(); | |
952 | ret = 0; | |
953 | } else { | |
954 | /* | |
955 | * Subject: Wait for Monarch to finish. | |
956 | */ | |
957 | while (atomic_read(&mce_executing) != 0) { | |
6c80f87e AL |
958 | if (mce_timed_out(&timeout, |
959 | "Timeout: Monarch CPU did not finish machine check processing")) | |
3c079792 AK |
960 | goto reset; |
961 | ndelay(SPINUNIT); | |
962 | } | |
963 | ||
964 | /* | |
965 | * Don't reset anything. That's done by the Monarch. | |
966 | */ | |
967 | return 0; | |
968 | } | |
969 | ||
970 | /* | |
971 | * Reset all global state. | |
972 | */ | |
973 | reset: | |
974 | atomic_set(&global_nwo, 0); | |
975 | atomic_set(&mce_callin, 0); | |
976 | barrier(); | |
977 | ||
978 | /* | |
979 | * Let others run again. | |
980 | */ | |
981 | atomic_set(&mce_executing, 0); | |
982 | return ret; | |
983 | } | |
984 | ||
9b1beaf2 AK |
985 | /* |
986 | * Check if the address reported by the CPU is in a format we can parse. | |
987 | * It would be possible to add code for most other cases, but all would | |
988 | * be somewhat complicated (e.g. segment offset would require an instruction | |
0d2eb44f | 989 | * parser). So only support physical addresses up to page granuality for now. |
9b1beaf2 AK |
990 | */ |
991 | static int mce_usable_address(struct mce *m) | |
992 | { | |
993 | if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) | |
994 | return 0; | |
2b90e77e | 995 | if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) |
9b1beaf2 | 996 | return 0; |
2b90e77e | 997 | if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) |
9b1beaf2 AK |
998 | return 0; |
999 | return 1; | |
1000 | } | |
1001 | ||
3c079792 AK |
1002 | static void mce_clear_state(unsigned long *toclear) |
1003 | { | |
1004 | int i; | |
1005 | ||
d203f0b8 | 1006 | for (i = 0; i < mca_cfg.banks; i++) { |
3c079792 | 1007 | if (test_bit(i, toclear)) |
a2d32bcb | 1008 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
3c079792 AK |
1009 | } |
1010 | } | |
1011 | ||
b79109c3 AK |
1012 | /* |
1013 | * The actual machine check handler. This only handles real | |
1014 | * exceptions when something got corrupted coming in through int 18. | |
1015 | * | |
1016 | * This is executed in NMI context not subject to normal locking rules. This | |
1017 | * implies that most kernel services cannot be safely used. Don't even | |
1018 | * think about putting a printk in there! | |
3c079792 AK |
1019 | * |
1020 | * On Intel systems this is entered on all CPUs in parallel through | |
1021 | * MCE broadcast. However some CPUs might be broken beyond repair, | |
1022 | * so be always careful when synchronizing with others. | |
1da177e4 | 1023 | */ |
e9eee03e | 1024 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 | 1025 | { |
1462594b | 1026 | struct mca_config *cfg = &mca_cfg; |
3c079792 | 1027 | struct mce m, *final; |
95927475 | 1028 | enum ctx_state prev_state; |
1da177e4 | 1029 | int i; |
3c079792 AK |
1030 | int worst = 0; |
1031 | int severity; | |
1032 | /* | |
1033 | * Establish sequential order between the CPUs entering the machine | |
1034 | * check handler. | |
1035 | */ | |
7fb06fc9 | 1036 | int order; |
bd78432c TH |
1037 | /* |
1038 | * If no_way_out gets set, there is no safe way to recover from this | |
d203f0b8 | 1039 | * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway. |
bd78432c TH |
1040 | */ |
1041 | int no_way_out = 0; | |
1042 | /* | |
1043 | * If kill_it gets set, there might be a way to recover from this | |
1044 | * error. | |
1045 | */ | |
1046 | int kill_it = 0; | |
b79109c3 | 1047 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
95022b8c | 1048 | DECLARE_BITMAP(valid_banks, MAX_NR_BANKS); |
bd19a5e6 | 1049 | char *msg = "Unknown"; |
d4812e16 TL |
1050 | u64 recover_paddr = ~0ull; |
1051 | int flags = MF_ACTION_REQUIRED; | |
1da177e4 | 1052 | |
95927475 AL |
1053 | prev_state = ist_enter(regs); |
1054 | ||
c6ae41e7 | 1055 | this_cpu_inc(mce_exception_count); |
01ca79f1 | 1056 | |
1462594b | 1057 | if (!cfg->banks) |
32561696 | 1058 | goto out; |
1da177e4 | 1059 | |
b8325c5b | 1060 | mce_gather_info(&m, regs); |
b5f2fa4e | 1061 | |
89cbc767 | 1062 | final = this_cpu_ptr(&mces_seen); |
3c079792 AK |
1063 | *final = m; |
1064 | ||
95022b8c | 1065 | memset(valid_banks, 0, sizeof(valid_banks)); |
61b0fccd | 1066 | no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs); |
680b6cfd | 1067 | |
1da177e4 LT |
1068 | barrier(); |
1069 | ||
ed7290d0 | 1070 | /* |
a8c321fb TL |
1071 | * When no restart IP might need to kill or panic. |
1072 | * Assume the worst for now, but if we find the | |
1073 | * severity is MCE_AR_SEVERITY we have other options. | |
ed7290d0 AK |
1074 | */ |
1075 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
1076 | kill_it = 1; | |
1077 | ||
3c079792 AK |
1078 | /* |
1079 | * Go through all the banks in exclusion of the other CPUs. | |
1080 | * This way we don't report duplicated events on shared banks | |
1081 | * because the first one to see it will clear it. | |
1082 | */ | |
7fb06fc9 | 1083 | order = mce_start(&no_way_out); |
1462594b | 1084 | for (i = 0; i < cfg->banks; i++) { |
b79109c3 | 1085 | __clear_bit(i, toclear); |
95022b8c TL |
1086 | if (!test_bit(i, valid_banks)) |
1087 | continue; | |
cebe1820 | 1088 | if (!mce_banks[i].ctl) |
1da177e4 | 1089 | continue; |
d88203d1 TG |
1090 | |
1091 | m.misc = 0; | |
1da177e4 LT |
1092 | m.addr = 0; |
1093 | m.bank = i; | |
1da177e4 | 1094 | |
a2d32bcb | 1095 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
1da177e4 LT |
1096 | if ((m.status & MCI_STATUS_VAL) == 0) |
1097 | continue; | |
1098 | ||
b79109c3 | 1099 | /* |
ed7290d0 AK |
1100 | * Non uncorrected or non signaled errors are handled by |
1101 | * machine_check_poll. Leave them alone, unless this panics. | |
b79109c3 | 1102 | */ |
1462594b | 1103 | if (!(m.status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) && |
ed7290d0 | 1104 | !no_way_out) |
b79109c3 AK |
1105 | continue; |
1106 | ||
1107 | /* | |
1108 | * Set taint even when machine check was not enabled. | |
1109 | */ | |
373d4d09 | 1110 | add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); |
b79109c3 | 1111 | |
e3480271 | 1112 | severity = mce_severity(&m, cfg->tolerant, NULL, true); |
b79109c3 | 1113 | |
ed7290d0 | 1114 | /* |
e3480271 CY |
1115 | * When machine check was for corrected/deferred handler don't |
1116 | * touch, unless we're panicing. | |
ed7290d0 | 1117 | */ |
e3480271 CY |
1118 | if ((severity == MCE_KEEP_SEVERITY || |
1119 | severity == MCE_UCNA_SEVERITY) && !no_way_out) | |
ed7290d0 AK |
1120 | continue; |
1121 | __set_bit(i, toclear); | |
1122 | if (severity == MCE_NO_SEVERITY) { | |
b79109c3 AK |
1123 | /* |
1124 | * Machine check event was not enabled. Clear, but | |
1125 | * ignore. | |
1126 | */ | |
1127 | continue; | |
1da177e4 LT |
1128 | } |
1129 | ||
85f92694 | 1130 | mce_read_aux(&m, i); |
1da177e4 | 1131 | |
9b1beaf2 AK |
1132 | /* |
1133 | * Action optional error. Queue address for later processing. | |
1134 | * When the ring overflows we just ignore the AO error. | |
1135 | * RED-PEN add some logging mechanism when | |
1136 | * usable_address or mce_add_ring fails. | |
d203f0b8 | 1137 | * RED-PEN don't ignore overflow for mca_cfg.tolerant == 0 |
9b1beaf2 AK |
1138 | */ |
1139 | if (severity == MCE_AO_SEVERITY && mce_usable_address(&m)) | |
1140 | mce_ring_add(m.addr >> PAGE_SHIFT); | |
1141 | ||
b79109c3 | 1142 | mce_log(&m); |
1da177e4 | 1143 | |
3c079792 AK |
1144 | if (severity > worst) { |
1145 | *final = m; | |
1146 | worst = severity; | |
1da177e4 | 1147 | } |
1da177e4 LT |
1148 | } |
1149 | ||
a8c321fb TL |
1150 | /* mce_clear_state will clear *final, save locally for use later */ |
1151 | m = *final; | |
1152 | ||
3c079792 AK |
1153 | if (!no_way_out) |
1154 | mce_clear_state(toclear); | |
1155 | ||
e9eee03e | 1156 | /* |
3c079792 AK |
1157 | * Do most of the synchronization with other CPUs. |
1158 | * When there's any problem use only local no_way_out state. | |
e9eee03e | 1159 | */ |
3c079792 AK |
1160 | if (mce_end(order) < 0) |
1161 | no_way_out = worst >= MCE_PANIC_SEVERITY; | |
bd78432c TH |
1162 | |
1163 | /* | |
a8c321fb TL |
1164 | * At insane "tolerant" levels we take no action. Otherwise |
1165 | * we only die if we have no other choice. For less serious | |
1166 | * issues we try to recover, or limit damage to the current | |
1167 | * process. | |
bd78432c | 1168 | */ |
1462594b | 1169 | if (cfg->tolerant < 3) { |
a8c321fb TL |
1170 | if (no_way_out) |
1171 | mce_panic("Fatal machine check on current CPU", &m, msg); | |
1172 | if (worst == MCE_AR_SEVERITY) { | |
d4812e16 TL |
1173 | recover_paddr = m.addr; |
1174 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
1175 | flags |= MF_MUST_KILL; | |
a8c321fb TL |
1176 | } else if (kill_it) { |
1177 | force_sig(SIGBUS, current); | |
1178 | } | |
1179 | } | |
e02e68d3 | 1180 | |
3c079792 AK |
1181 | if (worst > 0) |
1182 | mce_report_event(regs); | |
5f8c1a54 | 1183 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 1184 | out: |
88921be3 | 1185 | sync_core(); |
d4812e16 TL |
1186 | |
1187 | if (recover_paddr == ~0ull) | |
1188 | goto done; | |
1189 | ||
1190 | pr_err("Uncorrected hardware memory error in user-access at %llx", | |
1191 | recover_paddr); | |
1192 | /* | |
1193 | * We must call memory_failure() here even if the current process is | |
1194 | * doomed. We still need to mark the page as poisoned and alert any | |
1195 | * other users of the page. | |
1196 | */ | |
1197 | ist_begin_non_atomic(regs); | |
1198 | local_irq_enable(); | |
1199 | if (memory_failure(recover_paddr >> PAGE_SHIFT, MCE_VECTOR, flags) < 0) { | |
1200 | pr_err("Memory error not recovered"); | |
1201 | force_sig(SIGBUS, current); | |
1202 | } | |
1203 | local_irq_disable(); | |
1204 | ist_end_non_atomic(); | |
1205 | done: | |
95927475 | 1206 | ist_exit(regs, prev_state); |
1da177e4 | 1207 | } |
ea149b36 | 1208 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 1209 | |
cd42f4a3 TL |
1210 | #ifndef CONFIG_MEMORY_FAILURE |
1211 | int memory_failure(unsigned long pfn, int vector, int flags) | |
9b1beaf2 | 1212 | { |
a8c321fb TL |
1213 | /* mce_severity() should not hand us an ACTION_REQUIRED error */ |
1214 | BUG_ON(flags & MF_ACTION_REQUIRED); | |
c767a54b JP |
1215 | pr_err("Uncorrected memory error in page 0x%lx ignored\n" |
1216 | "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", | |
1217 | pfn); | |
cd42f4a3 TL |
1218 | |
1219 | return 0; | |
9b1beaf2 | 1220 | } |
cd42f4a3 | 1221 | #endif |
9b1beaf2 | 1222 | |
a8c321fb TL |
1223 | /* |
1224 | * Action optional processing happens here (picking up | |
1225 | * from the list of faulting pages that do_machine_check() | |
1226 | * placed into the "ring"). | |
1227 | */ | |
9b1beaf2 AK |
1228 | static void mce_process_work(struct work_struct *dummy) |
1229 | { | |
a8c321fb TL |
1230 | unsigned long pfn; |
1231 | ||
1232 | while (mce_ring_get(&pfn)) | |
1233 | memory_failure(pfn, MCE_VECTOR, 0); | |
9b1beaf2 AK |
1234 | } |
1235 | ||
15d5f839 DZ |
1236 | #ifdef CONFIG_X86_MCE_INTEL |
1237 | /*** | |
1238 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 1239 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
1240 | * @status: Event status information |
1241 | * | |
1242 | * This function should be called by the thermal interrupt after the | |
1243 | * event has been processed and the decision was made to log the event | |
1244 | * further. | |
1245 | * | |
1246 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
1247 | * and historically has been the register value of the | |
1248 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
1249 | */ | |
b5f2fa4e | 1250 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
1251 | { |
1252 | struct mce m; | |
1253 | ||
b5f2fa4e | 1254 | mce_setup(&m); |
15d5f839 DZ |
1255 | m.bank = MCE_THERMAL_BANK; |
1256 | m.status = status; | |
15d5f839 DZ |
1257 | mce_log(&m); |
1258 | } | |
1259 | #endif /* CONFIG_X86_MCE_INTEL */ | |
1260 | ||
1da177e4 | 1261 | /* |
8a336b0a TH |
1262 | * Periodic polling timer for "silent" machine check errors. If the |
1263 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
1264 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 1265 | */ |
3f2f0680 | 1266 | static unsigned long check_interval = INITIAL_CHECK_INTERVAL; |
e9eee03e | 1267 | |
82f7af09 | 1268 | static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */ |
52d168e2 | 1269 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 1270 | |
55babd8f CG |
1271 | static unsigned long mce_adjust_timer_default(unsigned long interval) |
1272 | { | |
1273 | return interval; | |
1274 | } | |
1275 | ||
3f2f0680 | 1276 | static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default; |
55babd8f | 1277 | |
3f2f0680 | 1278 | static void __restart_timer(struct timer_list *t, unsigned long interval) |
27f6c573 | 1279 | { |
3f2f0680 BP |
1280 | unsigned long when = jiffies + interval; |
1281 | unsigned long flags; | |
27f6c573 | 1282 | |
3f2f0680 BP |
1283 | local_irq_save(flags); |
1284 | ||
1285 | if (timer_pending(t)) { | |
1286 | if (time_before(when, t->expires)) | |
1287 | mod_timer_pinned(t, when); | |
1288 | } else { | |
1289 | t->expires = round_jiffies(when); | |
1290 | add_timer_on(t, smp_processor_id()); | |
1291 | } | |
1292 | ||
1293 | local_irq_restore(flags); | |
27f6c573 CG |
1294 | } |
1295 | ||
82f7af09 | 1296 | static void mce_timer_fn(unsigned long data) |
1da177e4 | 1297 | { |
89cbc767 | 1298 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
3f2f0680 | 1299 | int cpu = smp_processor_id(); |
82f7af09 | 1300 | unsigned long iv; |
52d168e2 | 1301 | |
3f2f0680 BP |
1302 | WARN_ON(cpu != data); |
1303 | ||
1304 | iv = __this_cpu_read(mce_next_interval); | |
52d168e2 | 1305 | |
89cbc767 | 1306 | if (mce_available(this_cpu_ptr(&cpu_info))) { |
3f2f0680 BP |
1307 | machine_check_poll(MCP_TIMESTAMP, this_cpu_ptr(&mce_poll_banks)); |
1308 | ||
1309 | if (mce_intel_cmci_poll()) { | |
1310 | iv = mce_adjust_timer(iv); | |
1311 | goto done; | |
1312 | } | |
e9eee03e | 1313 | } |
1da177e4 LT |
1314 | |
1315 | /* | |
3f2f0680 BP |
1316 | * Alert userspace if needed. If we logged an MCE, reduce the polling |
1317 | * interval, otherwise increase the polling interval. | |
1da177e4 | 1318 | */ |
3f2f0680 | 1319 | if (mce_notify_irq()) |
958fb3c5 | 1320 | iv = max(iv / 2, (unsigned long) HZ/100); |
3f2f0680 | 1321 | else |
82f7af09 | 1322 | iv = min(iv * 2, round_jiffies_relative(check_interval * HZ)); |
3f2f0680 BP |
1323 | |
1324 | done: | |
82f7af09 | 1325 | __this_cpu_write(mce_next_interval, iv); |
3f2f0680 | 1326 | __restart_timer(t, iv); |
55babd8f | 1327 | } |
e02e68d3 | 1328 | |
55babd8f CG |
1329 | /* |
1330 | * Ensure that the timer is firing in @interval from now. | |
1331 | */ | |
1332 | void mce_timer_kick(unsigned long interval) | |
1333 | { | |
89cbc767 | 1334 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
55babd8f CG |
1335 | unsigned long iv = __this_cpu_read(mce_next_interval); |
1336 | ||
3f2f0680 BP |
1337 | __restart_timer(t, interval); |
1338 | ||
55babd8f CG |
1339 | if (interval < iv) |
1340 | __this_cpu_write(mce_next_interval, interval); | |
e02e68d3 TH |
1341 | } |
1342 | ||
9aaef96f HS |
1343 | /* Must not be called in IRQ context where del_timer_sync() can deadlock */ |
1344 | static void mce_timer_delete_all(void) | |
1345 | { | |
1346 | int cpu; | |
1347 | ||
1348 | for_each_online_cpu(cpu) | |
1349 | del_timer_sync(&per_cpu(mce_timer, cpu)); | |
1350 | } | |
1351 | ||
9bd98405 AK |
1352 | static void mce_do_trigger(struct work_struct *work) |
1353 | { | |
1020bcbc | 1354 | call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT); |
9bd98405 AK |
1355 | } |
1356 | ||
1357 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
1358 | ||
e02e68d3 | 1359 | /* |
9bd98405 AK |
1360 | * Notify the user(s) about new machine check events. |
1361 | * Can be called from interrupt context, but not from machine check/NMI | |
1362 | * context. | |
e02e68d3 | 1363 | */ |
9ff36ee9 | 1364 | int mce_notify_irq(void) |
e02e68d3 | 1365 | { |
8457c84d AK |
1366 | /* Not more than two messages every minute */ |
1367 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
1368 | ||
1020bcbc | 1369 | if (test_and_clear_bit(0, &mce_need_notify)) { |
93b62c3c HS |
1370 | /* wake processes polling /dev/mcelog */ |
1371 | wake_up_interruptible(&mce_chrdev_wait); | |
9bd98405 | 1372 | |
4d899be5 | 1373 | if (mce_helper[0]) |
9bd98405 | 1374 | schedule_work(&mce_trigger_work); |
e02e68d3 | 1375 | |
8457c84d | 1376 | if (__ratelimit(&ratelimit)) |
a2d7b0d4 | 1377 | pr_info(HW_ERR "Machine check events logged\n"); |
e02e68d3 TH |
1378 | |
1379 | return 1; | |
1da177e4 | 1380 | } |
e02e68d3 TH |
1381 | return 0; |
1382 | } | |
9ff36ee9 | 1383 | EXPORT_SYMBOL_GPL(mce_notify_irq); |
8a336b0a | 1384 | |
148f9bb8 | 1385 | static int __mcheck_cpu_mce_banks_init(void) |
cebe1820 AK |
1386 | { |
1387 | int i; | |
d203f0b8 | 1388 | u8 num_banks = mca_cfg.banks; |
cebe1820 | 1389 | |
d203f0b8 | 1390 | mce_banks = kzalloc(num_banks * sizeof(struct mce_bank), GFP_KERNEL); |
cebe1820 AK |
1391 | if (!mce_banks) |
1392 | return -ENOMEM; | |
d203f0b8 BP |
1393 | |
1394 | for (i = 0; i < num_banks; i++) { | |
cebe1820 | 1395 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1396 | |
cebe1820 AK |
1397 | b->ctl = -1ULL; |
1398 | b->init = 1; | |
1399 | } | |
1400 | return 0; | |
1401 | } | |
1402 | ||
d88203d1 | 1403 | /* |
1da177e4 LT |
1404 | * Initialize Machine Checks for a CPU. |
1405 | */ | |
148f9bb8 | 1406 | static int __mcheck_cpu_cap_init(void) |
1da177e4 | 1407 | { |
0d7482e3 | 1408 | unsigned b; |
e9eee03e | 1409 | u64 cap; |
1da177e4 LT |
1410 | |
1411 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
1412 | |
1413 | b = cap & MCG_BANKCNT_MASK; | |
d203f0b8 | 1414 | if (!mca_cfg.banks) |
c767a54b | 1415 | pr_info("CPU supports %d MCE banks\n", b); |
b659294b | 1416 | |
0d7482e3 | 1417 | if (b > MAX_NR_BANKS) { |
c767a54b | 1418 | pr_warn("Using only %u machine check banks out of %u\n", |
0d7482e3 AK |
1419 | MAX_NR_BANKS, b); |
1420 | b = MAX_NR_BANKS; | |
1421 | } | |
1422 | ||
1423 | /* Don't support asymmetric configurations today */ | |
d203f0b8 BP |
1424 | WARN_ON(mca_cfg.banks != 0 && b != mca_cfg.banks); |
1425 | mca_cfg.banks = b; | |
1426 | ||
cebe1820 | 1427 | if (!mce_banks) { |
cffd377e | 1428 | int err = __mcheck_cpu_mce_banks_init(); |
11868a2d | 1429 | |
cebe1820 AK |
1430 | if (err) |
1431 | return err; | |
1da177e4 | 1432 | } |
0d7482e3 | 1433 | |
94ad8474 | 1434 | /* Use accurate RIP reporting if available. */ |
01c6680a | 1435 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
84c2559d | 1436 | mca_cfg.rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 1437 | |
ed7290d0 | 1438 | if (cap & MCG_SER_P) |
1462594b | 1439 | mca_cfg.ser = true; |
ed7290d0 | 1440 | |
0d7482e3 AK |
1441 | return 0; |
1442 | } | |
1443 | ||
5e09954a | 1444 | static void __mcheck_cpu_init_generic(void) |
0d7482e3 | 1445 | { |
84c2559d | 1446 | enum mcp_flags m_fl = 0; |
e9eee03e | 1447 | mce_banks_t all_banks; |
0d7482e3 AK |
1448 | u64 cap; |
1449 | int i; | |
1450 | ||
84c2559d BP |
1451 | if (!mca_cfg.bootlog) |
1452 | m_fl = MCP_DONTLOG; | |
1453 | ||
b79109c3 AK |
1454 | /* |
1455 | * Log the machine checks left over from the previous reset. | |
1456 | */ | |
ee031c31 | 1457 | bitmap_fill(all_banks, MAX_NR_BANKS); |
84c2559d | 1458 | machine_check_poll(MCP_UC | m_fl, &all_banks); |
1da177e4 LT |
1459 | |
1460 | set_in_cr4(X86_CR4_MCE); | |
1461 | ||
0d7482e3 | 1462 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
1463 | if (cap & MCG_CTL_P) |
1464 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
1465 | ||
d203f0b8 | 1466 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 1467 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1468 | |
cebe1820 | 1469 | if (!b->init) |
06b7a7a5 | 1470 | continue; |
a2d32bcb AK |
1471 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
1472 | wrmsrl(MSR_IA32_MCx_STATUS(i), 0); | |
d88203d1 | 1473 | } |
1da177e4 LT |
1474 | } |
1475 | ||
61b0fccd TL |
1476 | /* |
1477 | * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and | |
1478 | * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM | |
1479 | * Vol 3B Table 15-20). But this confuses both the code that determines | |
1480 | * whether the machine check occurred in kernel or user mode, and also | |
1481 | * the severity assessment code. Pretend that EIPV was set, and take the | |
1482 | * ip/cs values from the pt_regs that mce_gather_info() ignored earlier. | |
1483 | */ | |
1484 | static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs) | |
1485 | { | |
1486 | if (bank != 0) | |
1487 | return; | |
1488 | if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0) | |
1489 | return; | |
1490 | if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC| | |
1491 | MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV| | |
1492 | MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR| | |
1493 | MCACOD)) != | |
1494 | (MCI_STATUS_UC|MCI_STATUS_EN| | |
1495 | MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S| | |
1496 | MCI_STATUS_AR|MCACOD_INSTR)) | |
1497 | return; | |
1498 | ||
1499 | m->mcgstatus |= MCG_STATUS_EIPV; | |
1500 | m->ip = regs->ip; | |
1501 | m->cs = regs->cs; | |
1502 | } | |
1503 | ||
1da177e4 | 1504 | /* Add per CPU specific workarounds here */ |
148f9bb8 | 1505 | static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 1506 | { |
d203f0b8 BP |
1507 | struct mca_config *cfg = &mca_cfg; |
1508 | ||
e412cd25 | 1509 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { |
c767a54b | 1510 | pr_info("unknown CPU type - not enabling MCE support\n"); |
e412cd25 IM |
1511 | return -EOPNOTSUPP; |
1512 | } | |
1513 | ||
1da177e4 | 1514 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 1515 | if (c->x86_vendor == X86_VENDOR_AMD) { |
d203f0b8 | 1516 | if (c->x86 == 15 && cfg->banks > 4) { |
e9eee03e IM |
1517 | /* |
1518 | * disable GART TBL walk error reporting, which | |
1519 | * trips off incorrectly with the IOMMU & 3ware | |
1520 | * & Cerberus: | |
1521 | */ | |
cebe1820 | 1522 | clear_bit(10, (unsigned long *)&mce_banks[4].ctl); |
e9eee03e | 1523 | } |
84c2559d | 1524 | if (c->x86 <= 17 && cfg->bootlog < 0) { |
e9eee03e IM |
1525 | /* |
1526 | * Lots of broken BIOS around that don't clear them | |
1527 | * by default and leave crap in there. Don't log: | |
1528 | */ | |
84c2559d | 1529 | cfg->bootlog = 0; |
e9eee03e | 1530 | } |
2e6f694f AK |
1531 | /* |
1532 | * Various K7s with broken bank 0 around. Always disable | |
1533 | * by default. | |
1534 | */ | |
c9ce8712 | 1535 | if (c->x86 == 6 && cfg->banks > 0) |
cebe1820 | 1536 | mce_banks[0].ctl = 0; |
575203b4 | 1537 | |
bf80bbd7 AG |
1538 | /* |
1539 | * overflow_recov is supported for F15h Models 00h-0fh | |
1540 | * even though we don't have a CPUID bit for it. | |
1541 | */ | |
1542 | if (c->x86 == 0x15 && c->x86_model <= 0xf) | |
1543 | mce_flags.overflow_recov = 1; | |
1544 | ||
c9ce8712 BP |
1545 | /* |
1546 | * Turn off MC4_MISC thresholding banks on those models since | |
1547 | * they're not supported there. | |
1548 | */ | |
1549 | if (c->x86 == 0x15 && | |
1550 | (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) { | |
1551 | int i; | |
1552 | u64 hwcr; | |
1553 | bool need_toggle; | |
1554 | u32 msrs[] = { | |
575203b4 BP |
1555 | 0x00000413, /* MC4_MISC0 */ |
1556 | 0xc0000408, /* MC4_MISC1 */ | |
c9ce8712 | 1557 | }; |
575203b4 | 1558 | |
c9ce8712 | 1559 | rdmsrl(MSR_K7_HWCR, hwcr); |
575203b4 | 1560 | |
c9ce8712 BP |
1561 | /* McStatusWrEn has to be set */ |
1562 | need_toggle = !(hwcr & BIT(18)); | |
575203b4 | 1563 | |
c9ce8712 BP |
1564 | if (need_toggle) |
1565 | wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); | |
575203b4 | 1566 | |
c9ce8712 BP |
1567 | /* Clear CntP bit safely */ |
1568 | for (i = 0; i < ARRAY_SIZE(msrs); i++) | |
1569 | msr_clear_bit(msrs[i], 62); | |
575203b4 | 1570 | |
c9ce8712 BP |
1571 | /* restore old settings */ |
1572 | if (need_toggle) | |
1573 | wrmsrl(MSR_K7_HWCR, hwcr); | |
1574 | } | |
1da177e4 | 1575 | } |
e583538f | 1576 | |
06b7a7a5 AK |
1577 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
1578 | /* | |
1579 | * SDM documents that on family 6 bank 0 should not be written | |
1580 | * because it aliases to another special BIOS controlled | |
1581 | * register. | |
1582 | * But it's not aliased anymore on model 0x1a+ | |
1583 | * Don't ignore bank 0 completely because there could be a | |
1584 | * valid event later, merely don't write CTL0. | |
1585 | */ | |
1586 | ||
d203f0b8 | 1587 | if (c->x86 == 6 && c->x86_model < 0x1A && cfg->banks > 0) |
cebe1820 | 1588 | mce_banks[0].init = 0; |
3c079792 AK |
1589 | |
1590 | /* | |
1591 | * All newer Intel systems support MCE broadcasting. Enable | |
1592 | * synchronization with a one second timeout. | |
1593 | */ | |
1594 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && | |
84c2559d BP |
1595 | cfg->monarch_timeout < 0) |
1596 | cfg->monarch_timeout = USEC_PER_SEC; | |
c7f6fa44 | 1597 | |
e412cd25 IM |
1598 | /* |
1599 | * There are also broken BIOSes on some Pentium M and | |
1600 | * earlier systems: | |
1601 | */ | |
84c2559d BP |
1602 | if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0) |
1603 | cfg->bootlog = 0; | |
61b0fccd TL |
1604 | |
1605 | if (c->x86 == 6 && c->x86_model == 45) | |
1606 | quirk_no_way_out = quirk_sandybridge_ifu; | |
06b7a7a5 | 1607 | } |
84c2559d BP |
1608 | if (cfg->monarch_timeout < 0) |
1609 | cfg->monarch_timeout = 0; | |
1610 | if (cfg->bootlog != 0) | |
7af19e4a | 1611 | cfg->panic_timeout = 30; |
e412cd25 IM |
1612 | |
1613 | return 0; | |
d88203d1 | 1614 | } |
1da177e4 | 1615 | |
148f9bb8 | 1616 | static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) |
4efc0670 AK |
1617 | { |
1618 | if (c->x86 != 5) | |
3a97fc34 HS |
1619 | return 0; |
1620 | ||
4efc0670 AK |
1621 | switch (c->x86_vendor) { |
1622 | case X86_VENDOR_INTEL: | |
c6978369 | 1623 | intel_p5_mcheck_init(c); |
3a97fc34 | 1624 | return 1; |
4efc0670 AK |
1625 | break; |
1626 | case X86_VENDOR_CENTAUR: | |
1627 | winchip_mcheck_init(c); | |
3a97fc34 | 1628 | return 1; |
4efc0670 AK |
1629 | break; |
1630 | } | |
3a97fc34 HS |
1631 | |
1632 | return 0; | |
4efc0670 AK |
1633 | } |
1634 | ||
5e09954a | 1635 | static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
1636 | { |
1637 | switch (c->x86_vendor) { | |
1638 | case X86_VENDOR_INTEL: | |
1639 | mce_intel_feature_init(c); | |
3f2f0680 | 1640 | mce_adjust_timer = cmci_intel_adjust_timer; |
1da177e4 | 1641 | break; |
89b831ef JS |
1642 | case X86_VENDOR_AMD: |
1643 | mce_amd_feature_init(c); | |
bf80bbd7 | 1644 | mce_flags.overflow_recov = cpuid_ebx(0x80000007) & 0x1; |
89b831ef | 1645 | break; |
1da177e4 LT |
1646 | default: |
1647 | break; | |
1648 | } | |
1649 | } | |
1650 | ||
26c3c283 | 1651 | static void mce_start_timer(unsigned int cpu, struct timer_list *t) |
52d168e2 | 1652 | { |
4f75d841 | 1653 | unsigned long iv = check_interval * HZ; |
bc09effa | 1654 | |
7af19e4a | 1655 | if (mca_cfg.ignore_ce || !iv) |
62fdac59 HS |
1656 | return; |
1657 | ||
4f75d841 BP |
1658 | per_cpu(mce_next_interval, cpu) = iv; |
1659 | ||
82f7af09 | 1660 | t->expires = round_jiffies(jiffies + iv); |
4f75d841 | 1661 | add_timer_on(t, cpu); |
52d168e2 AK |
1662 | } |
1663 | ||
26c3c283 TG |
1664 | static void __mcheck_cpu_init_timer(void) |
1665 | { | |
89cbc767 | 1666 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
26c3c283 TG |
1667 | unsigned int cpu = smp_processor_id(); |
1668 | ||
1669 | setup_timer(t, mce_timer_fn, cpu); | |
1670 | mce_start_timer(cpu, t); | |
1671 | } | |
1672 | ||
9eda8cb3 AK |
1673 | /* Handle unconfigured int18 (should never happen) */ |
1674 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
1675 | { | |
c767a54b | 1676 | pr_err("CPU#%d: Unexpected int18 (Machine Check)\n", |
9eda8cb3 AK |
1677 | smp_processor_id()); |
1678 | } | |
1679 | ||
1680 | /* Call the installed machine check handler for this CPU setup. */ | |
1681 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
1682 | unexpected_machine_check; | |
1683 | ||
d88203d1 | 1684 | /* |
1da177e4 | 1685 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 1686 | * Must be called with preempt off: |
1da177e4 | 1687 | */ |
148f9bb8 | 1688 | void mcheck_cpu_init(struct cpuinfo_x86 *c) |
1da177e4 | 1689 | { |
1462594b | 1690 | if (mca_cfg.disabled) |
4efc0670 AK |
1691 | return; |
1692 | ||
3a97fc34 HS |
1693 | if (__mcheck_cpu_ancient_init(c)) |
1694 | return; | |
4efc0670 | 1695 | |
5b4408fd | 1696 | if (!mce_available(c)) |
1da177e4 LT |
1697 | return; |
1698 | ||
5e09954a | 1699 | if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) { |
1462594b | 1700 | mca_cfg.disabled = true; |
0d7482e3 AK |
1701 | return; |
1702 | } | |
0d7482e3 | 1703 | |
5d727926 AK |
1704 | machine_check_vector = do_machine_check; |
1705 | ||
5e09954a BP |
1706 | __mcheck_cpu_init_generic(); |
1707 | __mcheck_cpu_init_vendor(c); | |
1708 | __mcheck_cpu_init_timer(); | |
89cbc767 CL |
1709 | INIT_WORK(this_cpu_ptr(&mce_work), mce_process_work); |
1710 | init_irq_work(this_cpu_ptr(&mce_irq_work), &mce_irq_work_cb); | |
1da177e4 LT |
1711 | } |
1712 | ||
1713 | /* | |
93b62c3c | 1714 | * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log. |
1da177e4 LT |
1715 | */ |
1716 | ||
93b62c3c HS |
1717 | static DEFINE_SPINLOCK(mce_chrdev_state_lock); |
1718 | static int mce_chrdev_open_count; /* #times opened */ | |
1719 | static int mce_chrdev_open_exclu; /* already open exclusive? */ | |
f528e7ba | 1720 | |
93b62c3c | 1721 | static int mce_chrdev_open(struct inode *inode, struct file *file) |
f528e7ba | 1722 | { |
93b62c3c | 1723 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1724 | |
93b62c3c HS |
1725 | if (mce_chrdev_open_exclu || |
1726 | (mce_chrdev_open_count && (file->f_flags & O_EXCL))) { | |
1727 | spin_unlock(&mce_chrdev_state_lock); | |
e9eee03e | 1728 | |
f528e7ba TH |
1729 | return -EBUSY; |
1730 | } | |
1731 | ||
1732 | if (file->f_flags & O_EXCL) | |
93b62c3c HS |
1733 | mce_chrdev_open_exclu = 1; |
1734 | mce_chrdev_open_count++; | |
f528e7ba | 1735 | |
93b62c3c | 1736 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba | 1737 | |
bd78432c | 1738 | return nonseekable_open(inode, file); |
f528e7ba TH |
1739 | } |
1740 | ||
93b62c3c | 1741 | static int mce_chrdev_release(struct inode *inode, struct file *file) |
f528e7ba | 1742 | { |
93b62c3c | 1743 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1744 | |
93b62c3c HS |
1745 | mce_chrdev_open_count--; |
1746 | mce_chrdev_open_exclu = 0; | |
f528e7ba | 1747 | |
93b62c3c | 1748 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba TH |
1749 | |
1750 | return 0; | |
1751 | } | |
1752 | ||
d88203d1 TG |
1753 | static void collect_tscs(void *data) |
1754 | { | |
1da177e4 | 1755 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 1756 | |
1da177e4 | 1757 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 1758 | } |
1da177e4 | 1759 | |
482908b4 HY |
1760 | static int mce_apei_read_done; |
1761 | ||
1762 | /* Collect MCE record of previous boot in persistent storage via APEI ERST. */ | |
1763 | static int __mce_read_apei(char __user **ubuf, size_t usize) | |
1764 | { | |
1765 | int rc; | |
1766 | u64 record_id; | |
1767 | struct mce m; | |
1768 | ||
1769 | if (usize < sizeof(struct mce)) | |
1770 | return -EINVAL; | |
1771 | ||
1772 | rc = apei_read_mce(&m, &record_id); | |
1773 | /* Error or no more MCE record */ | |
1774 | if (rc <= 0) { | |
1775 | mce_apei_read_done = 1; | |
fadd85f1 NH |
1776 | /* |
1777 | * When ERST is disabled, mce_chrdev_read() should return | |
1778 | * "no record" instead of "no device." | |
1779 | */ | |
1780 | if (rc == -ENODEV) | |
1781 | return 0; | |
482908b4 HY |
1782 | return rc; |
1783 | } | |
1784 | rc = -EFAULT; | |
1785 | if (copy_to_user(*ubuf, &m, sizeof(struct mce))) | |
1786 | return rc; | |
1787 | /* | |
1788 | * In fact, we should have cleared the record after that has | |
1789 | * been flushed to the disk or sent to network in | |
1790 | * /sbin/mcelog, but we have no interface to support that now, | |
1791 | * so just clear it to avoid duplication. | |
1792 | */ | |
1793 | rc = apei_clear_mce(record_id); | |
1794 | if (rc) { | |
1795 | mce_apei_read_done = 1; | |
1796 | return rc; | |
1797 | } | |
1798 | *ubuf += sizeof(struct mce); | |
1799 | ||
1800 | return 0; | |
1801 | } | |
1802 | ||
93b62c3c HS |
1803 | static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf, |
1804 | size_t usize, loff_t *off) | |
1da177e4 | 1805 | { |
e9eee03e | 1806 | char __user *buf = ubuf; |
f0de53bb | 1807 | unsigned long *cpu_tsc; |
ef41df43 | 1808 | unsigned prev, next; |
1da177e4 LT |
1809 | int i, err; |
1810 | ||
6bca67f9 | 1811 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
1812 | if (!cpu_tsc) |
1813 | return -ENOMEM; | |
1814 | ||
93b62c3c | 1815 | mutex_lock(&mce_chrdev_read_mutex); |
482908b4 HY |
1816 | |
1817 | if (!mce_apei_read_done) { | |
1818 | err = __mce_read_apei(&buf, usize); | |
1819 | if (err || buf != ubuf) | |
1820 | goto out; | |
1821 | } | |
1822 | ||
f56e8a07 | 1823 | next = rcu_dereference_check_mce(mcelog.next); |
1da177e4 LT |
1824 | |
1825 | /* Only supports full reads right now */ | |
482908b4 HY |
1826 | err = -EINVAL; |
1827 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) | |
1828 | goto out; | |
1da177e4 LT |
1829 | |
1830 | err = 0; | |
ef41df43 HY |
1831 | prev = 0; |
1832 | do { | |
1833 | for (i = prev; i < next; i++) { | |
1834 | unsigned long start = jiffies; | |
559faa6b | 1835 | struct mce *m = &mcelog.entry[i]; |
ef41df43 | 1836 | |
559faa6b | 1837 | while (!m->finished) { |
ef41df43 | 1838 | if (time_after_eq(jiffies, start + 2)) { |
559faa6b | 1839 | memset(m, 0, sizeof(*m)); |
ef41df43 HY |
1840 | goto timeout; |
1841 | } | |
1842 | cpu_relax(); | |
673242c1 | 1843 | } |
ef41df43 | 1844 | smp_rmb(); |
559faa6b HS |
1845 | err |= copy_to_user(buf, m, sizeof(*m)); |
1846 | buf += sizeof(*m); | |
ef41df43 HY |
1847 | timeout: |
1848 | ; | |
673242c1 | 1849 | } |
1da177e4 | 1850 | |
ef41df43 HY |
1851 | memset(mcelog.entry + prev, 0, |
1852 | (next - prev) * sizeof(struct mce)); | |
1853 | prev = next; | |
1854 | next = cmpxchg(&mcelog.next, prev, 0); | |
1855 | } while (next != prev); | |
1da177e4 | 1856 | |
b2b18660 | 1857 | synchronize_sched(); |
1da177e4 | 1858 | |
d88203d1 TG |
1859 | /* |
1860 | * Collect entries that were still getting written before the | |
1861 | * synchronize. | |
1862 | */ | |
15c8b6c1 | 1863 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 1864 | |
d88203d1 | 1865 | for (i = next; i < MCE_LOG_LEN; i++) { |
559faa6b HS |
1866 | struct mce *m = &mcelog.entry[i]; |
1867 | ||
1868 | if (m->finished && m->tsc < cpu_tsc[m->cpu]) { | |
1869 | err |= copy_to_user(buf, m, sizeof(*m)); | |
1da177e4 | 1870 | smp_rmb(); |
559faa6b HS |
1871 | buf += sizeof(*m); |
1872 | memset(m, 0, sizeof(*m)); | |
1da177e4 | 1873 | } |
d88203d1 | 1874 | } |
482908b4 HY |
1875 | |
1876 | if (err) | |
1877 | err = -EFAULT; | |
1878 | ||
1879 | out: | |
93b62c3c | 1880 | mutex_unlock(&mce_chrdev_read_mutex); |
f0de53bb | 1881 | kfree(cpu_tsc); |
e9eee03e | 1882 | |
482908b4 | 1883 | return err ? err : buf - ubuf; |
1da177e4 LT |
1884 | } |
1885 | ||
93b62c3c | 1886 | static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait) |
e02e68d3 | 1887 | { |
93b62c3c | 1888 | poll_wait(file, &mce_chrdev_wait, wait); |
a4dd9925 | 1889 | if (rcu_access_index(mcelog.next)) |
e02e68d3 | 1890 | return POLLIN | POLLRDNORM; |
482908b4 HY |
1891 | if (!mce_apei_read_done && apei_check_mce()) |
1892 | return POLLIN | POLLRDNORM; | |
e02e68d3 TH |
1893 | return 0; |
1894 | } | |
1895 | ||
93b62c3c HS |
1896 | static long mce_chrdev_ioctl(struct file *f, unsigned int cmd, |
1897 | unsigned long arg) | |
1da177e4 LT |
1898 | { |
1899 | int __user *p = (int __user *)arg; | |
d88203d1 | 1900 | |
1da177e4 | 1901 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 1902 | return -EPERM; |
e9eee03e | 1903 | |
1da177e4 | 1904 | switch (cmd) { |
d88203d1 | 1905 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
1906 | return put_user(sizeof(struct mce), p); |
1907 | case MCE_GET_LOG_LEN: | |
d88203d1 | 1908 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
1909 | case MCE_GETCLEAR_FLAGS: { |
1910 | unsigned flags; | |
d88203d1 TG |
1911 | |
1912 | do { | |
1da177e4 | 1913 | flags = mcelog.flags; |
d88203d1 | 1914 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 1915 | |
d88203d1 | 1916 | return put_user(flags, p); |
1da177e4 LT |
1917 | } |
1918 | default: | |
d88203d1 TG |
1919 | return -ENOTTY; |
1920 | } | |
1da177e4 LT |
1921 | } |
1922 | ||
66f5ddf3 TL |
1923 | static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf, |
1924 | size_t usize, loff_t *off); | |
1925 | ||
1926 | void register_mce_write_callback(ssize_t (*fn)(struct file *filp, | |
1927 | const char __user *ubuf, | |
1928 | size_t usize, loff_t *off)) | |
1929 | { | |
1930 | mce_write = fn; | |
1931 | } | |
1932 | EXPORT_SYMBOL_GPL(register_mce_write_callback); | |
1933 | ||
1934 | ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf, | |
1935 | size_t usize, loff_t *off) | |
1936 | { | |
1937 | if (mce_write) | |
1938 | return mce_write(filp, ubuf, usize, off); | |
1939 | else | |
1940 | return -EINVAL; | |
1941 | } | |
1942 | ||
1943 | static const struct file_operations mce_chrdev_ops = { | |
93b62c3c HS |
1944 | .open = mce_chrdev_open, |
1945 | .release = mce_chrdev_release, | |
1946 | .read = mce_chrdev_read, | |
66f5ddf3 | 1947 | .write = mce_chrdev_write, |
93b62c3c HS |
1948 | .poll = mce_chrdev_poll, |
1949 | .unlocked_ioctl = mce_chrdev_ioctl, | |
1950 | .llseek = no_llseek, | |
1da177e4 LT |
1951 | }; |
1952 | ||
93b62c3c | 1953 | static struct miscdevice mce_chrdev_device = { |
1da177e4 LT |
1954 | MISC_MCELOG_MINOR, |
1955 | "mcelog", | |
1956 | &mce_chrdev_ops, | |
1957 | }; | |
1958 | ||
c3d1fb56 NR |
1959 | static void __mce_disable_bank(void *arg) |
1960 | { | |
1961 | int bank = *((int *)arg); | |
89cbc767 | 1962 | __clear_bit(bank, this_cpu_ptr(mce_poll_banks)); |
c3d1fb56 NR |
1963 | cmci_disable_bank(bank); |
1964 | } | |
1965 | ||
1966 | void mce_disable_bank(int bank) | |
1967 | { | |
1968 | if (bank >= mca_cfg.banks) { | |
1969 | pr_warn(FW_BUG | |
1970 | "Ignoring request to disable invalid MCA bank %d.\n", | |
1971 | bank); | |
1972 | return; | |
1973 | } | |
1974 | set_bit(bank, mce_banks_ce_disabled); | |
1975 | on_each_cpu(__mce_disable_bank, &bank, 1); | |
1976 | } | |
1977 | ||
13503fa9 | 1978 | /* |
62fdac59 HS |
1979 | * mce=off Disables machine check |
1980 | * mce=no_cmci Disables CMCI | |
1981 | * mce=dont_log_ce Clears corrected events silently, no log created for CEs. | |
1982 | * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. | |
3c079792 AK |
1983 | * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) |
1984 | * monarchtimeout is how long to wait for other CPUs on machine | |
1985 | * check, or 0 to not wait | |
13503fa9 HS |
1986 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. |
1987 | * mce=nobootlog Don't log MCEs from before booting. | |
450cc201 | 1988 | * mce=bios_cmci_threshold Don't program the CMCI threshold |
13503fa9 | 1989 | */ |
1da177e4 LT |
1990 | static int __init mcheck_enable(char *str) |
1991 | { | |
d203f0b8 BP |
1992 | struct mca_config *cfg = &mca_cfg; |
1993 | ||
e3346fc4 | 1994 | if (*str == 0) { |
4efc0670 | 1995 | enable_p5_mce(); |
e3346fc4 BZ |
1996 | return 1; |
1997 | } | |
4efc0670 AK |
1998 | if (*str == '=') |
1999 | str++; | |
1da177e4 | 2000 | if (!strcmp(str, "off")) |
1462594b | 2001 | cfg->disabled = true; |
62fdac59 | 2002 | else if (!strcmp(str, "no_cmci")) |
7af19e4a | 2003 | cfg->cmci_disabled = true; |
62fdac59 | 2004 | else if (!strcmp(str, "dont_log_ce")) |
d203f0b8 | 2005 | cfg->dont_log_ce = true; |
62fdac59 | 2006 | else if (!strcmp(str, "ignore_ce")) |
7af19e4a | 2007 | cfg->ignore_ce = true; |
13503fa9 | 2008 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
84c2559d | 2009 | cfg->bootlog = (str[0] == 'b'); |
450cc201 | 2010 | else if (!strcmp(str, "bios_cmci_threshold")) |
1462594b | 2011 | cfg->bios_cmci_threshold = true; |
3c079792 | 2012 | else if (isdigit(str[0])) { |
d203f0b8 | 2013 | get_option(&str, &(cfg->tolerant)); |
3c079792 AK |
2014 | if (*str == ',') { |
2015 | ++str; | |
84c2559d | 2016 | get_option(&str, &(cfg->monarch_timeout)); |
3c079792 AK |
2017 | } |
2018 | } else { | |
c767a54b | 2019 | pr_info("mce argument %s ignored. Please use /sys\n", str); |
13503fa9 HS |
2020 | return 0; |
2021 | } | |
9b41046c | 2022 | return 1; |
1da177e4 | 2023 | } |
4efc0670 | 2024 | __setup("mce", mcheck_enable); |
1da177e4 | 2025 | |
a2202aa2 | 2026 | int __init mcheck_init(void) |
b33a6363 | 2027 | { |
a2202aa2 YW |
2028 | mcheck_intel_therm_init(); |
2029 | ||
b33a6363 BP |
2030 | return 0; |
2031 | } | |
b33a6363 | 2032 | |
d88203d1 | 2033 | /* |
c7cece89 | 2034 | * mce_syscore: PM support |
d88203d1 | 2035 | */ |
1da177e4 | 2036 | |
973a2dd1 AK |
2037 | /* |
2038 | * Disable machine checks on suspend and shutdown. We can't really handle | |
2039 | * them later. | |
2040 | */ | |
5e09954a | 2041 | static int mce_disable_error_reporting(void) |
973a2dd1 AK |
2042 | { |
2043 | int i; | |
2044 | ||
d203f0b8 | 2045 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2046 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2047 | |
cebe1820 | 2048 | if (b->init) |
a2d32bcb | 2049 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 2050 | } |
973a2dd1 AK |
2051 | return 0; |
2052 | } | |
2053 | ||
c7cece89 | 2054 | static int mce_syscore_suspend(void) |
973a2dd1 | 2055 | { |
5e09954a | 2056 | return mce_disable_error_reporting(); |
973a2dd1 AK |
2057 | } |
2058 | ||
c7cece89 | 2059 | static void mce_syscore_shutdown(void) |
973a2dd1 | 2060 | { |
f3c6ea1b | 2061 | mce_disable_error_reporting(); |
973a2dd1 AK |
2062 | } |
2063 | ||
e9eee03e IM |
2064 | /* |
2065 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
2066 | * Only one CPU is active at this time, the others get re-added later using | |
2067 | * CPU hotplug: | |
2068 | */ | |
c7cece89 | 2069 | static void mce_syscore_resume(void) |
1da177e4 | 2070 | { |
5e09954a | 2071 | __mcheck_cpu_init_generic(); |
89cbc767 | 2072 | __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info)); |
1da177e4 LT |
2073 | } |
2074 | ||
f3c6ea1b | 2075 | static struct syscore_ops mce_syscore_ops = { |
c7cece89 HS |
2076 | .suspend = mce_syscore_suspend, |
2077 | .shutdown = mce_syscore_shutdown, | |
2078 | .resume = mce_syscore_resume, | |
f3c6ea1b RW |
2079 | }; |
2080 | ||
c7cece89 | 2081 | /* |
8a25a2fd | 2082 | * mce_device: Sysfs support |
c7cece89 HS |
2083 | */ |
2084 | ||
52d168e2 AK |
2085 | static void mce_cpu_restart(void *data) |
2086 | { | |
89cbc767 | 2087 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
33edbf02 | 2088 | return; |
5e09954a BP |
2089 | __mcheck_cpu_init_generic(); |
2090 | __mcheck_cpu_init_timer(); | |
52d168e2 AK |
2091 | } |
2092 | ||
1da177e4 | 2093 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
2094 | static void mce_restart(void) |
2095 | { | |
9aaef96f | 2096 | mce_timer_delete_all(); |
52d168e2 | 2097 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
2098 | } |
2099 | ||
9af43b54 | 2100 | /* Toggle features for corrected errors */ |
9aaef96f | 2101 | static void mce_disable_cmci(void *data) |
9af43b54 | 2102 | { |
89cbc767 | 2103 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
9af43b54 | 2104 | return; |
9af43b54 HS |
2105 | cmci_clear(); |
2106 | } | |
2107 | ||
2108 | static void mce_enable_ce(void *all) | |
2109 | { | |
89cbc767 | 2110 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
9af43b54 HS |
2111 | return; |
2112 | cmci_reenable(); | |
2113 | cmci_recheck(); | |
2114 | if (all) | |
5e09954a | 2115 | __mcheck_cpu_init_timer(); |
9af43b54 HS |
2116 | } |
2117 | ||
8a25a2fd | 2118 | static struct bus_type mce_subsys = { |
e9eee03e | 2119 | .name = "machinecheck", |
8a25a2fd | 2120 | .dev_name = "machinecheck", |
1da177e4 LT |
2121 | }; |
2122 | ||
d6126ef5 | 2123 | DEFINE_PER_CPU(struct device *, mce_device); |
e9eee03e | 2124 | |
e9eee03e | 2125 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); |
1da177e4 | 2126 | |
8a25a2fd | 2127 | static inline struct mce_bank *attr_to_bank(struct device_attribute *attr) |
cebe1820 AK |
2128 | { |
2129 | return container_of(attr, struct mce_bank, attr); | |
2130 | } | |
0d7482e3 | 2131 | |
8a25a2fd | 2132 | static ssize_t show_bank(struct device *s, struct device_attribute *attr, |
0d7482e3 AK |
2133 | char *buf) |
2134 | { | |
cebe1820 | 2135 | return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl); |
0d7482e3 AK |
2136 | } |
2137 | ||
8a25a2fd | 2138 | static ssize_t set_bank(struct device *s, struct device_attribute *attr, |
9319cec8 | 2139 | const char *buf, size_t size) |
0d7482e3 | 2140 | { |
9319cec8 | 2141 | u64 new; |
e9eee03e | 2142 | |
164109e3 | 2143 | if (kstrtou64(buf, 0, &new) < 0) |
0d7482e3 | 2144 | return -EINVAL; |
e9eee03e | 2145 | |
cebe1820 | 2146 | attr_to_bank(attr)->ctl = new; |
0d7482e3 | 2147 | mce_restart(); |
e9eee03e | 2148 | |
9319cec8 | 2149 | return size; |
0d7482e3 | 2150 | } |
a98f0dd3 | 2151 | |
e9eee03e | 2152 | static ssize_t |
8a25a2fd | 2153 | show_trigger(struct device *s, struct device_attribute *attr, char *buf) |
a98f0dd3 | 2154 | { |
1020bcbc | 2155 | strcpy(buf, mce_helper); |
a98f0dd3 | 2156 | strcat(buf, "\n"); |
1020bcbc | 2157 | return strlen(mce_helper) + 1; |
a98f0dd3 AK |
2158 | } |
2159 | ||
8a25a2fd | 2160 | static ssize_t set_trigger(struct device *s, struct device_attribute *attr, |
e9eee03e | 2161 | const char *buf, size_t siz) |
a98f0dd3 AK |
2162 | { |
2163 | char *p; | |
e9eee03e | 2164 | |
1020bcbc HS |
2165 | strncpy(mce_helper, buf, sizeof(mce_helper)); |
2166 | mce_helper[sizeof(mce_helper)-1] = 0; | |
1020bcbc | 2167 | p = strchr(mce_helper, '\n'); |
e9eee03e | 2168 | |
e9084ec9 | 2169 | if (p) |
e9eee03e IM |
2170 | *p = 0; |
2171 | ||
e9084ec9 | 2172 | return strlen(mce_helper) + !!p; |
a98f0dd3 AK |
2173 | } |
2174 | ||
8a25a2fd KS |
2175 | static ssize_t set_ignore_ce(struct device *s, |
2176 | struct device_attribute *attr, | |
9af43b54 HS |
2177 | const char *buf, size_t size) |
2178 | { | |
2179 | u64 new; | |
2180 | ||
164109e3 | 2181 | if (kstrtou64(buf, 0, &new) < 0) |
9af43b54 HS |
2182 | return -EINVAL; |
2183 | ||
7af19e4a | 2184 | if (mca_cfg.ignore_ce ^ !!new) { |
9af43b54 HS |
2185 | if (new) { |
2186 | /* disable ce features */ | |
9aaef96f HS |
2187 | mce_timer_delete_all(); |
2188 | on_each_cpu(mce_disable_cmci, NULL, 1); | |
7af19e4a | 2189 | mca_cfg.ignore_ce = true; |
9af43b54 HS |
2190 | } else { |
2191 | /* enable ce features */ | |
7af19e4a | 2192 | mca_cfg.ignore_ce = false; |
9af43b54 HS |
2193 | on_each_cpu(mce_enable_ce, (void *)1, 1); |
2194 | } | |
2195 | } | |
2196 | return size; | |
2197 | } | |
2198 | ||
8a25a2fd KS |
2199 | static ssize_t set_cmci_disabled(struct device *s, |
2200 | struct device_attribute *attr, | |
9af43b54 HS |
2201 | const char *buf, size_t size) |
2202 | { | |
2203 | u64 new; | |
2204 | ||
164109e3 | 2205 | if (kstrtou64(buf, 0, &new) < 0) |
9af43b54 HS |
2206 | return -EINVAL; |
2207 | ||
7af19e4a | 2208 | if (mca_cfg.cmci_disabled ^ !!new) { |
9af43b54 HS |
2209 | if (new) { |
2210 | /* disable cmci */ | |
9aaef96f | 2211 | on_each_cpu(mce_disable_cmci, NULL, 1); |
7af19e4a | 2212 | mca_cfg.cmci_disabled = true; |
9af43b54 HS |
2213 | } else { |
2214 | /* enable cmci */ | |
7af19e4a | 2215 | mca_cfg.cmci_disabled = false; |
9af43b54 HS |
2216 | on_each_cpu(mce_enable_ce, NULL, 1); |
2217 | } | |
2218 | } | |
2219 | return size; | |
2220 | } | |
2221 | ||
8a25a2fd KS |
2222 | static ssize_t store_int_with_restart(struct device *s, |
2223 | struct device_attribute *attr, | |
b56f642d AK |
2224 | const char *buf, size_t size) |
2225 | { | |
8a25a2fd | 2226 | ssize_t ret = device_store_int(s, attr, buf, size); |
b56f642d AK |
2227 | mce_restart(); |
2228 | return ret; | |
2229 | } | |
2230 | ||
8a25a2fd | 2231 | static DEVICE_ATTR(trigger, 0644, show_trigger, set_trigger); |
d203f0b8 | 2232 | static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant); |
84c2559d | 2233 | static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout); |
d203f0b8 | 2234 | static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce); |
e9eee03e | 2235 | |
8a25a2fd KS |
2236 | static struct dev_ext_attribute dev_attr_check_interval = { |
2237 | __ATTR(check_interval, 0644, device_show_int, store_int_with_restart), | |
b56f642d AK |
2238 | &check_interval |
2239 | }; | |
e9eee03e | 2240 | |
8a25a2fd | 2241 | static struct dev_ext_attribute dev_attr_ignore_ce = { |
7af19e4a BP |
2242 | __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce), |
2243 | &mca_cfg.ignore_ce | |
9af43b54 HS |
2244 | }; |
2245 | ||
8a25a2fd | 2246 | static struct dev_ext_attribute dev_attr_cmci_disabled = { |
7af19e4a BP |
2247 | __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled), |
2248 | &mca_cfg.cmci_disabled | |
9af43b54 HS |
2249 | }; |
2250 | ||
8a25a2fd KS |
2251 | static struct device_attribute *mce_device_attrs[] = { |
2252 | &dev_attr_tolerant.attr, | |
2253 | &dev_attr_check_interval.attr, | |
2254 | &dev_attr_trigger, | |
2255 | &dev_attr_monarch_timeout.attr, | |
2256 | &dev_attr_dont_log_ce.attr, | |
2257 | &dev_attr_ignore_ce.attr, | |
2258 | &dev_attr_cmci_disabled.attr, | |
a98f0dd3 AK |
2259 | NULL |
2260 | }; | |
1da177e4 | 2261 | |
8a25a2fd | 2262 | static cpumask_var_t mce_device_initialized; |
bae19fe0 | 2263 | |
e032d807 GKH |
2264 | static void mce_device_release(struct device *dev) |
2265 | { | |
2266 | kfree(dev); | |
2267 | } | |
2268 | ||
8a25a2fd | 2269 | /* Per cpu device init. All of the cpus still share the same ctrl bank: */ |
148f9bb8 | 2270 | static int mce_device_create(unsigned int cpu) |
1da177e4 | 2271 | { |
e032d807 | 2272 | struct device *dev; |
1da177e4 | 2273 | int err; |
b1f49f95 | 2274 | int i, j; |
92cb7612 | 2275 | |
90367556 | 2276 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
2277 | return -EIO; |
2278 | ||
e032d807 GKH |
2279 | dev = kzalloc(sizeof *dev, GFP_KERNEL); |
2280 | if (!dev) | |
2281 | return -ENOMEM; | |
8a25a2fd KS |
2282 | dev->id = cpu; |
2283 | dev->bus = &mce_subsys; | |
e032d807 | 2284 | dev->release = &mce_device_release; |
91c6d400 | 2285 | |
8a25a2fd | 2286 | err = device_register(dev); |
853d9b18 LK |
2287 | if (err) { |
2288 | put_device(dev); | |
d435d862 | 2289 | return err; |
853d9b18 | 2290 | } |
d435d862 | 2291 | |
8a25a2fd KS |
2292 | for (i = 0; mce_device_attrs[i]; i++) { |
2293 | err = device_create_file(dev, mce_device_attrs[i]); | |
d435d862 AM |
2294 | if (err) |
2295 | goto error; | |
2296 | } | |
d203f0b8 | 2297 | for (j = 0; j < mca_cfg.banks; j++) { |
8a25a2fd | 2298 | err = device_create_file(dev, &mce_banks[j].attr); |
0d7482e3 AK |
2299 | if (err) |
2300 | goto error2; | |
2301 | } | |
8a25a2fd | 2302 | cpumask_set_cpu(cpu, mce_device_initialized); |
d6126ef5 | 2303 | per_cpu(mce_device, cpu) = dev; |
91c6d400 | 2304 | |
d435d862 | 2305 | return 0; |
0d7482e3 | 2306 | error2: |
b1f49f95 | 2307 | while (--j >= 0) |
8a25a2fd | 2308 | device_remove_file(dev, &mce_banks[j].attr); |
d435d862 | 2309 | error: |
cb491fca | 2310 | while (--i >= 0) |
8a25a2fd | 2311 | device_remove_file(dev, mce_device_attrs[i]); |
cb491fca | 2312 | |
8a25a2fd | 2313 | device_unregister(dev); |
d435d862 | 2314 | |
91c6d400 AK |
2315 | return err; |
2316 | } | |
2317 | ||
148f9bb8 | 2318 | static void mce_device_remove(unsigned int cpu) |
91c6d400 | 2319 | { |
d6126ef5 | 2320 | struct device *dev = per_cpu(mce_device, cpu); |
73ca5358 SL |
2321 | int i; |
2322 | ||
8a25a2fd | 2323 | if (!cpumask_test_cpu(cpu, mce_device_initialized)) |
bae19fe0 AH |
2324 | return; |
2325 | ||
8a25a2fd KS |
2326 | for (i = 0; mce_device_attrs[i]; i++) |
2327 | device_remove_file(dev, mce_device_attrs[i]); | |
cb491fca | 2328 | |
d203f0b8 | 2329 | for (i = 0; i < mca_cfg.banks; i++) |
8a25a2fd | 2330 | device_remove_file(dev, &mce_banks[i].attr); |
cb491fca | 2331 | |
8a25a2fd KS |
2332 | device_unregister(dev); |
2333 | cpumask_clear_cpu(cpu, mce_device_initialized); | |
d6126ef5 | 2334 | per_cpu(mce_device, cpu) = NULL; |
91c6d400 | 2335 | } |
91c6d400 | 2336 | |
d6b75584 | 2337 | /* Make sure there are no machine checks on offlined CPUs. */ |
148f9bb8 | 2338 | static void mce_disable_cpu(void *h) |
d6b75584 | 2339 | { |
88ccbedd | 2340 | unsigned long action = *(unsigned long *)h; |
cb491fca | 2341 | int i; |
d6b75584 | 2342 | |
89cbc767 | 2343 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
d6b75584 | 2344 | return; |
767df1bd | 2345 | |
88ccbedd AK |
2346 | if (!(action & CPU_TASKS_FROZEN)) |
2347 | cmci_clear(); | |
d203f0b8 | 2348 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2349 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2350 | |
cebe1820 | 2351 | if (b->init) |
a2d32bcb | 2352 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 2353 | } |
d6b75584 AK |
2354 | } |
2355 | ||
148f9bb8 | 2356 | static void mce_reenable_cpu(void *h) |
d6b75584 | 2357 | { |
88ccbedd | 2358 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 2359 | int i; |
d6b75584 | 2360 | |
89cbc767 | 2361 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
d6b75584 | 2362 | return; |
e9eee03e | 2363 | |
88ccbedd AK |
2364 | if (!(action & CPU_TASKS_FROZEN)) |
2365 | cmci_reenable(); | |
d203f0b8 | 2366 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2367 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2368 | |
cebe1820 | 2369 | if (b->init) |
a2d32bcb | 2370 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
06b7a7a5 | 2371 | } |
d6b75584 AK |
2372 | } |
2373 | ||
91c6d400 | 2374 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
148f9bb8 | 2375 | static int |
e9eee03e | 2376 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) |
91c6d400 AK |
2377 | { |
2378 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 2379 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 | 2380 | |
1a65f970 | 2381 | switch (action & ~CPU_TASKS_FROZEN) { |
bae19fe0 | 2382 | case CPU_ONLINE: |
8a25a2fd | 2383 | mce_device_create(cpu); |
8735728e RW |
2384 | if (threshold_cpu_callback) |
2385 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 2386 | break; |
91c6d400 | 2387 | case CPU_DEAD: |
8735728e RW |
2388 | if (threshold_cpu_callback) |
2389 | threshold_cpu_callback(action, cpu); | |
8a25a2fd | 2390 | mce_device_remove(cpu); |
55babd8f | 2391 | mce_intel_hcpu_update(cpu); |
38356c1f BP |
2392 | |
2393 | /* intentionally ignoring frozen here */ | |
2394 | if (!(action & CPU_TASKS_FROZEN)) | |
2395 | cmci_rediscover(); | |
91c6d400 | 2396 | break; |
52d168e2 | 2397 | case CPU_DOWN_PREPARE: |
88ccbedd | 2398 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
55babd8f | 2399 | del_timer_sync(t); |
52d168e2 AK |
2400 | break; |
2401 | case CPU_DOWN_FAILED: | |
88ccbedd | 2402 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
26c3c283 | 2403 | mce_start_timer(cpu, t); |
88ccbedd | 2404 | break; |
1a65f970 TG |
2405 | } |
2406 | ||
bae19fe0 | 2407 | return NOTIFY_OK; |
91c6d400 AK |
2408 | } |
2409 | ||
148f9bb8 | 2410 | static struct notifier_block mce_cpu_notifier = { |
91c6d400 AK |
2411 | .notifier_call = mce_cpu_callback, |
2412 | }; | |
2413 | ||
cebe1820 | 2414 | static __init void mce_init_banks(void) |
0d7482e3 AK |
2415 | { |
2416 | int i; | |
2417 | ||
d203f0b8 | 2418 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2419 | struct mce_bank *b = &mce_banks[i]; |
8a25a2fd | 2420 | struct device_attribute *a = &b->attr; |
e9eee03e | 2421 | |
a07e4156 | 2422 | sysfs_attr_init(&a->attr); |
cebe1820 AK |
2423 | a->attr.name = b->attrname; |
2424 | snprintf(b->attrname, ATTR_LEN, "bank%d", i); | |
e9eee03e IM |
2425 | |
2426 | a->attr.mode = 0644; | |
2427 | a->show = show_bank; | |
2428 | a->store = set_bank; | |
0d7482e3 | 2429 | } |
0d7482e3 AK |
2430 | } |
2431 | ||
5e09954a | 2432 | static __init int mcheck_init_device(void) |
91c6d400 AK |
2433 | { |
2434 | int err; | |
2435 | int i = 0; | |
2436 | ||
9c15a24b MS |
2437 | if (!mce_available(&boot_cpu_data)) { |
2438 | err = -EIO; | |
2439 | goto err_out; | |
2440 | } | |
0d7482e3 | 2441 | |
9c15a24b MS |
2442 | if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) { |
2443 | err = -ENOMEM; | |
2444 | goto err_out; | |
2445 | } | |
996867d0 | 2446 | |
cebe1820 | 2447 | mce_init_banks(); |
0d7482e3 | 2448 | |
8a25a2fd | 2449 | err = subsys_system_register(&mce_subsys, NULL); |
d435d862 | 2450 | if (err) |
9c15a24b | 2451 | goto err_out_mem; |
91c6d400 | 2452 | |
82a8f131 | 2453 | cpu_notifier_register_begin(); |
91c6d400 | 2454 | for_each_online_cpu(i) { |
8a25a2fd | 2455 | err = mce_device_create(i); |
82a8f131 | 2456 | if (err) { |
27c93415 BP |
2457 | /* |
2458 | * Register notifier anyway (and do not unreg it) so | |
2459 | * that we don't leave undeleted timers, see notifier | |
2460 | * callback above. | |
2461 | */ | |
2462 | __register_hotcpu_notifier(&mce_cpu_notifier); | |
82a8f131 | 2463 | cpu_notifier_register_done(); |
9c15a24b | 2464 | goto err_device_create; |
82a8f131 | 2465 | } |
91c6d400 AK |
2466 | } |
2467 | ||
82a8f131 SB |
2468 | __register_hotcpu_notifier(&mce_cpu_notifier); |
2469 | cpu_notifier_register_done(); | |
93b62c3c | 2470 | |
9c15a24b MS |
2471 | register_syscore_ops(&mce_syscore_ops); |
2472 | ||
93b62c3c | 2473 | /* register character device /dev/mcelog */ |
9c15a24b MS |
2474 | err = misc_register(&mce_chrdev_device); |
2475 | if (err) | |
2476 | goto err_register; | |
2477 | ||
2478 | return 0; | |
2479 | ||
2480 | err_register: | |
2481 | unregister_syscore_ops(&mce_syscore_ops); | |
2482 | ||
9c15a24b MS |
2483 | err_device_create: |
2484 | /* | |
2485 | * We didn't keep track of which devices were created above, but | |
2486 | * even if we had, the set of online cpus might have changed. | |
2487 | * Play safe and remove for every possible cpu, since | |
2488 | * mce_device_remove() will do the right thing. | |
2489 | */ | |
2490 | for_each_possible_cpu(i) | |
2491 | mce_device_remove(i); | |
2492 | ||
2493 | err_out_mem: | |
2494 | free_cpumask_var(mce_device_initialized); | |
2495 | ||
2496 | err_out: | |
2497 | pr_err("Unable to init device /dev/mcelog (rc: %d)\n", err); | |
e9eee03e | 2498 | |
1da177e4 | 2499 | return err; |
1da177e4 | 2500 | } |
cef12ee5 | 2501 | device_initcall_sync(mcheck_init_device); |
a988d334 | 2502 | |
d7c3c9a6 AK |
2503 | /* |
2504 | * Old style boot options parsing. Only for compatibility. | |
2505 | */ | |
2506 | static int __init mcheck_disable(char *str) | |
2507 | { | |
1462594b | 2508 | mca_cfg.disabled = true; |
d7c3c9a6 AK |
2509 | return 1; |
2510 | } | |
2511 | __setup("nomce", mcheck_disable); | |
a988d334 | 2512 | |
5be9ed25 HY |
2513 | #ifdef CONFIG_DEBUG_FS |
2514 | struct dentry *mce_get_debugfs_dir(void) | |
a988d334 | 2515 | { |
5be9ed25 | 2516 | static struct dentry *dmce; |
a988d334 | 2517 | |
5be9ed25 HY |
2518 | if (!dmce) |
2519 | dmce = debugfs_create_dir("mce", NULL); | |
a988d334 | 2520 | |
5be9ed25 HY |
2521 | return dmce; |
2522 | } | |
a988d334 | 2523 | |
bf783f9f HY |
2524 | static void mce_reset(void) |
2525 | { | |
2526 | cpu_missing = 0; | |
c7c9b392 | 2527 | atomic_set(&mce_fake_panicked, 0); |
bf783f9f HY |
2528 | atomic_set(&mce_executing, 0); |
2529 | atomic_set(&mce_callin, 0); | |
2530 | atomic_set(&global_nwo, 0); | |
2531 | } | |
a988d334 | 2532 | |
bf783f9f HY |
2533 | static int fake_panic_get(void *data, u64 *val) |
2534 | { | |
2535 | *val = fake_panic; | |
2536 | return 0; | |
a988d334 IM |
2537 | } |
2538 | ||
bf783f9f | 2539 | static int fake_panic_set(void *data, u64 val) |
a988d334 | 2540 | { |
bf783f9f HY |
2541 | mce_reset(); |
2542 | fake_panic = val; | |
2543 | return 0; | |
a988d334 | 2544 | } |
a988d334 | 2545 | |
bf783f9f HY |
2546 | DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get, |
2547 | fake_panic_set, "%llu\n"); | |
d7c3c9a6 | 2548 | |
5e09954a | 2549 | static int __init mcheck_debugfs_init(void) |
d7c3c9a6 | 2550 | { |
bf783f9f HY |
2551 | struct dentry *dmce, *ffake_panic; |
2552 | ||
2553 | dmce = mce_get_debugfs_dir(); | |
2554 | if (!dmce) | |
2555 | return -ENOMEM; | |
2556 | ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL, | |
2557 | &fake_panic_fops); | |
2558 | if (!ffake_panic) | |
2559 | return -ENOMEM; | |
2560 | ||
2561 | return 0; | |
d7c3c9a6 | 2562 | } |
5e09954a | 2563 | late_initcall(mcheck_debugfs_init); |
5be9ed25 | 2564 | #endif |