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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
e9eee03e IM |
10 | #include <linux/thread_info.h> |
11 | #include <linux/capability.h> | |
12 | #include <linux/miscdevice.h> | |
13 | #include <linux/ratelimit.h> | |
14 | #include <linux/kallsyms.h> | |
15 | #include <linux/rcupdate.h> | |
e9eee03e | 16 | #include <linux/kobject.h> |
14a02530 | 17 | #include <linux/uaccess.h> |
e9eee03e IM |
18 | #include <linux/kdebug.h> |
19 | #include <linux/kernel.h> | |
20 | #include <linux/percpu.h> | |
1da177e4 | 21 | #include <linux/string.h> |
1da177e4 | 22 | #include <linux/sysdev.h> |
f3c6ea1b | 23 | #include <linux/syscore_ops.h> |
3c079792 | 24 | #include <linux/delay.h> |
8c566ef5 | 25 | #include <linux/ctype.h> |
e9eee03e | 26 | #include <linux/sched.h> |
0d7482e3 | 27 | #include <linux/sysfs.h> |
e9eee03e | 28 | #include <linux/types.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
e9eee03e IM |
30 | #include <linux/init.h> |
31 | #include <linux/kmod.h> | |
32 | #include <linux/poll.h> | |
3c079792 | 33 | #include <linux/nmi.h> |
e9eee03e | 34 | #include <linux/cpu.h> |
14a02530 | 35 | #include <linux/smp.h> |
e9eee03e | 36 | #include <linux/fs.h> |
9b1beaf2 | 37 | #include <linux/mm.h> |
5be9ed25 | 38 | #include <linux/debugfs.h> |
b77e70bf | 39 | #include <linux/irq_work.h> |
69c60c88 | 40 | #include <linux/export.h> |
e9eee03e | 41 | |
d88203d1 | 42 | #include <asm/processor.h> |
e9eee03e IM |
43 | #include <asm/mce.h> |
44 | #include <asm/msr.h> | |
1da177e4 | 45 | |
bd19a5e6 | 46 | #include "mce-internal.h" |
711c2e48 | 47 | |
93b62c3c | 48 | static DEFINE_MUTEX(mce_chrdev_read_mutex); |
2aa2b50d | 49 | |
f56e8a07 | 50 | #define rcu_dereference_check_mce(p) \ |
ec8c27e0 | 51 | rcu_dereference_index_check((p), \ |
f56e8a07 | 52 | rcu_read_lock_sched_held() || \ |
93b62c3c | 53 | lockdep_is_held(&mce_chrdev_read_mutex)) |
f56e8a07 | 54 | |
8968f9d3 HS |
55 | #define CREATE_TRACE_POINTS |
56 | #include <trace/events/mce.h> | |
57 | ||
4e5b3e69 | 58 | int mce_disabled __read_mostly; |
04b2b1a4 | 59 | |
e9eee03e | 60 | #define MISC_MCELOG_MINOR 227 |
0d7482e3 | 61 | |
3c079792 AK |
62 | #define SPINUNIT 100 /* 100ns */ |
63 | ||
553f265f AK |
64 | atomic_t mce_entry; |
65 | ||
01ca79f1 AK |
66 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
67 | ||
bd78432c TH |
68 | /* |
69 | * Tolerant levels: | |
70 | * 0: always panic on uncorrected errors, log corrected errors | |
71 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
72 | * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors | |
73 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
74 | */ | |
4e5b3e69 HS |
75 | static int tolerant __read_mostly = 1; |
76 | static int banks __read_mostly; | |
4e5b3e69 HS |
77 | static int rip_msr __read_mostly; |
78 | static int mce_bootlog __read_mostly = -1; | |
79 | static int monarch_timeout __read_mostly = -1; | |
80 | static int mce_panic_timeout __read_mostly; | |
81 | static int mce_dont_log_ce __read_mostly; | |
82 | int mce_cmci_disabled __read_mostly; | |
83 | int mce_ignore_ce __read_mostly; | |
84 | int mce_ser __read_mostly; | |
a98f0dd3 | 85 | |
cebe1820 AK |
86 | struct mce_bank *mce_banks __read_mostly; |
87 | ||
1020bcbc HS |
88 | /* User mode helper program triggered by machine check event */ |
89 | static unsigned long mce_need_notify; | |
90 | static char mce_helper[128]; | |
91 | static char *mce_helper_argv[2] = { mce_helper, NULL }; | |
1da177e4 | 92 | |
93b62c3c HS |
93 | static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait); |
94 | ||
3c079792 AK |
95 | static DEFINE_PER_CPU(struct mce, mces_seen); |
96 | static int cpu_missing; | |
97 | ||
fb253195 BP |
98 | /* |
99 | * CPU/chipset specific EDAC code can register a notifier call here to print | |
100 | * MCE errors in a human-readable form. | |
101 | */ | |
102 | ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain); | |
103 | EXPORT_SYMBOL_GPL(x86_mce_decoder_chain); | |
104 | ||
ee031c31 AK |
105 | /* MCA banks polled by the period polling timer for corrected events */ |
106 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { | |
107 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
108 | }; | |
109 | ||
9b1beaf2 AK |
110 | static DEFINE_PER_CPU(struct work_struct, mce_work); |
111 | ||
b5f2fa4e AK |
112 | /* Do initial initialization of a struct mce */ |
113 | void mce_setup(struct mce *m) | |
114 | { | |
115 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 116 | m->cpu = m->extcpu = smp_processor_id(); |
b5f2fa4e | 117 | rdtscll(m->tsc); |
8ee08347 AK |
118 | /* We hope get_seconds stays lockless */ |
119 | m->time = get_seconds(); | |
120 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
121 | m->cpuid = cpuid_eax(1); | |
122 | #ifdef CONFIG_SMP | |
123 | m->socketid = cpu_data(m->extcpu).phys_proc_id; | |
124 | #endif | |
125 | m->apicid = cpu_data(m->extcpu).initial_apicid; | |
126 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
b5f2fa4e AK |
127 | } |
128 | ||
ea149b36 AK |
129 | DEFINE_PER_CPU(struct mce, injectm); |
130 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
131 | ||
1da177e4 LT |
132 | /* |
133 | * Lockless MCE logging infrastructure. | |
134 | * This avoids deadlocks on printk locks without having to break locks. Also | |
135 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
136 | */ | |
137 | ||
231fd906 | 138 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
139 | .signature = MCE_LOG_SIGNATURE, |
140 | .len = MCE_LOG_LEN, | |
141 | .recordlen = sizeof(struct mce), | |
d88203d1 | 142 | }; |
1da177e4 LT |
143 | |
144 | void mce_log(struct mce *mce) | |
145 | { | |
146 | unsigned next, entry; | |
f0cb5452 | 147 | int ret = 0; |
e9eee03e | 148 | |
8968f9d3 HS |
149 | /* Emit the trace record: */ |
150 | trace_mce_record(mce); | |
151 | ||
f0cb5452 BP |
152 | ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, mce); |
153 | if (ret == NOTIFY_STOP) | |
154 | return; | |
155 | ||
1da177e4 | 156 | mce->finished = 0; |
7644143c | 157 | wmb(); |
1da177e4 | 158 | for (;;) { |
f56e8a07 | 159 | entry = rcu_dereference_check_mce(mcelog.next); |
673242c1 | 160 | for (;;) { |
696e409d | 161 | |
e9eee03e IM |
162 | /* |
163 | * When the buffer fills up discard new entries. | |
164 | * Assume that the earlier errors are the more | |
165 | * interesting ones: | |
166 | */ | |
673242c1 | 167 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
168 | set_bit(MCE_OVERFLOW, |
169 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
170 | return; |
171 | } | |
e9eee03e | 172 | /* Old left over entry. Skip: */ |
673242c1 AK |
173 | if (mcelog.entry[entry].finished) { |
174 | entry++; | |
175 | continue; | |
176 | } | |
7644143c | 177 | break; |
1da177e4 | 178 | } |
1da177e4 LT |
179 | smp_rmb(); |
180 | next = entry + 1; | |
181 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
182 | break; | |
183 | } | |
184 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 185 | wmb(); |
1da177e4 | 186 | mcelog.entry[entry].finished = 1; |
7644143c | 187 | wmb(); |
1da177e4 | 188 | |
a0189c70 | 189 | mce->finished = 1; |
1020bcbc | 190 | set_bit(0, &mce_need_notify); |
1da177e4 LT |
191 | } |
192 | ||
77e26cca | 193 | static void print_mce(struct mce *m) |
1da177e4 | 194 | { |
dffa4b2f BP |
195 | int ret = 0; |
196 | ||
a2d7b0d4 | 197 | pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n", |
d620c67f | 198 | m->extcpu, m->mcgstatus, m->bank, m->status); |
f436f8bb | 199 | |
65ea5b03 | 200 | if (m->ip) { |
a2d7b0d4 | 201 | pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", |
f436f8bb IM |
202 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
203 | m->cs, m->ip); | |
204 | ||
1da177e4 | 205 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 206 | print_symbol("{%s}", m->ip); |
f436f8bb | 207 | pr_cont("\n"); |
1da177e4 | 208 | } |
f436f8bb | 209 | |
a2d7b0d4 | 210 | pr_emerg(HW_ERR "TSC %llx ", m->tsc); |
1da177e4 | 211 | if (m->addr) |
f436f8bb | 212 | pr_cont("ADDR %llx ", m->addr); |
1da177e4 | 213 | if (m->misc) |
f436f8bb | 214 | pr_cont("MISC %llx ", m->misc); |
549d042d | 215 | |
f436f8bb | 216 | pr_cont("\n"); |
506ed6b5 AK |
217 | /* |
218 | * Note this output is parsed by external tools and old fields | |
219 | * should not be changed. | |
220 | */ | |
881e23e5 | 221 | pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n", |
506ed6b5 AK |
222 | m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, |
223 | cpu_data(m->extcpu).microcode); | |
f436f8bb IM |
224 | |
225 | /* | |
226 | * Print out human-readable details about the MCE error, | |
fb253195 | 227 | * (if the CPU has an implementation for that) |
f436f8bb | 228 | */ |
dffa4b2f BP |
229 | ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); |
230 | if (ret == NOTIFY_STOP) | |
231 | return; | |
232 | ||
233 | pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); | |
86503560 AK |
234 | } |
235 | ||
f94b61c2 AK |
236 | #define PANIC_TIMEOUT 5 /* 5 seconds */ |
237 | ||
238 | static atomic_t mce_paniced; | |
239 | ||
bf783f9f HY |
240 | static int fake_panic; |
241 | static atomic_t mce_fake_paniced; | |
242 | ||
f94b61c2 AK |
243 | /* Panic in progress. Enable interrupts and wait for final IPI */ |
244 | static void wait_for_panic(void) | |
245 | { | |
246 | long timeout = PANIC_TIMEOUT*USEC_PER_SEC; | |
f436f8bb | 247 | |
f94b61c2 AK |
248 | preempt_disable(); |
249 | local_irq_enable(); | |
250 | while (timeout-- > 0) | |
251 | udelay(1); | |
29b0f591 AK |
252 | if (panic_timeout == 0) |
253 | panic_timeout = mce_panic_timeout; | |
f94b61c2 AK |
254 | panic("Panicing machine check CPU died"); |
255 | } | |
256 | ||
bd19a5e6 | 257 | static void mce_panic(char *msg, struct mce *final, char *exp) |
d88203d1 | 258 | { |
482908b4 | 259 | int i, apei_err = 0; |
e02e68d3 | 260 | |
bf783f9f HY |
261 | if (!fake_panic) { |
262 | /* | |
263 | * Make sure only one CPU runs in machine check panic | |
264 | */ | |
265 | if (atomic_inc_return(&mce_paniced) > 1) | |
266 | wait_for_panic(); | |
267 | barrier(); | |
f94b61c2 | 268 | |
bf783f9f HY |
269 | bust_spinlocks(1); |
270 | console_verbose(); | |
271 | } else { | |
272 | /* Don't log too much for fake panic */ | |
273 | if (atomic_inc_return(&mce_fake_paniced) > 1) | |
274 | return; | |
275 | } | |
a0189c70 | 276 | /* First print corrected ones that are still unlogged */ |
1da177e4 | 277 | for (i = 0; i < MCE_LOG_LEN; i++) { |
a0189c70 | 278 | struct mce *m = &mcelog.entry[i]; |
77e26cca HS |
279 | if (!(m->status & MCI_STATUS_VAL)) |
280 | continue; | |
482908b4 | 281 | if (!(m->status & MCI_STATUS_UC)) { |
77e26cca | 282 | print_mce(m); |
482908b4 HY |
283 | if (!apei_err) |
284 | apei_err = apei_write_mce(m); | |
285 | } | |
a0189c70 AK |
286 | } |
287 | /* Now print uncorrected but with the final one last */ | |
288 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
289 | struct mce *m = &mcelog.entry[i]; | |
290 | if (!(m->status & MCI_STATUS_VAL)) | |
1da177e4 | 291 | continue; |
77e26cca HS |
292 | if (!(m->status & MCI_STATUS_UC)) |
293 | continue; | |
482908b4 | 294 | if (!final || memcmp(m, final, sizeof(struct mce))) { |
77e26cca | 295 | print_mce(m); |
482908b4 HY |
296 | if (!apei_err) |
297 | apei_err = apei_write_mce(m); | |
298 | } | |
1da177e4 | 299 | } |
482908b4 | 300 | if (final) { |
77e26cca | 301 | print_mce(final); |
482908b4 HY |
302 | if (!apei_err) |
303 | apei_err = apei_write_mce(final); | |
304 | } | |
3c079792 | 305 | if (cpu_missing) |
a2d7b0d4 | 306 | pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n"); |
bd19a5e6 | 307 | if (exp) |
a2d7b0d4 | 308 | pr_emerg(HW_ERR "Machine check: %s\n", exp); |
bf783f9f HY |
309 | if (!fake_panic) { |
310 | if (panic_timeout == 0) | |
311 | panic_timeout = mce_panic_timeout; | |
312 | panic(msg); | |
313 | } else | |
a2d7b0d4 | 314 | pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); |
d88203d1 | 315 | } |
1da177e4 | 316 | |
ea149b36 AK |
317 | /* Support code for software error injection */ |
318 | ||
319 | static int msr_to_offset(u32 msr) | |
320 | { | |
0a3aee0d | 321 | unsigned bank = __this_cpu_read(injectm.bank); |
f436f8bb | 322 | |
ea149b36 AK |
323 | if (msr == rip_msr) |
324 | return offsetof(struct mce, ip); | |
a2d32bcb | 325 | if (msr == MSR_IA32_MCx_STATUS(bank)) |
ea149b36 | 326 | return offsetof(struct mce, status); |
a2d32bcb | 327 | if (msr == MSR_IA32_MCx_ADDR(bank)) |
ea149b36 | 328 | return offsetof(struct mce, addr); |
a2d32bcb | 329 | if (msr == MSR_IA32_MCx_MISC(bank)) |
ea149b36 AK |
330 | return offsetof(struct mce, misc); |
331 | if (msr == MSR_IA32_MCG_STATUS) | |
332 | return offsetof(struct mce, mcgstatus); | |
333 | return -1; | |
334 | } | |
335 | ||
5f8c1a54 AK |
336 | /* MSR access wrappers used for error injection */ |
337 | static u64 mce_rdmsrl(u32 msr) | |
338 | { | |
339 | u64 v; | |
11868a2d | 340 | |
0a3aee0d | 341 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 342 | int offset = msr_to_offset(msr); |
11868a2d | 343 | |
ea149b36 AK |
344 | if (offset < 0) |
345 | return 0; | |
346 | return *(u64 *)((char *)&__get_cpu_var(injectm) + offset); | |
347 | } | |
11868a2d IM |
348 | |
349 | if (rdmsrl_safe(msr, &v)) { | |
350 | WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr); | |
351 | /* | |
352 | * Return zero in case the access faulted. This should | |
353 | * not happen normally but can happen if the CPU does | |
354 | * something weird, or if the code is buggy. | |
355 | */ | |
356 | v = 0; | |
357 | } | |
358 | ||
5f8c1a54 AK |
359 | return v; |
360 | } | |
361 | ||
362 | static void mce_wrmsrl(u32 msr, u64 v) | |
363 | { | |
0a3aee0d | 364 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 365 | int offset = msr_to_offset(msr); |
11868a2d | 366 | |
ea149b36 AK |
367 | if (offset >= 0) |
368 | *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v; | |
369 | return; | |
370 | } | |
5f8c1a54 AK |
371 | wrmsrl(msr, v); |
372 | } | |
373 | ||
b8325c5b HS |
374 | /* |
375 | * Collect all global (w.r.t. this processor) status about this machine | |
376 | * check into our "mce" struct so that we can use it later to assess | |
377 | * the severity of the problem as we read per-bank specific details. | |
378 | */ | |
379 | static inline void mce_gather_info(struct mce *m, struct pt_regs *regs) | |
380 | { | |
381 | mce_setup(m); | |
382 | ||
383 | m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); | |
384 | if (regs) { | |
385 | /* | |
386 | * Get the address of the instruction at the time of | |
387 | * the machine check error. | |
388 | */ | |
389 | if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) { | |
390 | m->ip = regs->ip; | |
391 | m->cs = regs->cs; | |
392 | } | |
393 | /* Use accurate RIP reporting if available. */ | |
394 | if (rip_msr) | |
395 | m->ip = mce_rdmsrl(rip_msr); | |
396 | } | |
397 | } | |
398 | ||
9b1beaf2 AK |
399 | /* |
400 | * Simple lockless ring to communicate PFNs from the exception handler with the | |
401 | * process context work function. This is vastly simplified because there's | |
402 | * only a single reader and a single writer. | |
403 | */ | |
404 | #define MCE_RING_SIZE 16 /* we use one entry less */ | |
405 | ||
406 | struct mce_ring { | |
407 | unsigned short start; | |
408 | unsigned short end; | |
409 | unsigned long ring[MCE_RING_SIZE]; | |
410 | }; | |
411 | static DEFINE_PER_CPU(struct mce_ring, mce_ring); | |
412 | ||
413 | /* Runs with CPU affinity in workqueue */ | |
414 | static int mce_ring_empty(void) | |
415 | { | |
416 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
417 | ||
418 | return r->start == r->end; | |
419 | } | |
420 | ||
421 | static int mce_ring_get(unsigned long *pfn) | |
422 | { | |
423 | struct mce_ring *r; | |
424 | int ret = 0; | |
425 | ||
426 | *pfn = 0; | |
427 | get_cpu(); | |
428 | r = &__get_cpu_var(mce_ring); | |
429 | if (r->start == r->end) | |
430 | goto out; | |
431 | *pfn = r->ring[r->start]; | |
432 | r->start = (r->start + 1) % MCE_RING_SIZE; | |
433 | ret = 1; | |
434 | out: | |
435 | put_cpu(); | |
436 | return ret; | |
437 | } | |
438 | ||
439 | /* Always runs in MCE context with preempt off */ | |
440 | static int mce_ring_add(unsigned long pfn) | |
441 | { | |
442 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
443 | unsigned next; | |
444 | ||
445 | next = (r->end + 1) % MCE_RING_SIZE; | |
446 | if (next == r->start) | |
447 | return -1; | |
448 | r->ring[r->end] = pfn; | |
449 | wmb(); | |
450 | r->end = next; | |
451 | return 0; | |
452 | } | |
453 | ||
88ccbedd | 454 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 455 | { |
04b2b1a4 | 456 | if (mce_disabled) |
5b4408fd | 457 | return 0; |
3d1712c9 | 458 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
459 | } |
460 | ||
9b1beaf2 AK |
461 | static void mce_schedule_work(void) |
462 | { | |
463 | if (!mce_ring_empty()) { | |
464 | struct work_struct *work = &__get_cpu_var(mce_work); | |
465 | if (!work_pending(work)) | |
466 | schedule_work(work); | |
467 | } | |
468 | } | |
469 | ||
b77e70bf HS |
470 | DEFINE_PER_CPU(struct irq_work, mce_irq_work); |
471 | ||
472 | static void mce_irq_work_cb(struct irq_work *entry) | |
ccc3c319 | 473 | { |
9ff36ee9 | 474 | mce_notify_irq(); |
9b1beaf2 | 475 | mce_schedule_work(); |
ccc3c319 | 476 | } |
ccc3c319 AK |
477 | |
478 | static void mce_report_event(struct pt_regs *regs) | |
479 | { | |
480 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { | |
9ff36ee9 | 481 | mce_notify_irq(); |
9b1beaf2 AK |
482 | /* |
483 | * Triggering the work queue here is just an insurance | |
484 | * policy in case the syscall exit notify handler | |
485 | * doesn't run soon enough or ends up running on the | |
486 | * wrong CPU (can happen when audit sleeps) | |
487 | */ | |
488 | mce_schedule_work(); | |
ccc3c319 AK |
489 | return; |
490 | } | |
491 | ||
b77e70bf | 492 | irq_work_queue(&__get_cpu_var(mce_irq_work)); |
ccc3c319 AK |
493 | } |
494 | ||
ca84f696 AK |
495 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
496 | ||
d88203d1 | 497 | /* |
b79109c3 AK |
498 | * Poll for corrected events or events that happened before reset. |
499 | * Those are just logged through /dev/mcelog. | |
500 | * | |
501 | * This is executed in standard interrupt context. | |
ed7290d0 AK |
502 | * |
503 | * Note: spec recommends to panic for fatal unsignalled | |
504 | * errors here. However this would be quite problematic -- | |
505 | * we would need to reimplement the Monarch handling and | |
506 | * it would mess up the exclusion between exception handler | |
507 | * and poll hander -- * so we skip this for now. | |
508 | * These cases should not happen anyways, or only when the CPU | |
509 | * is already totally * confused. In this case it's likely it will | |
510 | * not fully execute the machine check handler either. | |
b79109c3 | 511 | */ |
ee031c31 | 512 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 AK |
513 | { |
514 | struct mce m; | |
515 | int i; | |
516 | ||
402af0d7 | 517 | percpu_inc(mce_poll_count); |
ca84f696 | 518 | |
b8325c5b | 519 | mce_gather_info(&m, NULL); |
b79109c3 | 520 | |
b79109c3 | 521 | for (i = 0; i < banks; i++) { |
cebe1820 | 522 | if (!mce_banks[i].ctl || !test_bit(i, *b)) |
b79109c3 AK |
523 | continue; |
524 | ||
525 | m.misc = 0; | |
526 | m.addr = 0; | |
527 | m.bank = i; | |
528 | m.tsc = 0; | |
529 | ||
530 | barrier(); | |
a2d32bcb | 531 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
b79109c3 AK |
532 | if (!(m.status & MCI_STATUS_VAL)) |
533 | continue; | |
534 | ||
535 | /* | |
ed7290d0 AK |
536 | * Uncorrected or signalled events are handled by the exception |
537 | * handler when it is enabled, so don't process those here. | |
b79109c3 AK |
538 | * |
539 | * TBD do the same check for MCI_STATUS_EN here? | |
540 | */ | |
ed7290d0 AK |
541 | if (!(flags & MCP_UC) && |
542 | (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC))) | |
b79109c3 AK |
543 | continue; |
544 | ||
545 | if (m.status & MCI_STATUS_MISCV) | |
a2d32bcb | 546 | m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); |
b79109c3 | 547 | if (m.status & MCI_STATUS_ADDRV) |
a2d32bcb | 548 | m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); |
b79109c3 AK |
549 | |
550 | if (!(flags & MCP_TIMESTAMP)) | |
551 | m.tsc = 0; | |
552 | /* | |
553 | * Don't get the IP here because it's unlikely to | |
554 | * have anything to do with the actual error location. | |
555 | */ | |
f0cb5452 | 556 | if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) |
5679af4c | 557 | mce_log(&m); |
b79109c3 AK |
558 | |
559 | /* | |
560 | * Clear state for this bank. | |
561 | */ | |
a2d32bcb | 562 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
b79109c3 AK |
563 | } |
564 | ||
565 | /* | |
566 | * Don't clear MCG_STATUS here because it's only defined for | |
567 | * exceptions. | |
568 | */ | |
88921be3 AK |
569 | |
570 | sync_core(); | |
b79109c3 | 571 | } |
ea149b36 | 572 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 | 573 | |
bd19a5e6 AK |
574 | /* |
575 | * Do a quick check if any of the events requires a panic. | |
576 | * This decides if we keep the events around or clear them. | |
577 | */ | |
578 | static int mce_no_way_out(struct mce *m, char **msg) | |
579 | { | |
580 | int i; | |
581 | ||
582 | for (i = 0; i < banks; i++) { | |
a2d32bcb | 583 | m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
bd19a5e6 AK |
584 | if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY) |
585 | return 1; | |
586 | } | |
587 | return 0; | |
588 | } | |
589 | ||
3c079792 AK |
590 | /* |
591 | * Variable to establish order between CPUs while scanning. | |
592 | * Each CPU spins initially until executing is equal its number. | |
593 | */ | |
594 | static atomic_t mce_executing; | |
595 | ||
596 | /* | |
597 | * Defines order of CPUs on entry. First CPU becomes Monarch. | |
598 | */ | |
599 | static atomic_t mce_callin; | |
600 | ||
601 | /* | |
602 | * Check if a timeout waiting for other CPUs happened. | |
603 | */ | |
604 | static int mce_timed_out(u64 *t) | |
605 | { | |
606 | /* | |
607 | * The others already did panic for some reason. | |
608 | * Bail out like in a timeout. | |
609 | * rmb() to tell the compiler that system_state | |
610 | * might have been modified by someone else. | |
611 | */ | |
612 | rmb(); | |
613 | if (atomic_read(&mce_paniced)) | |
614 | wait_for_panic(); | |
615 | if (!monarch_timeout) | |
616 | goto out; | |
617 | if ((s64)*t < SPINUNIT) { | |
618 | /* CHECKME: Make panic default for 1 too? */ | |
619 | if (tolerant < 1) | |
620 | mce_panic("Timeout synchronizing machine check over CPUs", | |
621 | NULL, NULL); | |
622 | cpu_missing = 1; | |
623 | return 1; | |
624 | } | |
625 | *t -= SPINUNIT; | |
626 | out: | |
627 | touch_nmi_watchdog(); | |
628 | return 0; | |
629 | } | |
630 | ||
631 | /* | |
632 | * The Monarch's reign. The Monarch is the CPU who entered | |
633 | * the machine check handler first. It waits for the others to | |
634 | * raise the exception too and then grades them. When any | |
635 | * error is fatal panic. Only then let the others continue. | |
636 | * | |
637 | * The other CPUs entering the MCE handler will be controlled by the | |
638 | * Monarch. They are called Subjects. | |
639 | * | |
640 | * This way we prevent any potential data corruption in a unrecoverable case | |
641 | * and also makes sure always all CPU's errors are examined. | |
642 | * | |
680b6cfd | 643 | * Also this detects the case of a machine check event coming from outer |
3c079792 AK |
644 | * space (not detected by any CPUs) In this case some external agent wants |
645 | * us to shut down, so panic too. | |
646 | * | |
647 | * The other CPUs might still decide to panic if the handler happens | |
648 | * in a unrecoverable place, but in this case the system is in a semi-stable | |
649 | * state and won't corrupt anything by itself. It's ok to let the others | |
650 | * continue for a bit first. | |
651 | * | |
652 | * All the spin loops have timeouts; when a timeout happens a CPU | |
653 | * typically elects itself to be Monarch. | |
654 | */ | |
655 | static void mce_reign(void) | |
656 | { | |
657 | int cpu; | |
658 | struct mce *m = NULL; | |
659 | int global_worst = 0; | |
660 | char *msg = NULL; | |
661 | char *nmsg = NULL; | |
662 | ||
663 | /* | |
664 | * This CPU is the Monarch and the other CPUs have run | |
665 | * through their handlers. | |
666 | * Grade the severity of the errors of all the CPUs. | |
667 | */ | |
668 | for_each_possible_cpu(cpu) { | |
669 | int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant, | |
670 | &nmsg); | |
671 | if (severity > global_worst) { | |
672 | msg = nmsg; | |
673 | global_worst = severity; | |
674 | m = &per_cpu(mces_seen, cpu); | |
675 | } | |
676 | } | |
677 | ||
678 | /* | |
679 | * Cannot recover? Panic here then. | |
680 | * This dumps all the mces in the log buffer and stops the | |
681 | * other CPUs. | |
682 | */ | |
683 | if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3) | |
ac960375 | 684 | mce_panic("Fatal Machine check", m, msg); |
3c079792 AK |
685 | |
686 | /* | |
687 | * For UC somewhere we let the CPU who detects it handle it. | |
688 | * Also must let continue the others, otherwise the handling | |
689 | * CPU could deadlock on a lock. | |
690 | */ | |
691 | ||
692 | /* | |
693 | * No machine check event found. Must be some external | |
694 | * source or one CPU is hung. Panic. | |
695 | */ | |
680b6cfd | 696 | if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3) |
3c079792 AK |
697 | mce_panic("Machine check from unknown source", NULL, NULL); |
698 | ||
699 | /* | |
700 | * Now clear all the mces_seen so that they don't reappear on | |
701 | * the next mce. | |
702 | */ | |
703 | for_each_possible_cpu(cpu) | |
704 | memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); | |
705 | } | |
706 | ||
707 | static atomic_t global_nwo; | |
708 | ||
709 | /* | |
710 | * Start of Monarch synchronization. This waits until all CPUs have | |
711 | * entered the exception handler and then determines if any of them | |
712 | * saw a fatal event that requires panic. Then it executes them | |
713 | * in the entry order. | |
714 | * TBD double check parallel CPU hotunplug | |
715 | */ | |
7fb06fc9 | 716 | static int mce_start(int *no_way_out) |
3c079792 | 717 | { |
7fb06fc9 | 718 | int order; |
3c079792 AK |
719 | int cpus = num_online_cpus(); |
720 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
721 | ||
7fb06fc9 HS |
722 | if (!timeout) |
723 | return -1; | |
3c079792 | 724 | |
7fb06fc9 | 725 | atomic_add(*no_way_out, &global_nwo); |
184e1fdf HY |
726 | /* |
727 | * global_nwo should be updated before mce_callin | |
728 | */ | |
729 | smp_wmb(); | |
a95436e4 | 730 | order = atomic_inc_return(&mce_callin); |
3c079792 AK |
731 | |
732 | /* | |
733 | * Wait for everyone. | |
734 | */ | |
735 | while (atomic_read(&mce_callin) != cpus) { | |
736 | if (mce_timed_out(&timeout)) { | |
737 | atomic_set(&global_nwo, 0); | |
7fb06fc9 | 738 | return -1; |
3c079792 AK |
739 | } |
740 | ndelay(SPINUNIT); | |
741 | } | |
742 | ||
184e1fdf HY |
743 | /* |
744 | * mce_callin should be read before global_nwo | |
745 | */ | |
746 | smp_rmb(); | |
3c079792 | 747 | |
7fb06fc9 HS |
748 | if (order == 1) { |
749 | /* | |
750 | * Monarch: Starts executing now, the others wait. | |
751 | */ | |
3c079792 | 752 | atomic_set(&mce_executing, 1); |
7fb06fc9 HS |
753 | } else { |
754 | /* | |
755 | * Subject: Now start the scanning loop one by one in | |
756 | * the original callin order. | |
757 | * This way when there are any shared banks it will be | |
758 | * only seen by one CPU before cleared, avoiding duplicates. | |
759 | */ | |
760 | while (atomic_read(&mce_executing) < order) { | |
761 | if (mce_timed_out(&timeout)) { | |
762 | atomic_set(&global_nwo, 0); | |
763 | return -1; | |
764 | } | |
765 | ndelay(SPINUNIT); | |
766 | } | |
3c079792 AK |
767 | } |
768 | ||
769 | /* | |
7fb06fc9 | 770 | * Cache the global no_way_out state. |
3c079792 | 771 | */ |
7fb06fc9 HS |
772 | *no_way_out = atomic_read(&global_nwo); |
773 | ||
774 | return order; | |
3c079792 AK |
775 | } |
776 | ||
777 | /* | |
778 | * Synchronize between CPUs after main scanning loop. | |
779 | * This invokes the bulk of the Monarch processing. | |
780 | */ | |
781 | static int mce_end(int order) | |
782 | { | |
783 | int ret = -1; | |
784 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
785 | ||
786 | if (!timeout) | |
787 | goto reset; | |
788 | if (order < 0) | |
789 | goto reset; | |
790 | ||
791 | /* | |
792 | * Allow others to run. | |
793 | */ | |
794 | atomic_inc(&mce_executing); | |
795 | ||
796 | if (order == 1) { | |
797 | /* CHECKME: Can this race with a parallel hotplug? */ | |
798 | int cpus = num_online_cpus(); | |
799 | ||
800 | /* | |
801 | * Monarch: Wait for everyone to go through their scanning | |
802 | * loops. | |
803 | */ | |
804 | while (atomic_read(&mce_executing) <= cpus) { | |
805 | if (mce_timed_out(&timeout)) | |
806 | goto reset; | |
807 | ndelay(SPINUNIT); | |
808 | } | |
809 | ||
810 | mce_reign(); | |
811 | barrier(); | |
812 | ret = 0; | |
813 | } else { | |
814 | /* | |
815 | * Subject: Wait for Monarch to finish. | |
816 | */ | |
817 | while (atomic_read(&mce_executing) != 0) { | |
818 | if (mce_timed_out(&timeout)) | |
819 | goto reset; | |
820 | ndelay(SPINUNIT); | |
821 | } | |
822 | ||
823 | /* | |
824 | * Don't reset anything. That's done by the Monarch. | |
825 | */ | |
826 | return 0; | |
827 | } | |
828 | ||
829 | /* | |
830 | * Reset all global state. | |
831 | */ | |
832 | reset: | |
833 | atomic_set(&global_nwo, 0); | |
834 | atomic_set(&mce_callin, 0); | |
835 | barrier(); | |
836 | ||
837 | /* | |
838 | * Let others run again. | |
839 | */ | |
840 | atomic_set(&mce_executing, 0); | |
841 | return ret; | |
842 | } | |
843 | ||
9b1beaf2 AK |
844 | /* |
845 | * Check if the address reported by the CPU is in a format we can parse. | |
846 | * It would be possible to add code for most other cases, but all would | |
847 | * be somewhat complicated (e.g. segment offset would require an instruction | |
0d2eb44f | 848 | * parser). So only support physical addresses up to page granuality for now. |
9b1beaf2 AK |
849 | */ |
850 | static int mce_usable_address(struct mce *m) | |
851 | { | |
852 | if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) | |
853 | return 0; | |
2b90e77e | 854 | if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) |
9b1beaf2 | 855 | return 0; |
2b90e77e | 856 | if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) |
9b1beaf2 AK |
857 | return 0; |
858 | return 1; | |
859 | } | |
860 | ||
3c079792 AK |
861 | static void mce_clear_state(unsigned long *toclear) |
862 | { | |
863 | int i; | |
864 | ||
865 | for (i = 0; i < banks; i++) { | |
866 | if (test_bit(i, toclear)) | |
a2d32bcb | 867 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
3c079792 AK |
868 | } |
869 | } | |
870 | ||
b79109c3 AK |
871 | /* |
872 | * The actual machine check handler. This only handles real | |
873 | * exceptions when something got corrupted coming in through int 18. | |
874 | * | |
875 | * This is executed in NMI context not subject to normal locking rules. This | |
876 | * implies that most kernel services cannot be safely used. Don't even | |
877 | * think about putting a printk in there! | |
3c079792 AK |
878 | * |
879 | * On Intel systems this is entered on all CPUs in parallel through | |
880 | * MCE broadcast. However some CPUs might be broken beyond repair, | |
881 | * so be always careful when synchronizing with others. | |
1da177e4 | 882 | */ |
e9eee03e | 883 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 | 884 | { |
3c079792 | 885 | struct mce m, *final; |
1da177e4 | 886 | int i; |
3c079792 AK |
887 | int worst = 0; |
888 | int severity; | |
889 | /* | |
890 | * Establish sequential order between the CPUs entering the machine | |
891 | * check handler. | |
892 | */ | |
7fb06fc9 | 893 | int order; |
bd78432c TH |
894 | /* |
895 | * If no_way_out gets set, there is no safe way to recover from this | |
896 | * MCE. If tolerant is cranked up, we'll try anyway. | |
897 | */ | |
898 | int no_way_out = 0; | |
899 | /* | |
900 | * If kill_it gets set, there might be a way to recover from this | |
901 | * error. | |
902 | */ | |
903 | int kill_it = 0; | |
b79109c3 | 904 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
bd19a5e6 | 905 | char *msg = "Unknown"; |
1da177e4 | 906 | |
553f265f AK |
907 | atomic_inc(&mce_entry); |
908 | ||
402af0d7 | 909 | percpu_inc(mce_exception_count); |
01ca79f1 | 910 | |
b79109c3 | 911 | if (!banks) |
32561696 | 912 | goto out; |
1da177e4 | 913 | |
b8325c5b | 914 | mce_gather_info(&m, regs); |
b5f2fa4e | 915 | |
3c079792 AK |
916 | final = &__get_cpu_var(mces_seen); |
917 | *final = m; | |
918 | ||
680b6cfd HS |
919 | no_way_out = mce_no_way_out(&m, &msg); |
920 | ||
1da177e4 LT |
921 | barrier(); |
922 | ||
ed7290d0 AK |
923 | /* |
924 | * When no restart IP must always kill or panic. | |
925 | */ | |
926 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
927 | kill_it = 1; | |
928 | ||
3c079792 AK |
929 | /* |
930 | * Go through all the banks in exclusion of the other CPUs. | |
931 | * This way we don't report duplicated events on shared banks | |
932 | * because the first one to see it will clear it. | |
933 | */ | |
7fb06fc9 | 934 | order = mce_start(&no_way_out); |
1da177e4 | 935 | for (i = 0; i < banks; i++) { |
b79109c3 | 936 | __clear_bit(i, toclear); |
cebe1820 | 937 | if (!mce_banks[i].ctl) |
1da177e4 | 938 | continue; |
d88203d1 TG |
939 | |
940 | m.misc = 0; | |
1da177e4 LT |
941 | m.addr = 0; |
942 | m.bank = i; | |
1da177e4 | 943 | |
a2d32bcb | 944 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
1da177e4 LT |
945 | if ((m.status & MCI_STATUS_VAL) == 0) |
946 | continue; | |
947 | ||
b79109c3 | 948 | /* |
ed7290d0 AK |
949 | * Non uncorrected or non signaled errors are handled by |
950 | * machine_check_poll. Leave them alone, unless this panics. | |
b79109c3 | 951 | */ |
ed7290d0 AK |
952 | if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) && |
953 | !no_way_out) | |
b79109c3 AK |
954 | continue; |
955 | ||
956 | /* | |
957 | * Set taint even when machine check was not enabled. | |
958 | */ | |
959 | add_taint(TAINT_MACHINE_CHECK); | |
960 | ||
ed7290d0 | 961 | severity = mce_severity(&m, tolerant, NULL); |
b79109c3 | 962 | |
ed7290d0 AK |
963 | /* |
964 | * When machine check was for corrected handler don't touch, | |
965 | * unless we're panicing. | |
966 | */ | |
967 | if (severity == MCE_KEEP_SEVERITY && !no_way_out) | |
968 | continue; | |
969 | __set_bit(i, toclear); | |
970 | if (severity == MCE_NO_SEVERITY) { | |
b79109c3 AK |
971 | /* |
972 | * Machine check event was not enabled. Clear, but | |
973 | * ignore. | |
974 | */ | |
975 | continue; | |
1da177e4 LT |
976 | } |
977 | ||
ed7290d0 AK |
978 | /* |
979 | * Kill on action required. | |
980 | */ | |
981 | if (severity == MCE_AR_SEVERITY) | |
982 | kill_it = 1; | |
983 | ||
1da177e4 | 984 | if (m.status & MCI_STATUS_MISCV) |
a2d32bcb | 985 | m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); |
1da177e4 | 986 | if (m.status & MCI_STATUS_ADDRV) |
a2d32bcb | 987 | m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); |
1da177e4 | 988 | |
9b1beaf2 AK |
989 | /* |
990 | * Action optional error. Queue address for later processing. | |
991 | * When the ring overflows we just ignore the AO error. | |
992 | * RED-PEN add some logging mechanism when | |
993 | * usable_address or mce_add_ring fails. | |
994 | * RED-PEN don't ignore overflow for tolerant == 0 | |
995 | */ | |
996 | if (severity == MCE_AO_SEVERITY && mce_usable_address(&m)) | |
997 | mce_ring_add(m.addr >> PAGE_SHIFT); | |
998 | ||
b79109c3 | 999 | mce_log(&m); |
1da177e4 | 1000 | |
3c079792 AK |
1001 | if (severity > worst) { |
1002 | *final = m; | |
1003 | worst = severity; | |
1da177e4 | 1004 | } |
1da177e4 LT |
1005 | } |
1006 | ||
3c079792 AK |
1007 | if (!no_way_out) |
1008 | mce_clear_state(toclear); | |
1009 | ||
e9eee03e | 1010 | /* |
3c079792 AK |
1011 | * Do most of the synchronization with other CPUs. |
1012 | * When there's any problem use only local no_way_out state. | |
e9eee03e | 1013 | */ |
3c079792 AK |
1014 | if (mce_end(order) < 0) |
1015 | no_way_out = worst >= MCE_PANIC_SEVERITY; | |
bd78432c TH |
1016 | |
1017 | /* | |
1018 | * If we have decided that we just CAN'T continue, and the user | |
e9eee03e | 1019 | * has not set tolerant to an insane level, give up and die. |
3c079792 AK |
1020 | * |
1021 | * This is mainly used in the case when the system doesn't | |
1022 | * support MCE broadcasting or it has been disabled. | |
bd78432c TH |
1023 | */ |
1024 | if (no_way_out && tolerant < 3) | |
ac960375 | 1025 | mce_panic("Fatal machine check on current CPU", final, msg); |
bd78432c TH |
1026 | |
1027 | /* | |
1028 | * If the error seems to be unrecoverable, something should be | |
1029 | * done. Try to kill as little as possible. If we can kill just | |
1030 | * one task, do that. If the user has set the tolerance very | |
1031 | * high, don't try to do anything at all. | |
1032 | */ | |
bd78432c | 1033 | |
ed7290d0 AK |
1034 | if (kill_it && tolerant < 3) |
1035 | force_sig(SIGBUS, current); | |
1da177e4 | 1036 | |
e02e68d3 TH |
1037 | /* notify userspace ASAP */ |
1038 | set_thread_flag(TIF_MCE_NOTIFY); | |
1039 | ||
3c079792 AK |
1040 | if (worst > 0) |
1041 | mce_report_event(regs); | |
5f8c1a54 | 1042 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 1043 | out: |
553f265f | 1044 | atomic_dec(&mce_entry); |
88921be3 | 1045 | sync_core(); |
1da177e4 | 1046 | } |
ea149b36 | 1047 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 1048 | |
9b1beaf2 AK |
1049 | /* dummy to break dependency. actual code is in mm/memory-failure.c */ |
1050 | void __attribute__((weak)) memory_failure(unsigned long pfn, int vector) | |
1051 | { | |
1052 | printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn); | |
1053 | } | |
1054 | ||
1055 | /* | |
1056 | * Called after mce notification in process context. This code | |
1057 | * is allowed to sleep. Call the high level VM handler to process | |
1058 | * any corrupted pages. | |
1059 | * Assume that the work queue code only calls this one at a time | |
1060 | * per CPU. | |
1061 | * Note we don't disable preemption, so this code might run on the wrong | |
1062 | * CPU. In this case the event is picked up by the scheduled work queue. | |
1063 | * This is merely a fast path to expedite processing in some common | |
1064 | * cases. | |
1065 | */ | |
1066 | void mce_notify_process(void) | |
1067 | { | |
1068 | unsigned long pfn; | |
1069 | mce_notify_irq(); | |
1070 | while (mce_ring_get(&pfn)) | |
1071 | memory_failure(pfn, MCE_VECTOR); | |
1072 | } | |
1073 | ||
1074 | static void mce_process_work(struct work_struct *dummy) | |
1075 | { | |
1076 | mce_notify_process(); | |
1077 | } | |
1078 | ||
15d5f839 DZ |
1079 | #ifdef CONFIG_X86_MCE_INTEL |
1080 | /*** | |
1081 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 1082 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
1083 | * @status: Event status information |
1084 | * | |
1085 | * This function should be called by the thermal interrupt after the | |
1086 | * event has been processed and the decision was made to log the event | |
1087 | * further. | |
1088 | * | |
1089 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
1090 | * and historically has been the register value of the | |
1091 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
1092 | */ | |
b5f2fa4e | 1093 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
1094 | { |
1095 | struct mce m; | |
1096 | ||
b5f2fa4e | 1097 | mce_setup(&m); |
15d5f839 DZ |
1098 | m.bank = MCE_THERMAL_BANK; |
1099 | m.status = status; | |
15d5f839 DZ |
1100 | mce_log(&m); |
1101 | } | |
1102 | #endif /* CONFIG_X86_MCE_INTEL */ | |
1103 | ||
1da177e4 | 1104 | /* |
8a336b0a TH |
1105 | * Periodic polling timer for "silent" machine check errors. If the |
1106 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
1107 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 1108 | */ |
1da177e4 | 1109 | static int check_interval = 5 * 60; /* 5 minutes */ |
e9eee03e | 1110 | |
245b2e70 | 1111 | static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */ |
52d168e2 | 1112 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 1113 | |
5e09954a | 1114 | static void mce_start_timer(unsigned long data) |
1da177e4 | 1115 | { |
52d168e2 | 1116 | struct timer_list *t = &per_cpu(mce_timer, data); |
6298c512 | 1117 | int *n; |
52d168e2 AK |
1118 | |
1119 | WARN_ON(smp_processor_id() != data); | |
1120 | ||
7b543a53 | 1121 | if (mce_available(__this_cpu_ptr(&cpu_info))) { |
ee031c31 AK |
1122 | machine_check_poll(MCP_TIMESTAMP, |
1123 | &__get_cpu_var(mce_poll_banks)); | |
e9eee03e | 1124 | } |
1da177e4 LT |
1125 | |
1126 | /* | |
e02e68d3 TH |
1127 | * Alert userspace if needed. If we logged an MCE, reduce the |
1128 | * polling interval, otherwise increase the polling interval. | |
1da177e4 | 1129 | */ |
245b2e70 | 1130 | n = &__get_cpu_var(mce_next_interval); |
9ff36ee9 | 1131 | if (mce_notify_irq()) |
6298c512 | 1132 | *n = max(*n/2, HZ/100); |
14a02530 | 1133 | else |
6298c512 | 1134 | *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ)); |
e02e68d3 | 1135 | |
6298c512 | 1136 | t->expires = jiffies + *n; |
5be6066a | 1137 | add_timer_on(t, smp_processor_id()); |
e02e68d3 TH |
1138 | } |
1139 | ||
9aaef96f HS |
1140 | /* Must not be called in IRQ context where del_timer_sync() can deadlock */ |
1141 | static void mce_timer_delete_all(void) | |
1142 | { | |
1143 | int cpu; | |
1144 | ||
1145 | for_each_online_cpu(cpu) | |
1146 | del_timer_sync(&per_cpu(mce_timer, cpu)); | |
1147 | } | |
1148 | ||
9bd98405 AK |
1149 | static void mce_do_trigger(struct work_struct *work) |
1150 | { | |
1020bcbc | 1151 | call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT); |
9bd98405 AK |
1152 | } |
1153 | ||
1154 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
1155 | ||
e02e68d3 | 1156 | /* |
9bd98405 AK |
1157 | * Notify the user(s) about new machine check events. |
1158 | * Can be called from interrupt context, but not from machine check/NMI | |
1159 | * context. | |
e02e68d3 | 1160 | */ |
9ff36ee9 | 1161 | int mce_notify_irq(void) |
e02e68d3 | 1162 | { |
8457c84d AK |
1163 | /* Not more than two messages every minute */ |
1164 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
1165 | ||
e02e68d3 | 1166 | clear_thread_flag(TIF_MCE_NOTIFY); |
e9eee03e | 1167 | |
1020bcbc | 1168 | if (test_and_clear_bit(0, &mce_need_notify)) { |
93b62c3c HS |
1169 | /* wake processes polling /dev/mcelog */ |
1170 | wake_up_interruptible(&mce_chrdev_wait); | |
9bd98405 AK |
1171 | |
1172 | /* | |
1173 | * There is no risk of missing notifications because | |
1174 | * work_pending is always cleared before the function is | |
1175 | * executed. | |
1176 | */ | |
1020bcbc | 1177 | if (mce_helper[0] && !work_pending(&mce_trigger_work)) |
9bd98405 | 1178 | schedule_work(&mce_trigger_work); |
e02e68d3 | 1179 | |
8457c84d | 1180 | if (__ratelimit(&ratelimit)) |
a2d7b0d4 | 1181 | pr_info(HW_ERR "Machine check events logged\n"); |
e02e68d3 TH |
1182 | |
1183 | return 1; | |
1da177e4 | 1184 | } |
e02e68d3 TH |
1185 | return 0; |
1186 | } | |
9ff36ee9 | 1187 | EXPORT_SYMBOL_GPL(mce_notify_irq); |
8a336b0a | 1188 | |
cffd377e | 1189 | static int __cpuinit __mcheck_cpu_mce_banks_init(void) |
cebe1820 AK |
1190 | { |
1191 | int i; | |
1192 | ||
1193 | mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL); | |
1194 | if (!mce_banks) | |
1195 | return -ENOMEM; | |
1196 | for (i = 0; i < banks; i++) { | |
1197 | struct mce_bank *b = &mce_banks[i]; | |
11868a2d | 1198 | |
cebe1820 AK |
1199 | b->ctl = -1ULL; |
1200 | b->init = 1; | |
1201 | } | |
1202 | return 0; | |
1203 | } | |
1204 | ||
d88203d1 | 1205 | /* |
1da177e4 LT |
1206 | * Initialize Machine Checks for a CPU. |
1207 | */ | |
5e09954a | 1208 | static int __cpuinit __mcheck_cpu_cap_init(void) |
1da177e4 | 1209 | { |
0d7482e3 | 1210 | unsigned b; |
e9eee03e | 1211 | u64 cap; |
1da177e4 LT |
1212 | |
1213 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
1214 | |
1215 | b = cap & MCG_BANKCNT_MASK; | |
93ae5012 RD |
1216 | if (!banks) |
1217 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b); | |
b659294b | 1218 | |
0d7482e3 AK |
1219 | if (b > MAX_NR_BANKS) { |
1220 | printk(KERN_WARNING | |
1221 | "MCE: Using only %u machine check banks out of %u\n", | |
1222 | MAX_NR_BANKS, b); | |
1223 | b = MAX_NR_BANKS; | |
1224 | } | |
1225 | ||
1226 | /* Don't support asymmetric configurations today */ | |
1227 | WARN_ON(banks != 0 && b != banks); | |
1228 | banks = b; | |
cebe1820 | 1229 | if (!mce_banks) { |
cffd377e | 1230 | int err = __mcheck_cpu_mce_banks_init(); |
11868a2d | 1231 | |
cebe1820 AK |
1232 | if (err) |
1233 | return err; | |
1da177e4 | 1234 | } |
0d7482e3 | 1235 | |
94ad8474 | 1236 | /* Use accurate RIP reporting if available. */ |
01c6680a | 1237 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
94ad8474 | 1238 | rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 1239 | |
ed7290d0 AK |
1240 | if (cap & MCG_SER_P) |
1241 | mce_ser = 1; | |
1242 | ||
0d7482e3 AK |
1243 | return 0; |
1244 | } | |
1245 | ||
5e09954a | 1246 | static void __mcheck_cpu_init_generic(void) |
0d7482e3 | 1247 | { |
e9eee03e | 1248 | mce_banks_t all_banks; |
0d7482e3 AK |
1249 | u64 cap; |
1250 | int i; | |
1251 | ||
b79109c3 AK |
1252 | /* |
1253 | * Log the machine checks left over from the previous reset. | |
1254 | */ | |
ee031c31 | 1255 | bitmap_fill(all_banks, MAX_NR_BANKS); |
5679af4c | 1256 | machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks); |
1da177e4 LT |
1257 | |
1258 | set_in_cr4(X86_CR4_MCE); | |
1259 | ||
0d7482e3 | 1260 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
1261 | if (cap & MCG_CTL_P) |
1262 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
1263 | ||
1264 | for (i = 0; i < banks; i++) { | |
cebe1820 | 1265 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1266 | |
cebe1820 | 1267 | if (!b->init) |
06b7a7a5 | 1268 | continue; |
a2d32bcb AK |
1269 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
1270 | wrmsrl(MSR_IA32_MCx_STATUS(i), 0); | |
d88203d1 | 1271 | } |
1da177e4 LT |
1272 | } |
1273 | ||
1274 | /* Add per CPU specific workarounds here */ | |
5e09954a | 1275 | static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 1276 | { |
e412cd25 IM |
1277 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { |
1278 | pr_info("MCE: unknown CPU type - not enabling MCE support.\n"); | |
1279 | return -EOPNOTSUPP; | |
1280 | } | |
1281 | ||
1da177e4 | 1282 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 1283 | if (c->x86_vendor == X86_VENDOR_AMD) { |
e9eee03e IM |
1284 | if (c->x86 == 15 && banks > 4) { |
1285 | /* | |
1286 | * disable GART TBL walk error reporting, which | |
1287 | * trips off incorrectly with the IOMMU & 3ware | |
1288 | * & Cerberus: | |
1289 | */ | |
cebe1820 | 1290 | clear_bit(10, (unsigned long *)&mce_banks[4].ctl); |
e9eee03e IM |
1291 | } |
1292 | if (c->x86 <= 17 && mce_bootlog < 0) { | |
1293 | /* | |
1294 | * Lots of broken BIOS around that don't clear them | |
1295 | * by default and leave crap in there. Don't log: | |
1296 | */ | |
911f6a7b | 1297 | mce_bootlog = 0; |
e9eee03e | 1298 | } |
2e6f694f AK |
1299 | /* |
1300 | * Various K7s with broken bank 0 around. Always disable | |
1301 | * by default. | |
1302 | */ | |
203abd67 | 1303 | if (c->x86 == 6 && banks > 0) |
cebe1820 | 1304 | mce_banks[0].ctl = 0; |
1da177e4 | 1305 | } |
e583538f | 1306 | |
06b7a7a5 AK |
1307 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
1308 | /* | |
1309 | * SDM documents that on family 6 bank 0 should not be written | |
1310 | * because it aliases to another special BIOS controlled | |
1311 | * register. | |
1312 | * But it's not aliased anymore on model 0x1a+ | |
1313 | * Don't ignore bank 0 completely because there could be a | |
1314 | * valid event later, merely don't write CTL0. | |
1315 | */ | |
1316 | ||
cebe1820 AK |
1317 | if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0) |
1318 | mce_banks[0].init = 0; | |
3c079792 AK |
1319 | |
1320 | /* | |
1321 | * All newer Intel systems support MCE broadcasting. Enable | |
1322 | * synchronization with a one second timeout. | |
1323 | */ | |
1324 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && | |
1325 | monarch_timeout < 0) | |
1326 | monarch_timeout = USEC_PER_SEC; | |
c7f6fa44 | 1327 | |
e412cd25 IM |
1328 | /* |
1329 | * There are also broken BIOSes on some Pentium M and | |
1330 | * earlier systems: | |
1331 | */ | |
1332 | if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0) | |
c7f6fa44 | 1333 | mce_bootlog = 0; |
06b7a7a5 | 1334 | } |
3c079792 AK |
1335 | if (monarch_timeout < 0) |
1336 | monarch_timeout = 0; | |
29b0f591 AK |
1337 | if (mce_bootlog != 0) |
1338 | mce_panic_timeout = 30; | |
e412cd25 IM |
1339 | |
1340 | return 0; | |
d88203d1 | 1341 | } |
1da177e4 | 1342 | |
3a97fc34 | 1343 | static int __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) |
4efc0670 AK |
1344 | { |
1345 | if (c->x86 != 5) | |
3a97fc34 HS |
1346 | return 0; |
1347 | ||
4efc0670 AK |
1348 | switch (c->x86_vendor) { |
1349 | case X86_VENDOR_INTEL: | |
c6978369 | 1350 | intel_p5_mcheck_init(c); |
3a97fc34 | 1351 | return 1; |
4efc0670 AK |
1352 | break; |
1353 | case X86_VENDOR_CENTAUR: | |
1354 | winchip_mcheck_init(c); | |
3a97fc34 | 1355 | return 1; |
4efc0670 AK |
1356 | break; |
1357 | } | |
3a97fc34 HS |
1358 | |
1359 | return 0; | |
4efc0670 AK |
1360 | } |
1361 | ||
5e09954a | 1362 | static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
1363 | { |
1364 | switch (c->x86_vendor) { | |
1365 | case X86_VENDOR_INTEL: | |
1366 | mce_intel_feature_init(c); | |
1367 | break; | |
89b831ef JS |
1368 | case X86_VENDOR_AMD: |
1369 | mce_amd_feature_init(c); | |
1370 | break; | |
1da177e4 LT |
1371 | default: |
1372 | break; | |
1373 | } | |
1374 | } | |
1375 | ||
5e09954a | 1376 | static void __mcheck_cpu_init_timer(void) |
52d168e2 AK |
1377 | { |
1378 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
245b2e70 | 1379 | int *n = &__get_cpu_var(mce_next_interval); |
52d168e2 | 1380 | |
bc09effa JB |
1381 | setup_timer(t, mce_start_timer, smp_processor_id()); |
1382 | ||
62fdac59 HS |
1383 | if (mce_ignore_ce) |
1384 | return; | |
1385 | ||
6298c512 AK |
1386 | *n = check_interval * HZ; |
1387 | if (!*n) | |
52d168e2 | 1388 | return; |
6298c512 | 1389 | t->expires = round_jiffies(jiffies + *n); |
5be6066a | 1390 | add_timer_on(t, smp_processor_id()); |
52d168e2 AK |
1391 | } |
1392 | ||
9eda8cb3 AK |
1393 | /* Handle unconfigured int18 (should never happen) */ |
1394 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
1395 | { | |
1396 | printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n", | |
1397 | smp_processor_id()); | |
1398 | } | |
1399 | ||
1400 | /* Call the installed machine check handler for this CPU setup. */ | |
1401 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
1402 | unexpected_machine_check; | |
1403 | ||
d88203d1 | 1404 | /* |
1da177e4 | 1405 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 1406 | * Must be called with preempt off: |
1da177e4 | 1407 | */ |
5e09954a | 1408 | void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c) |
1da177e4 | 1409 | { |
4efc0670 AK |
1410 | if (mce_disabled) |
1411 | return; | |
1412 | ||
3a97fc34 HS |
1413 | if (__mcheck_cpu_ancient_init(c)) |
1414 | return; | |
4efc0670 | 1415 | |
5b4408fd | 1416 | if (!mce_available(c)) |
1da177e4 LT |
1417 | return; |
1418 | ||
5e09954a | 1419 | if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) { |
04b2b1a4 | 1420 | mce_disabled = 1; |
0d7482e3 AK |
1421 | return; |
1422 | } | |
0d7482e3 | 1423 | |
5d727926 AK |
1424 | machine_check_vector = do_machine_check; |
1425 | ||
5e09954a BP |
1426 | __mcheck_cpu_init_generic(); |
1427 | __mcheck_cpu_init_vendor(c); | |
1428 | __mcheck_cpu_init_timer(); | |
9b1beaf2 | 1429 | INIT_WORK(&__get_cpu_var(mce_work), mce_process_work); |
b77e70bf | 1430 | init_irq_work(&__get_cpu_var(mce_irq_work), &mce_irq_work_cb); |
1da177e4 LT |
1431 | } |
1432 | ||
1433 | /* | |
93b62c3c | 1434 | * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log. |
1da177e4 LT |
1435 | */ |
1436 | ||
93b62c3c HS |
1437 | static DEFINE_SPINLOCK(mce_chrdev_state_lock); |
1438 | static int mce_chrdev_open_count; /* #times opened */ | |
1439 | static int mce_chrdev_open_exclu; /* already open exclusive? */ | |
f528e7ba | 1440 | |
93b62c3c | 1441 | static int mce_chrdev_open(struct inode *inode, struct file *file) |
f528e7ba | 1442 | { |
93b62c3c | 1443 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1444 | |
93b62c3c HS |
1445 | if (mce_chrdev_open_exclu || |
1446 | (mce_chrdev_open_count && (file->f_flags & O_EXCL))) { | |
1447 | spin_unlock(&mce_chrdev_state_lock); | |
e9eee03e | 1448 | |
f528e7ba TH |
1449 | return -EBUSY; |
1450 | } | |
1451 | ||
1452 | if (file->f_flags & O_EXCL) | |
93b62c3c HS |
1453 | mce_chrdev_open_exclu = 1; |
1454 | mce_chrdev_open_count++; | |
f528e7ba | 1455 | |
93b62c3c | 1456 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba | 1457 | |
bd78432c | 1458 | return nonseekable_open(inode, file); |
f528e7ba TH |
1459 | } |
1460 | ||
93b62c3c | 1461 | static int mce_chrdev_release(struct inode *inode, struct file *file) |
f528e7ba | 1462 | { |
93b62c3c | 1463 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1464 | |
93b62c3c HS |
1465 | mce_chrdev_open_count--; |
1466 | mce_chrdev_open_exclu = 0; | |
f528e7ba | 1467 | |
93b62c3c | 1468 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba TH |
1469 | |
1470 | return 0; | |
1471 | } | |
1472 | ||
d88203d1 TG |
1473 | static void collect_tscs(void *data) |
1474 | { | |
1da177e4 | 1475 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 1476 | |
1da177e4 | 1477 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 1478 | } |
1da177e4 | 1479 | |
482908b4 HY |
1480 | static int mce_apei_read_done; |
1481 | ||
1482 | /* Collect MCE record of previous boot in persistent storage via APEI ERST. */ | |
1483 | static int __mce_read_apei(char __user **ubuf, size_t usize) | |
1484 | { | |
1485 | int rc; | |
1486 | u64 record_id; | |
1487 | struct mce m; | |
1488 | ||
1489 | if (usize < sizeof(struct mce)) | |
1490 | return -EINVAL; | |
1491 | ||
1492 | rc = apei_read_mce(&m, &record_id); | |
1493 | /* Error or no more MCE record */ | |
1494 | if (rc <= 0) { | |
1495 | mce_apei_read_done = 1; | |
1496 | return rc; | |
1497 | } | |
1498 | rc = -EFAULT; | |
1499 | if (copy_to_user(*ubuf, &m, sizeof(struct mce))) | |
1500 | return rc; | |
1501 | /* | |
1502 | * In fact, we should have cleared the record after that has | |
1503 | * been flushed to the disk or sent to network in | |
1504 | * /sbin/mcelog, but we have no interface to support that now, | |
1505 | * so just clear it to avoid duplication. | |
1506 | */ | |
1507 | rc = apei_clear_mce(record_id); | |
1508 | if (rc) { | |
1509 | mce_apei_read_done = 1; | |
1510 | return rc; | |
1511 | } | |
1512 | *ubuf += sizeof(struct mce); | |
1513 | ||
1514 | return 0; | |
1515 | } | |
1516 | ||
93b62c3c HS |
1517 | static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf, |
1518 | size_t usize, loff_t *off) | |
1da177e4 | 1519 | { |
e9eee03e | 1520 | char __user *buf = ubuf; |
f0de53bb | 1521 | unsigned long *cpu_tsc; |
ef41df43 | 1522 | unsigned prev, next; |
1da177e4 LT |
1523 | int i, err; |
1524 | ||
6bca67f9 | 1525 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
1526 | if (!cpu_tsc) |
1527 | return -ENOMEM; | |
1528 | ||
93b62c3c | 1529 | mutex_lock(&mce_chrdev_read_mutex); |
482908b4 HY |
1530 | |
1531 | if (!mce_apei_read_done) { | |
1532 | err = __mce_read_apei(&buf, usize); | |
1533 | if (err || buf != ubuf) | |
1534 | goto out; | |
1535 | } | |
1536 | ||
f56e8a07 | 1537 | next = rcu_dereference_check_mce(mcelog.next); |
1da177e4 LT |
1538 | |
1539 | /* Only supports full reads right now */ | |
482908b4 HY |
1540 | err = -EINVAL; |
1541 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) | |
1542 | goto out; | |
1da177e4 LT |
1543 | |
1544 | err = 0; | |
ef41df43 HY |
1545 | prev = 0; |
1546 | do { | |
1547 | for (i = prev; i < next; i++) { | |
1548 | unsigned long start = jiffies; | |
559faa6b | 1549 | struct mce *m = &mcelog.entry[i]; |
ef41df43 | 1550 | |
559faa6b | 1551 | while (!m->finished) { |
ef41df43 | 1552 | if (time_after_eq(jiffies, start + 2)) { |
559faa6b | 1553 | memset(m, 0, sizeof(*m)); |
ef41df43 HY |
1554 | goto timeout; |
1555 | } | |
1556 | cpu_relax(); | |
673242c1 | 1557 | } |
ef41df43 | 1558 | smp_rmb(); |
559faa6b HS |
1559 | err |= copy_to_user(buf, m, sizeof(*m)); |
1560 | buf += sizeof(*m); | |
ef41df43 HY |
1561 | timeout: |
1562 | ; | |
673242c1 | 1563 | } |
1da177e4 | 1564 | |
ef41df43 HY |
1565 | memset(mcelog.entry + prev, 0, |
1566 | (next - prev) * sizeof(struct mce)); | |
1567 | prev = next; | |
1568 | next = cmpxchg(&mcelog.next, prev, 0); | |
1569 | } while (next != prev); | |
1da177e4 | 1570 | |
b2b18660 | 1571 | synchronize_sched(); |
1da177e4 | 1572 | |
d88203d1 TG |
1573 | /* |
1574 | * Collect entries that were still getting written before the | |
1575 | * synchronize. | |
1576 | */ | |
15c8b6c1 | 1577 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 1578 | |
d88203d1 | 1579 | for (i = next; i < MCE_LOG_LEN; i++) { |
559faa6b HS |
1580 | struct mce *m = &mcelog.entry[i]; |
1581 | ||
1582 | if (m->finished && m->tsc < cpu_tsc[m->cpu]) { | |
1583 | err |= copy_to_user(buf, m, sizeof(*m)); | |
1da177e4 | 1584 | smp_rmb(); |
559faa6b HS |
1585 | buf += sizeof(*m); |
1586 | memset(m, 0, sizeof(*m)); | |
1da177e4 | 1587 | } |
d88203d1 | 1588 | } |
482908b4 HY |
1589 | |
1590 | if (err) | |
1591 | err = -EFAULT; | |
1592 | ||
1593 | out: | |
93b62c3c | 1594 | mutex_unlock(&mce_chrdev_read_mutex); |
f0de53bb | 1595 | kfree(cpu_tsc); |
e9eee03e | 1596 | |
482908b4 | 1597 | return err ? err : buf - ubuf; |
1da177e4 LT |
1598 | } |
1599 | ||
93b62c3c | 1600 | static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait) |
e02e68d3 | 1601 | { |
93b62c3c | 1602 | poll_wait(file, &mce_chrdev_wait, wait); |
a4dd9925 | 1603 | if (rcu_access_index(mcelog.next)) |
e02e68d3 | 1604 | return POLLIN | POLLRDNORM; |
482908b4 HY |
1605 | if (!mce_apei_read_done && apei_check_mce()) |
1606 | return POLLIN | POLLRDNORM; | |
e02e68d3 TH |
1607 | return 0; |
1608 | } | |
1609 | ||
93b62c3c HS |
1610 | static long mce_chrdev_ioctl(struct file *f, unsigned int cmd, |
1611 | unsigned long arg) | |
1da177e4 LT |
1612 | { |
1613 | int __user *p = (int __user *)arg; | |
d88203d1 | 1614 | |
1da177e4 | 1615 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 1616 | return -EPERM; |
e9eee03e | 1617 | |
1da177e4 | 1618 | switch (cmd) { |
d88203d1 | 1619 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
1620 | return put_user(sizeof(struct mce), p); |
1621 | case MCE_GET_LOG_LEN: | |
d88203d1 | 1622 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
1623 | case MCE_GETCLEAR_FLAGS: { |
1624 | unsigned flags; | |
d88203d1 TG |
1625 | |
1626 | do { | |
1da177e4 | 1627 | flags = mcelog.flags; |
d88203d1 | 1628 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 1629 | |
d88203d1 | 1630 | return put_user(flags, p); |
1da177e4 LT |
1631 | } |
1632 | default: | |
d88203d1 TG |
1633 | return -ENOTTY; |
1634 | } | |
1da177e4 LT |
1635 | } |
1636 | ||
a1ff41bf | 1637 | /* Modified in mce-inject.c, so not static or const */ |
ea149b36 | 1638 | struct file_operations mce_chrdev_ops = { |
93b62c3c HS |
1639 | .open = mce_chrdev_open, |
1640 | .release = mce_chrdev_release, | |
1641 | .read = mce_chrdev_read, | |
1642 | .poll = mce_chrdev_poll, | |
1643 | .unlocked_ioctl = mce_chrdev_ioctl, | |
1644 | .llseek = no_llseek, | |
1da177e4 | 1645 | }; |
ea149b36 | 1646 | EXPORT_SYMBOL_GPL(mce_chrdev_ops); |
1da177e4 | 1647 | |
93b62c3c | 1648 | static struct miscdevice mce_chrdev_device = { |
1da177e4 LT |
1649 | MISC_MCELOG_MINOR, |
1650 | "mcelog", | |
1651 | &mce_chrdev_ops, | |
1652 | }; | |
1653 | ||
13503fa9 | 1654 | /* |
62fdac59 HS |
1655 | * mce=off Disables machine check |
1656 | * mce=no_cmci Disables CMCI | |
1657 | * mce=dont_log_ce Clears corrected events silently, no log created for CEs. | |
1658 | * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. | |
3c079792 AK |
1659 | * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) |
1660 | * monarchtimeout is how long to wait for other CPUs on machine | |
1661 | * check, or 0 to not wait | |
13503fa9 HS |
1662 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. |
1663 | * mce=nobootlog Don't log MCEs from before booting. | |
1664 | */ | |
1da177e4 LT |
1665 | static int __init mcheck_enable(char *str) |
1666 | { | |
e3346fc4 | 1667 | if (*str == 0) { |
4efc0670 | 1668 | enable_p5_mce(); |
e3346fc4 BZ |
1669 | return 1; |
1670 | } | |
4efc0670 AK |
1671 | if (*str == '=') |
1672 | str++; | |
1da177e4 | 1673 | if (!strcmp(str, "off")) |
04b2b1a4 | 1674 | mce_disabled = 1; |
62fdac59 HS |
1675 | else if (!strcmp(str, "no_cmci")) |
1676 | mce_cmci_disabled = 1; | |
1677 | else if (!strcmp(str, "dont_log_ce")) | |
1678 | mce_dont_log_ce = 1; | |
1679 | else if (!strcmp(str, "ignore_ce")) | |
1680 | mce_ignore_ce = 1; | |
13503fa9 HS |
1681 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
1682 | mce_bootlog = (str[0] == 'b'); | |
3c079792 | 1683 | else if (isdigit(str[0])) { |
8c566ef5 | 1684 | get_option(&str, &tolerant); |
3c079792 AK |
1685 | if (*str == ',') { |
1686 | ++str; | |
1687 | get_option(&str, &monarch_timeout); | |
1688 | } | |
1689 | } else { | |
4efc0670 | 1690 | printk(KERN_INFO "mce argument %s ignored. Please use /sys\n", |
13503fa9 HS |
1691 | str); |
1692 | return 0; | |
1693 | } | |
9b41046c | 1694 | return 1; |
1da177e4 | 1695 | } |
4efc0670 | 1696 | __setup("mce", mcheck_enable); |
1da177e4 | 1697 | |
a2202aa2 | 1698 | int __init mcheck_init(void) |
b33a6363 | 1699 | { |
a2202aa2 YW |
1700 | mcheck_intel_therm_init(); |
1701 | ||
b33a6363 BP |
1702 | return 0; |
1703 | } | |
b33a6363 | 1704 | |
d88203d1 | 1705 | /* |
c7cece89 | 1706 | * mce_syscore: PM support |
d88203d1 | 1707 | */ |
1da177e4 | 1708 | |
973a2dd1 AK |
1709 | /* |
1710 | * Disable machine checks on suspend and shutdown. We can't really handle | |
1711 | * them later. | |
1712 | */ | |
5e09954a | 1713 | static int mce_disable_error_reporting(void) |
973a2dd1 AK |
1714 | { |
1715 | int i; | |
1716 | ||
06b7a7a5 | 1717 | for (i = 0; i < banks; i++) { |
cebe1820 | 1718 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1719 | |
cebe1820 | 1720 | if (b->init) |
a2d32bcb | 1721 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 1722 | } |
973a2dd1 AK |
1723 | return 0; |
1724 | } | |
1725 | ||
c7cece89 | 1726 | static int mce_syscore_suspend(void) |
973a2dd1 | 1727 | { |
5e09954a | 1728 | return mce_disable_error_reporting(); |
973a2dd1 AK |
1729 | } |
1730 | ||
c7cece89 | 1731 | static void mce_syscore_shutdown(void) |
973a2dd1 | 1732 | { |
f3c6ea1b | 1733 | mce_disable_error_reporting(); |
973a2dd1 AK |
1734 | } |
1735 | ||
e9eee03e IM |
1736 | /* |
1737 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
1738 | * Only one CPU is active at this time, the others get re-added later using | |
1739 | * CPU hotplug: | |
1740 | */ | |
c7cece89 | 1741 | static void mce_syscore_resume(void) |
1da177e4 | 1742 | { |
5e09954a | 1743 | __mcheck_cpu_init_generic(); |
7b543a53 | 1744 | __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info)); |
1da177e4 LT |
1745 | } |
1746 | ||
f3c6ea1b | 1747 | static struct syscore_ops mce_syscore_ops = { |
c7cece89 HS |
1748 | .suspend = mce_syscore_suspend, |
1749 | .shutdown = mce_syscore_shutdown, | |
1750 | .resume = mce_syscore_resume, | |
f3c6ea1b RW |
1751 | }; |
1752 | ||
c7cece89 HS |
1753 | /* |
1754 | * mce_sysdev: Sysfs support | |
1755 | */ | |
1756 | ||
52d168e2 AK |
1757 | static void mce_cpu_restart(void *data) |
1758 | { | |
7b543a53 | 1759 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
33edbf02 | 1760 | return; |
5e09954a BP |
1761 | __mcheck_cpu_init_generic(); |
1762 | __mcheck_cpu_init_timer(); | |
52d168e2 AK |
1763 | } |
1764 | ||
1da177e4 | 1765 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
1766 | static void mce_restart(void) |
1767 | { | |
9aaef96f | 1768 | mce_timer_delete_all(); |
52d168e2 | 1769 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
1770 | } |
1771 | ||
9af43b54 | 1772 | /* Toggle features for corrected errors */ |
9aaef96f | 1773 | static void mce_disable_cmci(void *data) |
9af43b54 | 1774 | { |
7b543a53 | 1775 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
9af43b54 | 1776 | return; |
9af43b54 HS |
1777 | cmci_clear(); |
1778 | } | |
1779 | ||
1780 | static void mce_enable_ce(void *all) | |
1781 | { | |
7b543a53 | 1782 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
9af43b54 HS |
1783 | return; |
1784 | cmci_reenable(); | |
1785 | cmci_recheck(); | |
1786 | if (all) | |
5e09954a | 1787 | __mcheck_cpu_init_timer(); |
9af43b54 HS |
1788 | } |
1789 | ||
c7cece89 | 1790 | static struct sysdev_class mce_sysdev_class = { |
e9eee03e | 1791 | .name = "machinecheck", |
1da177e4 LT |
1792 | }; |
1793 | ||
c7cece89 | 1794 | DEFINE_PER_CPU(struct sys_device, mce_sysdev); |
e9eee03e IM |
1795 | |
1796 | __cpuinitdata | |
1797 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); | |
1da177e4 | 1798 | |
cebe1820 AK |
1799 | static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr) |
1800 | { | |
1801 | return container_of(attr, struct mce_bank, attr); | |
1802 | } | |
0d7482e3 AK |
1803 | |
1804 | static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
1805 | char *buf) | |
1806 | { | |
cebe1820 | 1807 | return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl); |
0d7482e3 AK |
1808 | } |
1809 | ||
1810 | static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
9319cec8 | 1811 | const char *buf, size_t size) |
0d7482e3 | 1812 | { |
9319cec8 | 1813 | u64 new; |
e9eee03e | 1814 | |
9319cec8 | 1815 | if (strict_strtoull(buf, 0, &new) < 0) |
0d7482e3 | 1816 | return -EINVAL; |
e9eee03e | 1817 | |
cebe1820 | 1818 | attr_to_bank(attr)->ctl = new; |
0d7482e3 | 1819 | mce_restart(); |
e9eee03e | 1820 | |
9319cec8 | 1821 | return size; |
0d7482e3 | 1822 | } |
a98f0dd3 | 1823 | |
e9eee03e IM |
1824 | static ssize_t |
1825 | show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf) | |
a98f0dd3 | 1826 | { |
1020bcbc | 1827 | strcpy(buf, mce_helper); |
a98f0dd3 | 1828 | strcat(buf, "\n"); |
1020bcbc | 1829 | return strlen(mce_helper) + 1; |
a98f0dd3 AK |
1830 | } |
1831 | ||
4a0b2b4d | 1832 | static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr, |
e9eee03e | 1833 | const char *buf, size_t siz) |
a98f0dd3 AK |
1834 | { |
1835 | char *p; | |
e9eee03e | 1836 | |
1020bcbc HS |
1837 | strncpy(mce_helper, buf, sizeof(mce_helper)); |
1838 | mce_helper[sizeof(mce_helper)-1] = 0; | |
1020bcbc | 1839 | p = strchr(mce_helper, '\n'); |
e9eee03e | 1840 | |
e9084ec9 | 1841 | if (p) |
e9eee03e IM |
1842 | *p = 0; |
1843 | ||
e9084ec9 | 1844 | return strlen(mce_helper) + !!p; |
a98f0dd3 AK |
1845 | } |
1846 | ||
9af43b54 HS |
1847 | static ssize_t set_ignore_ce(struct sys_device *s, |
1848 | struct sysdev_attribute *attr, | |
1849 | const char *buf, size_t size) | |
1850 | { | |
1851 | u64 new; | |
1852 | ||
1853 | if (strict_strtoull(buf, 0, &new) < 0) | |
1854 | return -EINVAL; | |
1855 | ||
1856 | if (mce_ignore_ce ^ !!new) { | |
1857 | if (new) { | |
1858 | /* disable ce features */ | |
9aaef96f HS |
1859 | mce_timer_delete_all(); |
1860 | on_each_cpu(mce_disable_cmci, NULL, 1); | |
9af43b54 HS |
1861 | mce_ignore_ce = 1; |
1862 | } else { | |
1863 | /* enable ce features */ | |
1864 | mce_ignore_ce = 0; | |
1865 | on_each_cpu(mce_enable_ce, (void *)1, 1); | |
1866 | } | |
1867 | } | |
1868 | return size; | |
1869 | } | |
1870 | ||
1871 | static ssize_t set_cmci_disabled(struct sys_device *s, | |
1872 | struct sysdev_attribute *attr, | |
1873 | const char *buf, size_t size) | |
1874 | { | |
1875 | u64 new; | |
1876 | ||
1877 | if (strict_strtoull(buf, 0, &new) < 0) | |
1878 | return -EINVAL; | |
1879 | ||
1880 | if (mce_cmci_disabled ^ !!new) { | |
1881 | if (new) { | |
1882 | /* disable cmci */ | |
9aaef96f | 1883 | on_each_cpu(mce_disable_cmci, NULL, 1); |
9af43b54 HS |
1884 | mce_cmci_disabled = 1; |
1885 | } else { | |
1886 | /* enable cmci */ | |
1887 | mce_cmci_disabled = 0; | |
1888 | on_each_cpu(mce_enable_ce, NULL, 1); | |
1889 | } | |
1890 | } | |
1891 | return size; | |
1892 | } | |
1893 | ||
b56f642d AK |
1894 | static ssize_t store_int_with_restart(struct sys_device *s, |
1895 | struct sysdev_attribute *attr, | |
1896 | const char *buf, size_t size) | |
1897 | { | |
1898 | ssize_t ret = sysdev_store_int(s, attr, buf, size); | |
1899 | mce_restart(); | |
1900 | return ret; | |
1901 | } | |
1902 | ||
a98f0dd3 | 1903 | static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger); |
d95d62c0 | 1904 | static SYSDEV_INT_ATTR(tolerant, 0644, tolerant); |
3c079792 | 1905 | static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout); |
9af43b54 | 1906 | static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce); |
e9eee03e | 1907 | |
b56f642d AK |
1908 | static struct sysdev_ext_attribute attr_check_interval = { |
1909 | _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int, | |
1910 | store_int_with_restart), | |
1911 | &check_interval | |
1912 | }; | |
e9eee03e | 1913 | |
9af43b54 HS |
1914 | static struct sysdev_ext_attribute attr_ignore_ce = { |
1915 | _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce), | |
1916 | &mce_ignore_ce | |
1917 | }; | |
1918 | ||
1919 | static struct sysdev_ext_attribute attr_cmci_disabled = { | |
74b602c7 | 1920 | _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled), |
9af43b54 HS |
1921 | &mce_cmci_disabled |
1922 | }; | |
1923 | ||
c7cece89 | 1924 | static struct sysdev_attribute *mce_sysdev_attrs[] = { |
9af43b54 HS |
1925 | &attr_tolerant.attr, |
1926 | &attr_check_interval.attr, | |
1927 | &attr_trigger, | |
3c079792 | 1928 | &attr_monarch_timeout.attr, |
9af43b54 HS |
1929 | &attr_dont_log_ce.attr, |
1930 | &attr_ignore_ce.attr, | |
1931 | &attr_cmci_disabled.attr, | |
a98f0dd3 AK |
1932 | NULL |
1933 | }; | |
1da177e4 | 1934 | |
c7cece89 | 1935 | static cpumask_var_t mce_sysdev_initialized; |
bae19fe0 | 1936 | |
e9eee03e | 1937 | /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */ |
c7cece89 | 1938 | static __cpuinit int mce_sysdev_create(unsigned int cpu) |
1da177e4 | 1939 | { |
c7cece89 | 1940 | struct sys_device *sysdev = &per_cpu(mce_sysdev, cpu); |
1da177e4 | 1941 | int err; |
b1f49f95 | 1942 | int i, j; |
92cb7612 | 1943 | |
90367556 | 1944 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
1945 | return -EIO; |
1946 | ||
f6783c42 HS |
1947 | memset(&sysdev->kobj, 0, sizeof(struct kobject)); |
1948 | sysdev->id = cpu; | |
c7cece89 | 1949 | sysdev->cls = &mce_sysdev_class; |
91c6d400 | 1950 | |
f6783c42 | 1951 | err = sysdev_register(sysdev); |
d435d862 AM |
1952 | if (err) |
1953 | return err; | |
1954 | ||
c7cece89 HS |
1955 | for (i = 0; mce_sysdev_attrs[i]; i++) { |
1956 | err = sysdev_create_file(sysdev, mce_sysdev_attrs[i]); | |
d435d862 AM |
1957 | if (err) |
1958 | goto error; | |
1959 | } | |
b1f49f95 | 1960 | for (j = 0; j < banks; j++) { |
f6783c42 | 1961 | err = sysdev_create_file(sysdev, &mce_banks[j].attr); |
0d7482e3 AK |
1962 | if (err) |
1963 | goto error2; | |
1964 | } | |
c7cece89 | 1965 | cpumask_set_cpu(cpu, mce_sysdev_initialized); |
91c6d400 | 1966 | |
d435d862 | 1967 | return 0; |
0d7482e3 | 1968 | error2: |
b1f49f95 | 1969 | while (--j >= 0) |
f6783c42 | 1970 | sysdev_remove_file(sysdev, &mce_banks[j].attr); |
d435d862 | 1971 | error: |
cb491fca | 1972 | while (--i >= 0) |
c7cece89 | 1973 | sysdev_remove_file(sysdev, mce_sysdev_attrs[i]); |
cb491fca | 1974 | |
f6783c42 | 1975 | sysdev_unregister(sysdev); |
d435d862 | 1976 | |
91c6d400 AK |
1977 | return err; |
1978 | } | |
1979 | ||
c7cece89 | 1980 | static __cpuinit void mce_sysdev_remove(unsigned int cpu) |
91c6d400 | 1981 | { |
c7cece89 | 1982 | struct sys_device *sysdev = &per_cpu(mce_sysdev, cpu); |
73ca5358 SL |
1983 | int i; |
1984 | ||
c7cece89 | 1985 | if (!cpumask_test_cpu(cpu, mce_sysdev_initialized)) |
bae19fe0 AH |
1986 | return; |
1987 | ||
c7cece89 HS |
1988 | for (i = 0; mce_sysdev_attrs[i]; i++) |
1989 | sysdev_remove_file(sysdev, mce_sysdev_attrs[i]); | |
cb491fca | 1990 | |
0d7482e3 | 1991 | for (i = 0; i < banks; i++) |
f6783c42 | 1992 | sysdev_remove_file(sysdev, &mce_banks[i].attr); |
cb491fca | 1993 | |
f6783c42 | 1994 | sysdev_unregister(sysdev); |
c7cece89 | 1995 | cpumask_clear_cpu(cpu, mce_sysdev_initialized); |
91c6d400 | 1996 | } |
91c6d400 | 1997 | |
d6b75584 | 1998 | /* Make sure there are no machine checks on offlined CPUs. */ |
767df1bd | 1999 | static void __cpuinit mce_disable_cpu(void *h) |
d6b75584 | 2000 | { |
88ccbedd | 2001 | unsigned long action = *(unsigned long *)h; |
cb491fca | 2002 | int i; |
d6b75584 | 2003 | |
7b543a53 | 2004 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
d6b75584 | 2005 | return; |
767df1bd | 2006 | |
88ccbedd AK |
2007 | if (!(action & CPU_TASKS_FROZEN)) |
2008 | cmci_clear(); | |
06b7a7a5 | 2009 | for (i = 0; i < banks; i++) { |
cebe1820 | 2010 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2011 | |
cebe1820 | 2012 | if (b->init) |
a2d32bcb | 2013 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 2014 | } |
d6b75584 AK |
2015 | } |
2016 | ||
767df1bd | 2017 | static void __cpuinit mce_reenable_cpu(void *h) |
d6b75584 | 2018 | { |
88ccbedd | 2019 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 2020 | int i; |
d6b75584 | 2021 | |
7b543a53 | 2022 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
d6b75584 | 2023 | return; |
e9eee03e | 2024 | |
88ccbedd AK |
2025 | if (!(action & CPU_TASKS_FROZEN)) |
2026 | cmci_reenable(); | |
06b7a7a5 | 2027 | for (i = 0; i < banks; i++) { |
cebe1820 | 2028 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2029 | |
cebe1820 | 2030 | if (b->init) |
a2d32bcb | 2031 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
06b7a7a5 | 2032 | } |
d6b75584 AK |
2033 | } |
2034 | ||
91c6d400 | 2035 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
e9eee03e IM |
2036 | static int __cpuinit |
2037 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) | |
91c6d400 AK |
2038 | { |
2039 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 2040 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 AK |
2041 | |
2042 | switch (action) { | |
bae19fe0 AH |
2043 | case CPU_ONLINE: |
2044 | case CPU_ONLINE_FROZEN: | |
c7cece89 | 2045 | mce_sysdev_create(cpu); |
8735728e RW |
2046 | if (threshold_cpu_callback) |
2047 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 2048 | break; |
91c6d400 | 2049 | case CPU_DEAD: |
8bb78442 | 2050 | case CPU_DEAD_FROZEN: |
8735728e RW |
2051 | if (threshold_cpu_callback) |
2052 | threshold_cpu_callback(action, cpu); | |
c7cece89 | 2053 | mce_sysdev_remove(cpu); |
91c6d400 | 2054 | break; |
52d168e2 AK |
2055 | case CPU_DOWN_PREPARE: |
2056 | case CPU_DOWN_PREPARE_FROZEN: | |
2057 | del_timer_sync(t); | |
88ccbedd | 2058 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
52d168e2 AK |
2059 | break; |
2060 | case CPU_DOWN_FAILED: | |
2061 | case CPU_DOWN_FAILED_FROZEN: | |
fe5ed91d HS |
2062 | if (!mce_ignore_ce && check_interval) { |
2063 | t->expires = round_jiffies(jiffies + | |
245b2e70 | 2064 | __get_cpu_var(mce_next_interval)); |
fe5ed91d HS |
2065 | add_timer_on(t, cpu); |
2066 | } | |
88ccbedd AK |
2067 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
2068 | break; | |
2069 | case CPU_POST_DEAD: | |
2070 | /* intentionally ignoring frozen here */ | |
2071 | cmci_rediscover(cpu); | |
52d168e2 | 2072 | break; |
91c6d400 | 2073 | } |
bae19fe0 | 2074 | return NOTIFY_OK; |
91c6d400 AK |
2075 | } |
2076 | ||
1e35669d | 2077 | static struct notifier_block mce_cpu_notifier __cpuinitdata = { |
91c6d400 AK |
2078 | .notifier_call = mce_cpu_callback, |
2079 | }; | |
2080 | ||
cebe1820 | 2081 | static __init void mce_init_banks(void) |
0d7482e3 AK |
2082 | { |
2083 | int i; | |
2084 | ||
0d7482e3 | 2085 | for (i = 0; i < banks; i++) { |
cebe1820 AK |
2086 | struct mce_bank *b = &mce_banks[i]; |
2087 | struct sysdev_attribute *a = &b->attr; | |
e9eee03e | 2088 | |
a07e4156 | 2089 | sysfs_attr_init(&a->attr); |
cebe1820 AK |
2090 | a->attr.name = b->attrname; |
2091 | snprintf(b->attrname, ATTR_LEN, "bank%d", i); | |
e9eee03e IM |
2092 | |
2093 | a->attr.mode = 0644; | |
2094 | a->show = show_bank; | |
2095 | a->store = set_bank; | |
0d7482e3 | 2096 | } |
0d7482e3 AK |
2097 | } |
2098 | ||
5e09954a | 2099 | static __init int mcheck_init_device(void) |
91c6d400 AK |
2100 | { |
2101 | int err; | |
2102 | int i = 0; | |
2103 | ||
1da177e4 LT |
2104 | if (!mce_available(&boot_cpu_data)) |
2105 | return -EIO; | |
0d7482e3 | 2106 | |
c7cece89 | 2107 | zalloc_cpumask_var(&mce_sysdev_initialized, GFP_KERNEL); |
996867d0 | 2108 | |
cebe1820 | 2109 | mce_init_banks(); |
0d7482e3 | 2110 | |
c7cece89 | 2111 | err = sysdev_class_register(&mce_sysdev_class); |
d435d862 AM |
2112 | if (err) |
2113 | return err; | |
91c6d400 AK |
2114 | |
2115 | for_each_online_cpu(i) { | |
c7cece89 | 2116 | err = mce_sysdev_create(i); |
d435d862 AM |
2117 | if (err) |
2118 | return err; | |
91c6d400 AK |
2119 | } |
2120 | ||
f3c6ea1b | 2121 | register_syscore_ops(&mce_syscore_ops); |
be6b5a35 | 2122 | register_hotcpu_notifier(&mce_cpu_notifier); |
93b62c3c HS |
2123 | |
2124 | /* register character device /dev/mcelog */ | |
2125 | misc_register(&mce_chrdev_device); | |
e9eee03e | 2126 | |
1da177e4 | 2127 | return err; |
1da177e4 | 2128 | } |
5e09954a | 2129 | device_initcall(mcheck_init_device); |
a988d334 | 2130 | |
d7c3c9a6 AK |
2131 | /* |
2132 | * Old style boot options parsing. Only for compatibility. | |
2133 | */ | |
2134 | static int __init mcheck_disable(char *str) | |
2135 | { | |
2136 | mce_disabled = 1; | |
2137 | return 1; | |
2138 | } | |
2139 | __setup("nomce", mcheck_disable); | |
a988d334 | 2140 | |
5be9ed25 HY |
2141 | #ifdef CONFIG_DEBUG_FS |
2142 | struct dentry *mce_get_debugfs_dir(void) | |
a988d334 | 2143 | { |
5be9ed25 | 2144 | static struct dentry *dmce; |
a988d334 | 2145 | |
5be9ed25 HY |
2146 | if (!dmce) |
2147 | dmce = debugfs_create_dir("mce", NULL); | |
a988d334 | 2148 | |
5be9ed25 HY |
2149 | return dmce; |
2150 | } | |
a988d334 | 2151 | |
bf783f9f HY |
2152 | static void mce_reset(void) |
2153 | { | |
2154 | cpu_missing = 0; | |
2155 | atomic_set(&mce_fake_paniced, 0); | |
2156 | atomic_set(&mce_executing, 0); | |
2157 | atomic_set(&mce_callin, 0); | |
2158 | atomic_set(&global_nwo, 0); | |
2159 | } | |
a988d334 | 2160 | |
bf783f9f HY |
2161 | static int fake_panic_get(void *data, u64 *val) |
2162 | { | |
2163 | *val = fake_panic; | |
2164 | return 0; | |
a988d334 IM |
2165 | } |
2166 | ||
bf783f9f | 2167 | static int fake_panic_set(void *data, u64 val) |
a988d334 | 2168 | { |
bf783f9f HY |
2169 | mce_reset(); |
2170 | fake_panic = val; | |
2171 | return 0; | |
a988d334 | 2172 | } |
a988d334 | 2173 | |
bf783f9f HY |
2174 | DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get, |
2175 | fake_panic_set, "%llu\n"); | |
d7c3c9a6 | 2176 | |
5e09954a | 2177 | static int __init mcheck_debugfs_init(void) |
d7c3c9a6 | 2178 | { |
bf783f9f HY |
2179 | struct dentry *dmce, *ffake_panic; |
2180 | ||
2181 | dmce = mce_get_debugfs_dir(); | |
2182 | if (!dmce) | |
2183 | return -ENOMEM; | |
2184 | ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL, | |
2185 | &fake_panic_fops); | |
2186 | if (!ffake_panic) | |
2187 | return -ENOMEM; | |
2188 | ||
2189 | return 0; | |
d7c3c9a6 | 2190 | } |
5e09954a | 2191 | late_initcall(mcheck_debugfs_init); |
5be9ed25 | 2192 | #endif |