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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
e9eee03e IM |
10 | #include <linux/thread_info.h> |
11 | #include <linux/capability.h> | |
12 | #include <linux/miscdevice.h> | |
13 | #include <linux/ratelimit.h> | |
14 | #include <linux/kallsyms.h> | |
15 | #include <linux/rcupdate.h> | |
38c4c97c | 16 | #include <linux/smp_lock.h> |
e9eee03e IM |
17 | #include <linux/kobject.h> |
18 | #include <linux/kdebug.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/percpu.h> | |
1da177e4 | 21 | #include <linux/string.h> |
1da177e4 | 22 | #include <linux/sysdev.h> |
8c566ef5 | 23 | #include <linux/ctype.h> |
e9eee03e | 24 | #include <linux/sched.h> |
0d7482e3 | 25 | #include <linux/sysfs.h> |
e9eee03e IM |
26 | #include <linux/types.h> |
27 | #include <linux/init.h> | |
28 | #include <linux/kmod.h> | |
29 | #include <linux/poll.h> | |
30 | #include <linux/cpu.h> | |
31 | #include <linux/fs.h> | |
32 | ||
d88203d1 | 33 | #include <asm/processor.h> |
1da177e4 | 34 | #include <asm/uaccess.h> |
e02e68d3 | 35 | #include <asm/idle.h> |
e9eee03e IM |
36 | #include <asm/mce.h> |
37 | #include <asm/msr.h> | |
38 | #include <asm/smp.h> | |
1da177e4 | 39 | |
711c2e48 IM |
40 | #include "mce.h" |
41 | ||
42 | #ifdef CONFIG_X86_64 | |
43 | ||
e9eee03e | 44 | #define MISC_MCELOG_MINOR 227 |
0d7482e3 | 45 | |
553f265f AK |
46 | atomic_t mce_entry; |
47 | ||
e9eee03e | 48 | static int mce_dont_init; |
1da177e4 | 49 | |
bd78432c TH |
50 | /* |
51 | * Tolerant levels: | |
52 | * 0: always panic on uncorrected errors, log corrected errors | |
53 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
54 | * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors | |
55 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
56 | */ | |
e9eee03e IM |
57 | static int tolerant = 1; |
58 | static int banks; | |
59 | static u64 *bank; | |
60 | static unsigned long notify_user; | |
61 | static int rip_msr; | |
62 | static int mce_bootlog = -1; | |
63 | static atomic_t mce_events; | |
a98f0dd3 | 64 | |
e9eee03e IM |
65 | static char trigger[128]; |
66 | static char *trigger_argv[2] = { trigger, NULL }; | |
1da177e4 | 67 | |
e02e68d3 TH |
68 | static DECLARE_WAIT_QUEUE_HEAD(mce_wait); |
69 | ||
ee031c31 AK |
70 | /* MCA banks polled by the period polling timer for corrected events */ |
71 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { | |
72 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
73 | }; | |
74 | ||
b5f2fa4e AK |
75 | /* Do initial initialization of a struct mce */ |
76 | void mce_setup(struct mce *m) | |
77 | { | |
78 | memset(m, 0, sizeof(struct mce)); | |
79 | m->cpu = smp_processor_id(); | |
80 | rdtscll(m->tsc); | |
81 | } | |
82 | ||
1da177e4 LT |
83 | /* |
84 | * Lockless MCE logging infrastructure. | |
85 | * This avoids deadlocks on printk locks without having to break locks. Also | |
86 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
87 | */ | |
88 | ||
231fd906 | 89 | static struct mce_log mcelog = { |
1da177e4 LT |
90 | MCE_LOG_SIGNATURE, |
91 | MCE_LOG_LEN, | |
d88203d1 | 92 | }; |
1da177e4 LT |
93 | |
94 | void mce_log(struct mce *mce) | |
95 | { | |
96 | unsigned next, entry; | |
e9eee03e | 97 | |
a98f0dd3 | 98 | atomic_inc(&mce_events); |
1da177e4 | 99 | mce->finished = 0; |
7644143c | 100 | wmb(); |
1da177e4 LT |
101 | for (;;) { |
102 | entry = rcu_dereference(mcelog.next); | |
673242c1 | 103 | for (;;) { |
e9eee03e IM |
104 | /* |
105 | * When the buffer fills up discard new entries. | |
106 | * Assume that the earlier errors are the more | |
107 | * interesting ones: | |
108 | */ | |
673242c1 | 109 | if (entry >= MCE_LOG_LEN) { |
53756d37 | 110 | set_bit(MCE_OVERFLOW, (unsigned long *)&mcelog.flags); |
673242c1 AK |
111 | return; |
112 | } | |
e9eee03e | 113 | /* Old left over entry. Skip: */ |
673242c1 AK |
114 | if (mcelog.entry[entry].finished) { |
115 | entry++; | |
116 | continue; | |
117 | } | |
7644143c | 118 | break; |
1da177e4 | 119 | } |
1da177e4 LT |
120 | smp_rmb(); |
121 | next = entry + 1; | |
122 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
123 | break; | |
124 | } | |
125 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 126 | wmb(); |
1da177e4 | 127 | mcelog.entry[entry].finished = 1; |
7644143c | 128 | wmb(); |
1da177e4 | 129 | |
e02e68d3 | 130 | set_bit(0, ¬ify_user); |
1da177e4 LT |
131 | } |
132 | ||
133 | static void print_mce(struct mce *m) | |
134 | { | |
135 | printk(KERN_EMERG "\n" | |
4855170f | 136 | KERN_EMERG "HARDWARE ERROR\n" |
1da177e4 LT |
137 | KERN_EMERG |
138 | "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n", | |
139 | m->cpu, m->mcgstatus, m->bank, m->status); | |
65ea5b03 | 140 | if (m->ip) { |
d88203d1 | 141 | printk(KERN_EMERG "RIP%s %02x:<%016Lx> ", |
1da177e4 | 142 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
65ea5b03 | 143 | m->cs, m->ip); |
1da177e4 | 144 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 145 | print_symbol("{%s}", m->ip); |
1da177e4 LT |
146 | printk("\n"); |
147 | } | |
f6d1826d | 148 | printk(KERN_EMERG "TSC %llx ", m->tsc); |
1da177e4 | 149 | if (m->addr) |
f6d1826d | 150 | printk("ADDR %llx ", m->addr); |
1da177e4 | 151 | if (m->misc) |
f6d1826d | 152 | printk("MISC %llx ", m->misc); |
1da177e4 | 153 | printk("\n"); |
4855170f | 154 | printk(KERN_EMERG "This is not a software problem!\n"); |
d88203d1 TG |
155 | printk(KERN_EMERG "Run through mcelog --ascii to decode " |
156 | "and contact your hardware vendor\n"); | |
1da177e4 LT |
157 | } |
158 | ||
159 | static void mce_panic(char *msg, struct mce *backup, unsigned long start) | |
d88203d1 | 160 | { |
1da177e4 | 161 | int i; |
e02e68d3 | 162 | |
1da177e4 LT |
163 | oops_begin(); |
164 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
165 | unsigned long tsc = mcelog.entry[i].tsc; | |
d88203d1 | 166 | |
1da177e4 LT |
167 | if (time_before(tsc, start)) |
168 | continue; | |
d88203d1 | 169 | print_mce(&mcelog.entry[i]); |
1da177e4 LT |
170 | if (backup && mcelog.entry[i].tsc == backup->tsc) |
171 | backup = NULL; | |
172 | } | |
173 | if (backup) | |
174 | print_mce(backup); | |
e02e68d3 | 175 | panic(msg); |
d88203d1 | 176 | } |
1da177e4 | 177 | |
88ccbedd | 178 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 179 | { |
5b4408fd AK |
180 | if (mce_dont_init) |
181 | return 0; | |
3d1712c9 | 182 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
183 | } |
184 | ||
94ad8474 AK |
185 | static inline void mce_get_rip(struct mce *m, struct pt_regs *regs) |
186 | { | |
187 | if (regs && (m->mcgstatus & MCG_STATUS_RIPV)) { | |
65ea5b03 | 188 | m->ip = regs->ip; |
94ad8474 AK |
189 | m->cs = regs->cs; |
190 | } else { | |
65ea5b03 | 191 | m->ip = 0; |
94ad8474 AK |
192 | m->cs = 0; |
193 | } | |
194 | if (rip_msr) { | |
195 | /* Assume the RIP in the MSR is exact. Is this true? */ | |
196 | m->mcgstatus |= MCG_STATUS_EIPV; | |
65ea5b03 | 197 | rdmsrl(rip_msr, m->ip); |
94ad8474 AK |
198 | m->cs = 0; |
199 | } | |
200 | } | |
201 | ||
d88203d1 | 202 | /* |
b79109c3 AK |
203 | * Poll for corrected events or events that happened before reset. |
204 | * Those are just logged through /dev/mcelog. | |
205 | * | |
206 | * This is executed in standard interrupt context. | |
207 | */ | |
ee031c31 | 208 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 AK |
209 | { |
210 | struct mce m; | |
211 | int i; | |
212 | ||
213 | mce_setup(&m); | |
214 | ||
215 | rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); | |
216 | for (i = 0; i < banks; i++) { | |
ee031c31 | 217 | if (!bank[i] || !test_bit(i, *b)) |
b79109c3 AK |
218 | continue; |
219 | ||
220 | m.misc = 0; | |
221 | m.addr = 0; | |
222 | m.bank = i; | |
223 | m.tsc = 0; | |
224 | ||
225 | barrier(); | |
226 | rdmsrl(MSR_IA32_MC0_STATUS + i*4, m.status); | |
227 | if (!(m.status & MCI_STATUS_VAL)) | |
228 | continue; | |
229 | ||
230 | /* | |
231 | * Uncorrected events are handled by the exception handler | |
232 | * when it is enabled. But when the exception is disabled log | |
233 | * everything. | |
234 | * | |
235 | * TBD do the same check for MCI_STATUS_EN here? | |
236 | */ | |
237 | if ((m.status & MCI_STATUS_UC) && !(flags & MCP_UC)) | |
238 | continue; | |
239 | ||
240 | if (m.status & MCI_STATUS_MISCV) | |
241 | rdmsrl(MSR_IA32_MC0_MISC + i*4, m.misc); | |
242 | if (m.status & MCI_STATUS_ADDRV) | |
243 | rdmsrl(MSR_IA32_MC0_ADDR + i*4, m.addr); | |
244 | ||
245 | if (!(flags & MCP_TIMESTAMP)) | |
246 | m.tsc = 0; | |
247 | /* | |
248 | * Don't get the IP here because it's unlikely to | |
249 | * have anything to do with the actual error location. | |
250 | */ | |
5679af4c AK |
251 | if (!(flags & MCP_DONTLOG)) { |
252 | mce_log(&m); | |
253 | add_taint(TAINT_MACHINE_CHECK); | |
254 | } | |
b79109c3 AK |
255 | |
256 | /* | |
257 | * Clear state for this bank. | |
258 | */ | |
259 | wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); | |
260 | } | |
261 | ||
262 | /* | |
263 | * Don't clear MCG_STATUS here because it's only defined for | |
264 | * exceptions. | |
265 | */ | |
266 | } | |
267 | ||
268 | /* | |
269 | * The actual machine check handler. This only handles real | |
270 | * exceptions when something got corrupted coming in through int 18. | |
271 | * | |
272 | * This is executed in NMI context not subject to normal locking rules. This | |
273 | * implies that most kernel services cannot be safely used. Don't even | |
274 | * think about putting a printk in there! | |
1da177e4 | 275 | */ |
e9eee03e | 276 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 LT |
277 | { |
278 | struct mce m, panicm; | |
e9eee03e | 279 | int panicm_found = 0; |
1da177e4 LT |
280 | u64 mcestart = 0; |
281 | int i; | |
bd78432c TH |
282 | /* |
283 | * If no_way_out gets set, there is no safe way to recover from this | |
284 | * MCE. If tolerant is cranked up, we'll try anyway. | |
285 | */ | |
286 | int no_way_out = 0; | |
287 | /* | |
288 | * If kill_it gets set, there might be a way to recover from this | |
289 | * error. | |
290 | */ | |
291 | int kill_it = 0; | |
b79109c3 | 292 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
1da177e4 | 293 | |
553f265f AK |
294 | atomic_inc(&mce_entry); |
295 | ||
b79109c3 | 296 | if (notify_die(DIE_NMI, "machine check", regs, error_code, |
22f5991c | 297 | 18, SIGKILL) == NOTIFY_STOP) |
b79109c3 AK |
298 | goto out2; |
299 | if (!banks) | |
553f265f | 300 | goto out2; |
1da177e4 | 301 | |
b5f2fa4e AK |
302 | mce_setup(&m); |
303 | ||
1da177e4 | 304 | rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); |
e9eee03e | 305 | |
bd78432c | 306 | /* if the restart IP is not valid, we're done for */ |
1da177e4 | 307 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) |
bd78432c | 308 | no_way_out = 1; |
d88203d1 | 309 | |
1da177e4 LT |
310 | rdtscll(mcestart); |
311 | barrier(); | |
312 | ||
313 | for (i = 0; i < banks; i++) { | |
b79109c3 | 314 | __clear_bit(i, toclear); |
0d7482e3 | 315 | if (!bank[i]) |
1da177e4 | 316 | continue; |
d88203d1 TG |
317 | |
318 | m.misc = 0; | |
1da177e4 LT |
319 | m.addr = 0; |
320 | m.bank = i; | |
1da177e4 LT |
321 | |
322 | rdmsrl(MSR_IA32_MC0_STATUS + i*4, m.status); | |
323 | if ((m.status & MCI_STATUS_VAL) == 0) | |
324 | continue; | |
325 | ||
b79109c3 AK |
326 | /* |
327 | * Non uncorrected errors are handled by machine_check_poll | |
328 | * Leave them alone. | |
329 | */ | |
330 | if ((m.status & MCI_STATUS_UC) == 0) | |
331 | continue; | |
332 | ||
333 | /* | |
334 | * Set taint even when machine check was not enabled. | |
335 | */ | |
336 | add_taint(TAINT_MACHINE_CHECK); | |
337 | ||
338 | __set_bit(i, toclear); | |
339 | ||
1da177e4 | 340 | if (m.status & MCI_STATUS_EN) { |
bd78432c TH |
341 | /* if PCC was set, there's no way out */ |
342 | no_way_out |= !!(m.status & MCI_STATUS_PCC); | |
343 | /* | |
344 | * If this error was uncorrectable and there was | |
345 | * an overflow, we're in trouble. If no overflow, | |
346 | * we might get away with just killing a task. | |
347 | */ | |
348 | if (m.status & MCI_STATUS_UC) { | |
349 | if (tolerant < 1 || m.status & MCI_STATUS_OVER) | |
350 | no_way_out = 1; | |
351 | kill_it = 1; | |
352 | } | |
b79109c3 AK |
353 | } else { |
354 | /* | |
355 | * Machine check event was not enabled. Clear, but | |
356 | * ignore. | |
357 | */ | |
358 | continue; | |
1da177e4 LT |
359 | } |
360 | ||
361 | if (m.status & MCI_STATUS_MISCV) | |
362 | rdmsrl(MSR_IA32_MC0_MISC + i*4, m.misc); | |
363 | if (m.status & MCI_STATUS_ADDRV) | |
364 | rdmsrl(MSR_IA32_MC0_ADDR + i*4, m.addr); | |
365 | ||
94ad8474 | 366 | mce_get_rip(&m, regs); |
b79109c3 | 367 | mce_log(&m); |
1da177e4 | 368 | |
e9eee03e IM |
369 | /* |
370 | * Did this bank cause the exception? | |
371 | * | |
372 | * Assume that the bank with uncorrectable errors did it, | |
373 | * and that there is only a single one: | |
374 | */ | |
375 | if ((m.status & MCI_STATUS_UC) && | |
376 | (m.status & MCI_STATUS_EN)) { | |
1da177e4 LT |
377 | panicm = m; |
378 | panicm_found = 1; | |
379 | } | |
1da177e4 LT |
380 | } |
381 | ||
e9eee03e IM |
382 | /* |
383 | * If we didn't find an uncorrectable error, pick | |
384 | * the last one (shouldn't happen, just being safe). | |
385 | */ | |
1da177e4 LT |
386 | if (!panicm_found) |
387 | panicm = m; | |
bd78432c TH |
388 | |
389 | /* | |
390 | * If we have decided that we just CAN'T continue, and the user | |
e9eee03e | 391 | * has not set tolerant to an insane level, give up and die. |
bd78432c TH |
392 | */ |
393 | if (no_way_out && tolerant < 3) | |
1da177e4 | 394 | mce_panic("Machine check", &panicm, mcestart); |
bd78432c TH |
395 | |
396 | /* | |
397 | * If the error seems to be unrecoverable, something should be | |
398 | * done. Try to kill as little as possible. If we can kill just | |
399 | * one task, do that. If the user has set the tolerance very | |
400 | * high, don't try to do anything at all. | |
401 | */ | |
402 | if (kill_it && tolerant < 3) { | |
1da177e4 LT |
403 | int user_space = 0; |
404 | ||
bd78432c TH |
405 | /* |
406 | * If the EIPV bit is set, it means the saved IP is the | |
407 | * instruction which caused the MCE. | |
408 | */ | |
409 | if (m.mcgstatus & MCG_STATUS_EIPV) | |
65ea5b03 | 410 | user_space = panicm.ip && (panicm.cs & 3); |
bd78432c TH |
411 | |
412 | /* | |
413 | * If we know that the error was in user space, send a | |
414 | * SIGBUS. Otherwise, panic if tolerance is low. | |
415 | * | |
380851bc | 416 | * force_sig() takes an awful lot of locks and has a slight |
bd78432c TH |
417 | * risk of deadlocking. |
418 | */ | |
419 | if (user_space) { | |
380851bc | 420 | force_sig(SIGBUS, current); |
bd78432c TH |
421 | } else if (panic_on_oops || tolerant < 2) { |
422 | mce_panic("Uncorrected machine check", | |
423 | &panicm, mcestart); | |
424 | } | |
1da177e4 LT |
425 | } |
426 | ||
e02e68d3 TH |
427 | /* notify userspace ASAP */ |
428 | set_thread_flag(TIF_MCE_NOTIFY); | |
429 | ||
bd78432c | 430 | /* the last thing we do is clear state */ |
b79109c3 AK |
431 | for (i = 0; i < banks; i++) { |
432 | if (test_bit(i, toclear)) | |
433 | wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); | |
434 | } | |
1da177e4 | 435 | wrmsrl(MSR_IA32_MCG_STATUS, 0); |
553f265f AK |
436 | out2: |
437 | atomic_dec(&mce_entry); | |
1da177e4 LT |
438 | } |
439 | ||
15d5f839 DZ |
440 | #ifdef CONFIG_X86_MCE_INTEL |
441 | /*** | |
442 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 443 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
444 | * @status: Event status information |
445 | * | |
446 | * This function should be called by the thermal interrupt after the | |
447 | * event has been processed and the decision was made to log the event | |
448 | * further. | |
449 | * | |
450 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
451 | * and historically has been the register value of the | |
452 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
453 | */ | |
b5f2fa4e | 454 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
455 | { |
456 | struct mce m; | |
457 | ||
b5f2fa4e | 458 | mce_setup(&m); |
15d5f839 DZ |
459 | m.bank = MCE_THERMAL_BANK; |
460 | m.status = status; | |
15d5f839 DZ |
461 | mce_log(&m); |
462 | } | |
463 | #endif /* CONFIG_X86_MCE_INTEL */ | |
464 | ||
1da177e4 | 465 | /* |
8a336b0a TH |
466 | * Periodic polling timer for "silent" machine check errors. If the |
467 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
468 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 469 | */ |
1da177e4 | 470 | static int check_interval = 5 * 60; /* 5 minutes */ |
e9eee03e | 471 | |
6298c512 | 472 | static DEFINE_PER_CPU(int, next_interval); /* in jiffies */ |
52d168e2 | 473 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 474 | |
52d168e2 | 475 | static void mcheck_timer(unsigned long data) |
1da177e4 | 476 | { |
52d168e2 | 477 | struct timer_list *t = &per_cpu(mce_timer, data); |
6298c512 | 478 | int *n; |
52d168e2 AK |
479 | |
480 | WARN_ON(smp_processor_id() != data); | |
481 | ||
e9eee03e | 482 | if (mce_available(¤t_cpu_data)) { |
ee031c31 AK |
483 | machine_check_poll(MCP_TIMESTAMP, |
484 | &__get_cpu_var(mce_poll_banks)); | |
e9eee03e | 485 | } |
1da177e4 LT |
486 | |
487 | /* | |
e02e68d3 TH |
488 | * Alert userspace if needed. If we logged an MCE, reduce the |
489 | * polling interval, otherwise increase the polling interval. | |
1da177e4 | 490 | */ |
6298c512 | 491 | n = &__get_cpu_var(next_interval); |
e02e68d3 | 492 | if (mce_notify_user()) { |
6298c512 | 493 | *n = max(*n/2, HZ/100); |
e02e68d3 | 494 | } else { |
6298c512 | 495 | *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ)); |
e02e68d3 TH |
496 | } |
497 | ||
6298c512 | 498 | t->expires = jiffies + *n; |
52d168e2 | 499 | add_timer(t); |
e02e68d3 TH |
500 | } |
501 | ||
9bd98405 AK |
502 | static void mce_do_trigger(struct work_struct *work) |
503 | { | |
504 | call_usermodehelper(trigger, trigger_argv, NULL, UMH_NO_WAIT); | |
505 | } | |
506 | ||
507 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
508 | ||
e02e68d3 | 509 | /* |
9bd98405 AK |
510 | * Notify the user(s) about new machine check events. |
511 | * Can be called from interrupt context, but not from machine check/NMI | |
512 | * context. | |
e02e68d3 TH |
513 | */ |
514 | int mce_notify_user(void) | |
515 | { | |
8457c84d AK |
516 | /* Not more than two messages every minute */ |
517 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
518 | ||
e02e68d3 | 519 | clear_thread_flag(TIF_MCE_NOTIFY); |
e9eee03e | 520 | |
e02e68d3 | 521 | if (test_and_clear_bit(0, ¬ify_user)) { |
e02e68d3 | 522 | wake_up_interruptible(&mce_wait); |
9bd98405 AK |
523 | |
524 | /* | |
525 | * There is no risk of missing notifications because | |
526 | * work_pending is always cleared before the function is | |
527 | * executed. | |
528 | */ | |
529 | if (trigger[0] && !work_pending(&mce_trigger_work)) | |
530 | schedule_work(&mce_trigger_work); | |
e02e68d3 | 531 | |
8457c84d | 532 | if (__ratelimit(&ratelimit)) |
8a336b0a | 533 | printk(KERN_INFO "Machine check events logged\n"); |
e02e68d3 TH |
534 | |
535 | return 1; | |
1da177e4 | 536 | } |
e02e68d3 TH |
537 | return 0; |
538 | } | |
8a336b0a | 539 | |
e9eee03e | 540 | /* see if the idle task needs to notify userspace: */ |
e02e68d3 | 541 | static int |
e9eee03e IM |
542 | mce_idle_callback(struct notifier_block *nfb, unsigned long action, |
543 | void *unused) | |
e02e68d3 TH |
544 | { |
545 | /* IDLE_END should be safe - interrupts are back on */ | |
546 | if (action == IDLE_END && test_thread_flag(TIF_MCE_NOTIFY)) | |
547 | mce_notify_user(); | |
548 | ||
549 | return NOTIFY_OK; | |
1da177e4 LT |
550 | } |
551 | ||
e02e68d3 | 552 | static struct notifier_block mce_idle_notifier = { |
e9eee03e | 553 | .notifier_call = mce_idle_callback, |
e02e68d3 | 554 | }; |
1da177e4 LT |
555 | |
556 | static __init int periodic_mcheck_init(void) | |
d88203d1 | 557 | { |
52d168e2 AK |
558 | idle_notifier_register(&mce_idle_notifier); |
559 | return 0; | |
d88203d1 | 560 | } |
1da177e4 LT |
561 | __initcall(periodic_mcheck_init); |
562 | ||
d88203d1 | 563 | /* |
1da177e4 LT |
564 | * Initialize Machine Checks for a CPU. |
565 | */ | |
0d7482e3 | 566 | static int mce_cap_init(void) |
1da177e4 | 567 | { |
0d7482e3 | 568 | unsigned b; |
e9eee03e | 569 | u64 cap; |
1da177e4 LT |
570 | |
571 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
0d7482e3 AK |
572 | b = cap & 0xff; |
573 | if (b > MAX_NR_BANKS) { | |
574 | printk(KERN_WARNING | |
575 | "MCE: Using only %u machine check banks out of %u\n", | |
576 | MAX_NR_BANKS, b); | |
577 | b = MAX_NR_BANKS; | |
578 | } | |
579 | ||
580 | /* Don't support asymmetric configurations today */ | |
581 | WARN_ON(banks != 0 && b != banks); | |
582 | banks = b; | |
583 | if (!bank) { | |
584 | bank = kmalloc(banks * sizeof(u64), GFP_KERNEL); | |
585 | if (!bank) | |
586 | return -ENOMEM; | |
587 | memset(bank, 0xff, banks * sizeof(u64)); | |
1da177e4 | 588 | } |
0d7482e3 | 589 | |
94ad8474 AK |
590 | /* Use accurate RIP reporting if available. */ |
591 | if ((cap & (1<<9)) && ((cap >> 16) & 0xff) >= 9) | |
592 | rip_msr = MSR_IA32_MCG_EIP; | |
1da177e4 | 593 | |
0d7482e3 AK |
594 | return 0; |
595 | } | |
596 | ||
597 | static void mce_init(void *dummy) | |
598 | { | |
e9eee03e | 599 | mce_banks_t all_banks; |
0d7482e3 AK |
600 | u64 cap; |
601 | int i; | |
602 | ||
b79109c3 AK |
603 | /* |
604 | * Log the machine checks left over from the previous reset. | |
605 | */ | |
ee031c31 | 606 | bitmap_fill(all_banks, MAX_NR_BANKS); |
5679af4c | 607 | machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks); |
1da177e4 LT |
608 | |
609 | set_in_cr4(X86_CR4_MCE); | |
610 | ||
0d7482e3 | 611 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
612 | if (cap & MCG_CTL_P) |
613 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
614 | ||
615 | for (i = 0; i < banks; i++) { | |
0d7482e3 | 616 | wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]); |
1da177e4 | 617 | wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); |
d88203d1 | 618 | } |
1da177e4 LT |
619 | } |
620 | ||
621 | /* Add per CPU specific workarounds here */ | |
ec5b3d32 | 622 | static void mce_cpu_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 623 | { |
1da177e4 | 624 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 625 | if (c->x86_vendor == X86_VENDOR_AMD) { |
e9eee03e IM |
626 | if (c->x86 == 15 && banks > 4) { |
627 | /* | |
628 | * disable GART TBL walk error reporting, which | |
629 | * trips off incorrectly with the IOMMU & 3ware | |
630 | * & Cerberus: | |
631 | */ | |
0d7482e3 | 632 | clear_bit(10, (unsigned long *)&bank[4]); |
e9eee03e IM |
633 | } |
634 | if (c->x86 <= 17 && mce_bootlog < 0) { | |
635 | /* | |
636 | * Lots of broken BIOS around that don't clear them | |
637 | * by default and leave crap in there. Don't log: | |
638 | */ | |
911f6a7b | 639 | mce_bootlog = 0; |
e9eee03e | 640 | } |
1da177e4 | 641 | } |
e583538f | 642 | |
d88203d1 | 643 | } |
1da177e4 | 644 | |
cc3ca220 | 645 | static void mce_cpu_features(struct cpuinfo_x86 *c) |
1da177e4 LT |
646 | { |
647 | switch (c->x86_vendor) { | |
648 | case X86_VENDOR_INTEL: | |
649 | mce_intel_feature_init(c); | |
650 | break; | |
89b831ef JS |
651 | case X86_VENDOR_AMD: |
652 | mce_amd_feature_init(c); | |
653 | break; | |
1da177e4 LT |
654 | default: |
655 | break; | |
656 | } | |
657 | } | |
658 | ||
52d168e2 AK |
659 | static void mce_init_timer(void) |
660 | { | |
661 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
6298c512 | 662 | int *n = &__get_cpu_var(next_interval); |
52d168e2 | 663 | |
6298c512 AK |
664 | *n = check_interval * HZ; |
665 | if (!*n) | |
52d168e2 AK |
666 | return; |
667 | setup_timer(t, mcheck_timer, smp_processor_id()); | |
6298c512 | 668 | t->expires = round_jiffies(jiffies + *n); |
52d168e2 AK |
669 | add_timer(t); |
670 | } | |
671 | ||
d88203d1 | 672 | /* |
1da177e4 | 673 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 674 | * Must be called with preempt off: |
1da177e4 | 675 | */ |
e6982c67 | 676 | void __cpuinit mcheck_init(struct cpuinfo_x86 *c) |
1da177e4 | 677 | { |
5b4408fd | 678 | if (!mce_available(c)) |
1da177e4 LT |
679 | return; |
680 | ||
0d7482e3 AK |
681 | if (mce_cap_init() < 0) { |
682 | mce_dont_init = 1; | |
683 | return; | |
684 | } | |
685 | mce_cpu_quirks(c); | |
686 | ||
1da177e4 LT |
687 | mce_init(NULL); |
688 | mce_cpu_features(c); | |
52d168e2 | 689 | mce_init_timer(); |
1da177e4 LT |
690 | } |
691 | ||
692 | /* | |
693 | * Character device to read and clear the MCE log. | |
694 | */ | |
695 | ||
f528e7ba | 696 | static DEFINE_SPINLOCK(mce_state_lock); |
e9eee03e IM |
697 | static int open_count; /* #times opened */ |
698 | static int open_exclu; /* already open exclusive? */ | |
f528e7ba TH |
699 | |
700 | static int mce_open(struct inode *inode, struct file *file) | |
701 | { | |
38c4c97c | 702 | lock_kernel(); |
f528e7ba TH |
703 | spin_lock(&mce_state_lock); |
704 | ||
705 | if (open_exclu || (open_count && (file->f_flags & O_EXCL))) { | |
706 | spin_unlock(&mce_state_lock); | |
38c4c97c | 707 | unlock_kernel(); |
e9eee03e | 708 | |
f528e7ba TH |
709 | return -EBUSY; |
710 | } | |
711 | ||
712 | if (file->f_flags & O_EXCL) | |
713 | open_exclu = 1; | |
714 | open_count++; | |
715 | ||
716 | spin_unlock(&mce_state_lock); | |
38c4c97c | 717 | unlock_kernel(); |
f528e7ba | 718 | |
bd78432c | 719 | return nonseekable_open(inode, file); |
f528e7ba TH |
720 | } |
721 | ||
722 | static int mce_release(struct inode *inode, struct file *file) | |
723 | { | |
724 | spin_lock(&mce_state_lock); | |
725 | ||
726 | open_count--; | |
727 | open_exclu = 0; | |
728 | ||
729 | spin_unlock(&mce_state_lock); | |
730 | ||
731 | return 0; | |
732 | } | |
733 | ||
d88203d1 TG |
734 | static void collect_tscs(void *data) |
735 | { | |
1da177e4 | 736 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 737 | |
1da177e4 | 738 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 739 | } |
1da177e4 | 740 | |
e9eee03e IM |
741 | static DEFINE_MUTEX(mce_read_mutex); |
742 | ||
d88203d1 TG |
743 | static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize, |
744 | loff_t *off) | |
1da177e4 | 745 | { |
e9eee03e | 746 | char __user *buf = ubuf; |
f0de53bb | 747 | unsigned long *cpu_tsc; |
ef41df43 | 748 | unsigned prev, next; |
1da177e4 LT |
749 | int i, err; |
750 | ||
6bca67f9 | 751 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
752 | if (!cpu_tsc) |
753 | return -ENOMEM; | |
754 | ||
8c8b8859 | 755 | mutex_lock(&mce_read_mutex); |
1da177e4 LT |
756 | next = rcu_dereference(mcelog.next); |
757 | ||
758 | /* Only supports full reads right now */ | |
d88203d1 | 759 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) { |
8c8b8859 | 760 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 761 | kfree(cpu_tsc); |
e9eee03e | 762 | |
1da177e4 LT |
763 | return -EINVAL; |
764 | } | |
765 | ||
766 | err = 0; | |
ef41df43 HY |
767 | prev = 0; |
768 | do { | |
769 | for (i = prev; i < next; i++) { | |
770 | unsigned long start = jiffies; | |
771 | ||
772 | while (!mcelog.entry[i].finished) { | |
773 | if (time_after_eq(jiffies, start + 2)) { | |
774 | memset(mcelog.entry + i, 0, | |
775 | sizeof(struct mce)); | |
776 | goto timeout; | |
777 | } | |
778 | cpu_relax(); | |
673242c1 | 779 | } |
ef41df43 HY |
780 | smp_rmb(); |
781 | err |= copy_to_user(buf, mcelog.entry + i, | |
782 | sizeof(struct mce)); | |
783 | buf += sizeof(struct mce); | |
784 | timeout: | |
785 | ; | |
673242c1 | 786 | } |
1da177e4 | 787 | |
ef41df43 HY |
788 | memset(mcelog.entry + prev, 0, |
789 | (next - prev) * sizeof(struct mce)); | |
790 | prev = next; | |
791 | next = cmpxchg(&mcelog.next, prev, 0); | |
792 | } while (next != prev); | |
1da177e4 | 793 | |
b2b18660 | 794 | synchronize_sched(); |
1da177e4 | 795 | |
d88203d1 TG |
796 | /* |
797 | * Collect entries that were still getting written before the | |
798 | * synchronize. | |
799 | */ | |
15c8b6c1 | 800 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 801 | |
d88203d1 TG |
802 | for (i = next; i < MCE_LOG_LEN; i++) { |
803 | if (mcelog.entry[i].finished && | |
804 | mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) { | |
805 | err |= copy_to_user(buf, mcelog.entry+i, | |
806 | sizeof(struct mce)); | |
1da177e4 LT |
807 | smp_rmb(); |
808 | buf += sizeof(struct mce); | |
809 | memset(&mcelog.entry[i], 0, sizeof(struct mce)); | |
810 | } | |
d88203d1 | 811 | } |
8c8b8859 | 812 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 813 | kfree(cpu_tsc); |
e9eee03e | 814 | |
d88203d1 | 815 | return err ? -EFAULT : buf - ubuf; |
1da177e4 LT |
816 | } |
817 | ||
e02e68d3 TH |
818 | static unsigned int mce_poll(struct file *file, poll_table *wait) |
819 | { | |
820 | poll_wait(file, &mce_wait, wait); | |
821 | if (rcu_dereference(mcelog.next)) | |
822 | return POLLIN | POLLRDNORM; | |
823 | return 0; | |
824 | } | |
825 | ||
c68461b6 | 826 | static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg) |
1da177e4 LT |
827 | { |
828 | int __user *p = (int __user *)arg; | |
d88203d1 | 829 | |
1da177e4 | 830 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 831 | return -EPERM; |
e9eee03e | 832 | |
1da177e4 | 833 | switch (cmd) { |
d88203d1 | 834 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
835 | return put_user(sizeof(struct mce), p); |
836 | case MCE_GET_LOG_LEN: | |
d88203d1 | 837 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
838 | case MCE_GETCLEAR_FLAGS: { |
839 | unsigned flags; | |
d88203d1 TG |
840 | |
841 | do { | |
1da177e4 | 842 | flags = mcelog.flags; |
d88203d1 | 843 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 844 | |
d88203d1 | 845 | return put_user(flags, p); |
1da177e4 LT |
846 | } |
847 | default: | |
d88203d1 TG |
848 | return -ENOTTY; |
849 | } | |
1da177e4 LT |
850 | } |
851 | ||
5dfe4c96 | 852 | static const struct file_operations mce_chrdev_ops = { |
e9eee03e IM |
853 | .open = mce_open, |
854 | .release = mce_release, | |
855 | .read = mce_read, | |
856 | .poll = mce_poll, | |
857 | .unlocked_ioctl = mce_ioctl, | |
1da177e4 LT |
858 | }; |
859 | ||
860 | static struct miscdevice mce_log_device = { | |
861 | MISC_MCELOG_MINOR, | |
862 | "mcelog", | |
863 | &mce_chrdev_ops, | |
864 | }; | |
865 | ||
d88203d1 TG |
866 | /* |
867 | * Old style boot options parsing. Only for compatibility. | |
1da177e4 | 868 | */ |
1da177e4 LT |
869 | static int __init mcheck_disable(char *str) |
870 | { | |
871 | mce_dont_init = 1; | |
9b41046c | 872 | return 1; |
1da177e4 | 873 | } |
13503fa9 | 874 | __setup("nomce", mcheck_disable); |
1da177e4 | 875 | |
13503fa9 HS |
876 | /* |
877 | * mce=off disables machine check | |
878 | * mce=TOLERANCELEVEL (number, see above) | |
879 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. | |
880 | * mce=nobootlog Don't log MCEs from before booting. | |
881 | */ | |
1da177e4 LT |
882 | static int __init mcheck_enable(char *str) |
883 | { | |
884 | if (!strcmp(str, "off")) | |
885 | mce_dont_init = 1; | |
13503fa9 HS |
886 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
887 | mce_bootlog = (str[0] == 'b'); | |
8c566ef5 AK |
888 | else if (isdigit(str[0])) |
889 | get_option(&str, &tolerant); | |
13503fa9 HS |
890 | else { |
891 | printk(KERN_INFO "mce= argument %s ignored. Please use /sys\n", | |
892 | str); | |
893 | return 0; | |
894 | } | |
9b41046c | 895 | return 1; |
1da177e4 | 896 | } |
909dd324 | 897 | __setup("mce=", mcheck_enable); |
1da177e4 | 898 | |
d88203d1 | 899 | /* |
1da177e4 | 900 | * Sysfs support |
d88203d1 | 901 | */ |
1da177e4 | 902 | |
973a2dd1 AK |
903 | /* |
904 | * Disable machine checks on suspend and shutdown. We can't really handle | |
905 | * them later. | |
906 | */ | |
907 | static int mce_disable(void) | |
908 | { | |
909 | int i; | |
910 | ||
911 | for (i = 0; i < banks; i++) | |
912 | wrmsrl(MSR_IA32_MC0_CTL + i*4, 0); | |
913 | return 0; | |
914 | } | |
915 | ||
916 | static int mce_suspend(struct sys_device *dev, pm_message_t state) | |
917 | { | |
918 | return mce_disable(); | |
919 | } | |
920 | ||
921 | static int mce_shutdown(struct sys_device *dev) | |
922 | { | |
923 | return mce_disable(); | |
924 | } | |
925 | ||
e9eee03e IM |
926 | /* |
927 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
928 | * Only one CPU is active at this time, the others get re-added later using | |
929 | * CPU hotplug: | |
930 | */ | |
1da177e4 LT |
931 | static int mce_resume(struct sys_device *dev) |
932 | { | |
413588c7 | 933 | mce_init(NULL); |
6ec68bff | 934 | mce_cpu_features(¤t_cpu_data); |
e9eee03e | 935 | |
1da177e4 LT |
936 | return 0; |
937 | } | |
938 | ||
52d168e2 AK |
939 | static void mce_cpu_restart(void *data) |
940 | { | |
941 | del_timer_sync(&__get_cpu_var(mce_timer)); | |
942 | if (mce_available(¤t_cpu_data)) | |
943 | mce_init(NULL); | |
944 | mce_init_timer(); | |
945 | } | |
946 | ||
1da177e4 | 947 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
948 | static void mce_restart(void) |
949 | { | |
52d168e2 | 950 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
951 | } |
952 | ||
953 | static struct sysdev_class mce_sysclass = { | |
e9eee03e IM |
954 | .suspend = mce_suspend, |
955 | .shutdown = mce_shutdown, | |
956 | .resume = mce_resume, | |
957 | .name = "machinecheck", | |
1da177e4 LT |
958 | }; |
959 | ||
fff2e89f | 960 | DEFINE_PER_CPU(struct sys_device, device_mce); |
e9eee03e IM |
961 | |
962 | __cpuinitdata | |
963 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); | |
1da177e4 LT |
964 | |
965 | /* Why are there no generic functions for this? */ | |
966 | #define ACCESSOR(name, var, start) \ | |
4a0b2b4d AK |
967 | static ssize_t show_ ## name(struct sys_device *s, \ |
968 | struct sysdev_attribute *attr, \ | |
969 | char *buf) { \ | |
d88203d1 TG |
970 | return sprintf(buf, "%lx\n", (unsigned long)var); \ |
971 | } \ | |
4a0b2b4d AK |
972 | static ssize_t set_ ## name(struct sys_device *s, \ |
973 | struct sysdev_attribute *attr, \ | |
974 | const char *buf, size_t siz) { \ | |
d88203d1 TG |
975 | char *end; \ |
976 | unsigned long new = simple_strtoul(buf, &end, 0); \ | |
e9eee03e IM |
977 | \ |
978 | if (end == buf) \ | |
979 | return -EINVAL; \ | |
d88203d1 TG |
980 | var = new; \ |
981 | start; \ | |
e9eee03e | 982 | \ |
d88203d1 TG |
983 | return end-buf; \ |
984 | } \ | |
1da177e4 LT |
985 | static SYSDEV_ATTR(name, 0644, show_ ## name, set_ ## name); |
986 | ||
0d7482e3 AK |
987 | static struct sysdev_attribute *bank_attrs; |
988 | ||
989 | static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
990 | char *buf) | |
991 | { | |
992 | u64 b = bank[attr - bank_attrs]; | |
e9eee03e | 993 | |
f6d1826d | 994 | return sprintf(buf, "%llx\n", b); |
0d7482e3 AK |
995 | } |
996 | ||
997 | static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
998 | const char *buf, size_t siz) | |
999 | { | |
1000 | char *end; | |
1001 | u64 new = simple_strtoull(buf, &end, 0); | |
e9eee03e | 1002 | |
0d7482e3 AK |
1003 | if (end == buf) |
1004 | return -EINVAL; | |
e9eee03e | 1005 | |
0d7482e3 AK |
1006 | bank[attr - bank_attrs] = new; |
1007 | mce_restart(); | |
e9eee03e | 1008 | |
0d7482e3 AK |
1009 | return end-buf; |
1010 | } | |
a98f0dd3 | 1011 | |
e9eee03e IM |
1012 | static ssize_t |
1013 | show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf) | |
a98f0dd3 AK |
1014 | { |
1015 | strcpy(buf, trigger); | |
1016 | strcat(buf, "\n"); | |
1017 | return strlen(trigger) + 1; | |
1018 | } | |
1019 | ||
4a0b2b4d | 1020 | static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr, |
e9eee03e | 1021 | const char *buf, size_t siz) |
a98f0dd3 AK |
1022 | { |
1023 | char *p; | |
1024 | int len; | |
e9eee03e | 1025 | |
a98f0dd3 AK |
1026 | strncpy(trigger, buf, sizeof(trigger)); |
1027 | trigger[sizeof(trigger)-1] = 0; | |
1028 | len = strlen(trigger); | |
1029 | p = strchr(trigger, '\n'); | |
e9eee03e IM |
1030 | |
1031 | if (*p) | |
1032 | *p = 0; | |
1033 | ||
a98f0dd3 AK |
1034 | return len; |
1035 | } | |
1036 | ||
1037 | static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger); | |
d95d62c0 | 1038 | static SYSDEV_INT_ATTR(tolerant, 0644, tolerant); |
e9eee03e IM |
1039 | |
1040 | ACCESSOR(check_interval, check_interval, mce_restart()) | |
1041 | ||
a98f0dd3 | 1042 | static struct sysdev_attribute *mce_attributes[] = { |
d95d62c0 | 1043 | &attr_tolerant.attr, &attr_check_interval, &attr_trigger, |
a98f0dd3 AK |
1044 | NULL |
1045 | }; | |
1da177e4 | 1046 | |
996867d0 | 1047 | static cpumask_var_t mce_device_initialized; |
bae19fe0 | 1048 | |
e9eee03e | 1049 | /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */ |
91c6d400 | 1050 | static __cpuinit int mce_create_device(unsigned int cpu) |
1da177e4 LT |
1051 | { |
1052 | int err; | |
73ca5358 | 1053 | int i; |
92cb7612 | 1054 | |
90367556 | 1055 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
1056 | return -EIO; |
1057 | ||
d435d862 | 1058 | memset(&per_cpu(device_mce, cpu).kobj, 0, sizeof(struct kobject)); |
e9eee03e IM |
1059 | per_cpu(device_mce, cpu).id = cpu; |
1060 | per_cpu(device_mce, cpu).cls = &mce_sysclass; | |
91c6d400 | 1061 | |
e9eee03e | 1062 | err = sysdev_register(&per_cpu(device_mce, cpu)); |
d435d862 AM |
1063 | if (err) |
1064 | return err; | |
1065 | ||
1066 | for (i = 0; mce_attributes[i]; i++) { | |
e9eee03e | 1067 | err = sysdev_create_file(&per_cpu(device_mce, cpu), |
d435d862 AM |
1068 | mce_attributes[i]); |
1069 | if (err) | |
1070 | goto error; | |
1071 | } | |
0d7482e3 AK |
1072 | for (i = 0; i < banks; i++) { |
1073 | err = sysdev_create_file(&per_cpu(device_mce, cpu), | |
1074 | &bank_attrs[i]); | |
1075 | if (err) | |
1076 | goto error2; | |
1077 | } | |
996867d0 | 1078 | cpumask_set_cpu(cpu, mce_device_initialized); |
91c6d400 | 1079 | |
d435d862 | 1080 | return 0; |
0d7482e3 AK |
1081 | error2: |
1082 | while (--i >= 0) { | |
1083 | sysdev_remove_file(&per_cpu(device_mce, cpu), | |
1084 | &bank_attrs[i]); | |
1085 | } | |
d435d862 | 1086 | error: |
0d7482e3 | 1087 | while (--i >= 0) { |
e9eee03e | 1088 | sysdev_remove_file(&per_cpu(device_mce, cpu), |
d435d862 | 1089 | mce_attributes[i]); |
91c6d400 | 1090 | } |
e9eee03e | 1091 | sysdev_unregister(&per_cpu(device_mce, cpu)); |
d435d862 | 1092 | |
91c6d400 AK |
1093 | return err; |
1094 | } | |
1095 | ||
2d9cd6c2 | 1096 | static __cpuinit void mce_remove_device(unsigned int cpu) |
91c6d400 | 1097 | { |
73ca5358 SL |
1098 | int i; |
1099 | ||
996867d0 | 1100 | if (!cpumask_test_cpu(cpu, mce_device_initialized)) |
bae19fe0 AH |
1101 | return; |
1102 | ||
a98f0dd3 | 1103 | for (i = 0; mce_attributes[i]; i++) |
e9eee03e | 1104 | sysdev_remove_file(&per_cpu(device_mce, cpu), |
a98f0dd3 | 1105 | mce_attributes[i]); |
0d7482e3 AK |
1106 | for (i = 0; i < banks; i++) |
1107 | sysdev_remove_file(&per_cpu(device_mce, cpu), | |
1108 | &bank_attrs[i]); | |
e9eee03e | 1109 | sysdev_unregister(&per_cpu(device_mce, cpu)); |
996867d0 | 1110 | cpumask_clear_cpu(cpu, mce_device_initialized); |
91c6d400 | 1111 | } |
91c6d400 | 1112 | |
d6b75584 | 1113 | /* Make sure there are no machine checks on offlined CPUs. */ |
ec5b3d32 | 1114 | static void mce_disable_cpu(void *h) |
d6b75584 AK |
1115 | { |
1116 | int i; | |
88ccbedd | 1117 | unsigned long action = *(unsigned long *)h; |
d6b75584 AK |
1118 | |
1119 | if (!mce_available(¤t_cpu_data)) | |
1120 | return; | |
88ccbedd AK |
1121 | if (!(action & CPU_TASKS_FROZEN)) |
1122 | cmci_clear(); | |
d6b75584 AK |
1123 | for (i = 0; i < banks; i++) |
1124 | wrmsrl(MSR_IA32_MC0_CTL + i*4, 0); | |
1125 | } | |
1126 | ||
ec5b3d32 | 1127 | static void mce_reenable_cpu(void *h) |
d6b75584 | 1128 | { |
88ccbedd | 1129 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 1130 | int i; |
d6b75584 AK |
1131 | |
1132 | if (!mce_available(¤t_cpu_data)) | |
1133 | return; | |
e9eee03e | 1134 | |
88ccbedd AK |
1135 | if (!(action & CPU_TASKS_FROZEN)) |
1136 | cmci_reenable(); | |
d6b75584 AK |
1137 | for (i = 0; i < banks; i++) |
1138 | wrmsrl(MSR_IA32_MC0_CTL + i*4, bank[i]); | |
1139 | } | |
1140 | ||
91c6d400 | 1141 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
e9eee03e IM |
1142 | static int __cpuinit |
1143 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) | |
91c6d400 AK |
1144 | { |
1145 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 1146 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 AK |
1147 | |
1148 | switch (action) { | |
bae19fe0 AH |
1149 | case CPU_ONLINE: |
1150 | case CPU_ONLINE_FROZEN: | |
1151 | mce_create_device(cpu); | |
8735728e RW |
1152 | if (threshold_cpu_callback) |
1153 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 1154 | break; |
91c6d400 | 1155 | case CPU_DEAD: |
8bb78442 | 1156 | case CPU_DEAD_FROZEN: |
8735728e RW |
1157 | if (threshold_cpu_callback) |
1158 | threshold_cpu_callback(action, cpu); | |
91c6d400 AK |
1159 | mce_remove_device(cpu); |
1160 | break; | |
52d168e2 AK |
1161 | case CPU_DOWN_PREPARE: |
1162 | case CPU_DOWN_PREPARE_FROZEN: | |
1163 | del_timer_sync(t); | |
88ccbedd | 1164 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
52d168e2 AK |
1165 | break; |
1166 | case CPU_DOWN_FAILED: | |
1167 | case CPU_DOWN_FAILED_FROZEN: | |
6298c512 AK |
1168 | t->expires = round_jiffies(jiffies + |
1169 | __get_cpu_var(next_interval)); | |
52d168e2 | 1170 | add_timer_on(t, cpu); |
88ccbedd AK |
1171 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
1172 | break; | |
1173 | case CPU_POST_DEAD: | |
1174 | /* intentionally ignoring frozen here */ | |
1175 | cmci_rediscover(cpu); | |
52d168e2 | 1176 | break; |
91c6d400 | 1177 | } |
bae19fe0 | 1178 | return NOTIFY_OK; |
91c6d400 AK |
1179 | } |
1180 | ||
1e35669d | 1181 | static struct notifier_block mce_cpu_notifier __cpuinitdata = { |
91c6d400 AK |
1182 | .notifier_call = mce_cpu_callback, |
1183 | }; | |
1184 | ||
0d7482e3 AK |
1185 | static __init int mce_init_banks(void) |
1186 | { | |
1187 | int i; | |
1188 | ||
1189 | bank_attrs = kzalloc(sizeof(struct sysdev_attribute) * banks, | |
1190 | GFP_KERNEL); | |
1191 | if (!bank_attrs) | |
1192 | return -ENOMEM; | |
1193 | ||
1194 | for (i = 0; i < banks; i++) { | |
1195 | struct sysdev_attribute *a = &bank_attrs[i]; | |
e9eee03e IM |
1196 | |
1197 | a->attr.name = kasprintf(GFP_KERNEL, "bank%d", i); | |
0d7482e3 AK |
1198 | if (!a->attr.name) |
1199 | goto nomem; | |
e9eee03e IM |
1200 | |
1201 | a->attr.mode = 0644; | |
1202 | a->show = show_bank; | |
1203 | a->store = set_bank; | |
0d7482e3 AK |
1204 | } |
1205 | return 0; | |
1206 | ||
1207 | nomem: | |
1208 | while (--i >= 0) | |
1209 | kfree(bank_attrs[i].attr.name); | |
1210 | kfree(bank_attrs); | |
1211 | bank_attrs = NULL; | |
e9eee03e | 1212 | |
0d7482e3 AK |
1213 | return -ENOMEM; |
1214 | } | |
1215 | ||
91c6d400 AK |
1216 | static __init int mce_init_device(void) |
1217 | { | |
1218 | int err; | |
1219 | int i = 0; | |
1220 | ||
1da177e4 LT |
1221 | if (!mce_available(&boot_cpu_data)) |
1222 | return -EIO; | |
0d7482e3 | 1223 | |
996867d0 RR |
1224 | alloc_cpumask_var(&mce_device_initialized, GFP_KERNEL); |
1225 | ||
0d7482e3 AK |
1226 | err = mce_init_banks(); |
1227 | if (err) | |
1228 | return err; | |
1229 | ||
1da177e4 | 1230 | err = sysdev_class_register(&mce_sysclass); |
d435d862 AM |
1231 | if (err) |
1232 | return err; | |
91c6d400 AK |
1233 | |
1234 | for_each_online_cpu(i) { | |
d435d862 AM |
1235 | err = mce_create_device(i); |
1236 | if (err) | |
1237 | return err; | |
91c6d400 AK |
1238 | } |
1239 | ||
be6b5a35 | 1240 | register_hotcpu_notifier(&mce_cpu_notifier); |
1da177e4 | 1241 | misc_register(&mce_log_device); |
e9eee03e | 1242 | |
1da177e4 | 1243 | return err; |
1da177e4 | 1244 | } |
91c6d400 | 1245 | |
1da177e4 | 1246 | device_initcall(mce_init_device); |
a988d334 | 1247 | |
711c2e48 | 1248 | #else /* CONFIG_X86_32: */ |
a988d334 IM |
1249 | |
1250 | int mce_disabled; | |
1251 | ||
1252 | int nr_mce_banks; | |
1253 | EXPORT_SYMBOL_GPL(nr_mce_banks); /* non-fatal.o */ | |
1254 | ||
1255 | /* Handle unconfigured int18 (should never happen) */ | |
1256 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
1257 | { | |
1258 | printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n", | |
1259 | smp_processor_id()); | |
1260 | } | |
1261 | ||
1262 | /* Call the installed machine check handler for this CPU setup. */ | |
1263 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
1264 | unexpected_machine_check; | |
1265 | ||
1266 | /* This has to be run for each processor */ | |
1267 | void mcheck_init(struct cpuinfo_x86 *c) | |
1268 | { | |
1269 | if (mce_disabled == 1) | |
1270 | return; | |
1271 | ||
1272 | switch (c->x86_vendor) { | |
1273 | case X86_VENDOR_AMD: | |
1274 | amd_mcheck_init(c); | |
1275 | break; | |
1276 | ||
1277 | case X86_VENDOR_INTEL: | |
1278 | if (c->x86 == 5) | |
1279 | intel_p5_mcheck_init(c); | |
1280 | if (c->x86 == 6) | |
1281 | intel_p6_mcheck_init(c); | |
1282 | if (c->x86 == 15) | |
1283 | intel_p4_mcheck_init(c); | |
1284 | break; | |
1285 | ||
1286 | case X86_VENDOR_CENTAUR: | |
1287 | if (c->x86 == 5) | |
1288 | winchip_mcheck_init(c); | |
1289 | break; | |
1290 | ||
1291 | default: | |
1292 | break; | |
1293 | } | |
1294 | } | |
1295 | ||
1296 | static int __init mcheck_disable(char *str) | |
1297 | { | |
1298 | mce_disabled = 1; | |
1299 | return 1; | |
1300 | } | |
1301 | ||
1302 | static int __init mcheck_enable(char *str) | |
1303 | { | |
1304 | mce_disabled = -1; | |
1305 | return 1; | |
1306 | } | |
1307 | ||
1308 | __setup("nomce", mcheck_disable); | |
1309 | __setup("mce", mcheck_enable); | |
1310 | ||
1311 | #endif /* CONFIG_X86_32 */ |