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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
c767a54b JP |
10 | |
11 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
12 | ||
e9eee03e IM |
13 | #include <linux/thread_info.h> |
14 | #include <linux/capability.h> | |
15 | #include <linux/miscdevice.h> | |
16 | #include <linux/ratelimit.h> | |
17 | #include <linux/kallsyms.h> | |
18 | #include <linux/rcupdate.h> | |
e9eee03e | 19 | #include <linux/kobject.h> |
14a02530 | 20 | #include <linux/uaccess.h> |
e9eee03e IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/kernel.h> | |
23 | #include <linux/percpu.h> | |
1da177e4 | 24 | #include <linux/string.h> |
8a25a2fd | 25 | #include <linux/device.h> |
f3c6ea1b | 26 | #include <linux/syscore_ops.h> |
3c079792 | 27 | #include <linux/delay.h> |
8c566ef5 | 28 | #include <linux/ctype.h> |
e9eee03e | 29 | #include <linux/sched.h> |
0d7482e3 | 30 | #include <linux/sysfs.h> |
e9eee03e | 31 | #include <linux/types.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
e9eee03e IM |
33 | #include <linux/init.h> |
34 | #include <linux/kmod.h> | |
35 | #include <linux/poll.h> | |
3c079792 | 36 | #include <linux/nmi.h> |
e9eee03e | 37 | #include <linux/cpu.h> |
14a02530 | 38 | #include <linux/smp.h> |
e9eee03e | 39 | #include <linux/fs.h> |
9b1beaf2 | 40 | #include <linux/mm.h> |
5be9ed25 | 41 | #include <linux/debugfs.h> |
b77e70bf | 42 | #include <linux/irq_work.h> |
69c60c88 | 43 | #include <linux/export.h> |
e9eee03e | 44 | |
d88203d1 | 45 | #include <asm/processor.h> |
95927475 | 46 | #include <asm/traps.h> |
375074cc | 47 | #include <asm/tlbflush.h> |
e9eee03e IM |
48 | #include <asm/mce.h> |
49 | #include <asm/msr.h> | |
1da177e4 | 50 | |
bd19a5e6 | 51 | #include "mce-internal.h" |
711c2e48 | 52 | |
93b62c3c | 53 | static DEFINE_MUTEX(mce_chrdev_read_mutex); |
2aa2b50d | 54 | |
f56e8a07 | 55 | #define rcu_dereference_check_mce(p) \ |
e90328b8 PM |
56 | ({ \ |
57 | rcu_lockdep_assert(rcu_read_lock_sched_held() || \ | |
58 | lockdep_is_held(&mce_chrdev_read_mutex), \ | |
59 | "suspicious rcu_dereference_check_mce() usage"); \ | |
60 | smp_load_acquire(&(p)); \ | |
61 | }) | |
f56e8a07 | 62 | |
8968f9d3 HS |
63 | #define CREATE_TRACE_POINTS |
64 | #include <trace/events/mce.h> | |
65 | ||
3f2f0680 | 66 | #define SPINUNIT 100 /* 100ns */ |
3c079792 | 67 | |
01ca79f1 AK |
68 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
69 | ||
1462594b | 70 | struct mce_bank *mce_banks __read_mostly; |
bf80bbd7 | 71 | struct mce_vendor_flags mce_flags __read_mostly; |
cebe1820 | 72 | |
d203f0b8 | 73 | struct mca_config mca_cfg __read_mostly = { |
84c2559d | 74 | .bootlog = -1, |
d203f0b8 BP |
75 | /* |
76 | * Tolerant levels: | |
77 | * 0: always panic on uncorrected errors, log corrected errors | |
78 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
79 | * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors | |
80 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
81 | */ | |
84c2559d BP |
82 | .tolerant = 1, |
83 | .monarch_timeout = -1 | |
d203f0b8 BP |
84 | }; |
85 | ||
1020bcbc HS |
86 | /* User mode helper program triggered by machine check event */ |
87 | static unsigned long mce_need_notify; | |
88 | static char mce_helper[128]; | |
89 | static char *mce_helper_argv[2] = { mce_helper, NULL }; | |
1da177e4 | 90 | |
93b62c3c HS |
91 | static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait); |
92 | ||
3c079792 AK |
93 | static DEFINE_PER_CPU(struct mce, mces_seen); |
94 | static int cpu_missing; | |
95 | ||
0644414e NR |
96 | /* |
97 | * MCA banks polled by the period polling timer for corrected events. | |
98 | * With Intel CMCI, this only has MCA banks which do not support CMCI (if any). | |
99 | */ | |
ee031c31 AK |
100 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { |
101 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
102 | }; | |
103 | ||
c3d1fb56 NR |
104 | /* |
105 | * MCA banks controlled through firmware first for corrected errors. | |
106 | * This is a global list of banks for which we won't enable CMCI and we | |
107 | * won't poll. Firmware controls these banks and is responsible for | |
108 | * reporting corrected errors through GHES. Uncorrected/recoverable | |
109 | * errors are still notified through a machine check. | |
110 | */ | |
111 | mce_banks_t mce_banks_ce_disabled; | |
112 | ||
061120ae CG |
113 | static struct work_struct mce_work; |
114 | static struct irq_work mce_irq_work; | |
9b1beaf2 | 115 | |
61b0fccd | 116 | static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs); |
fd4cf79f | 117 | static int mce_usable_address(struct mce *m); |
61b0fccd | 118 | |
3653ada5 BP |
119 | /* |
120 | * CPU/chipset specific EDAC code can register a notifier call here to print | |
121 | * MCE errors in a human-readable form. | |
122 | */ | |
648ed940 | 123 | ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain); |
3653ada5 | 124 | |
b5f2fa4e AK |
125 | /* Do initial initialization of a struct mce */ |
126 | void mce_setup(struct mce *m) | |
127 | { | |
128 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 129 | m->cpu = m->extcpu = smp_processor_id(); |
b5f2fa4e | 130 | rdtscll(m->tsc); |
8ee08347 AK |
131 | /* We hope get_seconds stays lockless */ |
132 | m->time = get_seconds(); | |
133 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
134 | m->cpuid = cpuid_eax(1); | |
8ee08347 | 135 | m->socketid = cpu_data(m->extcpu).phys_proc_id; |
8ee08347 AK |
136 | m->apicid = cpu_data(m->extcpu).initial_apicid; |
137 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
b5f2fa4e AK |
138 | } |
139 | ||
ea149b36 AK |
140 | DEFINE_PER_CPU(struct mce, injectm); |
141 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
142 | ||
1da177e4 LT |
143 | /* |
144 | * Lockless MCE logging infrastructure. | |
145 | * This avoids deadlocks on printk locks without having to break locks. Also | |
146 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
147 | */ | |
148 | ||
231fd906 | 149 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
150 | .signature = MCE_LOG_SIGNATURE, |
151 | .len = MCE_LOG_LEN, | |
152 | .recordlen = sizeof(struct mce), | |
d88203d1 | 153 | }; |
1da177e4 LT |
154 | |
155 | void mce_log(struct mce *mce) | |
156 | { | |
157 | unsigned next, entry; | |
e9eee03e | 158 | |
8968f9d3 HS |
159 | /* Emit the trace record: */ |
160 | trace_mce_record(mce); | |
161 | ||
a2413d8b | 162 | atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, mce); |
f0cb5452 | 163 | |
1da177e4 | 164 | mce->finished = 0; |
7644143c | 165 | wmb(); |
1da177e4 | 166 | for (;;) { |
f56e8a07 | 167 | entry = rcu_dereference_check_mce(mcelog.next); |
673242c1 | 168 | for (;;) { |
696e409d | 169 | |
e9eee03e IM |
170 | /* |
171 | * When the buffer fills up discard new entries. | |
172 | * Assume that the earlier errors are the more | |
173 | * interesting ones: | |
174 | */ | |
673242c1 | 175 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
176 | set_bit(MCE_OVERFLOW, |
177 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
178 | return; |
179 | } | |
e9eee03e | 180 | /* Old left over entry. Skip: */ |
673242c1 AK |
181 | if (mcelog.entry[entry].finished) { |
182 | entry++; | |
183 | continue; | |
184 | } | |
7644143c | 185 | break; |
1da177e4 | 186 | } |
1da177e4 LT |
187 | smp_rmb(); |
188 | next = entry + 1; | |
189 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
190 | break; | |
191 | } | |
192 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 193 | wmb(); |
1da177e4 | 194 | mcelog.entry[entry].finished = 1; |
7644143c | 195 | wmb(); |
1da177e4 | 196 | |
a0189c70 | 197 | mce->finished = 1; |
1020bcbc | 198 | set_bit(0, &mce_need_notify); |
1da177e4 LT |
199 | } |
200 | ||
09371957 BP |
201 | static void drain_mcelog_buffer(void) |
202 | { | |
203 | unsigned int next, i, prev = 0; | |
204 | ||
b11e3d78 | 205 | next = ACCESS_ONCE(mcelog.next); |
09371957 BP |
206 | |
207 | do { | |
208 | struct mce *m; | |
209 | ||
210 | /* drain what was logged during boot */ | |
211 | for (i = prev; i < next; i++) { | |
212 | unsigned long start = jiffies; | |
213 | unsigned retries = 1; | |
214 | ||
215 | m = &mcelog.entry[i]; | |
216 | ||
217 | while (!m->finished) { | |
218 | if (time_after_eq(jiffies, start + 2*retries)) | |
219 | retries++; | |
220 | ||
221 | cpu_relax(); | |
222 | ||
223 | if (!m->finished && retries >= 4) { | |
c767a54b | 224 | pr_err("skipping error being logged currently!\n"); |
09371957 BP |
225 | break; |
226 | } | |
227 | } | |
228 | smp_rmb(); | |
229 | atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); | |
230 | } | |
231 | ||
232 | memset(mcelog.entry + prev, 0, (next - prev) * sizeof(*m)); | |
233 | prev = next; | |
234 | next = cmpxchg(&mcelog.next, prev, 0); | |
235 | } while (next != prev); | |
236 | } | |
237 | ||
fd4cf79f | 238 | static struct notifier_block mce_srao_nb; |
09371957 | 239 | |
fd4cf79f | 240 | void mce_register_decode_chain(struct notifier_block *nb, bool drain) |
3653ada5 | 241 | { |
fd4cf79f CG |
242 | /* Ensure SRAO notifier has the highest priority in the decode chain. */ |
243 | if (nb != &mce_srao_nb && nb->priority == INT_MAX) | |
244 | nb->priority -= 1; | |
245 | ||
3653ada5 | 246 | atomic_notifier_chain_register(&x86_mce_decoder_chain, nb); |
fd4cf79f CG |
247 | |
248 | if (drain) | |
249 | drain_mcelog_buffer(); | |
3653ada5 BP |
250 | } |
251 | EXPORT_SYMBOL_GPL(mce_register_decode_chain); | |
252 | ||
253 | void mce_unregister_decode_chain(struct notifier_block *nb) | |
254 | { | |
255 | atomic_notifier_chain_unregister(&x86_mce_decoder_chain, nb); | |
256 | } | |
257 | EXPORT_SYMBOL_GPL(mce_unregister_decode_chain); | |
258 | ||
77e26cca | 259 | static void print_mce(struct mce *m) |
1da177e4 | 260 | { |
dffa4b2f BP |
261 | int ret = 0; |
262 | ||
a2d7b0d4 | 263 | pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n", |
d620c67f | 264 | m->extcpu, m->mcgstatus, m->bank, m->status); |
f436f8bb | 265 | |
65ea5b03 | 266 | if (m->ip) { |
a2d7b0d4 | 267 | pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", |
f436f8bb IM |
268 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
269 | m->cs, m->ip); | |
270 | ||
1da177e4 | 271 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 272 | print_symbol("{%s}", m->ip); |
f436f8bb | 273 | pr_cont("\n"); |
1da177e4 | 274 | } |
f436f8bb | 275 | |
a2d7b0d4 | 276 | pr_emerg(HW_ERR "TSC %llx ", m->tsc); |
1da177e4 | 277 | if (m->addr) |
f436f8bb | 278 | pr_cont("ADDR %llx ", m->addr); |
1da177e4 | 279 | if (m->misc) |
f436f8bb | 280 | pr_cont("MISC %llx ", m->misc); |
549d042d | 281 | |
f436f8bb | 282 | pr_cont("\n"); |
506ed6b5 AK |
283 | /* |
284 | * Note this output is parsed by external tools and old fields | |
285 | * should not be changed. | |
286 | */ | |
881e23e5 | 287 | pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n", |
506ed6b5 AK |
288 | m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, |
289 | cpu_data(m->extcpu).microcode); | |
f436f8bb IM |
290 | |
291 | /* | |
292 | * Print out human-readable details about the MCE error, | |
fb253195 | 293 | * (if the CPU has an implementation for that) |
f436f8bb | 294 | */ |
dffa4b2f BP |
295 | ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); |
296 | if (ret == NOTIFY_STOP) | |
297 | return; | |
298 | ||
299 | pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); | |
86503560 AK |
300 | } |
301 | ||
f94b61c2 AK |
302 | #define PANIC_TIMEOUT 5 /* 5 seconds */ |
303 | ||
c7c9b392 | 304 | static atomic_t mce_panicked; |
f94b61c2 | 305 | |
bf783f9f | 306 | static int fake_panic; |
c7c9b392 | 307 | static atomic_t mce_fake_panicked; |
bf783f9f | 308 | |
f94b61c2 AK |
309 | /* Panic in progress. Enable interrupts and wait for final IPI */ |
310 | static void wait_for_panic(void) | |
311 | { | |
312 | long timeout = PANIC_TIMEOUT*USEC_PER_SEC; | |
f436f8bb | 313 | |
f94b61c2 AK |
314 | preempt_disable(); |
315 | local_irq_enable(); | |
316 | while (timeout-- > 0) | |
317 | udelay(1); | |
29b0f591 | 318 | if (panic_timeout == 0) |
7af19e4a | 319 | panic_timeout = mca_cfg.panic_timeout; |
f94b61c2 AK |
320 | panic("Panicing machine check CPU died"); |
321 | } | |
322 | ||
6c80f87e | 323 | static void mce_panic(const char *msg, struct mce *final, char *exp) |
d88203d1 | 324 | { |
482908b4 | 325 | int i, apei_err = 0; |
e02e68d3 | 326 | |
bf783f9f HY |
327 | if (!fake_panic) { |
328 | /* | |
329 | * Make sure only one CPU runs in machine check panic | |
330 | */ | |
c7c9b392 | 331 | if (atomic_inc_return(&mce_panicked) > 1) |
bf783f9f HY |
332 | wait_for_panic(); |
333 | barrier(); | |
f94b61c2 | 334 | |
bf783f9f HY |
335 | bust_spinlocks(1); |
336 | console_verbose(); | |
337 | } else { | |
338 | /* Don't log too much for fake panic */ | |
c7c9b392 | 339 | if (atomic_inc_return(&mce_fake_panicked) > 1) |
bf783f9f HY |
340 | return; |
341 | } | |
a0189c70 | 342 | /* First print corrected ones that are still unlogged */ |
1da177e4 | 343 | for (i = 0; i < MCE_LOG_LEN; i++) { |
a0189c70 | 344 | struct mce *m = &mcelog.entry[i]; |
77e26cca HS |
345 | if (!(m->status & MCI_STATUS_VAL)) |
346 | continue; | |
482908b4 | 347 | if (!(m->status & MCI_STATUS_UC)) { |
77e26cca | 348 | print_mce(m); |
482908b4 HY |
349 | if (!apei_err) |
350 | apei_err = apei_write_mce(m); | |
351 | } | |
a0189c70 AK |
352 | } |
353 | /* Now print uncorrected but with the final one last */ | |
354 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
355 | struct mce *m = &mcelog.entry[i]; | |
356 | if (!(m->status & MCI_STATUS_VAL)) | |
1da177e4 | 357 | continue; |
77e26cca HS |
358 | if (!(m->status & MCI_STATUS_UC)) |
359 | continue; | |
482908b4 | 360 | if (!final || memcmp(m, final, sizeof(struct mce))) { |
77e26cca | 361 | print_mce(m); |
482908b4 HY |
362 | if (!apei_err) |
363 | apei_err = apei_write_mce(m); | |
364 | } | |
1da177e4 | 365 | } |
482908b4 | 366 | if (final) { |
77e26cca | 367 | print_mce(final); |
482908b4 HY |
368 | if (!apei_err) |
369 | apei_err = apei_write_mce(final); | |
370 | } | |
3c079792 | 371 | if (cpu_missing) |
a2d7b0d4 | 372 | pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n"); |
bd19a5e6 | 373 | if (exp) |
a2d7b0d4 | 374 | pr_emerg(HW_ERR "Machine check: %s\n", exp); |
bf783f9f HY |
375 | if (!fake_panic) { |
376 | if (panic_timeout == 0) | |
7af19e4a | 377 | panic_timeout = mca_cfg.panic_timeout; |
bf783f9f HY |
378 | panic(msg); |
379 | } else | |
a2d7b0d4 | 380 | pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); |
d88203d1 | 381 | } |
1da177e4 | 382 | |
ea149b36 AK |
383 | /* Support code for software error injection */ |
384 | ||
385 | static int msr_to_offset(u32 msr) | |
386 | { | |
0a3aee0d | 387 | unsigned bank = __this_cpu_read(injectm.bank); |
f436f8bb | 388 | |
84c2559d | 389 | if (msr == mca_cfg.rip_msr) |
ea149b36 | 390 | return offsetof(struct mce, ip); |
a2d32bcb | 391 | if (msr == MSR_IA32_MCx_STATUS(bank)) |
ea149b36 | 392 | return offsetof(struct mce, status); |
a2d32bcb | 393 | if (msr == MSR_IA32_MCx_ADDR(bank)) |
ea149b36 | 394 | return offsetof(struct mce, addr); |
a2d32bcb | 395 | if (msr == MSR_IA32_MCx_MISC(bank)) |
ea149b36 AK |
396 | return offsetof(struct mce, misc); |
397 | if (msr == MSR_IA32_MCG_STATUS) | |
398 | return offsetof(struct mce, mcgstatus); | |
399 | return -1; | |
400 | } | |
401 | ||
5f8c1a54 AK |
402 | /* MSR access wrappers used for error injection */ |
403 | static u64 mce_rdmsrl(u32 msr) | |
404 | { | |
405 | u64 v; | |
11868a2d | 406 | |
0a3aee0d | 407 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 408 | int offset = msr_to_offset(msr); |
11868a2d | 409 | |
ea149b36 AK |
410 | if (offset < 0) |
411 | return 0; | |
89cbc767 | 412 | return *(u64 *)((char *)this_cpu_ptr(&injectm) + offset); |
ea149b36 | 413 | } |
11868a2d IM |
414 | |
415 | if (rdmsrl_safe(msr, &v)) { | |
416 | WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr); | |
417 | /* | |
418 | * Return zero in case the access faulted. This should | |
419 | * not happen normally but can happen if the CPU does | |
420 | * something weird, or if the code is buggy. | |
421 | */ | |
422 | v = 0; | |
423 | } | |
424 | ||
5f8c1a54 AK |
425 | return v; |
426 | } | |
427 | ||
428 | static void mce_wrmsrl(u32 msr, u64 v) | |
429 | { | |
0a3aee0d | 430 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 431 | int offset = msr_to_offset(msr); |
11868a2d | 432 | |
ea149b36 | 433 | if (offset >= 0) |
89cbc767 | 434 | *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v; |
ea149b36 AK |
435 | return; |
436 | } | |
5f8c1a54 AK |
437 | wrmsrl(msr, v); |
438 | } | |
439 | ||
b8325c5b HS |
440 | /* |
441 | * Collect all global (w.r.t. this processor) status about this machine | |
442 | * check into our "mce" struct so that we can use it later to assess | |
443 | * the severity of the problem as we read per-bank specific details. | |
444 | */ | |
445 | static inline void mce_gather_info(struct mce *m, struct pt_regs *regs) | |
446 | { | |
447 | mce_setup(m); | |
448 | ||
449 | m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); | |
450 | if (regs) { | |
451 | /* | |
452 | * Get the address of the instruction at the time of | |
453 | * the machine check error. | |
454 | */ | |
455 | if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) { | |
456 | m->ip = regs->ip; | |
457 | m->cs = regs->cs; | |
a129a7c8 AK |
458 | |
459 | /* | |
460 | * When in VM86 mode make the cs look like ring 3 | |
461 | * always. This is a lie, but it's better than passing | |
462 | * the additional vm86 bit around everywhere. | |
463 | */ | |
464 | if (v8086_mode(regs)) | |
465 | m->cs |= 3; | |
b8325c5b HS |
466 | } |
467 | /* Use accurate RIP reporting if available. */ | |
84c2559d BP |
468 | if (mca_cfg.rip_msr) |
469 | m->ip = mce_rdmsrl(mca_cfg.rip_msr); | |
b8325c5b HS |
470 | } |
471 | } | |
472 | ||
88ccbedd | 473 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 474 | { |
1462594b | 475 | if (mca_cfg.disabled) |
5b4408fd | 476 | return 0; |
3d1712c9 | 477 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
478 | } |
479 | ||
9b1beaf2 AK |
480 | static void mce_schedule_work(void) |
481 | { | |
fd4cf79f | 482 | if (!mce_gen_pool_empty() && keventd_up()) |
061120ae | 483 | schedule_work(&mce_work); |
9b1beaf2 AK |
484 | } |
485 | ||
b77e70bf | 486 | static void mce_irq_work_cb(struct irq_work *entry) |
ccc3c319 | 487 | { |
9ff36ee9 | 488 | mce_notify_irq(); |
9b1beaf2 | 489 | mce_schedule_work(); |
ccc3c319 | 490 | } |
ccc3c319 AK |
491 | |
492 | static void mce_report_event(struct pt_regs *regs) | |
493 | { | |
494 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { | |
9ff36ee9 | 495 | mce_notify_irq(); |
9b1beaf2 AK |
496 | /* |
497 | * Triggering the work queue here is just an insurance | |
498 | * policy in case the syscall exit notify handler | |
499 | * doesn't run soon enough or ends up running on the | |
500 | * wrong CPU (can happen when audit sleeps) | |
501 | */ | |
502 | mce_schedule_work(); | |
ccc3c319 AK |
503 | return; |
504 | } | |
505 | ||
061120ae | 506 | irq_work_queue(&mce_irq_work); |
ccc3c319 AK |
507 | } |
508 | ||
fd4cf79f CG |
509 | static int srao_decode_notifier(struct notifier_block *nb, unsigned long val, |
510 | void *data) | |
511 | { | |
512 | struct mce *mce = (struct mce *)data; | |
513 | unsigned long pfn; | |
514 | ||
515 | if (!mce) | |
516 | return NOTIFY_DONE; | |
517 | ||
518 | if (mce->usable_addr && (mce->severity == MCE_AO_SEVERITY)) { | |
519 | pfn = mce->addr >> PAGE_SHIFT; | |
520 | memory_failure(pfn, MCE_VECTOR, 0); | |
521 | } | |
522 | ||
523 | return NOTIFY_OK; | |
524 | } | |
525 | static struct notifier_block mce_srao_nb = { | |
526 | .notifier_call = srao_decode_notifier, | |
527 | .priority = INT_MAX, | |
528 | }; | |
529 | ||
85f92694 TL |
530 | /* |
531 | * Read ADDR and MISC registers. | |
532 | */ | |
533 | static void mce_read_aux(struct mce *m, int i) | |
534 | { | |
535 | if (m->status & MCI_STATUS_MISCV) | |
536 | m->misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); | |
537 | if (m->status & MCI_STATUS_ADDRV) { | |
538 | m->addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); | |
539 | ||
540 | /* | |
541 | * Mask the reported address by the reported granularity. | |
542 | */ | |
1462594b | 543 | if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) { |
85f92694 TL |
544 | u8 shift = MCI_MISC_ADDR_LSB(m->misc); |
545 | m->addr >>= shift; | |
546 | m->addr <<= shift; | |
547 | } | |
548 | } | |
549 | } | |
550 | ||
fa92c586 CY |
551 | static bool memory_error(struct mce *m) |
552 | { | |
553 | struct cpuinfo_x86 *c = &boot_cpu_data; | |
554 | ||
555 | if (c->x86_vendor == X86_VENDOR_AMD) { | |
556 | /* | |
557 | * coming soon | |
558 | */ | |
559 | return false; | |
560 | } else if (c->x86_vendor == X86_VENDOR_INTEL) { | |
561 | /* | |
562 | * Intel SDM Volume 3B - 15.9.2 Compound Error Codes | |
563 | * | |
564 | * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for | |
565 | * indicating a memory error. Bit 8 is used for indicating a | |
566 | * cache hierarchy error. The combination of bit 2 and bit 3 | |
567 | * is used for indicating a `generic' cache hierarchy error | |
568 | * But we can't just blindly check the above bits, because if | |
569 | * bit 11 is set, then it is a bus/interconnect error - and | |
570 | * either way the above bits just gives more detail on what | |
571 | * bus/interconnect error happened. Note that bit 12 can be | |
572 | * ignored, as it's the "filter" bit. | |
573 | */ | |
574 | return (m->status & 0xef80) == BIT(7) || | |
575 | (m->status & 0xef00) == BIT(8) || | |
576 | (m->status & 0xeffc) == 0xc; | |
577 | } | |
578 | ||
579 | return false; | |
580 | } | |
581 | ||
ca84f696 AK |
582 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
583 | ||
d88203d1 | 584 | /* |
b79109c3 AK |
585 | * Poll for corrected events or events that happened before reset. |
586 | * Those are just logged through /dev/mcelog. | |
587 | * | |
588 | * This is executed in standard interrupt context. | |
ed7290d0 AK |
589 | * |
590 | * Note: spec recommends to panic for fatal unsignalled | |
591 | * errors here. However this would be quite problematic -- | |
592 | * we would need to reimplement the Monarch handling and | |
593 | * it would mess up the exclusion between exception handler | |
594 | * and poll hander -- * so we skip this for now. | |
595 | * These cases should not happen anyways, or only when the CPU | |
596 | * is already totally * confused. In this case it's likely it will | |
597 | * not fully execute the machine check handler either. | |
b79109c3 | 598 | */ |
3f2f0680 | 599 | bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 | 600 | { |
3f2f0680 | 601 | bool error_logged = false; |
b79109c3 | 602 | struct mce m; |
fa92c586 | 603 | int severity; |
b79109c3 AK |
604 | int i; |
605 | ||
c6ae41e7 | 606 | this_cpu_inc(mce_poll_count); |
ca84f696 | 607 | |
b8325c5b | 608 | mce_gather_info(&m, NULL); |
b79109c3 | 609 | |
d203f0b8 | 610 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 611 | if (!mce_banks[i].ctl || !test_bit(i, *b)) |
b79109c3 AK |
612 | continue; |
613 | ||
614 | m.misc = 0; | |
615 | m.addr = 0; | |
616 | m.bank = i; | |
617 | m.tsc = 0; | |
618 | ||
619 | barrier(); | |
a2d32bcb | 620 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
b79109c3 AK |
621 | if (!(m.status & MCI_STATUS_VAL)) |
622 | continue; | |
623 | ||
3f2f0680 | 624 | |
b79109c3 | 625 | /* |
ed7290d0 AK |
626 | * Uncorrected or signalled events are handled by the exception |
627 | * handler when it is enabled, so don't process those here. | |
b79109c3 AK |
628 | * |
629 | * TBD do the same check for MCI_STATUS_EN here? | |
630 | */ | |
ed7290d0 | 631 | if (!(flags & MCP_UC) && |
1462594b | 632 | (m.status & (mca_cfg.ser ? MCI_STATUS_S : MCI_STATUS_UC))) |
b79109c3 AK |
633 | continue; |
634 | ||
85f92694 | 635 | mce_read_aux(&m, i); |
b79109c3 AK |
636 | |
637 | if (!(flags & MCP_TIMESTAMP)) | |
638 | m.tsc = 0; | |
fa92c586 CY |
639 | |
640 | severity = mce_severity(&m, mca_cfg.tolerant, NULL, false); | |
641 | ||
642 | /* | |
643 | * In the cases where we don't have a valid address after all, | |
644 | * do not add it into the ring buffer. | |
645 | */ | |
646 | if (severity == MCE_DEFERRED_SEVERITY && memory_error(&m)) { | |
647 | if (m.status & MCI_STATUS_ADDRV) { | |
fd4cf79f CG |
648 | m.severity = severity; |
649 | m.usable_addr = mce_usable_address(&m); | |
650 | ||
651 | if (!mce_gen_pool_add(&m)) | |
652 | mce_schedule_work(); | |
fa92c586 CY |
653 | } |
654 | } | |
655 | ||
b79109c3 AK |
656 | /* |
657 | * Don't get the IP here because it's unlikely to | |
658 | * have anything to do with the actual error location. | |
659 | */ | |
3f2f0680 BP |
660 | if (!(flags & MCP_DONTLOG) && !mca_cfg.dont_log_ce) { |
661 | error_logged = true; | |
5679af4c | 662 | mce_log(&m); |
3f2f0680 | 663 | } |
b79109c3 AK |
664 | |
665 | /* | |
666 | * Clear state for this bank. | |
667 | */ | |
a2d32bcb | 668 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
b79109c3 AK |
669 | } |
670 | ||
671 | /* | |
672 | * Don't clear MCG_STATUS here because it's only defined for | |
673 | * exceptions. | |
674 | */ | |
88921be3 AK |
675 | |
676 | sync_core(); | |
3f2f0680 BP |
677 | |
678 | return error_logged; | |
b79109c3 | 679 | } |
ea149b36 | 680 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 | 681 | |
bd19a5e6 AK |
682 | /* |
683 | * Do a quick check if any of the events requires a panic. | |
684 | * This decides if we keep the events around or clear them. | |
685 | */ | |
61b0fccd TL |
686 | static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp, |
687 | struct pt_regs *regs) | |
bd19a5e6 | 688 | { |
95022b8c | 689 | int i, ret = 0; |
17fea54b | 690 | char *tmp; |
bd19a5e6 | 691 | |
d203f0b8 | 692 | for (i = 0; i < mca_cfg.banks; i++) { |
a2d32bcb | 693 | m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
61b0fccd | 694 | if (m->status & MCI_STATUS_VAL) { |
95022b8c | 695 | __set_bit(i, validp); |
61b0fccd TL |
696 | if (quirk_no_way_out) |
697 | quirk_no_way_out(i, m, regs); | |
698 | } | |
17fea54b BP |
699 | |
700 | if (mce_severity(m, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) { | |
701 | *msg = tmp; | |
95022b8c | 702 | ret = 1; |
17fea54b | 703 | } |
bd19a5e6 | 704 | } |
95022b8c | 705 | return ret; |
bd19a5e6 AK |
706 | } |
707 | ||
3c079792 AK |
708 | /* |
709 | * Variable to establish order between CPUs while scanning. | |
710 | * Each CPU spins initially until executing is equal its number. | |
711 | */ | |
712 | static atomic_t mce_executing; | |
713 | ||
714 | /* | |
715 | * Defines order of CPUs on entry. First CPU becomes Monarch. | |
716 | */ | |
717 | static atomic_t mce_callin; | |
718 | ||
719 | /* | |
720 | * Check if a timeout waiting for other CPUs happened. | |
721 | */ | |
6c80f87e | 722 | static int mce_timed_out(u64 *t, const char *msg) |
3c079792 AK |
723 | { |
724 | /* | |
725 | * The others already did panic for some reason. | |
726 | * Bail out like in a timeout. | |
727 | * rmb() to tell the compiler that system_state | |
728 | * might have been modified by someone else. | |
729 | */ | |
730 | rmb(); | |
c7c9b392 | 731 | if (atomic_read(&mce_panicked)) |
3c079792 | 732 | wait_for_panic(); |
84c2559d | 733 | if (!mca_cfg.monarch_timeout) |
3c079792 AK |
734 | goto out; |
735 | if ((s64)*t < SPINUNIT) { | |
716079f6 | 736 | if (mca_cfg.tolerant <= 1) |
6c80f87e | 737 | mce_panic(msg, NULL, NULL); |
3c079792 AK |
738 | cpu_missing = 1; |
739 | return 1; | |
740 | } | |
741 | *t -= SPINUNIT; | |
742 | out: | |
743 | touch_nmi_watchdog(); | |
744 | return 0; | |
745 | } | |
746 | ||
747 | /* | |
748 | * The Monarch's reign. The Monarch is the CPU who entered | |
749 | * the machine check handler first. It waits for the others to | |
750 | * raise the exception too and then grades them. When any | |
751 | * error is fatal panic. Only then let the others continue. | |
752 | * | |
753 | * The other CPUs entering the MCE handler will be controlled by the | |
754 | * Monarch. They are called Subjects. | |
755 | * | |
756 | * This way we prevent any potential data corruption in a unrecoverable case | |
757 | * and also makes sure always all CPU's errors are examined. | |
758 | * | |
680b6cfd | 759 | * Also this detects the case of a machine check event coming from outer |
3c079792 AK |
760 | * space (not detected by any CPUs) In this case some external agent wants |
761 | * us to shut down, so panic too. | |
762 | * | |
763 | * The other CPUs might still decide to panic if the handler happens | |
764 | * in a unrecoverable place, but in this case the system is in a semi-stable | |
765 | * state and won't corrupt anything by itself. It's ok to let the others | |
766 | * continue for a bit first. | |
767 | * | |
768 | * All the spin loops have timeouts; when a timeout happens a CPU | |
769 | * typically elects itself to be Monarch. | |
770 | */ | |
771 | static void mce_reign(void) | |
772 | { | |
773 | int cpu; | |
774 | struct mce *m = NULL; | |
775 | int global_worst = 0; | |
776 | char *msg = NULL; | |
777 | char *nmsg = NULL; | |
778 | ||
779 | /* | |
780 | * This CPU is the Monarch and the other CPUs have run | |
781 | * through their handlers. | |
782 | * Grade the severity of the errors of all the CPUs. | |
783 | */ | |
784 | for_each_possible_cpu(cpu) { | |
d203f0b8 BP |
785 | int severity = mce_severity(&per_cpu(mces_seen, cpu), |
786 | mca_cfg.tolerant, | |
e3480271 | 787 | &nmsg, true); |
3c079792 AK |
788 | if (severity > global_worst) { |
789 | msg = nmsg; | |
790 | global_worst = severity; | |
791 | m = &per_cpu(mces_seen, cpu); | |
792 | } | |
793 | } | |
794 | ||
795 | /* | |
796 | * Cannot recover? Panic here then. | |
797 | * This dumps all the mces in the log buffer and stops the | |
798 | * other CPUs. | |
799 | */ | |
d203f0b8 | 800 | if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) |
8af7043a | 801 | mce_panic("Fatal machine check", m, msg); |
3c079792 AK |
802 | |
803 | /* | |
804 | * For UC somewhere we let the CPU who detects it handle it. | |
805 | * Also must let continue the others, otherwise the handling | |
806 | * CPU could deadlock on a lock. | |
807 | */ | |
808 | ||
809 | /* | |
810 | * No machine check event found. Must be some external | |
811 | * source or one CPU is hung. Panic. | |
812 | */ | |
d203f0b8 | 813 | if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3) |
8af7043a | 814 | mce_panic("Fatal machine check from unknown source", NULL, NULL); |
3c079792 AK |
815 | |
816 | /* | |
817 | * Now clear all the mces_seen so that they don't reappear on | |
818 | * the next mce. | |
819 | */ | |
820 | for_each_possible_cpu(cpu) | |
821 | memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); | |
822 | } | |
823 | ||
824 | static atomic_t global_nwo; | |
825 | ||
826 | /* | |
827 | * Start of Monarch synchronization. This waits until all CPUs have | |
828 | * entered the exception handler and then determines if any of them | |
829 | * saw a fatal event that requires panic. Then it executes them | |
830 | * in the entry order. | |
831 | * TBD double check parallel CPU hotunplug | |
832 | */ | |
7fb06fc9 | 833 | static int mce_start(int *no_way_out) |
3c079792 | 834 | { |
7fb06fc9 | 835 | int order; |
3c079792 | 836 | int cpus = num_online_cpus(); |
84c2559d | 837 | u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; |
3c079792 | 838 | |
7fb06fc9 HS |
839 | if (!timeout) |
840 | return -1; | |
3c079792 | 841 | |
7fb06fc9 | 842 | atomic_add(*no_way_out, &global_nwo); |
184e1fdf HY |
843 | /* |
844 | * global_nwo should be updated before mce_callin | |
845 | */ | |
846 | smp_wmb(); | |
a95436e4 | 847 | order = atomic_inc_return(&mce_callin); |
3c079792 AK |
848 | |
849 | /* | |
850 | * Wait for everyone. | |
851 | */ | |
852 | while (atomic_read(&mce_callin) != cpus) { | |
6c80f87e AL |
853 | if (mce_timed_out(&timeout, |
854 | "Timeout: Not all CPUs entered broadcast exception handler")) { | |
3c079792 | 855 | atomic_set(&global_nwo, 0); |
7fb06fc9 | 856 | return -1; |
3c079792 AK |
857 | } |
858 | ndelay(SPINUNIT); | |
859 | } | |
860 | ||
184e1fdf HY |
861 | /* |
862 | * mce_callin should be read before global_nwo | |
863 | */ | |
864 | smp_rmb(); | |
3c079792 | 865 | |
7fb06fc9 HS |
866 | if (order == 1) { |
867 | /* | |
868 | * Monarch: Starts executing now, the others wait. | |
869 | */ | |
3c079792 | 870 | atomic_set(&mce_executing, 1); |
7fb06fc9 HS |
871 | } else { |
872 | /* | |
873 | * Subject: Now start the scanning loop one by one in | |
874 | * the original callin order. | |
875 | * This way when there are any shared banks it will be | |
876 | * only seen by one CPU before cleared, avoiding duplicates. | |
877 | */ | |
878 | while (atomic_read(&mce_executing) < order) { | |
6c80f87e AL |
879 | if (mce_timed_out(&timeout, |
880 | "Timeout: Subject CPUs unable to finish machine check processing")) { | |
7fb06fc9 HS |
881 | atomic_set(&global_nwo, 0); |
882 | return -1; | |
883 | } | |
884 | ndelay(SPINUNIT); | |
885 | } | |
3c079792 AK |
886 | } |
887 | ||
888 | /* | |
7fb06fc9 | 889 | * Cache the global no_way_out state. |
3c079792 | 890 | */ |
7fb06fc9 HS |
891 | *no_way_out = atomic_read(&global_nwo); |
892 | ||
893 | return order; | |
3c079792 AK |
894 | } |
895 | ||
896 | /* | |
897 | * Synchronize between CPUs after main scanning loop. | |
898 | * This invokes the bulk of the Monarch processing. | |
899 | */ | |
900 | static int mce_end(int order) | |
901 | { | |
902 | int ret = -1; | |
84c2559d | 903 | u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; |
3c079792 AK |
904 | |
905 | if (!timeout) | |
906 | goto reset; | |
907 | if (order < 0) | |
908 | goto reset; | |
909 | ||
910 | /* | |
911 | * Allow others to run. | |
912 | */ | |
913 | atomic_inc(&mce_executing); | |
914 | ||
915 | if (order == 1) { | |
916 | /* CHECKME: Can this race with a parallel hotplug? */ | |
917 | int cpus = num_online_cpus(); | |
918 | ||
919 | /* | |
920 | * Monarch: Wait for everyone to go through their scanning | |
921 | * loops. | |
922 | */ | |
923 | while (atomic_read(&mce_executing) <= cpus) { | |
6c80f87e AL |
924 | if (mce_timed_out(&timeout, |
925 | "Timeout: Monarch CPU unable to finish machine check processing")) | |
3c079792 AK |
926 | goto reset; |
927 | ndelay(SPINUNIT); | |
928 | } | |
929 | ||
930 | mce_reign(); | |
931 | barrier(); | |
932 | ret = 0; | |
933 | } else { | |
934 | /* | |
935 | * Subject: Wait for Monarch to finish. | |
936 | */ | |
937 | while (atomic_read(&mce_executing) != 0) { | |
6c80f87e AL |
938 | if (mce_timed_out(&timeout, |
939 | "Timeout: Monarch CPU did not finish machine check processing")) | |
3c079792 AK |
940 | goto reset; |
941 | ndelay(SPINUNIT); | |
942 | } | |
943 | ||
944 | /* | |
945 | * Don't reset anything. That's done by the Monarch. | |
946 | */ | |
947 | return 0; | |
948 | } | |
949 | ||
950 | /* | |
951 | * Reset all global state. | |
952 | */ | |
953 | reset: | |
954 | atomic_set(&global_nwo, 0); | |
955 | atomic_set(&mce_callin, 0); | |
956 | barrier(); | |
957 | ||
958 | /* | |
959 | * Let others run again. | |
960 | */ | |
961 | atomic_set(&mce_executing, 0); | |
962 | return ret; | |
963 | } | |
964 | ||
9b1beaf2 AK |
965 | /* |
966 | * Check if the address reported by the CPU is in a format we can parse. | |
967 | * It would be possible to add code for most other cases, but all would | |
968 | * be somewhat complicated (e.g. segment offset would require an instruction | |
0d2eb44f | 969 | * parser). So only support physical addresses up to page granuality for now. |
9b1beaf2 AK |
970 | */ |
971 | static int mce_usable_address(struct mce *m) | |
972 | { | |
973 | if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) | |
974 | return 0; | |
2b90e77e | 975 | if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) |
9b1beaf2 | 976 | return 0; |
2b90e77e | 977 | if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) |
9b1beaf2 AK |
978 | return 0; |
979 | return 1; | |
980 | } | |
981 | ||
3c079792 AK |
982 | static void mce_clear_state(unsigned long *toclear) |
983 | { | |
984 | int i; | |
985 | ||
d203f0b8 | 986 | for (i = 0; i < mca_cfg.banks; i++) { |
3c079792 | 987 | if (test_bit(i, toclear)) |
a2d32bcb | 988 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
3c079792 AK |
989 | } |
990 | } | |
991 | ||
b79109c3 AK |
992 | /* |
993 | * The actual machine check handler. This only handles real | |
994 | * exceptions when something got corrupted coming in through int 18. | |
995 | * | |
996 | * This is executed in NMI context not subject to normal locking rules. This | |
997 | * implies that most kernel services cannot be safely used. Don't even | |
998 | * think about putting a printk in there! | |
3c079792 AK |
999 | * |
1000 | * On Intel systems this is entered on all CPUs in parallel through | |
1001 | * MCE broadcast. However some CPUs might be broken beyond repair, | |
1002 | * so be always careful when synchronizing with others. | |
1da177e4 | 1003 | */ |
e9eee03e | 1004 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 | 1005 | { |
1462594b | 1006 | struct mca_config *cfg = &mca_cfg; |
3c079792 | 1007 | struct mce m, *final; |
95927475 | 1008 | enum ctx_state prev_state; |
1da177e4 | 1009 | int i; |
3c079792 AK |
1010 | int worst = 0; |
1011 | int severity; | |
1012 | /* | |
1013 | * Establish sequential order between the CPUs entering the machine | |
1014 | * check handler. | |
1015 | */ | |
7fb06fc9 | 1016 | int order; |
bd78432c TH |
1017 | /* |
1018 | * If no_way_out gets set, there is no safe way to recover from this | |
d203f0b8 | 1019 | * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway. |
bd78432c TH |
1020 | */ |
1021 | int no_way_out = 0; | |
1022 | /* | |
1023 | * If kill_it gets set, there might be a way to recover from this | |
1024 | * error. | |
1025 | */ | |
1026 | int kill_it = 0; | |
b79109c3 | 1027 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
95022b8c | 1028 | DECLARE_BITMAP(valid_banks, MAX_NR_BANKS); |
bd19a5e6 | 1029 | char *msg = "Unknown"; |
d4812e16 TL |
1030 | u64 recover_paddr = ~0ull; |
1031 | int flags = MF_ACTION_REQUIRED; | |
243d657e | 1032 | int lmce = 0; |
1da177e4 | 1033 | |
95927475 AL |
1034 | prev_state = ist_enter(regs); |
1035 | ||
c6ae41e7 | 1036 | this_cpu_inc(mce_exception_count); |
01ca79f1 | 1037 | |
1462594b | 1038 | if (!cfg->banks) |
32561696 | 1039 | goto out; |
1da177e4 | 1040 | |
b8325c5b | 1041 | mce_gather_info(&m, regs); |
b5f2fa4e | 1042 | |
89cbc767 | 1043 | final = this_cpu_ptr(&mces_seen); |
3c079792 AK |
1044 | *final = m; |
1045 | ||
95022b8c | 1046 | memset(valid_banks, 0, sizeof(valid_banks)); |
61b0fccd | 1047 | no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs); |
680b6cfd | 1048 | |
1da177e4 LT |
1049 | barrier(); |
1050 | ||
ed7290d0 | 1051 | /* |
a8c321fb TL |
1052 | * When no restart IP might need to kill or panic. |
1053 | * Assume the worst for now, but if we find the | |
1054 | * severity is MCE_AR_SEVERITY we have other options. | |
ed7290d0 AK |
1055 | */ |
1056 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
1057 | kill_it = 1; | |
1058 | ||
3c079792 | 1059 | /* |
243d657e | 1060 | * Check if this MCE is signaled to only this logical processor |
3c079792 | 1061 | */ |
243d657e AR |
1062 | if (m.mcgstatus & MCG_STATUS_LMCES) |
1063 | lmce = 1; | |
1064 | else { | |
1065 | /* | |
1066 | * Go through all the banks in exclusion of the other CPUs. | |
1067 | * This way we don't report duplicated events on shared banks | |
1068 | * because the first one to see it will clear it. | |
1069 | * If this is a Local MCE, then no need to perform rendezvous. | |
1070 | */ | |
1071 | order = mce_start(&no_way_out); | |
1072 | } | |
1073 | ||
1462594b | 1074 | for (i = 0; i < cfg->banks; i++) { |
b79109c3 | 1075 | __clear_bit(i, toclear); |
95022b8c TL |
1076 | if (!test_bit(i, valid_banks)) |
1077 | continue; | |
cebe1820 | 1078 | if (!mce_banks[i].ctl) |
1da177e4 | 1079 | continue; |
d88203d1 TG |
1080 | |
1081 | m.misc = 0; | |
1da177e4 LT |
1082 | m.addr = 0; |
1083 | m.bank = i; | |
1da177e4 | 1084 | |
a2d32bcb | 1085 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
1da177e4 LT |
1086 | if ((m.status & MCI_STATUS_VAL) == 0) |
1087 | continue; | |
1088 | ||
b79109c3 | 1089 | /* |
ed7290d0 AK |
1090 | * Non uncorrected or non signaled errors are handled by |
1091 | * machine_check_poll. Leave them alone, unless this panics. | |
b79109c3 | 1092 | */ |
1462594b | 1093 | if (!(m.status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) && |
ed7290d0 | 1094 | !no_way_out) |
b79109c3 AK |
1095 | continue; |
1096 | ||
1097 | /* | |
1098 | * Set taint even when machine check was not enabled. | |
1099 | */ | |
373d4d09 | 1100 | add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); |
b79109c3 | 1101 | |
e3480271 | 1102 | severity = mce_severity(&m, cfg->tolerant, NULL, true); |
b79109c3 | 1103 | |
ed7290d0 | 1104 | /* |
e3480271 CY |
1105 | * When machine check was for corrected/deferred handler don't |
1106 | * touch, unless we're panicing. | |
ed7290d0 | 1107 | */ |
e3480271 CY |
1108 | if ((severity == MCE_KEEP_SEVERITY || |
1109 | severity == MCE_UCNA_SEVERITY) && !no_way_out) | |
ed7290d0 AK |
1110 | continue; |
1111 | __set_bit(i, toclear); | |
1112 | if (severity == MCE_NO_SEVERITY) { | |
b79109c3 AK |
1113 | /* |
1114 | * Machine check event was not enabled. Clear, but | |
1115 | * ignore. | |
1116 | */ | |
1117 | continue; | |
1da177e4 LT |
1118 | } |
1119 | ||
85f92694 | 1120 | mce_read_aux(&m, i); |
1da177e4 | 1121 | |
fd4cf79f CG |
1122 | /* assuming valid severity level != 0 */ |
1123 | m.severity = severity; | |
1124 | m.usable_addr = mce_usable_address(&m); | |
1125 | mce_gen_pool_add(&m); | |
9b1beaf2 | 1126 | |
b79109c3 | 1127 | mce_log(&m); |
1da177e4 | 1128 | |
3c079792 AK |
1129 | if (severity > worst) { |
1130 | *final = m; | |
1131 | worst = severity; | |
1da177e4 | 1132 | } |
1da177e4 LT |
1133 | } |
1134 | ||
a8c321fb TL |
1135 | /* mce_clear_state will clear *final, save locally for use later */ |
1136 | m = *final; | |
1137 | ||
3c079792 AK |
1138 | if (!no_way_out) |
1139 | mce_clear_state(toclear); | |
1140 | ||
e9eee03e | 1141 | /* |
3c079792 AK |
1142 | * Do most of the synchronization with other CPUs. |
1143 | * When there's any problem use only local no_way_out state. | |
e9eee03e | 1144 | */ |
243d657e AR |
1145 | if (!lmce) { |
1146 | if (mce_end(order) < 0) | |
1147 | no_way_out = worst >= MCE_PANIC_SEVERITY; | |
1148 | } else { | |
1149 | /* | |
1150 | * Local MCE skipped calling mce_reign() | |
1151 | * If we found a fatal error, we need to panic here. | |
1152 | */ | |
1153 | if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) | |
1154 | mce_panic("Machine check from unknown source", | |
1155 | NULL, NULL); | |
1156 | } | |
bd78432c TH |
1157 | |
1158 | /* | |
a8c321fb TL |
1159 | * At insane "tolerant" levels we take no action. Otherwise |
1160 | * we only die if we have no other choice. For less serious | |
1161 | * issues we try to recover, or limit damage to the current | |
1162 | * process. | |
bd78432c | 1163 | */ |
1462594b | 1164 | if (cfg->tolerant < 3) { |
a8c321fb TL |
1165 | if (no_way_out) |
1166 | mce_panic("Fatal machine check on current CPU", &m, msg); | |
1167 | if (worst == MCE_AR_SEVERITY) { | |
d4812e16 TL |
1168 | recover_paddr = m.addr; |
1169 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
1170 | flags |= MF_MUST_KILL; | |
a8c321fb TL |
1171 | } else if (kill_it) { |
1172 | force_sig(SIGBUS, current); | |
1173 | } | |
1174 | } | |
e02e68d3 | 1175 | |
3c079792 AK |
1176 | if (worst > 0) |
1177 | mce_report_event(regs); | |
5f8c1a54 | 1178 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 1179 | out: |
88921be3 | 1180 | sync_core(); |
d4812e16 TL |
1181 | |
1182 | if (recover_paddr == ~0ull) | |
1183 | goto done; | |
1184 | ||
1185 | pr_err("Uncorrected hardware memory error in user-access at %llx", | |
1186 | recover_paddr); | |
1187 | /* | |
1188 | * We must call memory_failure() here even if the current process is | |
1189 | * doomed. We still need to mark the page as poisoned and alert any | |
1190 | * other users of the page. | |
1191 | */ | |
1192 | ist_begin_non_atomic(regs); | |
1193 | local_irq_enable(); | |
1194 | if (memory_failure(recover_paddr >> PAGE_SHIFT, MCE_VECTOR, flags) < 0) { | |
1195 | pr_err("Memory error not recovered"); | |
1196 | force_sig(SIGBUS, current); | |
1197 | } | |
1198 | local_irq_disable(); | |
1199 | ist_end_non_atomic(); | |
1200 | done: | |
95927475 | 1201 | ist_exit(regs, prev_state); |
1da177e4 | 1202 | } |
ea149b36 | 1203 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 1204 | |
cd42f4a3 TL |
1205 | #ifndef CONFIG_MEMORY_FAILURE |
1206 | int memory_failure(unsigned long pfn, int vector, int flags) | |
9b1beaf2 | 1207 | { |
a8c321fb TL |
1208 | /* mce_severity() should not hand us an ACTION_REQUIRED error */ |
1209 | BUG_ON(flags & MF_ACTION_REQUIRED); | |
c767a54b JP |
1210 | pr_err("Uncorrected memory error in page 0x%lx ignored\n" |
1211 | "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", | |
1212 | pfn); | |
cd42f4a3 TL |
1213 | |
1214 | return 0; | |
9b1beaf2 | 1215 | } |
cd42f4a3 | 1216 | #endif |
9b1beaf2 | 1217 | |
a8c321fb TL |
1218 | /* |
1219 | * Action optional processing happens here (picking up | |
1220 | * from the list of faulting pages that do_machine_check() | |
fd4cf79f | 1221 | * placed into the genpool). |
a8c321fb | 1222 | */ |
9b1beaf2 AK |
1223 | static void mce_process_work(struct work_struct *dummy) |
1224 | { | |
fd4cf79f | 1225 | mce_gen_pool_process(); |
9b1beaf2 AK |
1226 | } |
1227 | ||
15d5f839 DZ |
1228 | #ifdef CONFIG_X86_MCE_INTEL |
1229 | /*** | |
1230 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 1231 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
1232 | * @status: Event status information |
1233 | * | |
1234 | * This function should be called by the thermal interrupt after the | |
1235 | * event has been processed and the decision was made to log the event | |
1236 | * further. | |
1237 | * | |
1238 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
1239 | * and historically has been the register value of the | |
1240 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
1241 | */ | |
b5f2fa4e | 1242 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
1243 | { |
1244 | struct mce m; | |
1245 | ||
b5f2fa4e | 1246 | mce_setup(&m); |
15d5f839 DZ |
1247 | m.bank = MCE_THERMAL_BANK; |
1248 | m.status = status; | |
15d5f839 DZ |
1249 | mce_log(&m); |
1250 | } | |
1251 | #endif /* CONFIG_X86_MCE_INTEL */ | |
1252 | ||
1da177e4 | 1253 | /* |
8a336b0a TH |
1254 | * Periodic polling timer for "silent" machine check errors. If the |
1255 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
1256 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 1257 | */ |
3f2f0680 | 1258 | static unsigned long check_interval = INITIAL_CHECK_INTERVAL; |
e9eee03e | 1259 | |
82f7af09 | 1260 | static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */ |
52d168e2 | 1261 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 1262 | |
55babd8f CG |
1263 | static unsigned long mce_adjust_timer_default(unsigned long interval) |
1264 | { | |
1265 | return interval; | |
1266 | } | |
1267 | ||
3f2f0680 | 1268 | static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default; |
55babd8f | 1269 | |
3f2f0680 | 1270 | static void __restart_timer(struct timer_list *t, unsigned long interval) |
27f6c573 | 1271 | { |
3f2f0680 BP |
1272 | unsigned long when = jiffies + interval; |
1273 | unsigned long flags; | |
27f6c573 | 1274 | |
3f2f0680 | 1275 | local_irq_save(flags); |
27f6c573 | 1276 | |
3f2f0680 BP |
1277 | if (timer_pending(t)) { |
1278 | if (time_before(when, t->expires)) | |
1279 | mod_timer_pinned(t, when); | |
1280 | } else { | |
1281 | t->expires = round_jiffies(when); | |
1282 | add_timer_on(t, smp_processor_id()); | |
1283 | } | |
1284 | ||
1285 | local_irq_restore(flags); | |
27f6c573 CG |
1286 | } |
1287 | ||
82f7af09 | 1288 | static void mce_timer_fn(unsigned long data) |
1da177e4 | 1289 | { |
89cbc767 | 1290 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
3f2f0680 | 1291 | int cpu = smp_processor_id(); |
82f7af09 | 1292 | unsigned long iv; |
52d168e2 | 1293 | |
3f2f0680 BP |
1294 | WARN_ON(cpu != data); |
1295 | ||
1296 | iv = __this_cpu_read(mce_next_interval); | |
52d168e2 | 1297 | |
89cbc767 | 1298 | if (mce_available(this_cpu_ptr(&cpu_info))) { |
3f2f0680 BP |
1299 | machine_check_poll(MCP_TIMESTAMP, this_cpu_ptr(&mce_poll_banks)); |
1300 | ||
1301 | if (mce_intel_cmci_poll()) { | |
1302 | iv = mce_adjust_timer(iv); | |
1303 | goto done; | |
1304 | } | |
e9eee03e | 1305 | } |
1da177e4 LT |
1306 | |
1307 | /* | |
3f2f0680 BP |
1308 | * Alert userspace if needed. If we logged an MCE, reduce the polling |
1309 | * interval, otherwise increase the polling interval. | |
1da177e4 | 1310 | */ |
3f2f0680 | 1311 | if (mce_notify_irq()) |
958fb3c5 | 1312 | iv = max(iv / 2, (unsigned long) HZ/100); |
3f2f0680 | 1313 | else |
82f7af09 | 1314 | iv = min(iv * 2, round_jiffies_relative(check_interval * HZ)); |
3f2f0680 BP |
1315 | |
1316 | done: | |
82f7af09 | 1317 | __this_cpu_write(mce_next_interval, iv); |
3f2f0680 | 1318 | __restart_timer(t, iv); |
55babd8f | 1319 | } |
e02e68d3 | 1320 | |
55babd8f CG |
1321 | /* |
1322 | * Ensure that the timer is firing in @interval from now. | |
1323 | */ | |
1324 | void mce_timer_kick(unsigned long interval) | |
1325 | { | |
89cbc767 | 1326 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
55babd8f CG |
1327 | unsigned long iv = __this_cpu_read(mce_next_interval); |
1328 | ||
3f2f0680 BP |
1329 | __restart_timer(t, interval); |
1330 | ||
55babd8f CG |
1331 | if (interval < iv) |
1332 | __this_cpu_write(mce_next_interval, interval); | |
e02e68d3 TH |
1333 | } |
1334 | ||
9aaef96f HS |
1335 | /* Must not be called in IRQ context where del_timer_sync() can deadlock */ |
1336 | static void mce_timer_delete_all(void) | |
1337 | { | |
1338 | int cpu; | |
1339 | ||
1340 | for_each_online_cpu(cpu) | |
1341 | del_timer_sync(&per_cpu(mce_timer, cpu)); | |
1342 | } | |
1343 | ||
9bd98405 AK |
1344 | static void mce_do_trigger(struct work_struct *work) |
1345 | { | |
1020bcbc | 1346 | call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT); |
9bd98405 AK |
1347 | } |
1348 | ||
1349 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
1350 | ||
e02e68d3 | 1351 | /* |
9bd98405 AK |
1352 | * Notify the user(s) about new machine check events. |
1353 | * Can be called from interrupt context, but not from machine check/NMI | |
1354 | * context. | |
e02e68d3 | 1355 | */ |
9ff36ee9 | 1356 | int mce_notify_irq(void) |
e02e68d3 | 1357 | { |
8457c84d AK |
1358 | /* Not more than two messages every minute */ |
1359 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
1360 | ||
1020bcbc | 1361 | if (test_and_clear_bit(0, &mce_need_notify)) { |
93b62c3c HS |
1362 | /* wake processes polling /dev/mcelog */ |
1363 | wake_up_interruptible(&mce_chrdev_wait); | |
9bd98405 | 1364 | |
4d899be5 | 1365 | if (mce_helper[0]) |
9bd98405 | 1366 | schedule_work(&mce_trigger_work); |
e02e68d3 | 1367 | |
8457c84d | 1368 | if (__ratelimit(&ratelimit)) |
a2d7b0d4 | 1369 | pr_info(HW_ERR "Machine check events logged\n"); |
e02e68d3 TH |
1370 | |
1371 | return 1; | |
1da177e4 | 1372 | } |
e02e68d3 TH |
1373 | return 0; |
1374 | } | |
9ff36ee9 | 1375 | EXPORT_SYMBOL_GPL(mce_notify_irq); |
8a336b0a | 1376 | |
148f9bb8 | 1377 | static int __mcheck_cpu_mce_banks_init(void) |
cebe1820 AK |
1378 | { |
1379 | int i; | |
d203f0b8 | 1380 | u8 num_banks = mca_cfg.banks; |
cebe1820 | 1381 | |
d203f0b8 | 1382 | mce_banks = kzalloc(num_banks * sizeof(struct mce_bank), GFP_KERNEL); |
cebe1820 AK |
1383 | if (!mce_banks) |
1384 | return -ENOMEM; | |
d203f0b8 BP |
1385 | |
1386 | for (i = 0; i < num_banks; i++) { | |
cebe1820 | 1387 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1388 | |
cebe1820 AK |
1389 | b->ctl = -1ULL; |
1390 | b->init = 1; | |
1391 | } | |
1392 | return 0; | |
1393 | } | |
1394 | ||
d88203d1 | 1395 | /* |
1da177e4 LT |
1396 | * Initialize Machine Checks for a CPU. |
1397 | */ | |
148f9bb8 | 1398 | static int __mcheck_cpu_cap_init(void) |
1da177e4 | 1399 | { |
0d7482e3 | 1400 | unsigned b; |
e9eee03e | 1401 | u64 cap; |
1da177e4 LT |
1402 | |
1403 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
1404 | |
1405 | b = cap & MCG_BANKCNT_MASK; | |
d203f0b8 | 1406 | if (!mca_cfg.banks) |
c767a54b | 1407 | pr_info("CPU supports %d MCE banks\n", b); |
b659294b | 1408 | |
0d7482e3 | 1409 | if (b > MAX_NR_BANKS) { |
c767a54b | 1410 | pr_warn("Using only %u machine check banks out of %u\n", |
0d7482e3 AK |
1411 | MAX_NR_BANKS, b); |
1412 | b = MAX_NR_BANKS; | |
1413 | } | |
1414 | ||
1415 | /* Don't support asymmetric configurations today */ | |
d203f0b8 BP |
1416 | WARN_ON(mca_cfg.banks != 0 && b != mca_cfg.banks); |
1417 | mca_cfg.banks = b; | |
1418 | ||
cebe1820 | 1419 | if (!mce_banks) { |
cffd377e | 1420 | int err = __mcheck_cpu_mce_banks_init(); |
11868a2d | 1421 | |
cebe1820 AK |
1422 | if (err) |
1423 | return err; | |
1da177e4 | 1424 | } |
0d7482e3 | 1425 | |
94ad8474 | 1426 | /* Use accurate RIP reporting if available. */ |
01c6680a | 1427 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
84c2559d | 1428 | mca_cfg.rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 1429 | |
ed7290d0 | 1430 | if (cap & MCG_SER_P) |
1462594b | 1431 | mca_cfg.ser = true; |
ed7290d0 | 1432 | |
0d7482e3 AK |
1433 | return 0; |
1434 | } | |
1435 | ||
5e09954a | 1436 | static void __mcheck_cpu_init_generic(void) |
0d7482e3 | 1437 | { |
84c2559d | 1438 | enum mcp_flags m_fl = 0; |
e9eee03e | 1439 | mce_banks_t all_banks; |
0d7482e3 AK |
1440 | u64 cap; |
1441 | int i; | |
1442 | ||
84c2559d BP |
1443 | if (!mca_cfg.bootlog) |
1444 | m_fl = MCP_DONTLOG; | |
1445 | ||
b79109c3 AK |
1446 | /* |
1447 | * Log the machine checks left over from the previous reset. | |
1448 | */ | |
ee031c31 | 1449 | bitmap_fill(all_banks, MAX_NR_BANKS); |
84c2559d | 1450 | machine_check_poll(MCP_UC | m_fl, &all_banks); |
1da177e4 | 1451 | |
375074cc | 1452 | cr4_set_bits(X86_CR4_MCE); |
1da177e4 | 1453 | |
0d7482e3 | 1454 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
1455 | if (cap & MCG_CTL_P) |
1456 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
1457 | ||
d203f0b8 | 1458 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 1459 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1460 | |
cebe1820 | 1461 | if (!b->init) |
06b7a7a5 | 1462 | continue; |
a2d32bcb AK |
1463 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
1464 | wrmsrl(MSR_IA32_MCx_STATUS(i), 0); | |
d88203d1 | 1465 | } |
1da177e4 LT |
1466 | } |
1467 | ||
61b0fccd TL |
1468 | /* |
1469 | * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and | |
1470 | * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM | |
1471 | * Vol 3B Table 15-20). But this confuses both the code that determines | |
1472 | * whether the machine check occurred in kernel or user mode, and also | |
1473 | * the severity assessment code. Pretend that EIPV was set, and take the | |
1474 | * ip/cs values from the pt_regs that mce_gather_info() ignored earlier. | |
1475 | */ | |
1476 | static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs) | |
1477 | { | |
1478 | if (bank != 0) | |
1479 | return; | |
1480 | if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0) | |
1481 | return; | |
1482 | if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC| | |
1483 | MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV| | |
1484 | MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR| | |
1485 | MCACOD)) != | |
1486 | (MCI_STATUS_UC|MCI_STATUS_EN| | |
1487 | MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S| | |
1488 | MCI_STATUS_AR|MCACOD_INSTR)) | |
1489 | return; | |
1490 | ||
1491 | m->mcgstatus |= MCG_STATUS_EIPV; | |
1492 | m->ip = regs->ip; | |
1493 | m->cs = regs->cs; | |
1494 | } | |
1495 | ||
1da177e4 | 1496 | /* Add per CPU specific workarounds here */ |
148f9bb8 | 1497 | static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 1498 | { |
d203f0b8 BP |
1499 | struct mca_config *cfg = &mca_cfg; |
1500 | ||
e412cd25 | 1501 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { |
c767a54b | 1502 | pr_info("unknown CPU type - not enabling MCE support\n"); |
e412cd25 IM |
1503 | return -EOPNOTSUPP; |
1504 | } | |
1505 | ||
1da177e4 | 1506 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 1507 | if (c->x86_vendor == X86_VENDOR_AMD) { |
d203f0b8 | 1508 | if (c->x86 == 15 && cfg->banks > 4) { |
e9eee03e IM |
1509 | /* |
1510 | * disable GART TBL walk error reporting, which | |
1511 | * trips off incorrectly with the IOMMU & 3ware | |
1512 | * & Cerberus: | |
1513 | */ | |
cebe1820 | 1514 | clear_bit(10, (unsigned long *)&mce_banks[4].ctl); |
e9eee03e | 1515 | } |
84c2559d | 1516 | if (c->x86 <= 17 && cfg->bootlog < 0) { |
e9eee03e IM |
1517 | /* |
1518 | * Lots of broken BIOS around that don't clear them | |
1519 | * by default and leave crap in there. Don't log: | |
1520 | */ | |
84c2559d | 1521 | cfg->bootlog = 0; |
e9eee03e | 1522 | } |
2e6f694f AK |
1523 | /* |
1524 | * Various K7s with broken bank 0 around. Always disable | |
1525 | * by default. | |
1526 | */ | |
c9ce8712 | 1527 | if (c->x86 == 6 && cfg->banks > 0) |
cebe1820 | 1528 | mce_banks[0].ctl = 0; |
575203b4 | 1529 | |
bf80bbd7 AG |
1530 | /* |
1531 | * overflow_recov is supported for F15h Models 00h-0fh | |
1532 | * even though we don't have a CPUID bit for it. | |
1533 | */ | |
1534 | if (c->x86 == 0x15 && c->x86_model <= 0xf) | |
1535 | mce_flags.overflow_recov = 1; | |
1536 | ||
c9ce8712 BP |
1537 | /* |
1538 | * Turn off MC4_MISC thresholding banks on those models since | |
1539 | * they're not supported there. | |
1540 | */ | |
1541 | if (c->x86 == 0x15 && | |
1542 | (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) { | |
1543 | int i; | |
1544 | u64 hwcr; | |
1545 | bool need_toggle; | |
1546 | u32 msrs[] = { | |
575203b4 BP |
1547 | 0x00000413, /* MC4_MISC0 */ |
1548 | 0xc0000408, /* MC4_MISC1 */ | |
c9ce8712 | 1549 | }; |
575203b4 | 1550 | |
c9ce8712 | 1551 | rdmsrl(MSR_K7_HWCR, hwcr); |
575203b4 | 1552 | |
c9ce8712 BP |
1553 | /* McStatusWrEn has to be set */ |
1554 | need_toggle = !(hwcr & BIT(18)); | |
575203b4 | 1555 | |
c9ce8712 BP |
1556 | if (need_toggle) |
1557 | wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); | |
575203b4 | 1558 | |
c9ce8712 BP |
1559 | /* Clear CntP bit safely */ |
1560 | for (i = 0; i < ARRAY_SIZE(msrs); i++) | |
1561 | msr_clear_bit(msrs[i], 62); | |
575203b4 | 1562 | |
c9ce8712 BP |
1563 | /* restore old settings */ |
1564 | if (need_toggle) | |
1565 | wrmsrl(MSR_K7_HWCR, hwcr); | |
1566 | } | |
1da177e4 | 1567 | } |
e583538f | 1568 | |
06b7a7a5 AK |
1569 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
1570 | /* | |
1571 | * SDM documents that on family 6 bank 0 should not be written | |
1572 | * because it aliases to another special BIOS controlled | |
1573 | * register. | |
1574 | * But it's not aliased anymore on model 0x1a+ | |
1575 | * Don't ignore bank 0 completely because there could be a | |
1576 | * valid event later, merely don't write CTL0. | |
1577 | */ | |
1578 | ||
d203f0b8 | 1579 | if (c->x86 == 6 && c->x86_model < 0x1A && cfg->banks > 0) |
cebe1820 | 1580 | mce_banks[0].init = 0; |
3c079792 AK |
1581 | |
1582 | /* | |
1583 | * All newer Intel systems support MCE broadcasting. Enable | |
1584 | * synchronization with a one second timeout. | |
1585 | */ | |
1586 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && | |
84c2559d BP |
1587 | cfg->monarch_timeout < 0) |
1588 | cfg->monarch_timeout = USEC_PER_SEC; | |
c7f6fa44 | 1589 | |
e412cd25 IM |
1590 | /* |
1591 | * There are also broken BIOSes on some Pentium M and | |
1592 | * earlier systems: | |
1593 | */ | |
84c2559d BP |
1594 | if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0) |
1595 | cfg->bootlog = 0; | |
61b0fccd TL |
1596 | |
1597 | if (c->x86 == 6 && c->x86_model == 45) | |
1598 | quirk_no_way_out = quirk_sandybridge_ifu; | |
06b7a7a5 | 1599 | } |
84c2559d BP |
1600 | if (cfg->monarch_timeout < 0) |
1601 | cfg->monarch_timeout = 0; | |
1602 | if (cfg->bootlog != 0) | |
7af19e4a | 1603 | cfg->panic_timeout = 30; |
e412cd25 IM |
1604 | |
1605 | return 0; | |
d88203d1 | 1606 | } |
1da177e4 | 1607 | |
148f9bb8 | 1608 | static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) |
4efc0670 AK |
1609 | { |
1610 | if (c->x86 != 5) | |
3a97fc34 HS |
1611 | return 0; |
1612 | ||
4efc0670 AK |
1613 | switch (c->x86_vendor) { |
1614 | case X86_VENDOR_INTEL: | |
c6978369 | 1615 | intel_p5_mcheck_init(c); |
3a97fc34 | 1616 | return 1; |
4efc0670 AK |
1617 | break; |
1618 | case X86_VENDOR_CENTAUR: | |
1619 | winchip_mcheck_init(c); | |
3a97fc34 | 1620 | return 1; |
4efc0670 AK |
1621 | break; |
1622 | } | |
3a97fc34 HS |
1623 | |
1624 | return 0; | |
4efc0670 AK |
1625 | } |
1626 | ||
5e09954a | 1627 | static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
1628 | { |
1629 | switch (c->x86_vendor) { | |
1630 | case X86_VENDOR_INTEL: | |
1631 | mce_intel_feature_init(c); | |
3f2f0680 | 1632 | mce_adjust_timer = cmci_intel_adjust_timer; |
1da177e4 | 1633 | break; |
7559e13f AG |
1634 | |
1635 | case X86_VENDOR_AMD: { | |
1636 | u32 ebx = cpuid_ebx(0x80000007); | |
1637 | ||
89b831ef | 1638 | mce_amd_feature_init(c); |
7559e13f AG |
1639 | mce_flags.overflow_recov = !!(ebx & BIT(0)); |
1640 | mce_flags.succor = !!(ebx & BIT(1)); | |
89b831ef | 1641 | break; |
7559e13f AG |
1642 | } |
1643 | ||
1da177e4 LT |
1644 | default: |
1645 | break; | |
1646 | } | |
1647 | } | |
1648 | ||
26c3c283 | 1649 | static void mce_start_timer(unsigned int cpu, struct timer_list *t) |
52d168e2 | 1650 | { |
4f75d841 | 1651 | unsigned long iv = check_interval * HZ; |
bc09effa | 1652 | |
7af19e4a | 1653 | if (mca_cfg.ignore_ce || !iv) |
62fdac59 HS |
1654 | return; |
1655 | ||
4f75d841 BP |
1656 | per_cpu(mce_next_interval, cpu) = iv; |
1657 | ||
82f7af09 | 1658 | t->expires = round_jiffies(jiffies + iv); |
4f75d841 | 1659 | add_timer_on(t, cpu); |
52d168e2 AK |
1660 | } |
1661 | ||
26c3c283 TG |
1662 | static void __mcheck_cpu_init_timer(void) |
1663 | { | |
89cbc767 | 1664 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
26c3c283 TG |
1665 | unsigned int cpu = smp_processor_id(); |
1666 | ||
1667 | setup_timer(t, mce_timer_fn, cpu); | |
1668 | mce_start_timer(cpu, t); | |
1669 | } | |
1670 | ||
9eda8cb3 AK |
1671 | /* Handle unconfigured int18 (should never happen) */ |
1672 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
1673 | { | |
c767a54b | 1674 | pr_err("CPU#%d: Unexpected int18 (Machine Check)\n", |
9eda8cb3 AK |
1675 | smp_processor_id()); |
1676 | } | |
1677 | ||
1678 | /* Call the installed machine check handler for this CPU setup. */ | |
1679 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
1680 | unexpected_machine_check; | |
1681 | ||
d88203d1 | 1682 | /* |
1da177e4 | 1683 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 1684 | * Must be called with preempt off: |
1da177e4 | 1685 | */ |
148f9bb8 | 1686 | void mcheck_cpu_init(struct cpuinfo_x86 *c) |
1da177e4 | 1687 | { |
1462594b | 1688 | if (mca_cfg.disabled) |
4efc0670 AK |
1689 | return; |
1690 | ||
3a97fc34 HS |
1691 | if (__mcheck_cpu_ancient_init(c)) |
1692 | return; | |
4efc0670 | 1693 | |
5b4408fd | 1694 | if (!mce_available(c)) |
1da177e4 LT |
1695 | return; |
1696 | ||
5e09954a | 1697 | if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) { |
1462594b | 1698 | mca_cfg.disabled = true; |
0d7482e3 AK |
1699 | return; |
1700 | } | |
0d7482e3 | 1701 | |
648ed940 CG |
1702 | if (mce_gen_pool_init()) { |
1703 | mca_cfg.disabled = true; | |
1704 | pr_emerg("Couldn't allocate MCE records pool!\n"); | |
1705 | return; | |
1706 | } | |
1707 | ||
5d727926 AK |
1708 | machine_check_vector = do_machine_check; |
1709 | ||
5e09954a BP |
1710 | __mcheck_cpu_init_generic(); |
1711 | __mcheck_cpu_init_vendor(c); | |
1712 | __mcheck_cpu_init_timer(); | |
1da177e4 LT |
1713 | } |
1714 | ||
1715 | /* | |
93b62c3c | 1716 | * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log. |
1da177e4 LT |
1717 | */ |
1718 | ||
93b62c3c HS |
1719 | static DEFINE_SPINLOCK(mce_chrdev_state_lock); |
1720 | static int mce_chrdev_open_count; /* #times opened */ | |
1721 | static int mce_chrdev_open_exclu; /* already open exclusive? */ | |
f528e7ba | 1722 | |
93b62c3c | 1723 | static int mce_chrdev_open(struct inode *inode, struct file *file) |
f528e7ba | 1724 | { |
93b62c3c | 1725 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1726 | |
93b62c3c HS |
1727 | if (mce_chrdev_open_exclu || |
1728 | (mce_chrdev_open_count && (file->f_flags & O_EXCL))) { | |
1729 | spin_unlock(&mce_chrdev_state_lock); | |
e9eee03e | 1730 | |
f528e7ba TH |
1731 | return -EBUSY; |
1732 | } | |
1733 | ||
1734 | if (file->f_flags & O_EXCL) | |
93b62c3c HS |
1735 | mce_chrdev_open_exclu = 1; |
1736 | mce_chrdev_open_count++; | |
f528e7ba | 1737 | |
93b62c3c | 1738 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba | 1739 | |
bd78432c | 1740 | return nonseekable_open(inode, file); |
f528e7ba TH |
1741 | } |
1742 | ||
93b62c3c | 1743 | static int mce_chrdev_release(struct inode *inode, struct file *file) |
f528e7ba | 1744 | { |
93b62c3c | 1745 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1746 | |
93b62c3c HS |
1747 | mce_chrdev_open_count--; |
1748 | mce_chrdev_open_exclu = 0; | |
f528e7ba | 1749 | |
93b62c3c | 1750 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba TH |
1751 | |
1752 | return 0; | |
1753 | } | |
1754 | ||
d88203d1 TG |
1755 | static void collect_tscs(void *data) |
1756 | { | |
1da177e4 | 1757 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 1758 | |
1da177e4 | 1759 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 1760 | } |
1da177e4 | 1761 | |
482908b4 HY |
1762 | static int mce_apei_read_done; |
1763 | ||
1764 | /* Collect MCE record of previous boot in persistent storage via APEI ERST. */ | |
1765 | static int __mce_read_apei(char __user **ubuf, size_t usize) | |
1766 | { | |
1767 | int rc; | |
1768 | u64 record_id; | |
1769 | struct mce m; | |
1770 | ||
1771 | if (usize < sizeof(struct mce)) | |
1772 | return -EINVAL; | |
1773 | ||
1774 | rc = apei_read_mce(&m, &record_id); | |
1775 | /* Error or no more MCE record */ | |
1776 | if (rc <= 0) { | |
1777 | mce_apei_read_done = 1; | |
fadd85f1 NH |
1778 | /* |
1779 | * When ERST is disabled, mce_chrdev_read() should return | |
1780 | * "no record" instead of "no device." | |
1781 | */ | |
1782 | if (rc == -ENODEV) | |
1783 | return 0; | |
482908b4 HY |
1784 | return rc; |
1785 | } | |
1786 | rc = -EFAULT; | |
1787 | if (copy_to_user(*ubuf, &m, sizeof(struct mce))) | |
1788 | return rc; | |
1789 | /* | |
1790 | * In fact, we should have cleared the record after that has | |
1791 | * been flushed to the disk or sent to network in | |
1792 | * /sbin/mcelog, but we have no interface to support that now, | |
1793 | * so just clear it to avoid duplication. | |
1794 | */ | |
1795 | rc = apei_clear_mce(record_id); | |
1796 | if (rc) { | |
1797 | mce_apei_read_done = 1; | |
1798 | return rc; | |
1799 | } | |
1800 | *ubuf += sizeof(struct mce); | |
1801 | ||
1802 | return 0; | |
1803 | } | |
1804 | ||
93b62c3c HS |
1805 | static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf, |
1806 | size_t usize, loff_t *off) | |
1da177e4 | 1807 | { |
e9eee03e | 1808 | char __user *buf = ubuf; |
f0de53bb | 1809 | unsigned long *cpu_tsc; |
ef41df43 | 1810 | unsigned prev, next; |
1da177e4 LT |
1811 | int i, err; |
1812 | ||
6bca67f9 | 1813 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
1814 | if (!cpu_tsc) |
1815 | return -ENOMEM; | |
1816 | ||
93b62c3c | 1817 | mutex_lock(&mce_chrdev_read_mutex); |
482908b4 HY |
1818 | |
1819 | if (!mce_apei_read_done) { | |
1820 | err = __mce_read_apei(&buf, usize); | |
1821 | if (err || buf != ubuf) | |
1822 | goto out; | |
1823 | } | |
1824 | ||
f56e8a07 | 1825 | next = rcu_dereference_check_mce(mcelog.next); |
1da177e4 LT |
1826 | |
1827 | /* Only supports full reads right now */ | |
482908b4 HY |
1828 | err = -EINVAL; |
1829 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) | |
1830 | goto out; | |
1da177e4 LT |
1831 | |
1832 | err = 0; | |
ef41df43 HY |
1833 | prev = 0; |
1834 | do { | |
1835 | for (i = prev; i < next; i++) { | |
1836 | unsigned long start = jiffies; | |
559faa6b | 1837 | struct mce *m = &mcelog.entry[i]; |
ef41df43 | 1838 | |
559faa6b | 1839 | while (!m->finished) { |
ef41df43 | 1840 | if (time_after_eq(jiffies, start + 2)) { |
559faa6b | 1841 | memset(m, 0, sizeof(*m)); |
ef41df43 HY |
1842 | goto timeout; |
1843 | } | |
1844 | cpu_relax(); | |
673242c1 | 1845 | } |
ef41df43 | 1846 | smp_rmb(); |
559faa6b HS |
1847 | err |= copy_to_user(buf, m, sizeof(*m)); |
1848 | buf += sizeof(*m); | |
ef41df43 HY |
1849 | timeout: |
1850 | ; | |
673242c1 | 1851 | } |
1da177e4 | 1852 | |
ef41df43 HY |
1853 | memset(mcelog.entry + prev, 0, |
1854 | (next - prev) * sizeof(struct mce)); | |
1855 | prev = next; | |
1856 | next = cmpxchg(&mcelog.next, prev, 0); | |
1857 | } while (next != prev); | |
1da177e4 | 1858 | |
b2b18660 | 1859 | synchronize_sched(); |
1da177e4 | 1860 | |
d88203d1 TG |
1861 | /* |
1862 | * Collect entries that were still getting written before the | |
1863 | * synchronize. | |
1864 | */ | |
15c8b6c1 | 1865 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 1866 | |
d88203d1 | 1867 | for (i = next; i < MCE_LOG_LEN; i++) { |
559faa6b HS |
1868 | struct mce *m = &mcelog.entry[i]; |
1869 | ||
1870 | if (m->finished && m->tsc < cpu_tsc[m->cpu]) { | |
1871 | err |= copy_to_user(buf, m, sizeof(*m)); | |
1da177e4 | 1872 | smp_rmb(); |
559faa6b HS |
1873 | buf += sizeof(*m); |
1874 | memset(m, 0, sizeof(*m)); | |
1da177e4 | 1875 | } |
d88203d1 | 1876 | } |
482908b4 HY |
1877 | |
1878 | if (err) | |
1879 | err = -EFAULT; | |
1880 | ||
1881 | out: | |
93b62c3c | 1882 | mutex_unlock(&mce_chrdev_read_mutex); |
f0de53bb | 1883 | kfree(cpu_tsc); |
e9eee03e | 1884 | |
482908b4 | 1885 | return err ? err : buf - ubuf; |
1da177e4 LT |
1886 | } |
1887 | ||
93b62c3c | 1888 | static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait) |
e02e68d3 | 1889 | { |
93b62c3c | 1890 | poll_wait(file, &mce_chrdev_wait, wait); |
e90328b8 | 1891 | if (READ_ONCE(mcelog.next)) |
e02e68d3 | 1892 | return POLLIN | POLLRDNORM; |
482908b4 HY |
1893 | if (!mce_apei_read_done && apei_check_mce()) |
1894 | return POLLIN | POLLRDNORM; | |
e02e68d3 TH |
1895 | return 0; |
1896 | } | |
1897 | ||
93b62c3c HS |
1898 | static long mce_chrdev_ioctl(struct file *f, unsigned int cmd, |
1899 | unsigned long arg) | |
1da177e4 LT |
1900 | { |
1901 | int __user *p = (int __user *)arg; | |
d88203d1 | 1902 | |
1da177e4 | 1903 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 1904 | return -EPERM; |
e9eee03e | 1905 | |
1da177e4 | 1906 | switch (cmd) { |
d88203d1 | 1907 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
1908 | return put_user(sizeof(struct mce), p); |
1909 | case MCE_GET_LOG_LEN: | |
d88203d1 | 1910 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
1911 | case MCE_GETCLEAR_FLAGS: { |
1912 | unsigned flags; | |
d88203d1 TG |
1913 | |
1914 | do { | |
1da177e4 | 1915 | flags = mcelog.flags; |
d88203d1 | 1916 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 1917 | |
d88203d1 | 1918 | return put_user(flags, p); |
1da177e4 LT |
1919 | } |
1920 | default: | |
d88203d1 TG |
1921 | return -ENOTTY; |
1922 | } | |
1da177e4 LT |
1923 | } |
1924 | ||
66f5ddf3 TL |
1925 | static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf, |
1926 | size_t usize, loff_t *off); | |
1927 | ||
1928 | void register_mce_write_callback(ssize_t (*fn)(struct file *filp, | |
1929 | const char __user *ubuf, | |
1930 | size_t usize, loff_t *off)) | |
1931 | { | |
1932 | mce_write = fn; | |
1933 | } | |
1934 | EXPORT_SYMBOL_GPL(register_mce_write_callback); | |
1935 | ||
29c6820f PM |
1936 | static ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf, |
1937 | size_t usize, loff_t *off) | |
66f5ddf3 TL |
1938 | { |
1939 | if (mce_write) | |
1940 | return mce_write(filp, ubuf, usize, off); | |
1941 | else | |
1942 | return -EINVAL; | |
1943 | } | |
1944 | ||
1945 | static const struct file_operations mce_chrdev_ops = { | |
93b62c3c HS |
1946 | .open = mce_chrdev_open, |
1947 | .release = mce_chrdev_release, | |
1948 | .read = mce_chrdev_read, | |
66f5ddf3 | 1949 | .write = mce_chrdev_write, |
93b62c3c HS |
1950 | .poll = mce_chrdev_poll, |
1951 | .unlocked_ioctl = mce_chrdev_ioctl, | |
1952 | .llseek = no_llseek, | |
1da177e4 LT |
1953 | }; |
1954 | ||
93b62c3c | 1955 | static struct miscdevice mce_chrdev_device = { |
1da177e4 LT |
1956 | MISC_MCELOG_MINOR, |
1957 | "mcelog", | |
1958 | &mce_chrdev_ops, | |
1959 | }; | |
1960 | ||
c3d1fb56 NR |
1961 | static void __mce_disable_bank(void *arg) |
1962 | { | |
1963 | int bank = *((int *)arg); | |
89cbc767 | 1964 | __clear_bit(bank, this_cpu_ptr(mce_poll_banks)); |
c3d1fb56 NR |
1965 | cmci_disable_bank(bank); |
1966 | } | |
1967 | ||
1968 | void mce_disable_bank(int bank) | |
1969 | { | |
1970 | if (bank >= mca_cfg.banks) { | |
1971 | pr_warn(FW_BUG | |
1972 | "Ignoring request to disable invalid MCA bank %d.\n", | |
1973 | bank); | |
1974 | return; | |
1975 | } | |
1976 | set_bit(bank, mce_banks_ce_disabled); | |
1977 | on_each_cpu(__mce_disable_bank, &bank, 1); | |
1978 | } | |
1979 | ||
13503fa9 | 1980 | /* |
62fdac59 HS |
1981 | * mce=off Disables machine check |
1982 | * mce=no_cmci Disables CMCI | |
88d53867 | 1983 | * mce=no_lmce Disables LMCE |
62fdac59 HS |
1984 | * mce=dont_log_ce Clears corrected events silently, no log created for CEs. |
1985 | * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. | |
3c079792 AK |
1986 | * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) |
1987 | * monarchtimeout is how long to wait for other CPUs on machine | |
1988 | * check, or 0 to not wait | |
13503fa9 HS |
1989 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. |
1990 | * mce=nobootlog Don't log MCEs from before booting. | |
450cc201 | 1991 | * mce=bios_cmci_threshold Don't program the CMCI threshold |
13503fa9 | 1992 | */ |
1da177e4 LT |
1993 | static int __init mcheck_enable(char *str) |
1994 | { | |
d203f0b8 BP |
1995 | struct mca_config *cfg = &mca_cfg; |
1996 | ||
e3346fc4 | 1997 | if (*str == 0) { |
4efc0670 | 1998 | enable_p5_mce(); |
e3346fc4 BZ |
1999 | return 1; |
2000 | } | |
4efc0670 AK |
2001 | if (*str == '=') |
2002 | str++; | |
1da177e4 | 2003 | if (!strcmp(str, "off")) |
1462594b | 2004 | cfg->disabled = true; |
62fdac59 | 2005 | else if (!strcmp(str, "no_cmci")) |
7af19e4a | 2006 | cfg->cmci_disabled = true; |
88d53867 AR |
2007 | else if (!strcmp(str, "no_lmce")) |
2008 | cfg->lmce_disabled = true; | |
62fdac59 | 2009 | else if (!strcmp(str, "dont_log_ce")) |
d203f0b8 | 2010 | cfg->dont_log_ce = true; |
62fdac59 | 2011 | else if (!strcmp(str, "ignore_ce")) |
7af19e4a | 2012 | cfg->ignore_ce = true; |
13503fa9 | 2013 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
84c2559d | 2014 | cfg->bootlog = (str[0] == 'b'); |
450cc201 | 2015 | else if (!strcmp(str, "bios_cmci_threshold")) |
1462594b | 2016 | cfg->bios_cmci_threshold = true; |
3c079792 | 2017 | else if (isdigit(str[0])) { |
5c31b280 | 2018 | if (get_option(&str, &cfg->tolerant) == 2) |
84c2559d | 2019 | get_option(&str, &(cfg->monarch_timeout)); |
3c079792 | 2020 | } else { |
c767a54b | 2021 | pr_info("mce argument %s ignored. Please use /sys\n", str); |
13503fa9 HS |
2022 | return 0; |
2023 | } | |
9b41046c | 2024 | return 1; |
1da177e4 | 2025 | } |
4efc0670 | 2026 | __setup("mce", mcheck_enable); |
1da177e4 | 2027 | |
a2202aa2 | 2028 | int __init mcheck_init(void) |
b33a6363 | 2029 | { |
a2202aa2 | 2030 | mcheck_intel_therm_init(); |
fd4cf79f | 2031 | mce_register_decode_chain(&mce_srao_nb, false); |
43eaa2a1 | 2032 | mcheck_vendor_init_severity(); |
a2202aa2 | 2033 | |
061120ae CG |
2034 | INIT_WORK(&mce_work, mce_process_work); |
2035 | init_irq_work(&mce_irq_work, mce_irq_work_cb); | |
2036 | ||
b33a6363 BP |
2037 | return 0; |
2038 | } | |
b33a6363 | 2039 | |
d88203d1 | 2040 | /* |
c7cece89 | 2041 | * mce_syscore: PM support |
d88203d1 | 2042 | */ |
1da177e4 | 2043 | |
973a2dd1 AK |
2044 | /* |
2045 | * Disable machine checks on suspend and shutdown. We can't really handle | |
2046 | * them later. | |
2047 | */ | |
5e09954a | 2048 | static int mce_disable_error_reporting(void) |
973a2dd1 AK |
2049 | { |
2050 | int i; | |
2051 | ||
d203f0b8 | 2052 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2053 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2054 | |
cebe1820 | 2055 | if (b->init) |
a2d32bcb | 2056 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 2057 | } |
973a2dd1 AK |
2058 | return 0; |
2059 | } | |
2060 | ||
c7cece89 | 2061 | static int mce_syscore_suspend(void) |
973a2dd1 | 2062 | { |
5e09954a | 2063 | return mce_disable_error_reporting(); |
973a2dd1 AK |
2064 | } |
2065 | ||
c7cece89 | 2066 | static void mce_syscore_shutdown(void) |
973a2dd1 | 2067 | { |
f3c6ea1b | 2068 | mce_disable_error_reporting(); |
973a2dd1 AK |
2069 | } |
2070 | ||
e9eee03e IM |
2071 | /* |
2072 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
2073 | * Only one CPU is active at this time, the others get re-added later using | |
2074 | * CPU hotplug: | |
2075 | */ | |
c7cece89 | 2076 | static void mce_syscore_resume(void) |
1da177e4 | 2077 | { |
5e09954a | 2078 | __mcheck_cpu_init_generic(); |
89cbc767 | 2079 | __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info)); |
1da177e4 LT |
2080 | } |
2081 | ||
f3c6ea1b | 2082 | static struct syscore_ops mce_syscore_ops = { |
c7cece89 HS |
2083 | .suspend = mce_syscore_suspend, |
2084 | .shutdown = mce_syscore_shutdown, | |
2085 | .resume = mce_syscore_resume, | |
f3c6ea1b RW |
2086 | }; |
2087 | ||
c7cece89 | 2088 | /* |
8a25a2fd | 2089 | * mce_device: Sysfs support |
c7cece89 HS |
2090 | */ |
2091 | ||
52d168e2 AK |
2092 | static void mce_cpu_restart(void *data) |
2093 | { | |
89cbc767 | 2094 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
33edbf02 | 2095 | return; |
5e09954a BP |
2096 | __mcheck_cpu_init_generic(); |
2097 | __mcheck_cpu_init_timer(); | |
52d168e2 AK |
2098 | } |
2099 | ||
1da177e4 | 2100 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
2101 | static void mce_restart(void) |
2102 | { | |
9aaef96f | 2103 | mce_timer_delete_all(); |
52d168e2 | 2104 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
2105 | } |
2106 | ||
9af43b54 | 2107 | /* Toggle features for corrected errors */ |
9aaef96f | 2108 | static void mce_disable_cmci(void *data) |
9af43b54 | 2109 | { |
89cbc767 | 2110 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
9af43b54 | 2111 | return; |
9af43b54 HS |
2112 | cmci_clear(); |
2113 | } | |
2114 | ||
2115 | static void mce_enable_ce(void *all) | |
2116 | { | |
89cbc767 | 2117 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
9af43b54 HS |
2118 | return; |
2119 | cmci_reenable(); | |
2120 | cmci_recheck(); | |
2121 | if (all) | |
5e09954a | 2122 | __mcheck_cpu_init_timer(); |
9af43b54 HS |
2123 | } |
2124 | ||
8a25a2fd | 2125 | static struct bus_type mce_subsys = { |
e9eee03e | 2126 | .name = "machinecheck", |
8a25a2fd | 2127 | .dev_name = "machinecheck", |
1da177e4 LT |
2128 | }; |
2129 | ||
d6126ef5 | 2130 | DEFINE_PER_CPU(struct device *, mce_device); |
e9eee03e | 2131 | |
e9eee03e | 2132 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); |
1da177e4 | 2133 | |
8a25a2fd | 2134 | static inline struct mce_bank *attr_to_bank(struct device_attribute *attr) |
cebe1820 AK |
2135 | { |
2136 | return container_of(attr, struct mce_bank, attr); | |
2137 | } | |
0d7482e3 | 2138 | |
8a25a2fd | 2139 | static ssize_t show_bank(struct device *s, struct device_attribute *attr, |
0d7482e3 AK |
2140 | char *buf) |
2141 | { | |
cebe1820 | 2142 | return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl); |
0d7482e3 AK |
2143 | } |
2144 | ||
8a25a2fd | 2145 | static ssize_t set_bank(struct device *s, struct device_attribute *attr, |
9319cec8 | 2146 | const char *buf, size_t size) |
0d7482e3 | 2147 | { |
9319cec8 | 2148 | u64 new; |
e9eee03e | 2149 | |
164109e3 | 2150 | if (kstrtou64(buf, 0, &new) < 0) |
0d7482e3 | 2151 | return -EINVAL; |
e9eee03e | 2152 | |
cebe1820 | 2153 | attr_to_bank(attr)->ctl = new; |
0d7482e3 | 2154 | mce_restart(); |
e9eee03e | 2155 | |
9319cec8 | 2156 | return size; |
0d7482e3 | 2157 | } |
a98f0dd3 | 2158 | |
e9eee03e | 2159 | static ssize_t |
8a25a2fd | 2160 | show_trigger(struct device *s, struct device_attribute *attr, char *buf) |
a98f0dd3 | 2161 | { |
1020bcbc | 2162 | strcpy(buf, mce_helper); |
a98f0dd3 | 2163 | strcat(buf, "\n"); |
1020bcbc | 2164 | return strlen(mce_helper) + 1; |
a98f0dd3 AK |
2165 | } |
2166 | ||
8a25a2fd | 2167 | static ssize_t set_trigger(struct device *s, struct device_attribute *attr, |
e9eee03e | 2168 | const char *buf, size_t siz) |
a98f0dd3 AK |
2169 | { |
2170 | char *p; | |
e9eee03e | 2171 | |
1020bcbc HS |
2172 | strncpy(mce_helper, buf, sizeof(mce_helper)); |
2173 | mce_helper[sizeof(mce_helper)-1] = 0; | |
1020bcbc | 2174 | p = strchr(mce_helper, '\n'); |
e9eee03e | 2175 | |
e9084ec9 | 2176 | if (p) |
e9eee03e IM |
2177 | *p = 0; |
2178 | ||
e9084ec9 | 2179 | return strlen(mce_helper) + !!p; |
a98f0dd3 AK |
2180 | } |
2181 | ||
8a25a2fd KS |
2182 | static ssize_t set_ignore_ce(struct device *s, |
2183 | struct device_attribute *attr, | |
9af43b54 HS |
2184 | const char *buf, size_t size) |
2185 | { | |
2186 | u64 new; | |
2187 | ||
164109e3 | 2188 | if (kstrtou64(buf, 0, &new) < 0) |
9af43b54 HS |
2189 | return -EINVAL; |
2190 | ||
7af19e4a | 2191 | if (mca_cfg.ignore_ce ^ !!new) { |
9af43b54 HS |
2192 | if (new) { |
2193 | /* disable ce features */ | |
9aaef96f HS |
2194 | mce_timer_delete_all(); |
2195 | on_each_cpu(mce_disable_cmci, NULL, 1); | |
7af19e4a | 2196 | mca_cfg.ignore_ce = true; |
9af43b54 HS |
2197 | } else { |
2198 | /* enable ce features */ | |
7af19e4a | 2199 | mca_cfg.ignore_ce = false; |
9af43b54 HS |
2200 | on_each_cpu(mce_enable_ce, (void *)1, 1); |
2201 | } | |
2202 | } | |
2203 | return size; | |
2204 | } | |
2205 | ||
8a25a2fd KS |
2206 | static ssize_t set_cmci_disabled(struct device *s, |
2207 | struct device_attribute *attr, | |
9af43b54 HS |
2208 | const char *buf, size_t size) |
2209 | { | |
2210 | u64 new; | |
2211 | ||
164109e3 | 2212 | if (kstrtou64(buf, 0, &new) < 0) |
9af43b54 HS |
2213 | return -EINVAL; |
2214 | ||
7af19e4a | 2215 | if (mca_cfg.cmci_disabled ^ !!new) { |
9af43b54 HS |
2216 | if (new) { |
2217 | /* disable cmci */ | |
9aaef96f | 2218 | on_each_cpu(mce_disable_cmci, NULL, 1); |
7af19e4a | 2219 | mca_cfg.cmci_disabled = true; |
9af43b54 HS |
2220 | } else { |
2221 | /* enable cmci */ | |
7af19e4a | 2222 | mca_cfg.cmci_disabled = false; |
9af43b54 HS |
2223 | on_each_cpu(mce_enable_ce, NULL, 1); |
2224 | } | |
2225 | } | |
2226 | return size; | |
2227 | } | |
2228 | ||
8a25a2fd KS |
2229 | static ssize_t store_int_with_restart(struct device *s, |
2230 | struct device_attribute *attr, | |
b56f642d AK |
2231 | const char *buf, size_t size) |
2232 | { | |
8a25a2fd | 2233 | ssize_t ret = device_store_int(s, attr, buf, size); |
b56f642d AK |
2234 | mce_restart(); |
2235 | return ret; | |
2236 | } | |
2237 | ||
8a25a2fd | 2238 | static DEVICE_ATTR(trigger, 0644, show_trigger, set_trigger); |
d203f0b8 | 2239 | static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant); |
84c2559d | 2240 | static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout); |
d203f0b8 | 2241 | static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce); |
e9eee03e | 2242 | |
8a25a2fd KS |
2243 | static struct dev_ext_attribute dev_attr_check_interval = { |
2244 | __ATTR(check_interval, 0644, device_show_int, store_int_with_restart), | |
b56f642d AK |
2245 | &check_interval |
2246 | }; | |
e9eee03e | 2247 | |
8a25a2fd | 2248 | static struct dev_ext_attribute dev_attr_ignore_ce = { |
7af19e4a BP |
2249 | __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce), |
2250 | &mca_cfg.ignore_ce | |
9af43b54 HS |
2251 | }; |
2252 | ||
8a25a2fd | 2253 | static struct dev_ext_attribute dev_attr_cmci_disabled = { |
7af19e4a BP |
2254 | __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled), |
2255 | &mca_cfg.cmci_disabled | |
9af43b54 HS |
2256 | }; |
2257 | ||
8a25a2fd KS |
2258 | static struct device_attribute *mce_device_attrs[] = { |
2259 | &dev_attr_tolerant.attr, | |
2260 | &dev_attr_check_interval.attr, | |
2261 | &dev_attr_trigger, | |
2262 | &dev_attr_monarch_timeout.attr, | |
2263 | &dev_attr_dont_log_ce.attr, | |
2264 | &dev_attr_ignore_ce.attr, | |
2265 | &dev_attr_cmci_disabled.attr, | |
a98f0dd3 AK |
2266 | NULL |
2267 | }; | |
1da177e4 | 2268 | |
8a25a2fd | 2269 | static cpumask_var_t mce_device_initialized; |
bae19fe0 | 2270 | |
e032d807 GKH |
2271 | static void mce_device_release(struct device *dev) |
2272 | { | |
2273 | kfree(dev); | |
2274 | } | |
2275 | ||
8a25a2fd | 2276 | /* Per cpu device init. All of the cpus still share the same ctrl bank: */ |
148f9bb8 | 2277 | static int mce_device_create(unsigned int cpu) |
1da177e4 | 2278 | { |
e032d807 | 2279 | struct device *dev; |
1da177e4 | 2280 | int err; |
b1f49f95 | 2281 | int i, j; |
92cb7612 | 2282 | |
90367556 | 2283 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
2284 | return -EIO; |
2285 | ||
e032d807 GKH |
2286 | dev = kzalloc(sizeof *dev, GFP_KERNEL); |
2287 | if (!dev) | |
2288 | return -ENOMEM; | |
8a25a2fd KS |
2289 | dev->id = cpu; |
2290 | dev->bus = &mce_subsys; | |
e032d807 | 2291 | dev->release = &mce_device_release; |
91c6d400 | 2292 | |
8a25a2fd | 2293 | err = device_register(dev); |
853d9b18 LK |
2294 | if (err) { |
2295 | put_device(dev); | |
d435d862 | 2296 | return err; |
853d9b18 | 2297 | } |
d435d862 | 2298 | |
8a25a2fd KS |
2299 | for (i = 0; mce_device_attrs[i]; i++) { |
2300 | err = device_create_file(dev, mce_device_attrs[i]); | |
d435d862 AM |
2301 | if (err) |
2302 | goto error; | |
2303 | } | |
d203f0b8 | 2304 | for (j = 0; j < mca_cfg.banks; j++) { |
8a25a2fd | 2305 | err = device_create_file(dev, &mce_banks[j].attr); |
0d7482e3 AK |
2306 | if (err) |
2307 | goto error2; | |
2308 | } | |
8a25a2fd | 2309 | cpumask_set_cpu(cpu, mce_device_initialized); |
d6126ef5 | 2310 | per_cpu(mce_device, cpu) = dev; |
91c6d400 | 2311 | |
d435d862 | 2312 | return 0; |
0d7482e3 | 2313 | error2: |
b1f49f95 | 2314 | while (--j >= 0) |
8a25a2fd | 2315 | device_remove_file(dev, &mce_banks[j].attr); |
d435d862 | 2316 | error: |
cb491fca | 2317 | while (--i >= 0) |
8a25a2fd | 2318 | device_remove_file(dev, mce_device_attrs[i]); |
cb491fca | 2319 | |
8a25a2fd | 2320 | device_unregister(dev); |
d435d862 | 2321 | |
91c6d400 AK |
2322 | return err; |
2323 | } | |
2324 | ||
148f9bb8 | 2325 | static void mce_device_remove(unsigned int cpu) |
91c6d400 | 2326 | { |
d6126ef5 | 2327 | struct device *dev = per_cpu(mce_device, cpu); |
73ca5358 SL |
2328 | int i; |
2329 | ||
8a25a2fd | 2330 | if (!cpumask_test_cpu(cpu, mce_device_initialized)) |
bae19fe0 AH |
2331 | return; |
2332 | ||
8a25a2fd KS |
2333 | for (i = 0; mce_device_attrs[i]; i++) |
2334 | device_remove_file(dev, mce_device_attrs[i]); | |
cb491fca | 2335 | |
d203f0b8 | 2336 | for (i = 0; i < mca_cfg.banks; i++) |
8a25a2fd | 2337 | device_remove_file(dev, &mce_banks[i].attr); |
cb491fca | 2338 | |
8a25a2fd KS |
2339 | device_unregister(dev); |
2340 | cpumask_clear_cpu(cpu, mce_device_initialized); | |
d6126ef5 | 2341 | per_cpu(mce_device, cpu) = NULL; |
91c6d400 | 2342 | } |
91c6d400 | 2343 | |
d6b75584 | 2344 | /* Make sure there are no machine checks on offlined CPUs. */ |
148f9bb8 | 2345 | static void mce_disable_cpu(void *h) |
d6b75584 | 2346 | { |
88ccbedd | 2347 | unsigned long action = *(unsigned long *)h; |
cb491fca | 2348 | int i; |
d6b75584 | 2349 | |
89cbc767 | 2350 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
d6b75584 | 2351 | return; |
767df1bd | 2352 | |
88ccbedd AK |
2353 | if (!(action & CPU_TASKS_FROZEN)) |
2354 | cmci_clear(); | |
d203f0b8 | 2355 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2356 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2357 | |
cebe1820 | 2358 | if (b->init) |
a2d32bcb | 2359 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 2360 | } |
d6b75584 AK |
2361 | } |
2362 | ||
148f9bb8 | 2363 | static void mce_reenable_cpu(void *h) |
d6b75584 | 2364 | { |
88ccbedd | 2365 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 2366 | int i; |
d6b75584 | 2367 | |
89cbc767 | 2368 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
d6b75584 | 2369 | return; |
e9eee03e | 2370 | |
88ccbedd AK |
2371 | if (!(action & CPU_TASKS_FROZEN)) |
2372 | cmci_reenable(); | |
d203f0b8 | 2373 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2374 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2375 | |
cebe1820 | 2376 | if (b->init) |
a2d32bcb | 2377 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
06b7a7a5 | 2378 | } |
d6b75584 AK |
2379 | } |
2380 | ||
91c6d400 | 2381 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
148f9bb8 | 2382 | static int |
e9eee03e | 2383 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) |
91c6d400 AK |
2384 | { |
2385 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 2386 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 | 2387 | |
1a65f970 | 2388 | switch (action & ~CPU_TASKS_FROZEN) { |
bae19fe0 | 2389 | case CPU_ONLINE: |
8a25a2fd | 2390 | mce_device_create(cpu); |
8735728e RW |
2391 | if (threshold_cpu_callback) |
2392 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 2393 | break; |
91c6d400 | 2394 | case CPU_DEAD: |
8735728e RW |
2395 | if (threshold_cpu_callback) |
2396 | threshold_cpu_callback(action, cpu); | |
8a25a2fd | 2397 | mce_device_remove(cpu); |
55babd8f | 2398 | mce_intel_hcpu_update(cpu); |
38356c1f BP |
2399 | |
2400 | /* intentionally ignoring frozen here */ | |
2401 | if (!(action & CPU_TASKS_FROZEN)) | |
2402 | cmci_rediscover(); | |
91c6d400 | 2403 | break; |
52d168e2 | 2404 | case CPU_DOWN_PREPARE: |
88ccbedd | 2405 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
55babd8f | 2406 | del_timer_sync(t); |
52d168e2 AK |
2407 | break; |
2408 | case CPU_DOWN_FAILED: | |
88ccbedd | 2409 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
26c3c283 | 2410 | mce_start_timer(cpu, t); |
88ccbedd | 2411 | break; |
1a65f970 TG |
2412 | } |
2413 | ||
bae19fe0 | 2414 | return NOTIFY_OK; |
91c6d400 AK |
2415 | } |
2416 | ||
148f9bb8 | 2417 | static struct notifier_block mce_cpu_notifier = { |
91c6d400 AK |
2418 | .notifier_call = mce_cpu_callback, |
2419 | }; | |
2420 | ||
cebe1820 | 2421 | static __init void mce_init_banks(void) |
0d7482e3 AK |
2422 | { |
2423 | int i; | |
2424 | ||
d203f0b8 | 2425 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2426 | struct mce_bank *b = &mce_banks[i]; |
8a25a2fd | 2427 | struct device_attribute *a = &b->attr; |
e9eee03e | 2428 | |
a07e4156 | 2429 | sysfs_attr_init(&a->attr); |
cebe1820 AK |
2430 | a->attr.name = b->attrname; |
2431 | snprintf(b->attrname, ATTR_LEN, "bank%d", i); | |
e9eee03e IM |
2432 | |
2433 | a->attr.mode = 0644; | |
2434 | a->show = show_bank; | |
2435 | a->store = set_bank; | |
0d7482e3 | 2436 | } |
0d7482e3 AK |
2437 | } |
2438 | ||
5e09954a | 2439 | static __init int mcheck_init_device(void) |
91c6d400 AK |
2440 | { |
2441 | int err; | |
2442 | int i = 0; | |
2443 | ||
9c15a24b MS |
2444 | if (!mce_available(&boot_cpu_data)) { |
2445 | err = -EIO; | |
2446 | goto err_out; | |
2447 | } | |
0d7482e3 | 2448 | |
9c15a24b MS |
2449 | if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) { |
2450 | err = -ENOMEM; | |
2451 | goto err_out; | |
2452 | } | |
996867d0 | 2453 | |
cebe1820 | 2454 | mce_init_banks(); |
0d7482e3 | 2455 | |
8a25a2fd | 2456 | err = subsys_system_register(&mce_subsys, NULL); |
d435d862 | 2457 | if (err) |
9c15a24b | 2458 | goto err_out_mem; |
91c6d400 | 2459 | |
82a8f131 | 2460 | cpu_notifier_register_begin(); |
91c6d400 | 2461 | for_each_online_cpu(i) { |
8a25a2fd | 2462 | err = mce_device_create(i); |
82a8f131 | 2463 | if (err) { |
27c93415 BP |
2464 | /* |
2465 | * Register notifier anyway (and do not unreg it) so | |
2466 | * that we don't leave undeleted timers, see notifier | |
2467 | * callback above. | |
2468 | */ | |
2469 | __register_hotcpu_notifier(&mce_cpu_notifier); | |
82a8f131 | 2470 | cpu_notifier_register_done(); |
9c15a24b | 2471 | goto err_device_create; |
82a8f131 | 2472 | } |
91c6d400 AK |
2473 | } |
2474 | ||
82a8f131 SB |
2475 | __register_hotcpu_notifier(&mce_cpu_notifier); |
2476 | cpu_notifier_register_done(); | |
93b62c3c | 2477 | |
9c15a24b MS |
2478 | register_syscore_ops(&mce_syscore_ops); |
2479 | ||
93b62c3c | 2480 | /* register character device /dev/mcelog */ |
9c15a24b MS |
2481 | err = misc_register(&mce_chrdev_device); |
2482 | if (err) | |
2483 | goto err_register; | |
2484 | ||
2485 | return 0; | |
2486 | ||
2487 | err_register: | |
2488 | unregister_syscore_ops(&mce_syscore_ops); | |
2489 | ||
9c15a24b MS |
2490 | err_device_create: |
2491 | /* | |
2492 | * We didn't keep track of which devices were created above, but | |
2493 | * even if we had, the set of online cpus might have changed. | |
2494 | * Play safe and remove for every possible cpu, since | |
2495 | * mce_device_remove() will do the right thing. | |
2496 | */ | |
2497 | for_each_possible_cpu(i) | |
2498 | mce_device_remove(i); | |
2499 | ||
2500 | err_out_mem: | |
2501 | free_cpumask_var(mce_device_initialized); | |
2502 | ||
2503 | err_out: | |
2504 | pr_err("Unable to init device /dev/mcelog (rc: %d)\n", err); | |
e9eee03e | 2505 | |
1da177e4 | 2506 | return err; |
1da177e4 | 2507 | } |
cef12ee5 | 2508 | device_initcall_sync(mcheck_init_device); |
a988d334 | 2509 | |
d7c3c9a6 AK |
2510 | /* |
2511 | * Old style boot options parsing. Only for compatibility. | |
2512 | */ | |
2513 | static int __init mcheck_disable(char *str) | |
2514 | { | |
1462594b | 2515 | mca_cfg.disabled = true; |
d7c3c9a6 AK |
2516 | return 1; |
2517 | } | |
2518 | __setup("nomce", mcheck_disable); | |
a988d334 | 2519 | |
5be9ed25 HY |
2520 | #ifdef CONFIG_DEBUG_FS |
2521 | struct dentry *mce_get_debugfs_dir(void) | |
a988d334 | 2522 | { |
5be9ed25 | 2523 | static struct dentry *dmce; |
a988d334 | 2524 | |
5be9ed25 HY |
2525 | if (!dmce) |
2526 | dmce = debugfs_create_dir("mce", NULL); | |
a988d334 | 2527 | |
5be9ed25 HY |
2528 | return dmce; |
2529 | } | |
a988d334 | 2530 | |
bf783f9f HY |
2531 | static void mce_reset(void) |
2532 | { | |
2533 | cpu_missing = 0; | |
c7c9b392 | 2534 | atomic_set(&mce_fake_panicked, 0); |
bf783f9f HY |
2535 | atomic_set(&mce_executing, 0); |
2536 | atomic_set(&mce_callin, 0); | |
2537 | atomic_set(&global_nwo, 0); | |
2538 | } | |
a988d334 | 2539 | |
bf783f9f HY |
2540 | static int fake_panic_get(void *data, u64 *val) |
2541 | { | |
2542 | *val = fake_panic; | |
2543 | return 0; | |
a988d334 IM |
2544 | } |
2545 | ||
bf783f9f | 2546 | static int fake_panic_set(void *data, u64 val) |
a988d334 | 2547 | { |
bf783f9f HY |
2548 | mce_reset(); |
2549 | fake_panic = val; | |
2550 | return 0; | |
a988d334 | 2551 | } |
a988d334 | 2552 | |
bf783f9f HY |
2553 | DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get, |
2554 | fake_panic_set, "%llu\n"); | |
d7c3c9a6 | 2555 | |
5e09954a | 2556 | static int __init mcheck_debugfs_init(void) |
d7c3c9a6 | 2557 | { |
bf783f9f HY |
2558 | struct dentry *dmce, *ffake_panic; |
2559 | ||
2560 | dmce = mce_get_debugfs_dir(); | |
2561 | if (!dmce) | |
2562 | return -ENOMEM; | |
2563 | ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL, | |
2564 | &fake_panic_fops); | |
2565 | if (!ffake_panic) | |
2566 | return -ENOMEM; | |
2567 | ||
2568 | return 0; | |
d7c3c9a6 | 2569 | } |
fd4cf79f CG |
2570 | #else |
2571 | static int __init mcheck_debugfs_init(void) { return -EINVAL; } | |
5be9ed25 | 2572 | #endif |
fd4cf79f CG |
2573 | |
2574 | static int __init mcheck_late_init(void) | |
2575 | { | |
2576 | mcheck_debugfs_init(); | |
2577 | ||
2578 | /* | |
2579 | * Flush out everything that has been logged during early boot, now that | |
2580 | * everything has been initialized (workqueues, decoders, ...). | |
2581 | */ | |
2582 | mce_schedule_work(); | |
2583 | ||
2584 | return 0; | |
2585 | } | |
2586 | late_initcall(mcheck_late_init); |