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Commit | Line | Data |
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89b831ef | 1 | /* |
ea2ca36b | 2 | * (c) 2005-2016 Advanced Micro Devices, Inc. |
89b831ef JS |
3 | * Your use of this code is subject to the terms and conditions of the |
4 | * GNU general public license version 2. See "COPYING" or | |
5 | * http://www.gnu.org/licenses/gpl.html | |
6 | * | |
7 | * Written by Jacob Shin - AMD, Inc. | |
e6d41e8c | 8 | * Maintained by: Borislav Petkov <bp@alien8.de> |
89b831ef | 9 | * |
3490c0e4 | 10 | * All MC4_MISCi registers are shared between cores on a node. |
89b831ef | 11 | */ |
89b831ef | 12 | #include <linux/interrupt.h> |
89b831ef | 13 | #include <linux/notifier.h> |
1cb2a8e1 | 14 | #include <linux/kobject.h> |
34fa1967 | 15 | #include <linux/percpu.h> |
1cb2a8e1 IM |
16 | #include <linux/errno.h> |
17 | #include <linux/sched.h> | |
89b831ef | 18 | #include <linux/sysfs.h> |
5a0e3ad6 | 19 | #include <linux/slab.h> |
1cb2a8e1 IM |
20 | #include <linux/init.h> |
21 | #include <linux/cpu.h> | |
22 | #include <linux/smp.h> | |
87a6d409 | 23 | #include <linux/string.h> |
1cb2a8e1 | 24 | |
019f34fc | 25 | #include <asm/amd_nb.h> |
89b831ef JS |
26 | #include <asm/apic.h> |
27 | #include <asm/mce.h> | |
28 | #include <asm/msr.h> | |
24fd78a8 | 29 | #include <asm/trace/irq_vectors.h> |
89b831ef | 30 | |
262e6811 BP |
31 | #include "mce-internal.h" |
32 | ||
60f116fc | 33 | #define NR_BLOCKS 5 |
2903ee85 JS |
34 | #define THRESHOLD_MAX 0xFFF |
35 | #define INT_TYPE_APIC 0x00020000 | |
36 | #define MASK_VALID_HI 0x80000000 | |
24ce0e96 JB |
37 | #define MASK_CNTP_HI 0x40000000 |
38 | #define MASK_LOCKED_HI 0x20000000 | |
2903ee85 JS |
39 | #define MASK_LVTOFF_HI 0x00F00000 |
40 | #define MASK_COUNT_EN_HI 0x00080000 | |
41 | #define MASK_INT_TYPE_HI 0x00060000 | |
42 | #define MASK_OVERFLOW_HI 0x00010000 | |
89b831ef | 43 | #define MASK_ERR_COUNT_HI 0x00000FFF |
95268664 JS |
44 | #define MASK_BLKPTR_LO 0xFF000000 |
45 | #define MCG_XBLK_ADDR 0xC0000400 | |
89b831ef | 46 | |
24fd78a8 AG |
47 | /* Deferred error settings */ |
48 | #define MSR_CU_DEF_ERR 0xC0000410 | |
49 | #define MASK_DEF_LVTOFF 0x000000F0 | |
50 | #define MASK_DEF_INT_TYPE 0x00000006 | |
51 | #define DEF_LVT_OFF 0x2 | |
52 | #define DEF_INT_TYPE_APIC 0x2 | |
53 | ||
f57a1f3c AG |
54 | /* Scalable MCA: */ |
55 | ||
56 | /* Threshold LVT offset is at MSR0xC0000410[15:12] */ | |
57 | #define SMCA_THR_LVT_OFF 0xF000 | |
58 | ||
4d7b02d5 SAS |
59 | static bool thresholding_en; |
60 | ||
336d335a BP |
61 | static const char * const th_names[] = { |
62 | "load_store", | |
63 | "insn_fetch", | |
64 | "combined_unit", | |
29f72ce3 | 65 | "decode_unit", |
336d335a BP |
66 | "northbridge", |
67 | "execution_unit", | |
68 | }; | |
69 | ||
87a6d409 YG |
70 | static const char * const smca_umc_block_names[] = { |
71 | "dram_ecc", | |
72 | "misc_umc" | |
73 | }; | |
74 | ||
c09a8c40 BP |
75 | struct smca_bank_name { |
76 | const char *name; /* Short name for sysfs */ | |
77 | const char *long_name; /* Long name for pretty-printing */ | |
78 | }; | |
79 | ||
80 | static struct smca_bank_name smca_names[] = { | |
5896820e YG |
81 | [SMCA_LS] = { "load_store", "Load Store Unit" }, |
82 | [SMCA_IF] = { "insn_fetch", "Instruction Fetch Unit" }, | |
83 | [SMCA_L2_CACHE] = { "l2_cache", "L2 Cache" }, | |
84 | [SMCA_DE] = { "decode_unit", "Decode Unit" }, | |
85 | [SMCA_EX] = { "execution_unit", "Execution Unit" }, | |
86 | [SMCA_FP] = { "floating_point", "Floating Point Unit" }, | |
87 | [SMCA_L3_CACHE] = { "l3_cache", "L3 Cache" }, | |
88 | [SMCA_CS] = { "coherent_slave", "Coherent Slave" }, | |
89 | [SMCA_PIE] = { "pie", "Power, Interrupts, etc." }, | |
90 | [SMCA_UMC] = { "umc", "Unified Memory Controller" }, | |
91 | [SMCA_PB] = { "param_block", "Parameter Block" }, | |
92 | [SMCA_PSP] = { "psp", "Platform Security Processor" }, | |
93 | [SMCA_SMU] = { "smu", "System Management Unit" }, | |
be0aec23 | 94 | }; |
c09a8c40 BP |
95 | |
96 | const char *smca_get_name(enum smca_bank_types t) | |
97 | { | |
98 | if (t >= N_SMCA_BANK_TYPES) | |
99 | return NULL; | |
100 | ||
101 | return smca_names[t].name; | |
102 | } | |
103 | ||
104 | const char *smca_get_long_name(enum smca_bank_types t) | |
105 | { | |
106 | if (t >= N_SMCA_BANK_TYPES) | |
107 | return NULL; | |
108 | ||
109 | return smca_names[t].long_name; | |
110 | } | |
111 | EXPORT_SYMBOL_GPL(smca_get_long_name); | |
5896820e | 112 | |
11cf8877 YG |
113 | static enum smca_bank_types smca_get_bank_type(struct mce *m) |
114 | { | |
115 | struct smca_bank *b; | |
116 | ||
117 | if (m->bank >= N_SMCA_BANK_TYPES) | |
118 | return N_SMCA_BANK_TYPES; | |
119 | ||
120 | b = &smca_banks[m->bank]; | |
121 | if (!b->hwid) | |
122 | return N_SMCA_BANK_TYPES; | |
123 | ||
124 | return b->hwid->bank_type; | |
125 | } | |
126 | ||
1ce9cd7f | 127 | static struct smca_hwid smca_hwid_mcatypes[] = { |
5896820e YG |
128 | /* { bank_type, hwid_mcatype, xec_bitmap } */ |
129 | ||
130 | /* ZN Core (HWID=0xB0) MCA types */ | |
131 | { SMCA_LS, HWID_MCATYPE(0xB0, 0x0), 0x1FFFEF }, | |
132 | { SMCA_IF, HWID_MCATYPE(0xB0, 0x1), 0x3FFF }, | |
133 | { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2), 0xF }, | |
134 | { SMCA_DE, HWID_MCATYPE(0xB0, 0x3), 0x1FF }, | |
135 | /* HWID 0xB0 MCATYPE 0x4 is Reserved */ | |
136 | { SMCA_EX, HWID_MCATYPE(0xB0, 0x5), 0x7FF }, | |
137 | { SMCA_FP, HWID_MCATYPE(0xB0, 0x6), 0x7F }, | |
138 | { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7), 0xFF }, | |
139 | ||
140 | /* Data Fabric MCA types */ | |
141 | { SMCA_CS, HWID_MCATYPE(0x2E, 0x0), 0x1FF }, | |
142 | { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1), 0xF }, | |
143 | ||
144 | /* Unified Memory Controller MCA type */ | |
145 | { SMCA_UMC, HWID_MCATYPE(0x96, 0x0), 0x3F }, | |
146 | ||
147 | /* Parameter Block MCA type */ | |
148 | { SMCA_PB, HWID_MCATYPE(0x05, 0x0), 0x1 }, | |
be0aec23 | 149 | |
5896820e YG |
150 | /* Platform Security Processor MCA type */ |
151 | { SMCA_PSP, HWID_MCATYPE(0xFF, 0x0), 0x1 }, | |
152 | ||
153 | /* System Management Unit MCA type */ | |
154 | { SMCA_SMU, HWID_MCATYPE(0x01, 0x0), 0x1 }, | |
be0aec23 | 155 | }; |
5896820e | 156 | |
79349f52 | 157 | struct smca_bank smca_banks[MAX_NR_BANKS]; |
5896820e | 158 | EXPORT_SYMBOL_GPL(smca_banks); |
be0aec23 | 159 | |
87a6d409 YG |
160 | /* |
161 | * In SMCA enabled processors, we can have multiple banks for a given IP type. | |
162 | * So to define a unique name for each bank, we use a temp c-string to append | |
163 | * the MCA_IPID[InstanceId] to type's name in get_name(). | |
164 | * | |
165 | * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN | |
166 | * is greater than 8 plus 1 (for underscore) plus length of longest type name. | |
167 | */ | |
168 | #define MAX_MCATYPE_NAME_LEN 30 | |
169 | static char buf_mcatype[MAX_MCATYPE_NAME_LEN]; | |
170 | ||
bafcdd3b | 171 | static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks); |
955d1427 | 172 | static DEFINE_PER_CPU(unsigned int, bank_map); /* see which banks are on */ |
89b831ef | 173 | |
b2762686 | 174 | static void amd_threshold_interrupt(void); |
24fd78a8 AG |
175 | static void amd_deferred_error_interrupt(void); |
176 | ||
177 | static void default_deferred_error_interrupt(void) | |
178 | { | |
179 | pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR); | |
180 | } | |
181 | void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; | |
b2762686 | 182 | |
84bcc1d5 | 183 | static void smca_configure(unsigned int bank, unsigned int cpu) |
5896820e | 184 | { |
84bcc1d5 | 185 | unsigned int i, hwid_mcatype; |
1ce9cd7f | 186 | struct smca_hwid *s_hwid; |
84bcc1d5 YG |
187 | u32 high, low; |
188 | u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); | |
189 | ||
190 | /* Set appropriate bits in MCA_CONFIG */ | |
191 | if (!rdmsr_safe(smca_config, &low, &high)) { | |
192 | /* | |
193 | * OS is required to set the MCAX bit to acknowledge that it is | |
194 | * now using the new MSR ranges and new registers under each | |
195 | * bank. It also means that the OS will configure deferred | |
196 | * errors in the new MCx_CONFIG register. If the bit is not set, | |
197 | * uncorrectable errors will cause a system panic. | |
198 | * | |
199 | * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.) | |
200 | */ | |
201 | high |= BIT(0); | |
202 | ||
203 | /* | |
204 | * SMCA sets the Deferred Error Interrupt type per bank. | |
205 | * | |
206 | * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us | |
207 | * if the DeferredIntType bit field is available. | |
208 | * | |
209 | * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the | |
210 | * high portion of the MSR). OS should set this to 0x1 to enable | |
211 | * APIC based interrupt. First, check that no interrupt has been | |
212 | * set. | |
213 | */ | |
214 | if ((low & BIT(5)) && !((high >> 5) & 0x3)) | |
215 | high |= BIT(5); | |
216 | ||
217 | wrmsr(smca_config, low, high); | |
218 | } | |
5896820e | 219 | |
9662d43f YG |
220 | /* Return early if this bank was already initialized. */ |
221 | if (smca_banks[bank].hwid) | |
5896820e YG |
222 | return; |
223 | ||
84bcc1d5 | 224 | if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) { |
5896820e YG |
225 | pr_warn("Failed to read MCA_IPID for bank %d\n", bank); |
226 | return; | |
227 | } | |
228 | ||
1ce9cd7f BP |
229 | hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID, |
230 | (high & MCI_IPID_MCATYPE) >> 16); | |
5896820e YG |
231 | |
232 | for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) { | |
1ce9cd7f BP |
233 | s_hwid = &smca_hwid_mcatypes[i]; |
234 | if (hwid_mcatype == s_hwid->hwid_mcatype) { | |
235 | smca_banks[bank].hwid = s_hwid; | |
84bcc1d5 | 236 | smca_banks[bank].id = low; |
0b737a9c | 237 | smca_banks[bank].sysfs_id = s_hwid->count++; |
5896820e YG |
238 | break; |
239 | } | |
240 | } | |
241 | } | |
242 | ||
4cd4601d | 243 | struct thresh_restart { |
1cb2a8e1 IM |
244 | struct threshold_block *b; |
245 | int reset; | |
9c37c9d8 RR |
246 | int set_lvt_off; |
247 | int lvt_off; | |
1cb2a8e1 | 248 | u16 old_limit; |
4cd4601d MT |
249 | }; |
250 | ||
c76e8164 BO |
251 | static inline bool is_shared_bank(int bank) |
252 | { | |
284b965c AG |
253 | /* |
254 | * Scalable MCA provides for only one core to have access to the MSRs of | |
255 | * a shared bank. | |
256 | */ | |
257 | if (mce_flags.smca) | |
258 | return false; | |
259 | ||
c76e8164 BO |
260 | /* Bank 4 is for northbridge reporting and is thus shared */ |
261 | return (bank == 4); | |
262 | } | |
263 | ||
2cd4c303 | 264 | static const char *bank4_names(const struct threshold_block *b) |
336d335a BP |
265 | { |
266 | switch (b->address) { | |
267 | /* MSR4_MISC0 */ | |
268 | case 0x00000413: | |
269 | return "dram"; | |
270 | ||
271 | case 0xc0000408: | |
272 | return "ht_links"; | |
273 | ||
274 | case 0xc0000409: | |
275 | return "l3_cache"; | |
276 | ||
277 | default: | |
278 | WARN(1, "Funny MSR: 0x%08x\n", b->address); | |
279 | return ""; | |
280 | } | |
281 | }; | |
282 | ||
283 | ||
f227d430 BP |
284 | static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) |
285 | { | |
286 | /* | |
287 | * bank 4 supports APIC LVT interrupts implicitly since forever. | |
288 | */ | |
289 | if (bank == 4) | |
290 | return true; | |
291 | ||
292 | /* | |
293 | * IntP: interrupt present; if this bit is set, the thresholding | |
294 | * bank can generate APIC LVT interrupts | |
295 | */ | |
296 | return msr_high_bits & BIT(28); | |
297 | } | |
298 | ||
bbaff08d RR |
299 | static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) |
300 | { | |
301 | int msr = (hi & MASK_LVTOFF_HI) >> 20; | |
302 | ||
303 | if (apic < 0) { | |
304 | pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " | |
305 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, | |
306 | b->bank, b->block, b->address, hi, lo); | |
307 | return 0; | |
308 | } | |
309 | ||
310 | if (apic != msr) { | |
f57a1f3c AG |
311 | /* |
312 | * On SMCA CPUs, LVT offset is programmed at a different MSR, and | |
313 | * the BIOS provides the value. The original field where LVT offset | |
314 | * was set is reserved. Return early here: | |
315 | */ | |
316 | if (mce_flags.smca) | |
317 | return 0; | |
318 | ||
bbaff08d RR |
319 | pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " |
320 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n", | |
321 | b->cpu, apic, b->bank, b->block, b->address, hi, lo); | |
322 | return 0; | |
323 | } | |
324 | ||
325 | return 1; | |
326 | }; | |
327 | ||
ea2ca36b | 328 | /* Reprogram MCx_MISC MSR behind this threshold bank. */ |
a6b6a14e | 329 | static void threshold_restart_bank(void *_tr) |
89b831ef | 330 | { |
4cd4601d | 331 | struct thresh_restart *tr = _tr; |
7203a049 | 332 | u32 hi, lo; |
89b831ef | 333 | |
7203a049 | 334 | rdmsr(tr->b->address, lo, hi); |
89b831ef | 335 | |
7203a049 | 336 | if (tr->b->threshold_limit < (hi & THRESHOLD_MAX)) |
4cd4601d | 337 | tr->reset = 1; /* limit cannot be lower than err count */ |
89b831ef | 338 | |
4cd4601d | 339 | if (tr->reset) { /* reset err count and overflow bit */ |
7203a049 RR |
340 | hi = |
341 | (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) | | |
4cd4601d MT |
342 | (THRESHOLD_MAX - tr->b->threshold_limit); |
343 | } else if (tr->old_limit) { /* change limit w/o reset */ | |
7203a049 | 344 | int new_count = (hi & THRESHOLD_MAX) + |
4cd4601d | 345 | (tr->old_limit - tr->b->threshold_limit); |
1cb2a8e1 | 346 | |
7203a049 | 347 | hi = (hi & ~MASK_ERR_COUNT_HI) | |
89b831ef JS |
348 | (new_count & THRESHOLD_MAX); |
349 | } | |
350 | ||
f227d430 BP |
351 | /* clear IntType */ |
352 | hi &= ~MASK_INT_TYPE_HI; | |
353 | ||
354 | if (!tr->b->interrupt_capable) | |
355 | goto done; | |
356 | ||
9c37c9d8 | 357 | if (tr->set_lvt_off) { |
bbaff08d RR |
358 | if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) { |
359 | /* set new lvt offset */ | |
360 | hi &= ~MASK_LVTOFF_HI; | |
361 | hi |= tr->lvt_off << 20; | |
362 | } | |
9c37c9d8 RR |
363 | } |
364 | ||
f227d430 BP |
365 | if (tr->b->interrupt_enable) |
366 | hi |= INT_TYPE_APIC; | |
367 | ||
368 | done: | |
89b831ef | 369 | |
7203a049 RR |
370 | hi |= MASK_COUNT_EN_HI; |
371 | wrmsr(tr->b->address, lo, hi); | |
89b831ef JS |
372 | } |
373 | ||
9c37c9d8 RR |
374 | static void mce_threshold_block_init(struct threshold_block *b, int offset) |
375 | { | |
376 | struct thresh_restart tr = { | |
377 | .b = b, | |
378 | .set_lvt_off = 1, | |
379 | .lvt_off = offset, | |
380 | }; | |
381 | ||
382 | b->threshold_limit = THRESHOLD_MAX; | |
383 | threshold_restart_bank(&tr); | |
384 | }; | |
385 | ||
868c00bb | 386 | static int setup_APIC_mce_threshold(int reserved, int new) |
bbaff08d RR |
387 | { |
388 | if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR, | |
389 | APIC_EILVT_MSG_FIX, 0)) | |
390 | return new; | |
391 | ||
392 | return reserved; | |
393 | } | |
394 | ||
24fd78a8 AG |
395 | static int setup_APIC_deferred_error(int reserved, int new) |
396 | { | |
397 | if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR, | |
398 | APIC_EILVT_MSG_FIX, 0)) | |
399 | return new; | |
400 | ||
401 | return reserved; | |
402 | } | |
403 | ||
404 | static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) | |
405 | { | |
406 | u32 low = 0, high = 0; | |
407 | int def_offset = -1, def_new; | |
408 | ||
409 | if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) | |
410 | return; | |
411 | ||
412 | def_new = (low & MASK_DEF_LVTOFF) >> 4; | |
413 | if (!(low & MASK_DEF_LVTOFF)) { | |
414 | pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n"); | |
415 | def_new = DEF_LVT_OFF; | |
416 | low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4); | |
417 | } | |
418 | ||
419 | def_offset = setup_APIC_deferred_error(def_offset, def_new); | |
420 | if ((def_offset == def_new) && | |
421 | (deferred_error_int_vector != amd_deferred_error_interrupt)) | |
422 | deferred_error_int_vector = amd_deferred_error_interrupt; | |
423 | ||
c8a4364c YG |
424 | if (!mce_flags.smca) |
425 | low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; | |
426 | ||
24fd78a8 AG |
427 | wrmsr(MSR_CU_DEF_ERR, low, high); |
428 | } | |
429 | ||
cfee4f6f | 430 | static u32 get_block_address(unsigned int cpu, u32 current_addr, u32 low, u32 high, |
8dd1e17a AG |
431 | unsigned int bank, unsigned int block) |
432 | { | |
433 | u32 addr = 0, offset = 0; | |
434 | ||
435 | if (mce_flags.smca) { | |
436 | if (!block) { | |
437 | addr = MSR_AMD64_SMCA_MCx_MISC(bank); | |
438 | } else { | |
439 | /* | |
440 | * For SMCA enabled processors, BLKPTR field of the | |
441 | * first MISC register (MCx_MISC0) indicates presence of | |
442 | * additional MISC register set (MISC1-4). | |
443 | */ | |
444 | u32 low, high; | |
445 | ||
cfee4f6f | 446 | if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) |
8dd1e17a AG |
447 | return addr; |
448 | ||
449 | if (!(low & MCI_CONFIG_MCAX)) | |
450 | return addr; | |
451 | ||
cfee4f6f | 452 | if (!rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) && |
8dd1e17a AG |
453 | (low & MASK_BLKPTR_LO)) |
454 | addr = MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); | |
455 | } | |
456 | return addr; | |
457 | } | |
458 | ||
459 | /* Fall back to method we used for older processors: */ | |
460 | switch (block) { | |
461 | case 0: | |
d9d73fcc | 462 | addr = msr_ops.misc(bank); |
8dd1e17a AG |
463 | break; |
464 | case 1: | |
465 | offset = ((low & MASK_BLKPTR_LO) >> 21); | |
466 | if (offset) | |
467 | addr = MCG_XBLK_ADDR + offset; | |
468 | break; | |
469 | default: | |
470 | addr = ++current_addr; | |
471 | } | |
472 | return addr; | |
473 | } | |
474 | ||
429893b1 BP |
475 | static int |
476 | prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, | |
477 | int offset, u32 misc_high) | |
478 | { | |
479 | unsigned int cpu = smp_processor_id(); | |
84bcc1d5 | 480 | u32 smca_low, smca_high; |
429893b1 BP |
481 | struct threshold_block b; |
482 | int new; | |
483 | ||
484 | if (!block) | |
485 | per_cpu(bank_map, cpu) |= (1 << bank); | |
486 | ||
487 | memset(&b, 0, sizeof(b)); | |
488 | b.cpu = cpu; | |
489 | b.bank = bank; | |
490 | b.block = block; | |
491 | b.address = addr; | |
492 | b.interrupt_capable = lvt_interrupt_supported(bank, misc_high); | |
493 | ||
494 | if (!b.interrupt_capable) | |
495 | goto done; | |
496 | ||
497 | b.interrupt_enable = 1; | |
498 | ||
e128b4f4 BP |
499 | if (!mce_flags.smca) { |
500 | new = (misc_high & MASK_LVTOFF_HI) >> 20; | |
501 | goto set_offset; | |
502 | } | |
32544f06 | 503 | |
e128b4f4 BP |
504 | /* Gather LVT offset for thresholding: */ |
505 | if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high)) | |
506 | goto out; | |
507 | ||
508 | new = (smca_low & SMCA_THR_LVT_OFF) >> 12; | |
509 | ||
510 | set_offset: | |
429893b1 BP |
511 | offset = setup_APIC_mce_threshold(offset, new); |
512 | ||
513 | if ((offset == new) && (mce_threshold_vector != amd_threshold_interrupt)) | |
514 | mce_threshold_vector = amd_threshold_interrupt; | |
515 | ||
516 | done: | |
517 | mce_threshold_block_init(&b, offset); | |
518 | ||
519 | out: | |
520 | return offset; | |
521 | } | |
522 | ||
95268664 | 523 | /* cpu init entry point, called from mce.c with preempt off */ |
cc3ca220 | 524 | void mce_amd_feature_init(struct cpuinfo_x86 *c) |
89b831ef | 525 | { |
95268664 | 526 | u32 low = 0, high = 0, address = 0; |
cfee4f6f | 527 | unsigned int bank, block, cpu = smp_processor_id(); |
429893b1 | 528 | int offset = -1; |
89b831ef | 529 | |
bafcdd3b | 530 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
5896820e | 531 | if (mce_flags.smca) |
84bcc1d5 | 532 | smca_configure(bank, cpu); |
5896820e | 533 | |
95268664 | 534 | for (block = 0; block < NR_BLOCKS; ++block) { |
cfee4f6f | 535 | address = get_block_address(cpu, address, low, high, bank, block); |
8dd1e17a AG |
536 | if (!address) |
537 | break; | |
95268664 JS |
538 | |
539 | if (rdmsr_safe(address, &low, &high)) | |
24ce0e96 | 540 | break; |
95268664 | 541 | |
6dcbfe4f BP |
542 | if (!(high & MASK_VALID_HI)) |
543 | continue; | |
95268664 | 544 | |
24ce0e96 JB |
545 | if (!(high & MASK_CNTP_HI) || |
546 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
547 | continue; |
548 | ||
429893b1 | 549 | offset = prepare_threshold_block(bank, block, address, offset, high); |
95268664 | 550 | } |
89b831ef | 551 | } |
24fd78a8 AG |
552 | |
553 | if (mce_flags.succor) | |
554 | deferred_error_interrupt_enable(c); | |
89b831ef JS |
555 | } |
556 | ||
f5382de9 YG |
557 | int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) |
558 | { | |
559 | u64 dram_base_addr, dram_limit_addr, dram_hole_base; | |
560 | /* We start from the normalized address */ | |
561 | u64 ret_addr = norm_addr; | |
562 | ||
563 | u32 tmp; | |
564 | ||
565 | u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; | |
566 | u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; | |
567 | u8 intlv_addr_sel, intlv_addr_bit; | |
568 | u8 num_intlv_bits, hashed_bit; | |
569 | u8 lgcy_mmio_hole_en, base = 0; | |
570 | u8 cs_mask, cs_id = 0; | |
571 | bool hash_enabled = false; | |
572 | ||
573 | /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */ | |
574 | if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp)) | |
575 | goto out_err; | |
576 | ||
577 | /* Remove HiAddrOffset from normalized address, if enabled: */ | |
578 | if (tmp & BIT(0)) { | |
579 | u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8; | |
580 | ||
581 | if (norm_addr >= hi_addr_offset) { | |
582 | ret_addr -= hi_addr_offset; | |
583 | base = 1; | |
584 | } | |
585 | } | |
586 | ||
587 | /* Read D18F0x110 (DramBaseAddress). */ | |
588 | if (amd_df_indirect_read(nid, 0, 0x110 + (8 * base), umc, &tmp)) | |
589 | goto out_err; | |
590 | ||
591 | /* Check if address range is valid. */ | |
592 | if (!(tmp & BIT(0))) { | |
593 | pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n", | |
594 | __func__, tmp); | |
595 | goto out_err; | |
596 | } | |
597 | ||
598 | lgcy_mmio_hole_en = tmp & BIT(1); | |
599 | intlv_num_chan = (tmp >> 4) & 0xF; | |
600 | intlv_addr_sel = (tmp >> 8) & 0x7; | |
601 | dram_base_addr = (tmp & GENMASK_ULL(31, 12)) << 16; | |
602 | ||
603 | /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ | |
604 | if (intlv_addr_sel > 3) { | |
605 | pr_err("%s: Invalid interleave address select %d.\n", | |
606 | __func__, intlv_addr_sel); | |
607 | goto out_err; | |
608 | } | |
609 | ||
610 | /* Read D18F0x114 (DramLimitAddress). */ | |
611 | if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp)) | |
612 | goto out_err; | |
613 | ||
614 | intlv_num_sockets = (tmp >> 8) & 0x1; | |
615 | intlv_num_dies = (tmp >> 10) & 0x3; | |
616 | dram_limit_addr = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); | |
617 | ||
618 | intlv_addr_bit = intlv_addr_sel + 8; | |
619 | ||
620 | /* Re-use intlv_num_chan by setting it equal to log2(#channels) */ | |
621 | switch (intlv_num_chan) { | |
622 | case 0: intlv_num_chan = 0; break; | |
623 | case 1: intlv_num_chan = 1; break; | |
624 | case 3: intlv_num_chan = 2; break; | |
625 | case 5: intlv_num_chan = 3; break; | |
626 | case 7: intlv_num_chan = 4; break; | |
627 | ||
628 | case 8: intlv_num_chan = 1; | |
629 | hash_enabled = true; | |
630 | break; | |
631 | default: | |
632 | pr_err("%s: Invalid number of interleaved channels %d.\n", | |
633 | __func__, intlv_num_chan); | |
634 | goto out_err; | |
635 | } | |
636 | ||
637 | num_intlv_bits = intlv_num_chan; | |
638 | ||
639 | if (intlv_num_dies > 2) { | |
640 | pr_err("%s: Invalid number of interleaved nodes/dies %d.\n", | |
641 | __func__, intlv_num_dies); | |
642 | goto out_err; | |
643 | } | |
644 | ||
645 | num_intlv_bits += intlv_num_dies; | |
646 | ||
647 | /* Add a bit if sockets are interleaved. */ | |
648 | num_intlv_bits += intlv_num_sockets; | |
649 | ||
650 | /* Assert num_intlv_bits <= 4 */ | |
651 | if (num_intlv_bits > 4) { | |
652 | pr_err("%s: Invalid interleave bits %d.\n", | |
653 | __func__, num_intlv_bits); | |
654 | goto out_err; | |
655 | } | |
656 | ||
657 | if (num_intlv_bits > 0) { | |
658 | u64 temp_addr_x, temp_addr_i, temp_addr_y; | |
659 | u8 die_id_bit, sock_id_bit, cs_fabric_id; | |
660 | ||
661 | /* | |
662 | * Read FabricBlockInstanceInformation3_CS[BlockFabricID]. | |
663 | * This is the fabric id for this coherent slave. Use | |
664 | * umc/channel# as instance id of the coherent slave | |
665 | * for FICAA. | |
666 | */ | |
667 | if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp)) | |
668 | goto out_err; | |
669 | ||
670 | cs_fabric_id = (tmp >> 8) & 0xFF; | |
671 | die_id_bit = 0; | |
672 | ||
673 | /* If interleaved over more than 1 channel: */ | |
674 | if (intlv_num_chan) { | |
675 | die_id_bit = intlv_num_chan; | |
676 | cs_mask = (1 << die_id_bit) - 1; | |
677 | cs_id = cs_fabric_id & cs_mask; | |
678 | } | |
679 | ||
680 | sock_id_bit = die_id_bit; | |
681 | ||
682 | /* Read D18F1x208 (SystemFabricIdMask). */ | |
683 | if (intlv_num_dies || intlv_num_sockets) | |
684 | if (amd_df_indirect_read(nid, 1, 0x208, umc, &tmp)) | |
685 | goto out_err; | |
686 | ||
687 | /* If interleaved over more than 1 die. */ | |
688 | if (intlv_num_dies) { | |
689 | sock_id_bit = die_id_bit + intlv_num_dies; | |
690 | die_id_shift = (tmp >> 24) & 0xF; | |
691 | die_id_mask = (tmp >> 8) & 0xFF; | |
692 | ||
693 | cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; | |
694 | } | |
695 | ||
696 | /* If interleaved over more than 1 socket. */ | |
697 | if (intlv_num_sockets) { | |
698 | socket_id_shift = (tmp >> 28) & 0xF; | |
699 | socket_id_mask = (tmp >> 16) & 0xFF; | |
700 | ||
701 | cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit; | |
702 | } | |
703 | ||
704 | /* | |
705 | * The pre-interleaved address consists of XXXXXXIIIYYYYY | |
706 | * where III is the ID for this CS, and XXXXXXYYYYY are the | |
707 | * address bits from the post-interleaved address. | |
708 | * "num_intlv_bits" has been calculated to tell us how many "I" | |
709 | * bits there are. "intlv_addr_bit" tells us how many "Y" bits | |
710 | * there are (where "I" starts). | |
711 | */ | |
712 | temp_addr_y = ret_addr & GENMASK_ULL(intlv_addr_bit-1, 0); | |
713 | temp_addr_i = (cs_id << intlv_addr_bit); | |
714 | temp_addr_x = (ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits; | |
715 | ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; | |
716 | } | |
717 | ||
718 | /* Add dram base address */ | |
719 | ret_addr += dram_base_addr; | |
720 | ||
721 | /* If legacy MMIO hole enabled */ | |
722 | if (lgcy_mmio_hole_en) { | |
723 | if (amd_df_indirect_read(nid, 0, 0x104, umc, &tmp)) | |
724 | goto out_err; | |
725 | ||
726 | dram_hole_base = tmp & GENMASK(31, 24); | |
727 | if (ret_addr >= dram_hole_base) | |
728 | ret_addr += (BIT_ULL(32) - dram_hole_base); | |
729 | } | |
730 | ||
731 | if (hash_enabled) { | |
732 | /* Save some parentheses and grab ls-bit at the end. */ | |
733 | hashed_bit = (ret_addr >> 12) ^ | |
734 | (ret_addr >> 18) ^ | |
735 | (ret_addr >> 21) ^ | |
736 | (ret_addr >> 30) ^ | |
737 | cs_id; | |
738 | ||
739 | hashed_bit &= BIT(0); | |
740 | ||
741 | if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0))) | |
742 | ret_addr ^= BIT(intlv_addr_bit); | |
743 | } | |
744 | ||
745 | /* Is calculated system address is above DRAM limit address? */ | |
746 | if (ret_addr > dram_limit_addr) | |
747 | goto out_err; | |
748 | ||
749 | *sys_addr = ret_addr; | |
750 | return 0; | |
751 | ||
752 | out_err: | |
753 | return -EINVAL; | |
754 | } | |
755 | EXPORT_SYMBOL_GPL(umc_normaddr_to_sysaddr); | |
756 | ||
37d43acf | 757 | static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) |
afdf344e AG |
758 | { |
759 | struct mce m; | |
afdf344e AG |
760 | |
761 | mce_setup(&m); | |
762 | ||
763 | m.status = status; | |
37d43acf | 764 | m.misc = misc; |
669c00f0 BP |
765 | m.bank = bank; |
766 | m.tsc = rdtsc(); | |
6e6e746e | 767 | |
4f29b73b | 768 | if (m.status & MCI_STATUS_ADDRV) { |
37d43acf | 769 | m.addr = addr; |
afdf344e | 770 | |
4f29b73b YG |
771 | /* |
772 | * Extract [55:<lsb>] where lsb is the least significant | |
773 | * *valid* bit of the address bits. | |
774 | */ | |
775 | if (mce_flags.smca) { | |
776 | u8 lsb = (m.addr >> 56) & 0x3f; | |
777 | ||
778 | m.addr &= GENMASK_ULL(55, lsb); | |
779 | } | |
780 | } | |
781 | ||
5828c46f YG |
782 | if (mce_flags.smca) { |
783 | rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid); | |
784 | ||
785 | if (m.status & MCI_STATUS_SYNDV) | |
786 | rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd); | |
787 | } | |
db819d60 | 788 | |
6e6e746e | 789 | mce_log(&m); |
afdf344e AG |
790 | } |
791 | ||
c4158ff5 | 792 | asmlinkage __visible void __irq_entry smp_deferred_error_interrupt(void) |
24fd78a8 AG |
793 | { |
794 | entering_irq(); | |
795 | trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR); | |
0f42ae28 TG |
796 | inc_irq_stat(irq_deferred_error_count); |
797 | deferred_error_int_vector(); | |
24fd78a8 AG |
798 | trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR); |
799 | exiting_ack_irq(); | |
800 | } | |
801 | ||
37d43acf YG |
802 | /* |
803 | * Returns true if the logged error is deferred. False, otherwise. | |
804 | */ | |
805 | static inline bool | |
806 | _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc) | |
24fd78a8 | 807 | { |
37d43acf | 808 | u64 status, addr = 0; |
24fd78a8 | 809 | |
37d43acf YG |
810 | rdmsrl(msr_stat, status); |
811 | if (!(status & MCI_STATUS_VAL)) | |
812 | return false; | |
34102009 | 813 | |
37d43acf YG |
814 | if (status & MCI_STATUS_ADDRV) |
815 | rdmsrl(msr_addr, addr); | |
24fd78a8 | 816 | |
37d43acf | 817 | __log_error(bank, status, addr, misc); |
24fd78a8 | 818 | |
a24b8c34 | 819 | wrmsrl(msr_stat, 0); |
37d43acf YG |
820 | |
821 | return status & MCI_STATUS_DEFERRED; | |
24fd78a8 AG |
822 | } |
823 | ||
89b831ef | 824 | /* |
37d43acf YG |
825 | * We have three scenarios for checking for Deferred errors: |
826 | * | |
827 | * 1) Non-SMCA systems check MCA_STATUS and log error if found. | |
828 | * 2) SMCA systems check MCA_STATUS. If error is found then log it and also | |
829 | * clear MCA_DESTAT. | |
830 | * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and | |
831 | * log it. | |
89b831ef | 832 | */ |
37d43acf YG |
833 | static void log_error_deferred(unsigned int bank) |
834 | { | |
835 | bool defrd; | |
836 | ||
837 | defrd = _log_error_bank(bank, msr_ops.status(bank), | |
838 | msr_ops.addr(bank), 0); | |
839 | ||
840 | if (!mce_flags.smca) | |
841 | return; | |
842 | ||
843 | /* Clear MCA_DESTAT if we logged the deferred error from MCA_STATUS. */ | |
844 | if (defrd) { | |
845 | wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0); | |
846 | return; | |
847 | } | |
848 | ||
849 | /* | |
850 | * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check | |
851 | * for a valid error. | |
852 | */ | |
853 | _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank), | |
854 | MSR_AMD64_SMCA_MCx_DEADDR(bank), 0); | |
855 | } | |
856 | ||
857 | /* APIC interrupt handler for deferred errors */ | |
858 | static void amd_deferred_error_interrupt(void) | |
859 | { | |
860 | unsigned int bank; | |
861 | ||
862 | for (bank = 0; bank < mca_cfg.banks; ++bank) | |
863 | log_error_deferred(bank); | |
864 | } | |
865 | ||
866 | static void log_error_thresholding(unsigned int bank, u64 misc) | |
867 | { | |
868 | _log_error_bank(bank, msr_ops.status(bank), msr_ops.addr(bank), misc); | |
869 | } | |
89b831ef | 870 | |
17ef4af0 YG |
871 | static void log_and_reset_block(struct threshold_block *block) |
872 | { | |
873 | struct thresh_restart tr; | |
874 | u32 low = 0, high = 0; | |
875 | ||
876 | if (!block) | |
877 | return; | |
878 | ||
879 | if (rdmsr_safe(block->address, &low, &high)) | |
880 | return; | |
881 | ||
882 | if (!(high & MASK_OVERFLOW_HI)) | |
883 | return; | |
884 | ||
885 | /* Log the MCE which caused the threshold event. */ | |
886 | log_error_thresholding(block->bank, ((u64)high << 32) | low); | |
887 | ||
888 | /* Reset threshold block after logging error. */ | |
889 | memset(&tr, 0, sizeof(tr)); | |
890 | tr.b = block; | |
891 | threshold_restart_bank(&tr); | |
892 | } | |
893 | ||
89b831ef | 894 | /* |
37d43acf YG |
895 | * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt |
896 | * goes off when error_count reaches threshold_limit. | |
89b831ef | 897 | */ |
b2762686 | 898 | static void amd_threshold_interrupt(void) |
89b831ef | 899 | { |
17ef4af0 YG |
900 | struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL; |
901 | unsigned int bank, cpu = smp_processor_id(); | |
89b831ef | 902 | |
bafcdd3b | 903 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
44612a3a | 904 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
24ce0e96 | 905 | continue; |
44612a3a | 906 | |
17ef4af0 YG |
907 | first_block = per_cpu(threshold_banks, cpu)[bank]->blocks; |
908 | if (!first_block) | |
909 | continue; | |
18807ddb | 910 | |
17ef4af0 YG |
911 | /* |
912 | * The first block is also the head of the list. Check it first | |
913 | * before iterating over the rest. | |
914 | */ | |
915 | log_and_reset_block(first_block); | |
916 | list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj) | |
917 | log_and_reset_block(block); | |
37d43acf | 918 | } |
89b831ef JS |
919 | } |
920 | ||
921 | /* | |
922 | * Sysfs Interface | |
923 | */ | |
924 | ||
89b831ef | 925 | struct threshold_attr { |
2903ee85 | 926 | struct attribute attr; |
1cb2a8e1 IM |
927 | ssize_t (*show) (struct threshold_block *, char *); |
928 | ssize_t (*store) (struct threshold_block *, const char *, size_t count); | |
89b831ef JS |
929 | }; |
930 | ||
1cb2a8e1 IM |
931 | #define SHOW_FIELDS(name) \ |
932 | static ssize_t show_ ## name(struct threshold_block *b, char *buf) \ | |
933 | { \ | |
18c20f37 | 934 | return sprintf(buf, "%lu\n", (unsigned long) b->name); \ |
2903ee85 | 935 | } |
89b831ef JS |
936 | SHOW_FIELDS(interrupt_enable) |
937 | SHOW_FIELDS(threshold_limit) | |
938 | ||
1cb2a8e1 | 939 | static ssize_t |
9319cec8 | 940 | store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size) |
89b831ef | 941 | { |
4cd4601d | 942 | struct thresh_restart tr; |
1cb2a8e1 | 943 | unsigned long new; |
1cb2a8e1 | 944 | |
f227d430 BP |
945 | if (!b->interrupt_capable) |
946 | return -EINVAL; | |
947 | ||
164109e3 | 948 | if (kstrtoul(buf, 0, &new) < 0) |
89b831ef | 949 | return -EINVAL; |
1cb2a8e1 | 950 | |
89b831ef JS |
951 | b->interrupt_enable = !!new; |
952 | ||
9c37c9d8 | 953 | memset(&tr, 0, sizeof(tr)); |
1cb2a8e1 | 954 | tr.b = b; |
1cb2a8e1 | 955 | |
a6b6a14e | 956 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef | 957 | |
9319cec8 | 958 | return size; |
89b831ef JS |
959 | } |
960 | ||
1cb2a8e1 | 961 | static ssize_t |
9319cec8 | 962 | store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) |
89b831ef | 963 | { |
4cd4601d | 964 | struct thresh_restart tr; |
1cb2a8e1 | 965 | unsigned long new; |
1cb2a8e1 | 966 | |
164109e3 | 967 | if (kstrtoul(buf, 0, &new) < 0) |
89b831ef | 968 | return -EINVAL; |
1cb2a8e1 | 969 | |
89b831ef JS |
970 | if (new > THRESHOLD_MAX) |
971 | new = THRESHOLD_MAX; | |
972 | if (new < 1) | |
973 | new = 1; | |
1cb2a8e1 | 974 | |
9c37c9d8 | 975 | memset(&tr, 0, sizeof(tr)); |
4cd4601d | 976 | tr.old_limit = b->threshold_limit; |
89b831ef | 977 | b->threshold_limit = new; |
4cd4601d | 978 | tr.b = b; |
89b831ef | 979 | |
a6b6a14e | 980 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef | 981 | |
9319cec8 | 982 | return size; |
89b831ef JS |
983 | } |
984 | ||
4cd4601d MT |
985 | static ssize_t show_error_count(struct threshold_block *b, char *buf) |
986 | { | |
2c9c42fa BP |
987 | u32 lo, hi; |
988 | ||
989 | rdmsr_on_cpu(b->cpu, b->address, &lo, &hi); | |
a6b6a14e | 990 | |
2c9c42fa BP |
991 | return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - |
992 | (THRESHOLD_MAX - b->threshold_limit))); | |
89b831ef JS |
993 | } |
994 | ||
6e927361 BP |
995 | static struct threshold_attr error_count = { |
996 | .attr = {.name = __stringify(error_count), .mode = 0444 }, | |
997 | .show = show_error_count, | |
998 | }; | |
89b831ef | 999 | |
34fa1967 HS |
1000 | #define RW_ATTR(val) \ |
1001 | static struct threshold_attr val = { \ | |
1002 | .attr = {.name = __stringify(val), .mode = 0644 }, \ | |
1003 | .show = show_## val, \ | |
1004 | .store = store_## val, \ | |
89b831ef JS |
1005 | }; |
1006 | ||
2903ee85 JS |
1007 | RW_ATTR(interrupt_enable); |
1008 | RW_ATTR(threshold_limit); | |
89b831ef JS |
1009 | |
1010 | static struct attribute *default_attrs[] = { | |
89b831ef JS |
1011 | &threshold_limit.attr, |
1012 | &error_count.attr, | |
d26ecc48 BP |
1013 | NULL, /* possibly interrupt_enable if supported, see below */ |
1014 | NULL, | |
89b831ef JS |
1015 | }; |
1016 | ||
1cb2a8e1 IM |
1017 | #define to_block(k) container_of(k, struct threshold_block, kobj) |
1018 | #define to_attr(a) container_of(a, struct threshold_attr, attr) | |
89b831ef JS |
1019 | |
1020 | static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) | |
1021 | { | |
95268664 | 1022 | struct threshold_block *b = to_block(kobj); |
89b831ef JS |
1023 | struct threshold_attr *a = to_attr(attr); |
1024 | ssize_t ret; | |
1cb2a8e1 | 1025 | |
89b831ef | 1026 | ret = a->show ? a->show(b, buf) : -EIO; |
1cb2a8e1 | 1027 | |
89b831ef JS |
1028 | return ret; |
1029 | } | |
1030 | ||
1031 | static ssize_t store(struct kobject *kobj, struct attribute *attr, | |
1032 | const char *buf, size_t count) | |
1033 | { | |
95268664 | 1034 | struct threshold_block *b = to_block(kobj); |
89b831ef JS |
1035 | struct threshold_attr *a = to_attr(attr); |
1036 | ssize_t ret; | |
1cb2a8e1 | 1037 | |
89b831ef | 1038 | ret = a->store ? a->store(b, buf, count) : -EIO; |
1cb2a8e1 | 1039 | |
89b831ef JS |
1040 | return ret; |
1041 | } | |
1042 | ||
52cf25d0 | 1043 | static const struct sysfs_ops threshold_ops = { |
1cb2a8e1 IM |
1044 | .show = show, |
1045 | .store = store, | |
89b831ef JS |
1046 | }; |
1047 | ||
1048 | static struct kobj_type threshold_ktype = { | |
1cb2a8e1 IM |
1049 | .sysfs_ops = &threshold_ops, |
1050 | .default_attrs = default_attrs, | |
89b831ef JS |
1051 | }; |
1052 | ||
87a6d409 YG |
1053 | static const char *get_name(unsigned int bank, struct threshold_block *b) |
1054 | { | |
1055 | unsigned int bank_type; | |
1056 | ||
1057 | if (!mce_flags.smca) { | |
1058 | if (b && bank == 4) | |
1059 | return bank4_names(b); | |
1060 | ||
1061 | return th_names[bank]; | |
1062 | } | |
1063 | ||
1ce9cd7f | 1064 | if (!smca_banks[bank].hwid) |
87a6d409 YG |
1065 | return NULL; |
1066 | ||
1ce9cd7f | 1067 | bank_type = smca_banks[bank].hwid->bank_type; |
87a6d409 YG |
1068 | |
1069 | if (b && bank_type == SMCA_UMC) { | |
1070 | if (b->block < ARRAY_SIZE(smca_umc_block_names)) | |
1071 | return smca_umc_block_names[b->block]; | |
1072 | return NULL; | |
1073 | } | |
1074 | ||
0b737a9c YG |
1075 | if (smca_banks[bank].hwid->count == 1) |
1076 | return smca_get_name(bank_type); | |
1077 | ||
87a6d409 | 1078 | snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN, |
c09a8c40 | 1079 | "%s_%x", smca_get_name(bank_type), |
0b737a9c | 1080 | smca_banks[bank].sysfs_id); |
87a6d409 YG |
1081 | return buf_mcatype; |
1082 | } | |
1083 | ||
148f9bb8 PG |
1084 | static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank, |
1085 | unsigned int block, u32 address) | |
95268664 | 1086 | { |
95268664 | 1087 | struct threshold_block *b = NULL; |
1cb2a8e1 IM |
1088 | u32 low, high; |
1089 | int err; | |
95268664 | 1090 | |
bafcdd3b | 1091 | if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS)) |
95268664 JS |
1092 | return 0; |
1093 | ||
a6b6a14e | 1094 | if (rdmsr_safe_on_cpu(cpu, address, &low, &high)) |
24ce0e96 | 1095 | return 0; |
95268664 JS |
1096 | |
1097 | if (!(high & MASK_VALID_HI)) { | |
1098 | if (block) | |
1099 | goto recurse; | |
1100 | else | |
1101 | return 0; | |
1102 | } | |
1103 | ||
24ce0e96 JB |
1104 | if (!(high & MASK_CNTP_HI) || |
1105 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
1106 | goto recurse; |
1107 | ||
1108 | b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL); | |
1109 | if (!b) | |
1110 | return -ENOMEM; | |
95268664 | 1111 | |
1cb2a8e1 IM |
1112 | b->block = block; |
1113 | b->bank = bank; | |
1114 | b->cpu = cpu; | |
1115 | b->address = address; | |
1116 | b->interrupt_enable = 0; | |
f227d430 | 1117 | b->interrupt_capable = lvt_interrupt_supported(bank, high); |
1cb2a8e1 | 1118 | b->threshold_limit = THRESHOLD_MAX; |
95268664 | 1119 | |
d79f931f | 1120 | if (b->interrupt_capable) { |
d26ecc48 | 1121 | threshold_ktype.default_attrs[2] = &interrupt_enable.attr; |
d79f931f AG |
1122 | b->interrupt_enable = 1; |
1123 | } else { | |
d26ecc48 | 1124 | threshold_ktype.default_attrs[2] = NULL; |
d79f931f | 1125 | } |
d26ecc48 | 1126 | |
95268664 JS |
1127 | INIT_LIST_HEAD(&b->miscj); |
1128 | ||
1cb2a8e1 | 1129 | if (per_cpu(threshold_banks, cpu)[bank]->blocks) { |
95268664 JS |
1130 | list_add(&b->miscj, |
1131 | &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj); | |
1cb2a8e1 | 1132 | } else { |
95268664 | 1133 | per_cpu(threshold_banks, cpu)[bank]->blocks = b; |
1cb2a8e1 | 1134 | } |
95268664 | 1135 | |
542eb75a GKH |
1136 | err = kobject_init_and_add(&b->kobj, &threshold_ktype, |
1137 | per_cpu(threshold_banks, cpu)[bank]->kobj, | |
87a6d409 | 1138 | get_name(bank, b)); |
95268664 JS |
1139 | if (err) |
1140 | goto out_free; | |
1141 | recurse: | |
cfee4f6f | 1142 | address = get_block_address(cpu, address, low, high, bank, ++block); |
8dd1e17a AG |
1143 | if (!address) |
1144 | return 0; | |
95268664 | 1145 | |
8dd1e17a | 1146 | err = allocate_threshold_blocks(cpu, bank, block, address); |
95268664 JS |
1147 | if (err) |
1148 | goto out_free; | |
1149 | ||
213eca7f GKH |
1150 | if (b) |
1151 | kobject_uevent(&b->kobj, KOBJ_ADD); | |
542eb75a | 1152 | |
95268664 JS |
1153 | return err; |
1154 | ||
1155 | out_free: | |
1156 | if (b) { | |
38a382ae | 1157 | kobject_put(&b->kobj); |
d9a5ac9e | 1158 | list_del(&b->miscj); |
95268664 JS |
1159 | kfree(b); |
1160 | } | |
1161 | return err; | |
1162 | } | |
1163 | ||
148f9bb8 | 1164 | static int __threshold_add_blocks(struct threshold_bank *b) |
019f34fc BP |
1165 | { |
1166 | struct list_head *head = &b->blocks->miscj; | |
1167 | struct threshold_block *pos = NULL; | |
1168 | struct threshold_block *tmp = NULL; | |
1169 | int err = 0; | |
1170 | ||
1171 | err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name); | |
1172 | if (err) | |
1173 | return err; | |
1174 | ||
1175 | list_for_each_entry_safe(pos, tmp, head, miscj) { | |
1176 | ||
1177 | err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name); | |
1178 | if (err) { | |
1179 | list_for_each_entry_safe_reverse(pos, tmp, head, miscj) | |
1180 | kobject_del(&pos->kobj); | |
1181 | ||
1182 | return err; | |
1183 | } | |
1184 | } | |
1185 | return err; | |
1186 | } | |
1187 | ||
148f9bb8 | 1188 | static int threshold_create_bank(unsigned int cpu, unsigned int bank) |
89b831ef | 1189 | { |
d6126ef5 | 1190 | struct device *dev = per_cpu(mce_device, cpu); |
019f34fc | 1191 | struct amd_northbridge *nb = NULL; |
92e26e2a | 1192 | struct threshold_bank *b = NULL; |
87a6d409 | 1193 | const char *name = get_name(bank, NULL); |
92e26e2a | 1194 | int err = 0; |
95268664 | 1195 | |
0dad3a30 TG |
1196 | if (!dev) |
1197 | return -ENODEV; | |
1198 | ||
c76e8164 | 1199 | if (is_shared_bank(bank)) { |
019f34fc | 1200 | nb = node_to_amd_nb(amd_get_nb_id(cpu)); |
019f34fc BP |
1201 | |
1202 | /* threshold descriptor already initialized on this node? */ | |
21c5e50e | 1203 | if (nb && nb->bank4) { |
019f34fc BP |
1204 | /* yes, use it */ |
1205 | b = nb->bank4; | |
1206 | err = kobject_add(b->kobj, &dev->kobj, name); | |
1207 | if (err) | |
1208 | goto out; | |
1209 | ||
1210 | per_cpu(threshold_banks, cpu)[bank] = b; | |
473e90b2 | 1211 | refcount_inc(&b->cpus); |
019f34fc BP |
1212 | |
1213 | err = __threshold_add_blocks(b); | |
1214 | ||
1215 | goto out; | |
1216 | } | |
1217 | } | |
1218 | ||
95268664 | 1219 | b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL); |
89b831ef JS |
1220 | if (!b) { |
1221 | err = -ENOMEM; | |
1222 | goto out; | |
1223 | } | |
89b831ef | 1224 | |
e032d807 | 1225 | b->kobj = kobject_create_and_add(name, &dev->kobj); |
92e26e2a BP |
1226 | if (!b->kobj) { |
1227 | err = -EINVAL; | |
a521cf20 | 1228 | goto out_free; |
92e26e2a | 1229 | } |
95268664 | 1230 | |
89b831ef | 1231 | per_cpu(threshold_banks, cpu)[bank] = b; |
95268664 | 1232 | |
c76e8164 | 1233 | if (is_shared_bank(bank)) { |
473e90b2 | 1234 | refcount_set(&b->cpus, 1); |
019f34fc BP |
1235 | |
1236 | /* nb is already initialized, see above */ | |
21c5e50e DB |
1237 | if (nb) { |
1238 | WARN_ON(nb->bank4); | |
1239 | nb->bank4 = b; | |
1240 | } | |
019f34fc BP |
1241 | } |
1242 | ||
74ab0e7a | 1243 | err = allocate_threshold_blocks(cpu, bank, 0, msr_ops.misc(bank)); |
92e26e2a BP |
1244 | if (!err) |
1245 | goto out; | |
95268664 | 1246 | |
019f34fc | 1247 | out_free: |
95268664 | 1248 | kfree(b); |
019f34fc BP |
1249 | |
1250 | out: | |
89b831ef JS |
1251 | return err; |
1252 | } | |
1253 | ||
be6b5a35 | 1254 | static void deallocate_threshold_block(unsigned int cpu, |
95268664 JS |
1255 | unsigned int bank) |
1256 | { | |
1257 | struct threshold_block *pos = NULL; | |
1258 | struct threshold_block *tmp = NULL; | |
1259 | struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank]; | |
1260 | ||
1261 | if (!head) | |
1262 | return; | |
1263 | ||
1264 | list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) { | |
38a382ae | 1265 | kobject_put(&pos->kobj); |
95268664 JS |
1266 | list_del(&pos->miscj); |
1267 | kfree(pos); | |
1268 | } | |
1269 | ||
1270 | kfree(per_cpu(threshold_banks, cpu)[bank]->blocks); | |
1271 | per_cpu(threshold_banks, cpu)[bank]->blocks = NULL; | |
1272 | } | |
1273 | ||
019f34fc BP |
1274 | static void __threshold_remove_blocks(struct threshold_bank *b) |
1275 | { | |
1276 | struct threshold_block *pos = NULL; | |
1277 | struct threshold_block *tmp = NULL; | |
1278 | ||
1279 | kobject_del(b->kobj); | |
1280 | ||
1281 | list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj) | |
1282 | kobject_del(&pos->kobj); | |
1283 | } | |
1284 | ||
be6b5a35 | 1285 | static void threshold_remove_bank(unsigned int cpu, int bank) |
89b831ef | 1286 | { |
019f34fc | 1287 | struct amd_northbridge *nb; |
89b831ef | 1288 | struct threshold_bank *b; |
89b831ef JS |
1289 | |
1290 | b = per_cpu(threshold_banks, cpu)[bank]; | |
1291 | if (!b) | |
1292 | return; | |
019f34fc | 1293 | |
95268664 JS |
1294 | if (!b->blocks) |
1295 | goto free_out; | |
1296 | ||
c76e8164 | 1297 | if (is_shared_bank(bank)) { |
473e90b2 | 1298 | if (!refcount_dec_and_test(&b->cpus)) { |
019f34fc BP |
1299 | __threshold_remove_blocks(b); |
1300 | per_cpu(threshold_banks, cpu)[bank] = NULL; | |
1301 | return; | |
1302 | } else { | |
1303 | /* | |
1304 | * the last CPU on this node using the shared bank is | |
1305 | * going away, remove that bank now. | |
1306 | */ | |
1307 | nb = node_to_amd_nb(amd_get_nb_id(cpu)); | |
1308 | nb->bank4 = NULL; | |
1309 | } | |
1310 | } | |
1311 | ||
95268664 JS |
1312 | deallocate_threshold_block(cpu, bank); |
1313 | ||
1314 | free_out: | |
8735728e | 1315 | kobject_del(b->kobj); |
38a382ae | 1316 | kobject_put(b->kobj); |
95268664 JS |
1317 | kfree(b); |
1318 | per_cpu(threshold_banks, cpu)[bank] = NULL; | |
89b831ef JS |
1319 | } |
1320 | ||
4d7b02d5 | 1321 | int mce_threshold_remove_device(unsigned int cpu) |
89b831ef | 1322 | { |
2903ee85 | 1323 | unsigned int bank; |
89b831ef | 1324 | |
4d7b02d5 SAS |
1325 | if (!thresholding_en) |
1326 | return 0; | |
1327 | ||
bafcdd3b | 1328 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
5a96f4a5 | 1329 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
89b831ef JS |
1330 | continue; |
1331 | threshold_remove_bank(cpu, bank); | |
1332 | } | |
bafcdd3b | 1333 | kfree(per_cpu(threshold_banks, cpu)); |
ec553abb | 1334 | per_cpu(threshold_banks, cpu) = NULL; |
4d7b02d5 | 1335 | return 0; |
89b831ef JS |
1336 | } |
1337 | ||
09436372 | 1338 | /* create dir/files for all valid threshold banks */ |
4d7b02d5 | 1339 | int mce_threshold_create_device(unsigned int cpu) |
89b831ef | 1340 | { |
09436372 SAS |
1341 | unsigned int bank; |
1342 | struct threshold_bank **bp; | |
1343 | int err = 0; | |
1344 | ||
4d7b02d5 SAS |
1345 | if (!thresholding_en) |
1346 | return 0; | |
1347 | ||
7f34b935 SAS |
1348 | bp = per_cpu(threshold_banks, cpu); |
1349 | if (bp) | |
1350 | return 0; | |
1351 | ||
09436372 SAS |
1352 | bp = kzalloc(sizeof(struct threshold_bank *) * mca_cfg.banks, |
1353 | GFP_KERNEL); | |
1354 | if (!bp) | |
1355 | return -ENOMEM; | |
1356 | ||
1357 | per_cpu(threshold_banks, cpu) = bp; | |
1358 | ||
1359 | for (bank = 0; bank < mca_cfg.banks; ++bank) { | |
1360 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) | |
1361 | continue; | |
1362 | err = threshold_create_bank(cpu, bank); | |
1363 | if (err) | |
ec553abb | 1364 | goto err; |
89b831ef | 1365 | } |
ec553abb SAS |
1366 | return err; |
1367 | err: | |
4d7b02d5 | 1368 | mce_threshold_remove_device(cpu); |
09436372 | 1369 | return err; |
89b831ef JS |
1370 | } |
1371 | ||
89b831ef JS |
1372 | static __init int threshold_init_device(void) |
1373 | { | |
2903ee85 | 1374 | unsigned lcpu = 0; |
89b831ef | 1375 | |
254fe9c7 BP |
1376 | if (mce_threshold_vector == amd_threshold_interrupt) |
1377 | thresholding_en = true; | |
1378 | ||
89b831ef JS |
1379 | /* to hit CPUs online before the notifier is up */ |
1380 | for_each_online_cpu(lcpu) { | |
4d7b02d5 | 1381 | int err = mce_threshold_create_device(lcpu); |
1cb2a8e1 | 1382 | |
89b831ef | 1383 | if (err) |
fff2e89f | 1384 | return err; |
89b831ef | 1385 | } |
1cb2a8e1 | 1386 | |
fff2e89f | 1387 | return 0; |
89b831ef | 1388 | } |
a8fccdb0 LJ |
1389 | /* |
1390 | * there are 3 funcs which need to be _initcalled in a logic sequence: | |
1391 | * 1. xen_late_init_mcelog | |
1392 | * 2. mcheck_init_device | |
1393 | * 3. threshold_init_device | |
1394 | * | |
1395 | * xen_late_init_mcelog must register xen_mce_chrdev_device before | |
1396 | * native mce_chrdev_device registration if running under xen platform; | |
1397 | * | |
1398 | * mcheck_init_device should be inited before threshold_init_device to | |
1399 | * initialize mce_device, otherwise a NULL ptr dereference will cause panic. | |
1400 | * | |
1401 | * so we use following _initcalls | |
1402 | * 1. device_initcall(xen_late_init_mcelog); | |
1403 | * 2. device_initcall_sync(mcheck_init_device); | |
1404 | * 3. late_initcall(threshold_init_device); | |
1405 | * | |
1406 | * when running under xen, the initcall order is 1,2,3; | |
1407 | * on baremetal, we skip 1 and we do only 2 and 3. | |
1408 | */ | |
1409 | late_initcall(threshold_init_device); |