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Commit | Line | Data |
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89b831ef | 1 | /* |
3490c0e4 | 2 | * (c) 2005-2015 Advanced Micro Devices, Inc. |
89b831ef JS |
3 | * Your use of this code is subject to the terms and conditions of the |
4 | * GNU general public license version 2. See "COPYING" or | |
5 | * http://www.gnu.org/licenses/gpl.html | |
6 | * | |
7 | * Written by Jacob Shin - AMD, Inc. | |
e6d41e8c | 8 | * Maintained by: Borislav Petkov <bp@alien8.de> |
89b831ef | 9 | * |
3490c0e4 | 10 | * All MC4_MISCi registers are shared between cores on a node. |
89b831ef | 11 | */ |
89b831ef | 12 | #include <linux/interrupt.h> |
89b831ef | 13 | #include <linux/notifier.h> |
1cb2a8e1 | 14 | #include <linux/kobject.h> |
34fa1967 | 15 | #include <linux/percpu.h> |
1cb2a8e1 IM |
16 | #include <linux/errno.h> |
17 | #include <linux/sched.h> | |
89b831ef | 18 | #include <linux/sysfs.h> |
5a0e3ad6 | 19 | #include <linux/slab.h> |
1cb2a8e1 IM |
20 | #include <linux/init.h> |
21 | #include <linux/cpu.h> | |
22 | #include <linux/smp.h> | |
23 | ||
019f34fc | 24 | #include <asm/amd_nb.h> |
89b831ef | 25 | #include <asm/apic.h> |
1cb2a8e1 | 26 | #include <asm/idle.h> |
89b831ef JS |
27 | #include <asm/mce.h> |
28 | #include <asm/msr.h> | |
24fd78a8 | 29 | #include <asm/trace/irq_vectors.h> |
89b831ef | 30 | |
2903ee85 JS |
31 | #define NR_BLOCKS 9 |
32 | #define THRESHOLD_MAX 0xFFF | |
33 | #define INT_TYPE_APIC 0x00020000 | |
34 | #define MASK_VALID_HI 0x80000000 | |
24ce0e96 JB |
35 | #define MASK_CNTP_HI 0x40000000 |
36 | #define MASK_LOCKED_HI 0x20000000 | |
2903ee85 JS |
37 | #define MASK_LVTOFF_HI 0x00F00000 |
38 | #define MASK_COUNT_EN_HI 0x00080000 | |
39 | #define MASK_INT_TYPE_HI 0x00060000 | |
40 | #define MASK_OVERFLOW_HI 0x00010000 | |
89b831ef | 41 | #define MASK_ERR_COUNT_HI 0x00000FFF |
95268664 JS |
42 | #define MASK_BLKPTR_LO 0xFF000000 |
43 | #define MCG_XBLK_ADDR 0xC0000400 | |
89b831ef | 44 | |
24fd78a8 AG |
45 | /* Deferred error settings */ |
46 | #define MSR_CU_DEF_ERR 0xC0000410 | |
47 | #define MASK_DEF_LVTOFF 0x000000F0 | |
48 | #define MASK_DEF_INT_TYPE 0x00000006 | |
49 | #define DEF_LVT_OFF 0x2 | |
50 | #define DEF_INT_TYPE_APIC 0x2 | |
51 | ||
336d335a BP |
52 | static const char * const th_names[] = { |
53 | "load_store", | |
54 | "insn_fetch", | |
55 | "combined_unit", | |
56 | "", | |
57 | "northbridge", | |
58 | "execution_unit", | |
59 | }; | |
60 | ||
bafcdd3b | 61 | static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks); |
89b831ef JS |
62 | static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */ |
63 | ||
b2762686 | 64 | static void amd_threshold_interrupt(void); |
24fd78a8 AG |
65 | static void amd_deferred_error_interrupt(void); |
66 | ||
67 | static void default_deferred_error_interrupt(void) | |
68 | { | |
69 | pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR); | |
70 | } | |
71 | void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; | |
b2762686 | 72 | |
89b831ef JS |
73 | /* |
74 | * CPU Initialization | |
75 | */ | |
76 | ||
4cd4601d | 77 | struct thresh_restart { |
1cb2a8e1 IM |
78 | struct threshold_block *b; |
79 | int reset; | |
9c37c9d8 RR |
80 | int set_lvt_off; |
81 | int lvt_off; | |
1cb2a8e1 | 82 | u16 old_limit; |
4cd4601d MT |
83 | }; |
84 | ||
c76e8164 BO |
85 | static inline bool is_shared_bank(int bank) |
86 | { | |
284b965c AG |
87 | /* |
88 | * Scalable MCA provides for only one core to have access to the MSRs of | |
89 | * a shared bank. | |
90 | */ | |
91 | if (mce_flags.smca) | |
92 | return false; | |
93 | ||
c76e8164 BO |
94 | /* Bank 4 is for northbridge reporting and is thus shared */ |
95 | return (bank == 4); | |
96 | } | |
97 | ||
2cd4c303 | 98 | static const char *bank4_names(const struct threshold_block *b) |
336d335a BP |
99 | { |
100 | switch (b->address) { | |
101 | /* MSR4_MISC0 */ | |
102 | case 0x00000413: | |
103 | return "dram"; | |
104 | ||
105 | case 0xc0000408: | |
106 | return "ht_links"; | |
107 | ||
108 | case 0xc0000409: | |
109 | return "l3_cache"; | |
110 | ||
111 | default: | |
112 | WARN(1, "Funny MSR: 0x%08x\n", b->address); | |
113 | return ""; | |
114 | } | |
115 | }; | |
116 | ||
117 | ||
f227d430 BP |
118 | static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) |
119 | { | |
120 | /* | |
121 | * bank 4 supports APIC LVT interrupts implicitly since forever. | |
122 | */ | |
123 | if (bank == 4) | |
124 | return true; | |
125 | ||
126 | /* | |
127 | * IntP: interrupt present; if this bit is set, the thresholding | |
128 | * bank can generate APIC LVT interrupts | |
129 | */ | |
130 | return msr_high_bits & BIT(28); | |
131 | } | |
132 | ||
bbaff08d RR |
133 | static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) |
134 | { | |
135 | int msr = (hi & MASK_LVTOFF_HI) >> 20; | |
136 | ||
137 | if (apic < 0) { | |
138 | pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " | |
139 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, | |
140 | b->bank, b->block, b->address, hi, lo); | |
141 | return 0; | |
142 | } | |
143 | ||
144 | if (apic != msr) { | |
145 | pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " | |
146 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n", | |
147 | b->cpu, apic, b->bank, b->block, b->address, hi, lo); | |
148 | return 0; | |
149 | } | |
150 | ||
151 | return 1; | |
152 | }; | |
153 | ||
f227d430 BP |
154 | /* |
155 | * Called via smp_call_function_single(), must be called with correct | |
156 | * cpu affinity. | |
157 | */ | |
a6b6a14e | 158 | static void threshold_restart_bank(void *_tr) |
89b831ef | 159 | { |
4cd4601d | 160 | struct thresh_restart *tr = _tr; |
7203a049 | 161 | u32 hi, lo; |
89b831ef | 162 | |
7203a049 | 163 | rdmsr(tr->b->address, lo, hi); |
89b831ef | 164 | |
7203a049 | 165 | if (tr->b->threshold_limit < (hi & THRESHOLD_MAX)) |
4cd4601d | 166 | tr->reset = 1; /* limit cannot be lower than err count */ |
89b831ef | 167 | |
4cd4601d | 168 | if (tr->reset) { /* reset err count and overflow bit */ |
7203a049 RR |
169 | hi = |
170 | (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) | | |
4cd4601d MT |
171 | (THRESHOLD_MAX - tr->b->threshold_limit); |
172 | } else if (tr->old_limit) { /* change limit w/o reset */ | |
7203a049 | 173 | int new_count = (hi & THRESHOLD_MAX) + |
4cd4601d | 174 | (tr->old_limit - tr->b->threshold_limit); |
1cb2a8e1 | 175 | |
7203a049 | 176 | hi = (hi & ~MASK_ERR_COUNT_HI) | |
89b831ef JS |
177 | (new_count & THRESHOLD_MAX); |
178 | } | |
179 | ||
f227d430 BP |
180 | /* clear IntType */ |
181 | hi &= ~MASK_INT_TYPE_HI; | |
182 | ||
183 | if (!tr->b->interrupt_capable) | |
184 | goto done; | |
185 | ||
9c37c9d8 | 186 | if (tr->set_lvt_off) { |
bbaff08d RR |
187 | if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) { |
188 | /* set new lvt offset */ | |
189 | hi &= ~MASK_LVTOFF_HI; | |
190 | hi |= tr->lvt_off << 20; | |
191 | } | |
9c37c9d8 RR |
192 | } |
193 | ||
f227d430 BP |
194 | if (tr->b->interrupt_enable) |
195 | hi |= INT_TYPE_APIC; | |
196 | ||
197 | done: | |
89b831ef | 198 | |
7203a049 RR |
199 | hi |= MASK_COUNT_EN_HI; |
200 | wrmsr(tr->b->address, lo, hi); | |
89b831ef JS |
201 | } |
202 | ||
9c37c9d8 RR |
203 | static void mce_threshold_block_init(struct threshold_block *b, int offset) |
204 | { | |
205 | struct thresh_restart tr = { | |
206 | .b = b, | |
207 | .set_lvt_off = 1, | |
208 | .lvt_off = offset, | |
209 | }; | |
210 | ||
211 | b->threshold_limit = THRESHOLD_MAX; | |
212 | threshold_restart_bank(&tr); | |
213 | }; | |
214 | ||
868c00bb | 215 | static int setup_APIC_mce_threshold(int reserved, int new) |
bbaff08d RR |
216 | { |
217 | if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR, | |
218 | APIC_EILVT_MSG_FIX, 0)) | |
219 | return new; | |
220 | ||
221 | return reserved; | |
222 | } | |
223 | ||
24fd78a8 AG |
224 | static int setup_APIC_deferred_error(int reserved, int new) |
225 | { | |
226 | if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR, | |
227 | APIC_EILVT_MSG_FIX, 0)) | |
228 | return new; | |
229 | ||
230 | return reserved; | |
231 | } | |
232 | ||
233 | static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) | |
234 | { | |
235 | u32 low = 0, high = 0; | |
236 | int def_offset = -1, def_new; | |
237 | ||
238 | if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) | |
239 | return; | |
240 | ||
241 | def_new = (low & MASK_DEF_LVTOFF) >> 4; | |
242 | if (!(low & MASK_DEF_LVTOFF)) { | |
243 | pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n"); | |
244 | def_new = DEF_LVT_OFF; | |
245 | low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4); | |
246 | } | |
247 | ||
248 | def_offset = setup_APIC_deferred_error(def_offset, def_new); | |
249 | if ((def_offset == def_new) && | |
250 | (deferred_error_int_vector != amd_deferred_error_interrupt)) | |
251 | deferred_error_int_vector = amd_deferred_error_interrupt; | |
252 | ||
253 | low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; | |
254 | wrmsr(MSR_CU_DEF_ERR, low, high); | |
255 | } | |
256 | ||
95268664 | 257 | /* cpu init entry point, called from mce.c with preempt off */ |
cc3ca220 | 258 | void mce_amd_feature_init(struct cpuinfo_x86 *c) |
89b831ef | 259 | { |
9c37c9d8 | 260 | struct threshold_block b; |
89b831ef | 261 | unsigned int cpu = smp_processor_id(); |
95268664 | 262 | u32 low = 0, high = 0, address = 0; |
1cb2a8e1 | 263 | unsigned int bank, block; |
8dcf32ea | 264 | int offset = -1, new; |
89b831ef | 265 | |
bafcdd3b | 266 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
95268664 JS |
267 | for (block = 0; block < NR_BLOCKS; ++block) { |
268 | if (block == 0) | |
4b737d78 | 269 | address = MSR_IA32_MCx_MISC(bank); |
24ce0e96 JB |
270 | else if (block == 1) { |
271 | address = (low & MASK_BLKPTR_LO) >> 21; | |
272 | if (!address) | |
273 | break; | |
6dcbfe4f | 274 | |
24ce0e96 | 275 | address += MCG_XBLK_ADDR; |
1cb2a8e1 | 276 | } else |
95268664 JS |
277 | ++address; |
278 | ||
279 | if (rdmsr_safe(address, &low, &high)) | |
24ce0e96 | 280 | break; |
95268664 | 281 | |
6dcbfe4f BP |
282 | if (!(high & MASK_VALID_HI)) |
283 | continue; | |
95268664 | 284 | |
24ce0e96 JB |
285 | if (!(high & MASK_CNTP_HI) || |
286 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
287 | continue; |
288 | ||
289 | if (!block) | |
290 | per_cpu(bank_map, cpu) |= (1 << bank); | |
141168c3 | 291 | |
9c37c9d8 | 292 | memset(&b, 0, sizeof(b)); |
f227d430 BP |
293 | b.cpu = cpu; |
294 | b.bank = bank; | |
295 | b.block = block; | |
296 | b.address = address; | |
297 | b.interrupt_capable = lvt_interrupt_supported(bank, high); | |
298 | ||
8dcf32ea CY |
299 | if (!b.interrupt_capable) |
300 | goto init; | |
b2762686 | 301 | |
d79f931f | 302 | b.interrupt_enable = 1; |
8dcf32ea | 303 | new = (high & MASK_LVTOFF_HI) >> 20; |
868c00bb | 304 | offset = setup_APIC_mce_threshold(offset, new); |
69b95758 | 305 | |
8dcf32ea CY |
306 | if ((offset == new) && |
307 | (mce_threshold_vector != amd_threshold_interrupt)) | |
69b95758 | 308 | mce_threshold_vector = amd_threshold_interrupt; |
8dcf32ea CY |
309 | |
310 | init: | |
311 | mce_threshold_block_init(&b, offset); | |
95268664 | 312 | } |
89b831ef | 313 | } |
24fd78a8 AG |
314 | |
315 | if (mce_flags.succor) | |
316 | deferred_error_interrupt_enable(c); | |
89b831ef JS |
317 | } |
318 | ||
afdf344e AG |
319 | static void __log_error(unsigned int bank, bool threshold_err, u64 misc) |
320 | { | |
321 | struct mce m; | |
322 | u64 status; | |
323 | ||
324 | rdmsrl(MSR_IA32_MCx_STATUS(bank), status); | |
325 | if (!(status & MCI_STATUS_VAL)) | |
326 | return; | |
327 | ||
328 | mce_setup(&m); | |
329 | ||
330 | m.status = status; | |
331 | m.bank = bank; | |
6e6e746e | 332 | |
afdf344e AG |
333 | if (threshold_err) |
334 | m.misc = misc; | |
335 | ||
6e6e746e AG |
336 | if (m.status & MCI_STATUS_ADDRV) |
337 | rdmsrl(MSR_IA32_MCx_ADDR(bank), m.addr); | |
afdf344e | 338 | |
6e6e746e | 339 | mce_log(&m); |
afdf344e AG |
340 | wrmsrl(MSR_IA32_MCx_STATUS(bank), 0); |
341 | } | |
342 | ||
24fd78a8 AG |
343 | static inline void __smp_deferred_error_interrupt(void) |
344 | { | |
345 | inc_irq_stat(irq_deferred_error_count); | |
346 | deferred_error_int_vector(); | |
347 | } | |
348 | ||
349 | asmlinkage __visible void smp_deferred_error_interrupt(void) | |
350 | { | |
351 | entering_irq(); | |
352 | __smp_deferred_error_interrupt(); | |
353 | exiting_ack_irq(); | |
354 | } | |
355 | ||
356 | asmlinkage __visible void smp_trace_deferred_error_interrupt(void) | |
357 | { | |
358 | entering_irq(); | |
359 | trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR); | |
360 | __smp_deferred_error_interrupt(); | |
361 | trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR); | |
362 | exiting_ack_irq(); | |
363 | } | |
364 | ||
365 | /* APIC interrupt handler for deferred errors */ | |
366 | static void amd_deferred_error_interrupt(void) | |
367 | { | |
368 | u64 status; | |
369 | unsigned int bank; | |
370 | ||
371 | for (bank = 0; bank < mca_cfg.banks; ++bank) { | |
372 | rdmsrl(MSR_IA32_MCx_STATUS(bank), status); | |
373 | ||
374 | if (!(status & MCI_STATUS_VAL) || | |
375 | !(status & MCI_STATUS_DEFERRED)) | |
376 | continue; | |
377 | ||
378 | __log_error(bank, false, 0); | |
379 | break; | |
380 | } | |
381 | } | |
382 | ||
89b831ef JS |
383 | /* |
384 | * APIC Interrupt Handler | |
385 | */ | |
386 | ||
387 | /* | |
388 | * threshold interrupt handler will service THRESHOLD_APIC_VECTOR. | |
389 | * the interrupt goes off when error_count reaches threshold_limit. | |
390 | * the handler will simply log mcelog w/ software defined bank number. | |
391 | */ | |
afdf344e | 392 | |
b2762686 | 393 | static void amd_threshold_interrupt(void) |
89b831ef | 394 | { |
1cb2a8e1 | 395 | u32 low = 0, high = 0, address = 0; |
44612a3a | 396 | int cpu = smp_processor_id(); |
95268664 | 397 | unsigned int bank, block; |
89b831ef | 398 | |
89b831ef | 399 | /* assume first bank caused it */ |
bafcdd3b | 400 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
44612a3a | 401 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
24ce0e96 | 402 | continue; |
95268664 | 403 | for (block = 0; block < NR_BLOCKS; ++block) { |
1cb2a8e1 | 404 | if (block == 0) { |
4b737d78 | 405 | address = MSR_IA32_MCx_MISC(bank); |
1cb2a8e1 | 406 | } else if (block == 1) { |
24ce0e96 JB |
407 | address = (low & MASK_BLKPTR_LO) >> 21; |
408 | if (!address) | |
409 | break; | |
410 | address += MCG_XBLK_ADDR; | |
1cb2a8e1 | 411 | } else { |
95268664 | 412 | ++address; |
1cb2a8e1 | 413 | } |
95268664 JS |
414 | |
415 | if (rdmsr_safe(address, &low, &high)) | |
24ce0e96 | 416 | break; |
95268664 JS |
417 | |
418 | if (!(high & MASK_VALID_HI)) { | |
419 | if (block) | |
420 | continue; | |
421 | else | |
422 | break; | |
423 | } | |
424 | ||
24ce0e96 JB |
425 | if (!(high & MASK_CNTP_HI) || |
426 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
427 | continue; |
428 | ||
1cb2a8e1 IM |
429 | /* |
430 | * Log the machine check that caused the threshold | |
431 | * event. | |
432 | */ | |
44612a3a CY |
433 | if (high & MASK_OVERFLOW_HI) |
434 | goto log; | |
89b831ef JS |
435 | } |
436 | } | |
44612a3a CY |
437 | return; |
438 | ||
439 | log: | |
afdf344e | 440 | __log_error(bank, true, ((u64)high << 32) | low); |
89b831ef JS |
441 | } |
442 | ||
443 | /* | |
444 | * Sysfs Interface | |
445 | */ | |
446 | ||
89b831ef | 447 | struct threshold_attr { |
2903ee85 | 448 | struct attribute attr; |
1cb2a8e1 IM |
449 | ssize_t (*show) (struct threshold_block *, char *); |
450 | ssize_t (*store) (struct threshold_block *, const char *, size_t count); | |
89b831ef JS |
451 | }; |
452 | ||
1cb2a8e1 IM |
453 | #define SHOW_FIELDS(name) \ |
454 | static ssize_t show_ ## name(struct threshold_block *b, char *buf) \ | |
455 | { \ | |
18c20f37 | 456 | return sprintf(buf, "%lu\n", (unsigned long) b->name); \ |
2903ee85 | 457 | } |
89b831ef JS |
458 | SHOW_FIELDS(interrupt_enable) |
459 | SHOW_FIELDS(threshold_limit) | |
460 | ||
1cb2a8e1 | 461 | static ssize_t |
9319cec8 | 462 | store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size) |
89b831ef | 463 | { |
4cd4601d | 464 | struct thresh_restart tr; |
1cb2a8e1 | 465 | unsigned long new; |
1cb2a8e1 | 466 | |
f227d430 BP |
467 | if (!b->interrupt_capable) |
468 | return -EINVAL; | |
469 | ||
164109e3 | 470 | if (kstrtoul(buf, 0, &new) < 0) |
89b831ef | 471 | return -EINVAL; |
1cb2a8e1 | 472 | |
89b831ef JS |
473 | b->interrupt_enable = !!new; |
474 | ||
9c37c9d8 | 475 | memset(&tr, 0, sizeof(tr)); |
1cb2a8e1 | 476 | tr.b = b; |
1cb2a8e1 | 477 | |
a6b6a14e | 478 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef | 479 | |
9319cec8 | 480 | return size; |
89b831ef JS |
481 | } |
482 | ||
1cb2a8e1 | 483 | static ssize_t |
9319cec8 | 484 | store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) |
89b831ef | 485 | { |
4cd4601d | 486 | struct thresh_restart tr; |
1cb2a8e1 | 487 | unsigned long new; |
1cb2a8e1 | 488 | |
164109e3 | 489 | if (kstrtoul(buf, 0, &new) < 0) |
89b831ef | 490 | return -EINVAL; |
1cb2a8e1 | 491 | |
89b831ef JS |
492 | if (new > THRESHOLD_MAX) |
493 | new = THRESHOLD_MAX; | |
494 | if (new < 1) | |
495 | new = 1; | |
1cb2a8e1 | 496 | |
9c37c9d8 | 497 | memset(&tr, 0, sizeof(tr)); |
4cd4601d | 498 | tr.old_limit = b->threshold_limit; |
89b831ef | 499 | b->threshold_limit = new; |
4cd4601d | 500 | tr.b = b; |
89b831ef | 501 | |
a6b6a14e | 502 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef | 503 | |
9319cec8 | 504 | return size; |
89b831ef JS |
505 | } |
506 | ||
4cd4601d MT |
507 | static ssize_t show_error_count(struct threshold_block *b, char *buf) |
508 | { | |
2c9c42fa BP |
509 | u32 lo, hi; |
510 | ||
511 | rdmsr_on_cpu(b->cpu, b->address, &lo, &hi); | |
a6b6a14e | 512 | |
2c9c42fa BP |
513 | return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - |
514 | (THRESHOLD_MAX - b->threshold_limit))); | |
89b831ef JS |
515 | } |
516 | ||
6e927361 BP |
517 | static struct threshold_attr error_count = { |
518 | .attr = {.name = __stringify(error_count), .mode = 0444 }, | |
519 | .show = show_error_count, | |
520 | }; | |
89b831ef | 521 | |
34fa1967 HS |
522 | #define RW_ATTR(val) \ |
523 | static struct threshold_attr val = { \ | |
524 | .attr = {.name = __stringify(val), .mode = 0644 }, \ | |
525 | .show = show_## val, \ | |
526 | .store = store_## val, \ | |
89b831ef JS |
527 | }; |
528 | ||
2903ee85 JS |
529 | RW_ATTR(interrupt_enable); |
530 | RW_ATTR(threshold_limit); | |
89b831ef JS |
531 | |
532 | static struct attribute *default_attrs[] = { | |
89b831ef JS |
533 | &threshold_limit.attr, |
534 | &error_count.attr, | |
d26ecc48 BP |
535 | NULL, /* possibly interrupt_enable if supported, see below */ |
536 | NULL, | |
89b831ef JS |
537 | }; |
538 | ||
1cb2a8e1 IM |
539 | #define to_block(k) container_of(k, struct threshold_block, kobj) |
540 | #define to_attr(a) container_of(a, struct threshold_attr, attr) | |
89b831ef JS |
541 | |
542 | static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) | |
543 | { | |
95268664 | 544 | struct threshold_block *b = to_block(kobj); |
89b831ef JS |
545 | struct threshold_attr *a = to_attr(attr); |
546 | ssize_t ret; | |
1cb2a8e1 | 547 | |
89b831ef | 548 | ret = a->show ? a->show(b, buf) : -EIO; |
1cb2a8e1 | 549 | |
89b831ef JS |
550 | return ret; |
551 | } | |
552 | ||
553 | static ssize_t store(struct kobject *kobj, struct attribute *attr, | |
554 | const char *buf, size_t count) | |
555 | { | |
95268664 | 556 | struct threshold_block *b = to_block(kobj); |
89b831ef JS |
557 | struct threshold_attr *a = to_attr(attr); |
558 | ssize_t ret; | |
1cb2a8e1 | 559 | |
89b831ef | 560 | ret = a->store ? a->store(b, buf, count) : -EIO; |
1cb2a8e1 | 561 | |
89b831ef JS |
562 | return ret; |
563 | } | |
564 | ||
52cf25d0 | 565 | static const struct sysfs_ops threshold_ops = { |
1cb2a8e1 IM |
566 | .show = show, |
567 | .store = store, | |
89b831ef JS |
568 | }; |
569 | ||
570 | static struct kobj_type threshold_ktype = { | |
1cb2a8e1 IM |
571 | .sysfs_ops = &threshold_ops, |
572 | .default_attrs = default_attrs, | |
89b831ef JS |
573 | }; |
574 | ||
148f9bb8 PG |
575 | static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank, |
576 | unsigned int block, u32 address) | |
95268664 | 577 | { |
95268664 | 578 | struct threshold_block *b = NULL; |
1cb2a8e1 IM |
579 | u32 low, high; |
580 | int err; | |
95268664 | 581 | |
bafcdd3b | 582 | if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS)) |
95268664 JS |
583 | return 0; |
584 | ||
a6b6a14e | 585 | if (rdmsr_safe_on_cpu(cpu, address, &low, &high)) |
24ce0e96 | 586 | return 0; |
95268664 JS |
587 | |
588 | if (!(high & MASK_VALID_HI)) { | |
589 | if (block) | |
590 | goto recurse; | |
591 | else | |
592 | return 0; | |
593 | } | |
594 | ||
24ce0e96 JB |
595 | if (!(high & MASK_CNTP_HI) || |
596 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
597 | goto recurse; |
598 | ||
599 | b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL); | |
600 | if (!b) | |
601 | return -ENOMEM; | |
95268664 | 602 | |
1cb2a8e1 IM |
603 | b->block = block; |
604 | b->bank = bank; | |
605 | b->cpu = cpu; | |
606 | b->address = address; | |
607 | b->interrupt_enable = 0; | |
f227d430 | 608 | b->interrupt_capable = lvt_interrupt_supported(bank, high); |
1cb2a8e1 | 609 | b->threshold_limit = THRESHOLD_MAX; |
95268664 | 610 | |
d79f931f | 611 | if (b->interrupt_capable) { |
d26ecc48 | 612 | threshold_ktype.default_attrs[2] = &interrupt_enable.attr; |
d79f931f AG |
613 | b->interrupt_enable = 1; |
614 | } else { | |
d26ecc48 | 615 | threshold_ktype.default_attrs[2] = NULL; |
d79f931f | 616 | } |
d26ecc48 | 617 | |
95268664 JS |
618 | INIT_LIST_HEAD(&b->miscj); |
619 | ||
1cb2a8e1 | 620 | if (per_cpu(threshold_banks, cpu)[bank]->blocks) { |
95268664 JS |
621 | list_add(&b->miscj, |
622 | &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj); | |
1cb2a8e1 | 623 | } else { |
95268664 | 624 | per_cpu(threshold_banks, cpu)[bank]->blocks = b; |
1cb2a8e1 | 625 | } |
95268664 | 626 | |
542eb75a GKH |
627 | err = kobject_init_and_add(&b->kobj, &threshold_ktype, |
628 | per_cpu(threshold_banks, cpu)[bank]->kobj, | |
336d335a | 629 | (bank == 4 ? bank4_names(b) : th_names[bank])); |
95268664 JS |
630 | if (err) |
631 | goto out_free; | |
632 | recurse: | |
633 | if (!block) { | |
634 | address = (low & MASK_BLKPTR_LO) >> 21; | |
635 | if (!address) | |
636 | return 0; | |
637 | address += MCG_XBLK_ADDR; | |
1cb2a8e1 | 638 | } else { |
95268664 | 639 | ++address; |
1cb2a8e1 | 640 | } |
95268664 JS |
641 | |
642 | err = allocate_threshold_blocks(cpu, bank, ++block, address); | |
643 | if (err) | |
644 | goto out_free; | |
645 | ||
213eca7f GKH |
646 | if (b) |
647 | kobject_uevent(&b->kobj, KOBJ_ADD); | |
542eb75a | 648 | |
95268664 JS |
649 | return err; |
650 | ||
651 | out_free: | |
652 | if (b) { | |
38a382ae | 653 | kobject_put(&b->kobj); |
d9a5ac9e | 654 | list_del(&b->miscj); |
95268664 JS |
655 | kfree(b); |
656 | } | |
657 | return err; | |
658 | } | |
659 | ||
148f9bb8 | 660 | static int __threshold_add_blocks(struct threshold_bank *b) |
019f34fc BP |
661 | { |
662 | struct list_head *head = &b->blocks->miscj; | |
663 | struct threshold_block *pos = NULL; | |
664 | struct threshold_block *tmp = NULL; | |
665 | int err = 0; | |
666 | ||
667 | err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name); | |
668 | if (err) | |
669 | return err; | |
670 | ||
671 | list_for_each_entry_safe(pos, tmp, head, miscj) { | |
672 | ||
673 | err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name); | |
674 | if (err) { | |
675 | list_for_each_entry_safe_reverse(pos, tmp, head, miscj) | |
676 | kobject_del(&pos->kobj); | |
677 | ||
678 | return err; | |
679 | } | |
680 | } | |
681 | return err; | |
682 | } | |
683 | ||
148f9bb8 | 684 | static int threshold_create_bank(unsigned int cpu, unsigned int bank) |
89b831ef | 685 | { |
d6126ef5 | 686 | struct device *dev = per_cpu(mce_device, cpu); |
019f34fc | 687 | struct amd_northbridge *nb = NULL; |
92e26e2a | 688 | struct threshold_bank *b = NULL; |
336d335a | 689 | const char *name = th_names[bank]; |
92e26e2a | 690 | int err = 0; |
95268664 | 691 | |
c76e8164 | 692 | if (is_shared_bank(bank)) { |
019f34fc | 693 | nb = node_to_amd_nb(amd_get_nb_id(cpu)); |
019f34fc BP |
694 | |
695 | /* threshold descriptor already initialized on this node? */ | |
21c5e50e | 696 | if (nb && nb->bank4) { |
019f34fc BP |
697 | /* yes, use it */ |
698 | b = nb->bank4; | |
699 | err = kobject_add(b->kobj, &dev->kobj, name); | |
700 | if (err) | |
701 | goto out; | |
702 | ||
703 | per_cpu(threshold_banks, cpu)[bank] = b; | |
704 | atomic_inc(&b->cpus); | |
705 | ||
706 | err = __threshold_add_blocks(b); | |
707 | ||
708 | goto out; | |
709 | } | |
710 | } | |
711 | ||
95268664 | 712 | b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL); |
89b831ef JS |
713 | if (!b) { |
714 | err = -ENOMEM; | |
715 | goto out; | |
716 | } | |
89b831ef | 717 | |
e032d807 | 718 | b->kobj = kobject_create_and_add(name, &dev->kobj); |
92e26e2a BP |
719 | if (!b->kobj) { |
720 | err = -EINVAL; | |
a521cf20 | 721 | goto out_free; |
92e26e2a | 722 | } |
95268664 | 723 | |
89b831ef | 724 | per_cpu(threshold_banks, cpu)[bank] = b; |
95268664 | 725 | |
c76e8164 | 726 | if (is_shared_bank(bank)) { |
019f34fc BP |
727 | atomic_set(&b->cpus, 1); |
728 | ||
729 | /* nb is already initialized, see above */ | |
21c5e50e DB |
730 | if (nb) { |
731 | WARN_ON(nb->bank4); | |
732 | nb->bank4 = b; | |
733 | } | |
019f34fc BP |
734 | } |
735 | ||
4b737d78 | 736 | err = allocate_threshold_blocks(cpu, bank, 0, MSR_IA32_MCx_MISC(bank)); |
92e26e2a BP |
737 | if (!err) |
738 | goto out; | |
95268664 | 739 | |
019f34fc | 740 | out_free: |
95268664 | 741 | kfree(b); |
019f34fc BP |
742 | |
743 | out: | |
89b831ef JS |
744 | return err; |
745 | } | |
746 | ||
747 | /* create dir/files for all valid threshold banks */ | |
148f9bb8 | 748 | static int threshold_create_device(unsigned int cpu) |
89b831ef | 749 | { |
2903ee85 | 750 | unsigned int bank; |
bafcdd3b | 751 | struct threshold_bank **bp; |
89b831ef JS |
752 | int err = 0; |
753 | ||
bafcdd3b BO |
754 | bp = kzalloc(sizeof(struct threshold_bank *) * mca_cfg.banks, |
755 | GFP_KERNEL); | |
756 | if (!bp) | |
757 | return -ENOMEM; | |
758 | ||
759 | per_cpu(threshold_banks, cpu) = bp; | |
760 | ||
761 | for (bank = 0; bank < mca_cfg.banks; ++bank) { | |
5a96f4a5 | 762 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
89b831ef JS |
763 | continue; |
764 | err = threshold_create_bank(cpu, bank); | |
765 | if (err) | |
0a17941e | 766 | return err; |
89b831ef | 767 | } |
0a17941e | 768 | |
89b831ef JS |
769 | return err; |
770 | } | |
771 | ||
be6b5a35 | 772 | static void deallocate_threshold_block(unsigned int cpu, |
95268664 JS |
773 | unsigned int bank) |
774 | { | |
775 | struct threshold_block *pos = NULL; | |
776 | struct threshold_block *tmp = NULL; | |
777 | struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank]; | |
778 | ||
779 | if (!head) | |
780 | return; | |
781 | ||
782 | list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) { | |
38a382ae | 783 | kobject_put(&pos->kobj); |
95268664 JS |
784 | list_del(&pos->miscj); |
785 | kfree(pos); | |
786 | } | |
787 | ||
788 | kfree(per_cpu(threshold_banks, cpu)[bank]->blocks); | |
789 | per_cpu(threshold_banks, cpu)[bank]->blocks = NULL; | |
790 | } | |
791 | ||
019f34fc BP |
792 | static void __threshold_remove_blocks(struct threshold_bank *b) |
793 | { | |
794 | struct threshold_block *pos = NULL; | |
795 | struct threshold_block *tmp = NULL; | |
796 | ||
797 | kobject_del(b->kobj); | |
798 | ||
799 | list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj) | |
800 | kobject_del(&pos->kobj); | |
801 | } | |
802 | ||
be6b5a35 | 803 | static void threshold_remove_bank(unsigned int cpu, int bank) |
89b831ef | 804 | { |
019f34fc | 805 | struct amd_northbridge *nb; |
89b831ef | 806 | struct threshold_bank *b; |
89b831ef JS |
807 | |
808 | b = per_cpu(threshold_banks, cpu)[bank]; | |
809 | if (!b) | |
810 | return; | |
019f34fc | 811 | |
95268664 JS |
812 | if (!b->blocks) |
813 | goto free_out; | |
814 | ||
c76e8164 | 815 | if (is_shared_bank(bank)) { |
019f34fc BP |
816 | if (!atomic_dec_and_test(&b->cpus)) { |
817 | __threshold_remove_blocks(b); | |
818 | per_cpu(threshold_banks, cpu)[bank] = NULL; | |
819 | return; | |
820 | } else { | |
821 | /* | |
822 | * the last CPU on this node using the shared bank is | |
823 | * going away, remove that bank now. | |
824 | */ | |
825 | nb = node_to_amd_nb(amd_get_nb_id(cpu)); | |
826 | nb->bank4 = NULL; | |
827 | } | |
828 | } | |
829 | ||
95268664 JS |
830 | deallocate_threshold_block(cpu, bank); |
831 | ||
832 | free_out: | |
8735728e | 833 | kobject_del(b->kobj); |
38a382ae | 834 | kobject_put(b->kobj); |
95268664 JS |
835 | kfree(b); |
836 | per_cpu(threshold_banks, cpu)[bank] = NULL; | |
89b831ef JS |
837 | } |
838 | ||
be6b5a35 | 839 | static void threshold_remove_device(unsigned int cpu) |
89b831ef | 840 | { |
2903ee85 | 841 | unsigned int bank; |
89b831ef | 842 | |
bafcdd3b | 843 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
5a96f4a5 | 844 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
89b831ef JS |
845 | continue; |
846 | threshold_remove_bank(cpu, bank); | |
847 | } | |
bafcdd3b | 848 | kfree(per_cpu(threshold_banks, cpu)); |
89b831ef JS |
849 | } |
850 | ||
89b831ef | 851 | /* get notified when a cpu comes on/off */ |
148f9bb8 | 852 | static void |
1cb2a8e1 | 853 | amd_64_threshold_cpu_callback(unsigned long action, unsigned int cpu) |
89b831ef | 854 | { |
89b831ef JS |
855 | switch (action) { |
856 | case CPU_ONLINE: | |
8bb78442 | 857 | case CPU_ONLINE_FROZEN: |
89b831ef | 858 | threshold_create_device(cpu); |
89b831ef JS |
859 | break; |
860 | case CPU_DEAD: | |
8bb78442 | 861 | case CPU_DEAD_FROZEN: |
89b831ef JS |
862 | threshold_remove_device(cpu); |
863 | break; | |
864 | default: | |
865 | break; | |
866 | } | |
89b831ef JS |
867 | } |
868 | ||
89b831ef JS |
869 | static __init int threshold_init_device(void) |
870 | { | |
2903ee85 | 871 | unsigned lcpu = 0; |
89b831ef | 872 | |
89b831ef JS |
873 | /* to hit CPUs online before the notifier is up */ |
874 | for_each_online_cpu(lcpu) { | |
fff2e89f | 875 | int err = threshold_create_device(lcpu); |
1cb2a8e1 | 876 | |
89b831ef | 877 | if (err) |
fff2e89f | 878 | return err; |
89b831ef | 879 | } |
8735728e | 880 | threshold_cpu_callback = amd_64_threshold_cpu_callback; |
1cb2a8e1 | 881 | |
fff2e89f | 882 | return 0; |
89b831ef | 883 | } |
a8fccdb0 LJ |
884 | /* |
885 | * there are 3 funcs which need to be _initcalled in a logic sequence: | |
886 | * 1. xen_late_init_mcelog | |
887 | * 2. mcheck_init_device | |
888 | * 3. threshold_init_device | |
889 | * | |
890 | * xen_late_init_mcelog must register xen_mce_chrdev_device before | |
891 | * native mce_chrdev_device registration if running under xen platform; | |
892 | * | |
893 | * mcheck_init_device should be inited before threshold_init_device to | |
894 | * initialize mce_device, otherwise a NULL ptr dereference will cause panic. | |
895 | * | |
896 | * so we use following _initcalls | |
897 | * 1. device_initcall(xen_late_init_mcelog); | |
898 | * 2. device_initcall_sync(mcheck_init_device); | |
899 | * 3. late_initcall(threshold_init_device); | |
900 | * | |
901 | * when running under xen, the initcall order is 1,2,3; | |
902 | * on baremetal, we skip 1 and we do only 2 and 3. | |
903 | */ | |
904 | late_initcall(threshold_init_device); |