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Commit | Line | Data |
---|---|---|
89b831ef | 1 | /* |
95268664 | 2 | * (c) 2005, 2006 Advanced Micro Devices, Inc. |
89b831ef JS |
3 | * Your use of this code is subject to the terms and conditions of the |
4 | * GNU general public license version 2. See "COPYING" or | |
5 | * http://www.gnu.org/licenses/gpl.html | |
6 | * | |
7 | * Written by Jacob Shin - AMD, Inc. | |
8 | * | |
9 | * Support : jacob.shin@amd.com | |
10 | * | |
95268664 JS |
11 | * April 2006 |
12 | * - added support for AMD Family 0x10 processors | |
89b831ef | 13 | * |
95268664 | 14 | * All MC4_MISCi registers are shared between multi-cores |
89b831ef | 15 | */ |
89b831ef | 16 | #include <linux/interrupt.h> |
89b831ef | 17 | #include <linux/notifier.h> |
1cb2a8e1 | 18 | #include <linux/kobject.h> |
34fa1967 | 19 | #include <linux/percpu.h> |
1cb2a8e1 IM |
20 | #include <linux/errno.h> |
21 | #include <linux/sched.h> | |
89b831ef | 22 | #include <linux/sysfs.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
1cb2a8e1 IM |
24 | #include <linux/init.h> |
25 | #include <linux/cpu.h> | |
26 | #include <linux/smp.h> | |
27 | ||
89b831ef | 28 | #include <asm/apic.h> |
1cb2a8e1 | 29 | #include <asm/idle.h> |
89b831ef JS |
30 | #include <asm/mce.h> |
31 | #include <asm/msr.h> | |
89b831ef | 32 | |
2903ee85 JS |
33 | #define NR_BANKS 6 |
34 | #define NR_BLOCKS 9 | |
35 | #define THRESHOLD_MAX 0xFFF | |
36 | #define INT_TYPE_APIC 0x00020000 | |
37 | #define MASK_VALID_HI 0x80000000 | |
24ce0e96 JB |
38 | #define MASK_CNTP_HI 0x40000000 |
39 | #define MASK_LOCKED_HI 0x20000000 | |
2903ee85 JS |
40 | #define MASK_LVTOFF_HI 0x00F00000 |
41 | #define MASK_COUNT_EN_HI 0x00080000 | |
42 | #define MASK_INT_TYPE_HI 0x00060000 | |
43 | #define MASK_OVERFLOW_HI 0x00010000 | |
89b831ef | 44 | #define MASK_ERR_COUNT_HI 0x00000FFF |
95268664 JS |
45 | #define MASK_BLKPTR_LO 0xFF000000 |
46 | #define MCG_XBLK_ADDR 0xC0000400 | |
89b831ef | 47 | |
95268664 | 48 | struct threshold_block { |
1cb2a8e1 IM |
49 | unsigned int block; |
50 | unsigned int bank; | |
51 | unsigned int cpu; | |
52 | u32 address; | |
53 | u16 interrupt_enable; | |
54 | u16 threshold_limit; | |
55 | struct kobject kobj; | |
56 | struct list_head miscj; | |
89b831ef JS |
57 | }; |
58 | ||
95268664 | 59 | struct threshold_bank { |
1cb2a8e1 IM |
60 | struct kobject *kobj; |
61 | struct threshold_block *blocks; | |
62 | cpumask_var_t cpus; | |
95268664 | 63 | }; |
204fba4a | 64 | static DEFINE_PER_CPU(struct threshold_bank * [NR_BANKS], threshold_banks); |
95268664 | 65 | |
89b831ef JS |
66 | static unsigned char shared_bank[NR_BANKS] = { |
67 | 0, 0, 0, 0, 1 | |
68 | }; | |
89b831ef JS |
69 | |
70 | static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */ | |
71 | ||
b2762686 AK |
72 | static void amd_threshold_interrupt(void); |
73 | ||
89b831ef JS |
74 | /* |
75 | * CPU Initialization | |
76 | */ | |
77 | ||
4cd4601d | 78 | struct thresh_restart { |
1cb2a8e1 IM |
79 | struct threshold_block *b; |
80 | int reset; | |
9c37c9d8 RR |
81 | int set_lvt_off; |
82 | int lvt_off; | |
1cb2a8e1 | 83 | u16 old_limit; |
4cd4601d MT |
84 | }; |
85 | ||
bbaff08d RR |
86 | static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) |
87 | { | |
88 | int msr = (hi & MASK_LVTOFF_HI) >> 20; | |
89 | ||
90 | if (apic < 0) { | |
91 | pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " | |
92 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, | |
93 | b->bank, b->block, b->address, hi, lo); | |
94 | return 0; | |
95 | } | |
96 | ||
97 | if (apic != msr) { | |
98 | pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " | |
99 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n", | |
100 | b->cpu, apic, b->bank, b->block, b->address, hi, lo); | |
101 | return 0; | |
102 | } | |
103 | ||
104 | return 1; | |
105 | }; | |
106 | ||
89b831ef | 107 | /* must be called with correct cpu affinity */ |
a6b6a14e AM |
108 | /* Called via smp_call_function_single() */ |
109 | static void threshold_restart_bank(void *_tr) | |
89b831ef | 110 | { |
4cd4601d | 111 | struct thresh_restart *tr = _tr; |
7203a049 | 112 | u32 hi, lo; |
89b831ef | 113 | |
7203a049 | 114 | rdmsr(tr->b->address, lo, hi); |
89b831ef | 115 | |
7203a049 | 116 | if (tr->b->threshold_limit < (hi & THRESHOLD_MAX)) |
4cd4601d | 117 | tr->reset = 1; /* limit cannot be lower than err count */ |
89b831ef | 118 | |
4cd4601d | 119 | if (tr->reset) { /* reset err count and overflow bit */ |
7203a049 RR |
120 | hi = |
121 | (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) | | |
4cd4601d MT |
122 | (THRESHOLD_MAX - tr->b->threshold_limit); |
123 | } else if (tr->old_limit) { /* change limit w/o reset */ | |
7203a049 | 124 | int new_count = (hi & THRESHOLD_MAX) + |
4cd4601d | 125 | (tr->old_limit - tr->b->threshold_limit); |
1cb2a8e1 | 126 | |
7203a049 | 127 | hi = (hi & ~MASK_ERR_COUNT_HI) | |
89b831ef JS |
128 | (new_count & THRESHOLD_MAX); |
129 | } | |
130 | ||
9c37c9d8 | 131 | if (tr->set_lvt_off) { |
bbaff08d RR |
132 | if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) { |
133 | /* set new lvt offset */ | |
134 | hi &= ~MASK_LVTOFF_HI; | |
135 | hi |= tr->lvt_off << 20; | |
136 | } | |
9c37c9d8 RR |
137 | } |
138 | ||
4cd4601d | 139 | tr->b->interrupt_enable ? |
7203a049 RR |
140 | (hi = (hi & ~MASK_INT_TYPE_HI) | INT_TYPE_APIC) : |
141 | (hi &= ~MASK_INT_TYPE_HI); | |
89b831ef | 142 | |
7203a049 RR |
143 | hi |= MASK_COUNT_EN_HI; |
144 | wrmsr(tr->b->address, lo, hi); | |
89b831ef JS |
145 | } |
146 | ||
9c37c9d8 RR |
147 | static void mce_threshold_block_init(struct threshold_block *b, int offset) |
148 | { | |
149 | struct thresh_restart tr = { | |
150 | .b = b, | |
151 | .set_lvt_off = 1, | |
152 | .lvt_off = offset, | |
153 | }; | |
154 | ||
155 | b->threshold_limit = THRESHOLD_MAX; | |
156 | threshold_restart_bank(&tr); | |
157 | }; | |
158 | ||
bbaff08d RR |
159 | static int setup_APIC_mce(int reserved, int new) |
160 | { | |
161 | if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR, | |
162 | APIC_EILVT_MSG_FIX, 0)) | |
163 | return new; | |
164 | ||
165 | return reserved; | |
166 | } | |
167 | ||
95268664 | 168 | /* cpu init entry point, called from mce.c with preempt off */ |
cc3ca220 | 169 | void mce_amd_feature_init(struct cpuinfo_x86 *c) |
89b831ef | 170 | { |
9c37c9d8 | 171 | struct threshold_block b; |
89b831ef | 172 | unsigned int cpu = smp_processor_id(); |
95268664 | 173 | u32 low = 0, high = 0, address = 0; |
1cb2a8e1 | 174 | unsigned int bank, block; |
bbaff08d | 175 | int offset = -1; |
89b831ef JS |
176 | |
177 | for (bank = 0; bank < NR_BANKS; ++bank) { | |
95268664 JS |
178 | for (block = 0; block < NR_BLOCKS; ++block) { |
179 | if (block == 0) | |
180 | address = MSR_IA32_MC0_MISC + bank * 4; | |
24ce0e96 JB |
181 | else if (block == 1) { |
182 | address = (low & MASK_BLKPTR_LO) >> 21; | |
183 | if (!address) | |
184 | break; | |
6dcbfe4f | 185 | |
24ce0e96 | 186 | address += MCG_XBLK_ADDR; |
1cb2a8e1 | 187 | } else |
95268664 JS |
188 | ++address; |
189 | ||
190 | if (rdmsr_safe(address, &low, &high)) | |
24ce0e96 | 191 | break; |
95268664 | 192 | |
6dcbfe4f BP |
193 | if (!(high & MASK_VALID_HI)) |
194 | continue; | |
95268664 | 195 | |
24ce0e96 JB |
196 | if (!(high & MASK_CNTP_HI) || |
197 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
198 | continue; |
199 | ||
200 | if (!block) | |
201 | per_cpu(bank_map, cpu) |= (1 << bank); | |
95268664 JS |
202 | if (shared_bank[bank] && c->cpu_core_id) |
203 | break; | |
141168c3 | 204 | |
bbaff08d RR |
205 | offset = setup_APIC_mce(offset, |
206 | (high & MASK_LVTOFF_HI) >> 20); | |
7b83dae7 | 207 | |
9c37c9d8 RR |
208 | memset(&b, 0, sizeof(b)); |
209 | b.cpu = cpu; | |
210 | b.bank = bank; | |
211 | b.block = block; | |
212 | b.address = address; | |
b2762686 | 213 | |
9c37c9d8 | 214 | mce_threshold_block_init(&b, offset); |
b2762686 | 215 | mce_threshold_vector = amd_threshold_interrupt; |
95268664 | 216 | } |
89b831ef JS |
217 | } |
218 | } | |
219 | ||
220 | /* | |
221 | * APIC Interrupt Handler | |
222 | */ | |
223 | ||
224 | /* | |
225 | * threshold interrupt handler will service THRESHOLD_APIC_VECTOR. | |
226 | * the interrupt goes off when error_count reaches threshold_limit. | |
227 | * the handler will simply log mcelog w/ software defined bank number. | |
228 | */ | |
b2762686 | 229 | static void amd_threshold_interrupt(void) |
89b831ef | 230 | { |
1cb2a8e1 | 231 | u32 low = 0, high = 0, address = 0; |
95268664 | 232 | unsigned int bank, block; |
89b831ef JS |
233 | struct mce m; |
234 | ||
b5f2fa4e | 235 | mce_setup(&m); |
89b831ef JS |
236 | |
237 | /* assume first bank caused it */ | |
238 | for (bank = 0; bank < NR_BANKS; ++bank) { | |
24ce0e96 JB |
239 | if (!(per_cpu(bank_map, m.cpu) & (1 << bank))) |
240 | continue; | |
95268664 | 241 | for (block = 0; block < NR_BLOCKS; ++block) { |
1cb2a8e1 | 242 | if (block == 0) { |
95268664 | 243 | address = MSR_IA32_MC0_MISC + bank * 4; |
1cb2a8e1 | 244 | } else if (block == 1) { |
24ce0e96 JB |
245 | address = (low & MASK_BLKPTR_LO) >> 21; |
246 | if (!address) | |
247 | break; | |
248 | address += MCG_XBLK_ADDR; | |
1cb2a8e1 | 249 | } else { |
95268664 | 250 | ++address; |
1cb2a8e1 | 251 | } |
95268664 JS |
252 | |
253 | if (rdmsr_safe(address, &low, &high)) | |
24ce0e96 | 254 | break; |
95268664 JS |
255 | |
256 | if (!(high & MASK_VALID_HI)) { | |
257 | if (block) | |
258 | continue; | |
259 | else | |
260 | break; | |
261 | } | |
262 | ||
24ce0e96 JB |
263 | if (!(high & MASK_CNTP_HI) || |
264 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
265 | continue; |
266 | ||
1cb2a8e1 IM |
267 | /* |
268 | * Log the machine check that caused the threshold | |
269 | * event. | |
270 | */ | |
ee031c31 AK |
271 | machine_check_poll(MCP_TIMESTAMP, |
272 | &__get_cpu_var(mce_poll_banks)); | |
a98f0dd3 | 273 | |
95268664 JS |
274 | if (high & MASK_OVERFLOW_HI) { |
275 | rdmsrl(address, m.misc); | |
276 | rdmsrl(MSR_IA32_MC0_STATUS + bank * 4, | |
277 | m.status); | |
278 | m.bank = K8_MCE_THRESHOLD_BASE | |
279 | + bank * NR_BLOCKS | |
280 | + block; | |
281 | mce_log(&m); | |
b2762686 | 282 | return; |
95268664 | 283 | } |
89b831ef JS |
284 | } |
285 | } | |
89b831ef JS |
286 | } |
287 | ||
288 | /* | |
289 | * Sysfs Interface | |
290 | */ | |
291 | ||
89b831ef | 292 | struct threshold_attr { |
2903ee85 | 293 | struct attribute attr; |
1cb2a8e1 IM |
294 | ssize_t (*show) (struct threshold_block *, char *); |
295 | ssize_t (*store) (struct threshold_block *, const char *, size_t count); | |
89b831ef JS |
296 | }; |
297 | ||
1cb2a8e1 IM |
298 | #define SHOW_FIELDS(name) \ |
299 | static ssize_t show_ ## name(struct threshold_block *b, char *buf) \ | |
300 | { \ | |
301 | return sprintf(buf, "%lx\n", (unsigned long) b->name); \ | |
2903ee85 | 302 | } |
89b831ef JS |
303 | SHOW_FIELDS(interrupt_enable) |
304 | SHOW_FIELDS(threshold_limit) | |
305 | ||
1cb2a8e1 | 306 | static ssize_t |
9319cec8 | 307 | store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size) |
89b831ef | 308 | { |
4cd4601d | 309 | struct thresh_restart tr; |
1cb2a8e1 | 310 | unsigned long new; |
1cb2a8e1 | 311 | |
9319cec8 | 312 | if (strict_strtoul(buf, 0, &new) < 0) |
89b831ef | 313 | return -EINVAL; |
1cb2a8e1 | 314 | |
89b831ef JS |
315 | b->interrupt_enable = !!new; |
316 | ||
9c37c9d8 | 317 | memset(&tr, 0, sizeof(tr)); |
1cb2a8e1 | 318 | tr.b = b; |
1cb2a8e1 | 319 | |
a6b6a14e | 320 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef | 321 | |
9319cec8 | 322 | return size; |
89b831ef JS |
323 | } |
324 | ||
1cb2a8e1 | 325 | static ssize_t |
9319cec8 | 326 | store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) |
89b831ef | 327 | { |
4cd4601d | 328 | struct thresh_restart tr; |
1cb2a8e1 | 329 | unsigned long new; |
1cb2a8e1 | 330 | |
9319cec8 | 331 | if (strict_strtoul(buf, 0, &new) < 0) |
89b831ef | 332 | return -EINVAL; |
1cb2a8e1 | 333 | |
89b831ef JS |
334 | if (new > THRESHOLD_MAX) |
335 | new = THRESHOLD_MAX; | |
336 | if (new < 1) | |
337 | new = 1; | |
1cb2a8e1 | 338 | |
9c37c9d8 | 339 | memset(&tr, 0, sizeof(tr)); |
4cd4601d | 340 | tr.old_limit = b->threshold_limit; |
89b831ef | 341 | b->threshold_limit = new; |
4cd4601d | 342 | tr.b = b; |
89b831ef | 343 | |
a6b6a14e | 344 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef | 345 | |
9319cec8 | 346 | return size; |
89b831ef JS |
347 | } |
348 | ||
a6b6a14e | 349 | struct threshold_block_cross_cpu { |
1cb2a8e1 IM |
350 | struct threshold_block *tb; |
351 | long retval; | |
a6b6a14e AM |
352 | }; |
353 | ||
354 | static void local_error_count_handler(void *_tbcc) | |
89b831ef | 355 | { |
a6b6a14e AM |
356 | struct threshold_block_cross_cpu *tbcc = _tbcc; |
357 | struct threshold_block *b = tbcc->tb; | |
4cd4601d MT |
358 | u32 low, high; |
359 | ||
95268664 | 360 | rdmsr(b->address, low, high); |
a6b6a14e | 361 | tbcc->retval = (high & 0xFFF) - (THRESHOLD_MAX - b->threshold_limit); |
4cd4601d MT |
362 | } |
363 | ||
364 | static ssize_t show_error_count(struct threshold_block *b, char *buf) | |
365 | { | |
a6b6a14e AM |
366 | struct threshold_block_cross_cpu tbcc = { .tb = b, }; |
367 | ||
368 | smp_call_function_single(b->cpu, local_error_count_handler, &tbcc, 1); | |
369 | return sprintf(buf, "%lx\n", tbcc.retval); | |
89b831ef JS |
370 | } |
371 | ||
95268664 | 372 | static ssize_t store_error_count(struct threshold_block *b, |
89b831ef JS |
373 | const char *buf, size_t count) |
374 | { | |
4cd4601d MT |
375 | struct thresh_restart tr = { .b = b, .reset = 1, .old_limit = 0 }; |
376 | ||
a6b6a14e | 377 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef JS |
378 | return 1; |
379 | } | |
380 | ||
34fa1967 HS |
381 | #define RW_ATTR(val) \ |
382 | static struct threshold_attr val = { \ | |
383 | .attr = {.name = __stringify(val), .mode = 0644 }, \ | |
384 | .show = show_## val, \ | |
385 | .store = store_## val, \ | |
89b831ef JS |
386 | }; |
387 | ||
2903ee85 JS |
388 | RW_ATTR(interrupt_enable); |
389 | RW_ATTR(threshold_limit); | |
390 | RW_ATTR(error_count); | |
89b831ef JS |
391 | |
392 | static struct attribute *default_attrs[] = { | |
393 | &interrupt_enable.attr, | |
394 | &threshold_limit.attr, | |
395 | &error_count.attr, | |
396 | NULL | |
397 | }; | |
398 | ||
1cb2a8e1 IM |
399 | #define to_block(k) container_of(k, struct threshold_block, kobj) |
400 | #define to_attr(a) container_of(a, struct threshold_attr, attr) | |
89b831ef JS |
401 | |
402 | static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) | |
403 | { | |
95268664 | 404 | struct threshold_block *b = to_block(kobj); |
89b831ef JS |
405 | struct threshold_attr *a = to_attr(attr); |
406 | ssize_t ret; | |
1cb2a8e1 | 407 | |
89b831ef | 408 | ret = a->show ? a->show(b, buf) : -EIO; |
1cb2a8e1 | 409 | |
89b831ef JS |
410 | return ret; |
411 | } | |
412 | ||
413 | static ssize_t store(struct kobject *kobj, struct attribute *attr, | |
414 | const char *buf, size_t count) | |
415 | { | |
95268664 | 416 | struct threshold_block *b = to_block(kobj); |
89b831ef JS |
417 | struct threshold_attr *a = to_attr(attr); |
418 | ssize_t ret; | |
1cb2a8e1 | 419 | |
89b831ef | 420 | ret = a->store ? a->store(b, buf, count) : -EIO; |
1cb2a8e1 | 421 | |
89b831ef JS |
422 | return ret; |
423 | } | |
424 | ||
52cf25d0 | 425 | static const struct sysfs_ops threshold_ops = { |
1cb2a8e1 IM |
426 | .show = show, |
427 | .store = store, | |
89b831ef JS |
428 | }; |
429 | ||
430 | static struct kobj_type threshold_ktype = { | |
1cb2a8e1 IM |
431 | .sysfs_ops = &threshold_ops, |
432 | .default_attrs = default_attrs, | |
89b831ef JS |
433 | }; |
434 | ||
95268664 JS |
435 | static __cpuinit int allocate_threshold_blocks(unsigned int cpu, |
436 | unsigned int bank, | |
437 | unsigned int block, | |
438 | u32 address) | |
439 | { | |
95268664 | 440 | struct threshold_block *b = NULL; |
1cb2a8e1 IM |
441 | u32 low, high; |
442 | int err; | |
95268664 JS |
443 | |
444 | if ((bank >= NR_BANKS) || (block >= NR_BLOCKS)) | |
445 | return 0; | |
446 | ||
a6b6a14e | 447 | if (rdmsr_safe_on_cpu(cpu, address, &low, &high)) |
24ce0e96 | 448 | return 0; |
95268664 JS |
449 | |
450 | if (!(high & MASK_VALID_HI)) { | |
451 | if (block) | |
452 | goto recurse; | |
453 | else | |
454 | return 0; | |
455 | } | |
456 | ||
24ce0e96 JB |
457 | if (!(high & MASK_CNTP_HI) || |
458 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
459 | goto recurse; |
460 | ||
461 | b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL); | |
462 | if (!b) | |
463 | return -ENOMEM; | |
95268664 | 464 | |
1cb2a8e1 IM |
465 | b->block = block; |
466 | b->bank = bank; | |
467 | b->cpu = cpu; | |
468 | b->address = address; | |
469 | b->interrupt_enable = 0; | |
470 | b->threshold_limit = THRESHOLD_MAX; | |
95268664 JS |
471 | |
472 | INIT_LIST_HEAD(&b->miscj); | |
473 | ||
1cb2a8e1 | 474 | if (per_cpu(threshold_banks, cpu)[bank]->blocks) { |
95268664 JS |
475 | list_add(&b->miscj, |
476 | &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj); | |
1cb2a8e1 | 477 | } else { |
95268664 | 478 | per_cpu(threshold_banks, cpu)[bank]->blocks = b; |
1cb2a8e1 | 479 | } |
95268664 | 480 | |
542eb75a GKH |
481 | err = kobject_init_and_add(&b->kobj, &threshold_ktype, |
482 | per_cpu(threshold_banks, cpu)[bank]->kobj, | |
483 | "misc%i", block); | |
95268664 JS |
484 | if (err) |
485 | goto out_free; | |
486 | recurse: | |
487 | if (!block) { | |
488 | address = (low & MASK_BLKPTR_LO) >> 21; | |
489 | if (!address) | |
490 | return 0; | |
491 | address += MCG_XBLK_ADDR; | |
1cb2a8e1 | 492 | } else { |
95268664 | 493 | ++address; |
1cb2a8e1 | 494 | } |
95268664 JS |
495 | |
496 | err = allocate_threshold_blocks(cpu, bank, ++block, address); | |
497 | if (err) | |
498 | goto out_free; | |
499 | ||
213eca7f GKH |
500 | if (b) |
501 | kobject_uevent(&b->kobj, KOBJ_ADD); | |
542eb75a | 502 | |
95268664 JS |
503 | return err; |
504 | ||
505 | out_free: | |
506 | if (b) { | |
38a382ae | 507 | kobject_put(&b->kobj); |
d9a5ac9e | 508 | list_del(&b->miscj); |
95268664 JS |
509 | kfree(b); |
510 | } | |
511 | return err; | |
512 | } | |
513 | ||
a6b6a14e AM |
514 | static __cpuinit long |
515 | local_allocate_threshold_blocks(int cpu, unsigned int bank) | |
4cd4601d | 516 | { |
a6b6a14e AM |
517 | return allocate_threshold_blocks(cpu, bank, 0, |
518 | MSR_IA32_MC0_MISC + bank * 4); | |
4cd4601d MT |
519 | } |
520 | ||
89b831ef | 521 | /* symlinks sibling shared banks to first core. first core owns dir/files. */ |
95268664 | 522 | static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank) |
89b831ef | 523 | { |
95268664 | 524 | int i, err = 0; |
68209407 | 525 | struct threshold_bank *b = NULL; |
e032d807 | 526 | struct device *dev = mce_device[cpu]; |
95268664 JS |
527 | char name[32]; |
528 | ||
529 | sprintf(name, "threshold_bank%i", bank); | |
89b831ef | 530 | |
3f806e50 | 531 | #ifdef CONFIG_SMP |
92cb7612 | 532 | if (cpu_data(cpu).cpu_core_id && shared_bank[bank]) { /* symlink */ |
b3d7336d | 533 | i = cpumask_first(cpu_llc_shared_mask(cpu)); |
95268664 JS |
534 | |
535 | /* first core not up yet */ | |
92cb7612 | 536 | if (cpu_data(i).cpu_core_id) |
95268664 JS |
537 | goto out; |
538 | ||
539 | /* already linked */ | |
540 | if (per_cpu(threshold_banks, cpu)[bank]) | |
541 | goto out; | |
542 | ||
543 | b = per_cpu(threshold_banks, i)[bank]; | |
89b831ef | 544 | |
89b831ef JS |
545 | if (!b) |
546 | goto out; | |
95268664 | 547 | |
e032d807 | 548 | err = sysfs_create_link(&dev->kobj, b->kobj, name); |
89b831ef JS |
549 | if (err) |
550 | goto out; | |
95268664 | 551 | |
b3d7336d | 552 | cpumask_copy(b->cpus, cpu_llc_shared_mask(cpu)); |
89b831ef | 553 | per_cpu(threshold_banks, cpu)[bank] = b; |
1cb2a8e1 | 554 | |
89b831ef JS |
555 | goto out; |
556 | } | |
3f806e50 | 557 | #endif |
89b831ef | 558 | |
95268664 | 559 | b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL); |
89b831ef JS |
560 | if (!b) { |
561 | err = -ENOMEM; | |
562 | goto out; | |
563 | } | |
1389298f | 564 | if (!zalloc_cpumask_var(&b->cpus, GFP_KERNEL)) { |
a1c33bbe MT |
565 | kfree(b); |
566 | err = -ENOMEM; | |
567 | goto out; | |
568 | } | |
89b831ef | 569 | |
e032d807 | 570 | b->kobj = kobject_create_and_add(name, &dev->kobj); |
a521cf20 GKH |
571 | if (!b->kobj) |
572 | goto out_free; | |
573 | ||
95268664 | 574 | #ifndef CONFIG_SMP |
a1c33bbe | 575 | cpumask_setall(b->cpus); |
95268664 | 576 | #else |
1389298f | 577 | cpumask_set_cpu(cpu, b->cpus); |
95268664 | 578 | #endif |
95268664 | 579 | |
89b831ef | 580 | per_cpu(threshold_banks, cpu)[bank] = b; |
95268664 | 581 | |
a6b6a14e | 582 | err = local_allocate_threshold_blocks(cpu, bank); |
95268664 JS |
583 | if (err) |
584 | goto out_free; | |
585 | ||
a1c33bbe | 586 | for_each_cpu(i, b->cpus) { |
95268664 JS |
587 | if (i == cpu) |
588 | continue; | |
589 | ||
e032d807 GKH |
590 | dev = mce_device[i]; |
591 | if (dev) | |
592 | err = sysfs_create_link(&dev->kobj,b->kobj, name); | |
95268664 JS |
593 | if (err) |
594 | goto out; | |
595 | ||
596 | per_cpu(threshold_banks, i)[bank] = b; | |
597 | } | |
598 | ||
599 | goto out; | |
600 | ||
601 | out_free: | |
602 | per_cpu(threshold_banks, cpu)[bank] = NULL; | |
a1c33bbe | 603 | free_cpumask_var(b->cpus); |
95268664 | 604 | kfree(b); |
2903ee85 | 605 | out: |
89b831ef JS |
606 | return err; |
607 | } | |
608 | ||
609 | /* create dir/files for all valid threshold banks */ | |
610 | static __cpuinit int threshold_create_device(unsigned int cpu) | |
611 | { | |
2903ee85 | 612 | unsigned int bank; |
89b831ef JS |
613 | int err = 0; |
614 | ||
89b831ef | 615 | for (bank = 0; bank < NR_BANKS; ++bank) { |
5a96f4a5 | 616 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
89b831ef JS |
617 | continue; |
618 | err = threshold_create_bank(cpu, bank); | |
619 | if (err) | |
0a17941e | 620 | return err; |
89b831ef | 621 | } |
0a17941e | 622 | |
89b831ef JS |
623 | return err; |
624 | } | |
625 | ||
89b831ef JS |
626 | /* |
627 | * let's be hotplug friendly. | |
628 | * in case of multiple core processors, the first core always takes ownership | |
629 | * of shared sysfs dir/files, and rest of the cores will be symlinked to it. | |
630 | */ | |
631 | ||
be6b5a35 | 632 | static void deallocate_threshold_block(unsigned int cpu, |
95268664 JS |
633 | unsigned int bank) |
634 | { | |
635 | struct threshold_block *pos = NULL; | |
636 | struct threshold_block *tmp = NULL; | |
637 | struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank]; | |
638 | ||
639 | if (!head) | |
640 | return; | |
641 | ||
642 | list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) { | |
38a382ae | 643 | kobject_put(&pos->kobj); |
95268664 JS |
644 | list_del(&pos->miscj); |
645 | kfree(pos); | |
646 | } | |
647 | ||
648 | kfree(per_cpu(threshold_banks, cpu)[bank]->blocks); | |
649 | per_cpu(threshold_banks, cpu)[bank]->blocks = NULL; | |
650 | } | |
651 | ||
be6b5a35 | 652 | static void threshold_remove_bank(unsigned int cpu, int bank) |
89b831ef JS |
653 | { |
654 | struct threshold_bank *b; | |
e032d807 | 655 | struct device *dev; |
95268664 | 656 | char name[32]; |
1cb2a8e1 | 657 | int i = 0; |
89b831ef JS |
658 | |
659 | b = per_cpu(threshold_banks, cpu)[bank]; | |
660 | if (!b) | |
661 | return; | |
95268664 JS |
662 | if (!b->blocks) |
663 | goto free_out; | |
664 | ||
665 | sprintf(name, "threshold_bank%i", bank); | |
666 | ||
02316067 | 667 | #ifdef CONFIG_SMP |
95268664 JS |
668 | /* sibling symlink */ |
669 | if (shared_bank[bank] && b->blocks->cpu != cpu) { | |
e032d807 | 670 | sysfs_remove_link(&mce_device[cpu]->kobj, name); |
0d2caebd | 671 | per_cpu(threshold_banks, cpu)[bank] = NULL; |
1cb2a8e1 | 672 | |
95268664 | 673 | return; |
89b831ef | 674 | } |
02316067 | 675 | #endif |
95268664 JS |
676 | |
677 | /* remove all sibling symlinks before unregistering */ | |
a1c33bbe | 678 | for_each_cpu(i, b->cpus) { |
95268664 JS |
679 | if (i == cpu) |
680 | continue; | |
681 | ||
e032d807 GKH |
682 | dev = mce_device[i]; |
683 | if (dev) | |
684 | sysfs_remove_link(&dev->kobj, name); | |
95268664 JS |
685 | per_cpu(threshold_banks, i)[bank] = NULL; |
686 | } | |
687 | ||
688 | deallocate_threshold_block(cpu, bank); | |
689 | ||
690 | free_out: | |
8735728e | 691 | kobject_del(b->kobj); |
38a382ae | 692 | kobject_put(b->kobj); |
a1c33bbe | 693 | free_cpumask_var(b->cpus); |
95268664 JS |
694 | kfree(b); |
695 | per_cpu(threshold_banks, cpu)[bank] = NULL; | |
89b831ef JS |
696 | } |
697 | ||
be6b5a35 | 698 | static void threshold_remove_device(unsigned int cpu) |
89b831ef | 699 | { |
2903ee85 | 700 | unsigned int bank; |
89b831ef JS |
701 | |
702 | for (bank = 0; bank < NR_BANKS; ++bank) { | |
5a96f4a5 | 703 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
89b831ef JS |
704 | continue; |
705 | threshold_remove_bank(cpu, bank); | |
706 | } | |
89b831ef JS |
707 | } |
708 | ||
89b831ef | 709 | /* get notified when a cpu comes on/off */ |
1cb2a8e1 IM |
710 | static void __cpuinit |
711 | amd_64_threshold_cpu_callback(unsigned long action, unsigned int cpu) | |
89b831ef | 712 | { |
89b831ef JS |
713 | switch (action) { |
714 | case CPU_ONLINE: | |
8bb78442 | 715 | case CPU_ONLINE_FROZEN: |
89b831ef | 716 | threshold_create_device(cpu); |
89b831ef JS |
717 | break; |
718 | case CPU_DEAD: | |
8bb78442 | 719 | case CPU_DEAD_FROZEN: |
89b831ef JS |
720 | threshold_remove_device(cpu); |
721 | break; | |
722 | default: | |
723 | break; | |
724 | } | |
89b831ef JS |
725 | } |
726 | ||
89b831ef JS |
727 | static __init int threshold_init_device(void) |
728 | { | |
2903ee85 | 729 | unsigned lcpu = 0; |
89b831ef | 730 | |
89b831ef JS |
731 | /* to hit CPUs online before the notifier is up */ |
732 | for_each_online_cpu(lcpu) { | |
fff2e89f | 733 | int err = threshold_create_device(lcpu); |
1cb2a8e1 | 734 | |
89b831ef | 735 | if (err) |
fff2e89f | 736 | return err; |
89b831ef | 737 | } |
8735728e | 738 | threshold_cpu_callback = amd_64_threshold_cpu_callback; |
1cb2a8e1 | 739 | |
fff2e89f | 740 | return 0; |
89b831ef | 741 | } |
89b831ef | 742 | device_initcall(threshold_init_device); |