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Commit | Line | Data |
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89b831ef | 1 | /* |
ea2ca36b | 2 | * (c) 2005-2016 Advanced Micro Devices, Inc. |
89b831ef JS |
3 | * Your use of this code is subject to the terms and conditions of the |
4 | * GNU general public license version 2. See "COPYING" or | |
5 | * http://www.gnu.org/licenses/gpl.html | |
6 | * | |
7 | * Written by Jacob Shin - AMD, Inc. | |
e6d41e8c | 8 | * Maintained by: Borislav Petkov <bp@alien8.de> |
89b831ef | 9 | * |
3490c0e4 | 10 | * All MC4_MISCi registers are shared between cores on a node. |
89b831ef | 11 | */ |
89b831ef | 12 | #include <linux/interrupt.h> |
89b831ef | 13 | #include <linux/notifier.h> |
1cb2a8e1 | 14 | #include <linux/kobject.h> |
34fa1967 | 15 | #include <linux/percpu.h> |
1cb2a8e1 IM |
16 | #include <linux/errno.h> |
17 | #include <linux/sched.h> | |
89b831ef | 18 | #include <linux/sysfs.h> |
5a0e3ad6 | 19 | #include <linux/slab.h> |
1cb2a8e1 IM |
20 | #include <linux/init.h> |
21 | #include <linux/cpu.h> | |
22 | #include <linux/smp.h> | |
23 | ||
019f34fc | 24 | #include <asm/amd_nb.h> |
89b831ef | 25 | #include <asm/apic.h> |
1cb2a8e1 | 26 | #include <asm/idle.h> |
89b831ef JS |
27 | #include <asm/mce.h> |
28 | #include <asm/msr.h> | |
24fd78a8 | 29 | #include <asm/trace/irq_vectors.h> |
89b831ef | 30 | |
60f116fc | 31 | #define NR_BLOCKS 5 |
2903ee85 JS |
32 | #define THRESHOLD_MAX 0xFFF |
33 | #define INT_TYPE_APIC 0x00020000 | |
34 | #define MASK_VALID_HI 0x80000000 | |
24ce0e96 JB |
35 | #define MASK_CNTP_HI 0x40000000 |
36 | #define MASK_LOCKED_HI 0x20000000 | |
2903ee85 JS |
37 | #define MASK_LVTOFF_HI 0x00F00000 |
38 | #define MASK_COUNT_EN_HI 0x00080000 | |
39 | #define MASK_INT_TYPE_HI 0x00060000 | |
40 | #define MASK_OVERFLOW_HI 0x00010000 | |
89b831ef | 41 | #define MASK_ERR_COUNT_HI 0x00000FFF |
95268664 JS |
42 | #define MASK_BLKPTR_LO 0xFF000000 |
43 | #define MCG_XBLK_ADDR 0xC0000400 | |
89b831ef | 44 | |
24fd78a8 AG |
45 | /* Deferred error settings */ |
46 | #define MSR_CU_DEF_ERR 0xC0000410 | |
47 | #define MASK_DEF_LVTOFF 0x000000F0 | |
48 | #define MASK_DEF_INT_TYPE 0x00000006 | |
49 | #define DEF_LVT_OFF 0x2 | |
50 | #define DEF_INT_TYPE_APIC 0x2 | |
51 | ||
f57a1f3c AG |
52 | /* Scalable MCA: */ |
53 | ||
54 | /* Threshold LVT offset is at MSR0xC0000410[15:12] */ | |
55 | #define SMCA_THR_LVT_OFF 0xF000 | |
56 | ||
336d335a BP |
57 | static const char * const th_names[] = { |
58 | "load_store", | |
59 | "insn_fetch", | |
60 | "combined_unit", | |
61 | "", | |
62 | "northbridge", | |
63 | "execution_unit", | |
64 | }; | |
65 | ||
5896820e YG |
66 | struct smca_bank_name smca_bank_names[] = { |
67 | [SMCA_LS] = { "load_store", "Load Store Unit" }, | |
68 | [SMCA_IF] = { "insn_fetch", "Instruction Fetch Unit" }, | |
69 | [SMCA_L2_CACHE] = { "l2_cache", "L2 Cache" }, | |
70 | [SMCA_DE] = { "decode_unit", "Decode Unit" }, | |
71 | [SMCA_EX] = { "execution_unit", "Execution Unit" }, | |
72 | [SMCA_FP] = { "floating_point", "Floating Point Unit" }, | |
73 | [SMCA_L3_CACHE] = { "l3_cache", "L3 Cache" }, | |
74 | [SMCA_CS] = { "coherent_slave", "Coherent Slave" }, | |
75 | [SMCA_PIE] = { "pie", "Power, Interrupts, etc." }, | |
76 | [SMCA_UMC] = { "umc", "Unified Memory Controller" }, | |
77 | [SMCA_PB] = { "param_block", "Parameter Block" }, | |
78 | [SMCA_PSP] = { "psp", "Platform Security Processor" }, | |
79 | [SMCA_SMU] = { "smu", "System Management Unit" }, | |
be0aec23 | 80 | }; |
5896820e YG |
81 | EXPORT_SYMBOL_GPL(smca_bank_names); |
82 | ||
83 | static struct smca_hwid_mcatype smca_hwid_mcatypes[] = { | |
84 | /* { bank_type, hwid_mcatype, xec_bitmap } */ | |
85 | ||
86 | /* ZN Core (HWID=0xB0) MCA types */ | |
87 | { SMCA_LS, HWID_MCATYPE(0xB0, 0x0), 0x1FFFEF }, | |
88 | { SMCA_IF, HWID_MCATYPE(0xB0, 0x1), 0x3FFF }, | |
89 | { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2), 0xF }, | |
90 | { SMCA_DE, HWID_MCATYPE(0xB0, 0x3), 0x1FF }, | |
91 | /* HWID 0xB0 MCATYPE 0x4 is Reserved */ | |
92 | { SMCA_EX, HWID_MCATYPE(0xB0, 0x5), 0x7FF }, | |
93 | { SMCA_FP, HWID_MCATYPE(0xB0, 0x6), 0x7F }, | |
94 | { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7), 0xFF }, | |
95 | ||
96 | /* Data Fabric MCA types */ | |
97 | { SMCA_CS, HWID_MCATYPE(0x2E, 0x0), 0x1FF }, | |
98 | { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1), 0xF }, | |
99 | ||
100 | /* Unified Memory Controller MCA type */ | |
101 | { SMCA_UMC, HWID_MCATYPE(0x96, 0x0), 0x3F }, | |
102 | ||
103 | /* Parameter Block MCA type */ | |
104 | { SMCA_PB, HWID_MCATYPE(0x05, 0x0), 0x1 }, | |
be0aec23 | 105 | |
5896820e YG |
106 | /* Platform Security Processor MCA type */ |
107 | { SMCA_PSP, HWID_MCATYPE(0xFF, 0x0), 0x1 }, | |
108 | ||
109 | /* System Management Unit MCA type */ | |
110 | { SMCA_SMU, HWID_MCATYPE(0x01, 0x0), 0x1 }, | |
be0aec23 | 111 | }; |
5896820e YG |
112 | |
113 | struct smca_bank_info smca_banks[MAX_NR_BANKS]; | |
114 | EXPORT_SYMBOL_GPL(smca_banks); | |
be0aec23 | 115 | |
bafcdd3b | 116 | static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks); |
955d1427 | 117 | static DEFINE_PER_CPU(unsigned int, bank_map); /* see which banks are on */ |
89b831ef | 118 | |
b2762686 | 119 | static void amd_threshold_interrupt(void); |
24fd78a8 AG |
120 | static void amd_deferred_error_interrupt(void); |
121 | ||
122 | static void default_deferred_error_interrupt(void) | |
123 | { | |
124 | pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR); | |
125 | } | |
126 | void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; | |
b2762686 | 127 | |
89b831ef JS |
128 | /* |
129 | * CPU Initialization | |
130 | */ | |
131 | ||
5896820e YG |
132 | static void get_smca_bank_info(unsigned int bank) |
133 | { | |
134 | unsigned int i, hwid_mcatype, cpu = smp_processor_id(); | |
135 | struct smca_hwid_mcatype *type; | |
136 | u32 high, instanceId; | |
137 | u16 hwid, mcatype; | |
138 | ||
139 | /* Collect bank_info using CPU 0 for now. */ | |
140 | if (cpu) | |
141 | return; | |
142 | ||
143 | if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_IPID(bank), &instanceId, &high)) { | |
144 | pr_warn("Failed to read MCA_IPID for bank %d\n", bank); | |
145 | return; | |
146 | } | |
147 | ||
148 | hwid = high & MCI_IPID_HWID; | |
149 | mcatype = (high & MCI_IPID_MCATYPE) >> 16; | |
150 | hwid_mcatype = HWID_MCATYPE(hwid, mcatype); | |
151 | ||
152 | for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) { | |
153 | type = &smca_hwid_mcatypes[i]; | |
154 | if (hwid_mcatype == type->hwid_mcatype) { | |
155 | smca_banks[bank].type = type; | |
156 | smca_banks[bank].type_instance = instanceId; | |
157 | break; | |
158 | } | |
159 | } | |
160 | } | |
161 | ||
4cd4601d | 162 | struct thresh_restart { |
1cb2a8e1 IM |
163 | struct threshold_block *b; |
164 | int reset; | |
9c37c9d8 RR |
165 | int set_lvt_off; |
166 | int lvt_off; | |
1cb2a8e1 | 167 | u16 old_limit; |
4cd4601d MT |
168 | }; |
169 | ||
c76e8164 BO |
170 | static inline bool is_shared_bank(int bank) |
171 | { | |
284b965c AG |
172 | /* |
173 | * Scalable MCA provides for only one core to have access to the MSRs of | |
174 | * a shared bank. | |
175 | */ | |
176 | if (mce_flags.smca) | |
177 | return false; | |
178 | ||
c76e8164 BO |
179 | /* Bank 4 is for northbridge reporting and is thus shared */ |
180 | return (bank == 4); | |
181 | } | |
182 | ||
2cd4c303 | 183 | static const char *bank4_names(const struct threshold_block *b) |
336d335a BP |
184 | { |
185 | switch (b->address) { | |
186 | /* MSR4_MISC0 */ | |
187 | case 0x00000413: | |
188 | return "dram"; | |
189 | ||
190 | case 0xc0000408: | |
191 | return "ht_links"; | |
192 | ||
193 | case 0xc0000409: | |
194 | return "l3_cache"; | |
195 | ||
196 | default: | |
197 | WARN(1, "Funny MSR: 0x%08x\n", b->address); | |
198 | return ""; | |
199 | } | |
200 | }; | |
201 | ||
202 | ||
f227d430 BP |
203 | static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) |
204 | { | |
205 | /* | |
206 | * bank 4 supports APIC LVT interrupts implicitly since forever. | |
207 | */ | |
208 | if (bank == 4) | |
209 | return true; | |
210 | ||
211 | /* | |
212 | * IntP: interrupt present; if this bit is set, the thresholding | |
213 | * bank can generate APIC LVT interrupts | |
214 | */ | |
215 | return msr_high_bits & BIT(28); | |
216 | } | |
217 | ||
bbaff08d RR |
218 | static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) |
219 | { | |
220 | int msr = (hi & MASK_LVTOFF_HI) >> 20; | |
221 | ||
222 | if (apic < 0) { | |
223 | pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " | |
224 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, | |
225 | b->bank, b->block, b->address, hi, lo); | |
226 | return 0; | |
227 | } | |
228 | ||
229 | if (apic != msr) { | |
f57a1f3c AG |
230 | /* |
231 | * On SMCA CPUs, LVT offset is programmed at a different MSR, and | |
232 | * the BIOS provides the value. The original field where LVT offset | |
233 | * was set is reserved. Return early here: | |
234 | */ | |
235 | if (mce_flags.smca) | |
236 | return 0; | |
237 | ||
bbaff08d RR |
238 | pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " |
239 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n", | |
240 | b->cpu, apic, b->bank, b->block, b->address, hi, lo); | |
241 | return 0; | |
242 | } | |
243 | ||
244 | return 1; | |
245 | }; | |
246 | ||
ea2ca36b | 247 | /* Reprogram MCx_MISC MSR behind this threshold bank. */ |
a6b6a14e | 248 | static void threshold_restart_bank(void *_tr) |
89b831ef | 249 | { |
4cd4601d | 250 | struct thresh_restart *tr = _tr; |
7203a049 | 251 | u32 hi, lo; |
89b831ef | 252 | |
7203a049 | 253 | rdmsr(tr->b->address, lo, hi); |
89b831ef | 254 | |
7203a049 | 255 | if (tr->b->threshold_limit < (hi & THRESHOLD_MAX)) |
4cd4601d | 256 | tr->reset = 1; /* limit cannot be lower than err count */ |
89b831ef | 257 | |
4cd4601d | 258 | if (tr->reset) { /* reset err count and overflow bit */ |
7203a049 RR |
259 | hi = |
260 | (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) | | |
4cd4601d MT |
261 | (THRESHOLD_MAX - tr->b->threshold_limit); |
262 | } else if (tr->old_limit) { /* change limit w/o reset */ | |
7203a049 | 263 | int new_count = (hi & THRESHOLD_MAX) + |
4cd4601d | 264 | (tr->old_limit - tr->b->threshold_limit); |
1cb2a8e1 | 265 | |
7203a049 | 266 | hi = (hi & ~MASK_ERR_COUNT_HI) | |
89b831ef JS |
267 | (new_count & THRESHOLD_MAX); |
268 | } | |
269 | ||
f227d430 BP |
270 | /* clear IntType */ |
271 | hi &= ~MASK_INT_TYPE_HI; | |
272 | ||
273 | if (!tr->b->interrupt_capable) | |
274 | goto done; | |
275 | ||
9c37c9d8 | 276 | if (tr->set_lvt_off) { |
bbaff08d RR |
277 | if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) { |
278 | /* set new lvt offset */ | |
279 | hi &= ~MASK_LVTOFF_HI; | |
280 | hi |= tr->lvt_off << 20; | |
281 | } | |
9c37c9d8 RR |
282 | } |
283 | ||
f227d430 BP |
284 | if (tr->b->interrupt_enable) |
285 | hi |= INT_TYPE_APIC; | |
286 | ||
287 | done: | |
89b831ef | 288 | |
7203a049 RR |
289 | hi |= MASK_COUNT_EN_HI; |
290 | wrmsr(tr->b->address, lo, hi); | |
89b831ef JS |
291 | } |
292 | ||
9c37c9d8 RR |
293 | static void mce_threshold_block_init(struct threshold_block *b, int offset) |
294 | { | |
295 | struct thresh_restart tr = { | |
296 | .b = b, | |
297 | .set_lvt_off = 1, | |
298 | .lvt_off = offset, | |
299 | }; | |
300 | ||
301 | b->threshold_limit = THRESHOLD_MAX; | |
302 | threshold_restart_bank(&tr); | |
303 | }; | |
304 | ||
868c00bb | 305 | static int setup_APIC_mce_threshold(int reserved, int new) |
bbaff08d RR |
306 | { |
307 | if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR, | |
308 | APIC_EILVT_MSG_FIX, 0)) | |
309 | return new; | |
310 | ||
311 | return reserved; | |
312 | } | |
313 | ||
24fd78a8 AG |
314 | static int setup_APIC_deferred_error(int reserved, int new) |
315 | { | |
316 | if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR, | |
317 | APIC_EILVT_MSG_FIX, 0)) | |
318 | return new; | |
319 | ||
320 | return reserved; | |
321 | } | |
322 | ||
323 | static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) | |
324 | { | |
325 | u32 low = 0, high = 0; | |
326 | int def_offset = -1, def_new; | |
327 | ||
328 | if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) | |
329 | return; | |
330 | ||
331 | def_new = (low & MASK_DEF_LVTOFF) >> 4; | |
332 | if (!(low & MASK_DEF_LVTOFF)) { | |
333 | pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n"); | |
334 | def_new = DEF_LVT_OFF; | |
335 | low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4); | |
336 | } | |
337 | ||
338 | def_offset = setup_APIC_deferred_error(def_offset, def_new); | |
339 | if ((def_offset == def_new) && | |
340 | (deferred_error_int_vector != amd_deferred_error_interrupt)) | |
341 | deferred_error_int_vector = amd_deferred_error_interrupt; | |
342 | ||
343 | low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; | |
344 | wrmsr(MSR_CU_DEF_ERR, low, high); | |
345 | } | |
346 | ||
cfee4f6f | 347 | static u32 get_block_address(unsigned int cpu, u32 current_addr, u32 low, u32 high, |
8dd1e17a AG |
348 | unsigned int bank, unsigned int block) |
349 | { | |
350 | u32 addr = 0, offset = 0; | |
351 | ||
352 | if (mce_flags.smca) { | |
353 | if (!block) { | |
354 | addr = MSR_AMD64_SMCA_MCx_MISC(bank); | |
355 | } else { | |
356 | /* | |
357 | * For SMCA enabled processors, BLKPTR field of the | |
358 | * first MISC register (MCx_MISC0) indicates presence of | |
359 | * additional MISC register set (MISC1-4). | |
360 | */ | |
361 | u32 low, high; | |
362 | ||
cfee4f6f | 363 | if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) |
8dd1e17a AG |
364 | return addr; |
365 | ||
366 | if (!(low & MCI_CONFIG_MCAX)) | |
367 | return addr; | |
368 | ||
cfee4f6f | 369 | if (!rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) && |
8dd1e17a AG |
370 | (low & MASK_BLKPTR_LO)) |
371 | addr = MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); | |
372 | } | |
373 | return addr; | |
374 | } | |
375 | ||
376 | /* Fall back to method we used for older processors: */ | |
377 | switch (block) { | |
378 | case 0: | |
d9d73fcc | 379 | addr = msr_ops.misc(bank); |
8dd1e17a AG |
380 | break; |
381 | case 1: | |
382 | offset = ((low & MASK_BLKPTR_LO) >> 21); | |
383 | if (offset) | |
384 | addr = MCG_XBLK_ADDR + offset; | |
385 | break; | |
386 | default: | |
387 | addr = ++current_addr; | |
388 | } | |
389 | return addr; | |
390 | } | |
391 | ||
429893b1 BP |
392 | static int |
393 | prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, | |
394 | int offset, u32 misc_high) | |
395 | { | |
396 | unsigned int cpu = smp_processor_id(); | |
e128b4f4 | 397 | u32 smca_low, smca_high, smca_addr; |
429893b1 BP |
398 | struct threshold_block b; |
399 | int new; | |
400 | ||
401 | if (!block) | |
402 | per_cpu(bank_map, cpu) |= (1 << bank); | |
403 | ||
404 | memset(&b, 0, sizeof(b)); | |
405 | b.cpu = cpu; | |
406 | b.bank = bank; | |
407 | b.block = block; | |
408 | b.address = addr; | |
409 | b.interrupt_capable = lvt_interrupt_supported(bank, misc_high); | |
410 | ||
411 | if (!b.interrupt_capable) | |
412 | goto done; | |
413 | ||
414 | b.interrupt_enable = 1; | |
415 | ||
e128b4f4 BP |
416 | if (!mce_flags.smca) { |
417 | new = (misc_high & MASK_LVTOFF_HI) >> 20; | |
418 | goto set_offset; | |
419 | } | |
32544f06 | 420 | |
e128b4f4 | 421 | smca_addr = MSR_AMD64_SMCA_MCx_CONFIG(bank); |
32544f06 | 422 | |
e128b4f4 BP |
423 | if (!rdmsr_safe(smca_addr, &smca_low, &smca_high)) { |
424 | /* | |
425 | * OS is required to set the MCAX bit to acknowledge that it is | |
426 | * now using the new MSR ranges and new registers under each | |
427 | * bank. It also means that the OS will configure deferred | |
428 | * errors in the new MCx_CONFIG register. If the bit is not set, | |
429 | * uncorrectable errors will cause a system panic. | |
430 | * | |
431 | * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.) | |
432 | */ | |
433 | smca_high |= BIT(0); | |
429893b1 | 434 | |
e128b4f4 BP |
435 | /* |
436 | * SMCA logs Deferred Error information in MCA_DE{STAT,ADDR} | |
437 | * registers with the option of additionally logging to | |
438 | * MCA_{STATUS,ADDR} if MCA_CONFIG[LogDeferredInMcaStat] is set. | |
439 | * | |
440 | * This bit is usually set by BIOS to retain the old behavior | |
441 | * for OSes that don't use the new registers. Linux supports the | |
442 | * new registers so let's disable that additional logging here. | |
443 | * | |
444 | * MCA_CONFIG[LogDeferredInMcaStat] is bit 34 (bit 2 in the high | |
445 | * portion of the MSR). | |
446 | */ | |
447 | smca_high &= ~BIT(2); | |
429893b1 | 448 | |
e128b4f4 | 449 | wrmsr(smca_addr, smca_low, smca_high); |
429893b1 BP |
450 | } |
451 | ||
e128b4f4 BP |
452 | /* Gather LVT offset for thresholding: */ |
453 | if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high)) | |
454 | goto out; | |
455 | ||
456 | new = (smca_low & SMCA_THR_LVT_OFF) >> 12; | |
457 | ||
458 | set_offset: | |
429893b1 BP |
459 | offset = setup_APIC_mce_threshold(offset, new); |
460 | ||
461 | if ((offset == new) && (mce_threshold_vector != amd_threshold_interrupt)) | |
462 | mce_threshold_vector = amd_threshold_interrupt; | |
463 | ||
464 | done: | |
465 | mce_threshold_block_init(&b, offset); | |
466 | ||
467 | out: | |
468 | return offset; | |
469 | } | |
470 | ||
95268664 | 471 | /* cpu init entry point, called from mce.c with preempt off */ |
cc3ca220 | 472 | void mce_amd_feature_init(struct cpuinfo_x86 *c) |
89b831ef | 473 | { |
95268664 | 474 | u32 low = 0, high = 0, address = 0; |
cfee4f6f | 475 | unsigned int bank, block, cpu = smp_processor_id(); |
429893b1 | 476 | int offset = -1; |
89b831ef | 477 | |
bafcdd3b | 478 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
5896820e YG |
479 | if (mce_flags.smca) |
480 | get_smca_bank_info(bank); | |
481 | ||
95268664 | 482 | for (block = 0; block < NR_BLOCKS; ++block) { |
cfee4f6f | 483 | address = get_block_address(cpu, address, low, high, bank, block); |
8dd1e17a AG |
484 | if (!address) |
485 | break; | |
95268664 JS |
486 | |
487 | if (rdmsr_safe(address, &low, &high)) | |
24ce0e96 | 488 | break; |
95268664 | 489 | |
6dcbfe4f BP |
490 | if (!(high & MASK_VALID_HI)) |
491 | continue; | |
95268664 | 492 | |
24ce0e96 JB |
493 | if (!(high & MASK_CNTP_HI) || |
494 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
495 | continue; |
496 | ||
429893b1 | 497 | offset = prepare_threshold_block(bank, block, address, offset, high); |
95268664 | 498 | } |
89b831ef | 499 | } |
24fd78a8 AG |
500 | |
501 | if (mce_flags.succor) | |
502 | deferred_error_interrupt_enable(c); | |
89b831ef JS |
503 | } |
504 | ||
34102009 YG |
505 | static void |
506 | __log_error(unsigned int bank, bool deferred_err, bool threshold_err, u64 misc) | |
afdf344e | 507 | { |
34102009 YG |
508 | u32 msr_status = msr_ops.status(bank); |
509 | u32 msr_addr = msr_ops.addr(bank); | |
afdf344e AG |
510 | struct mce m; |
511 | u64 status; | |
512 | ||
34102009 YG |
513 | WARN_ON_ONCE(deferred_err && threshold_err); |
514 | ||
515 | if (deferred_err && mce_flags.smca) { | |
516 | msr_status = MSR_AMD64_SMCA_MCx_DESTAT(bank); | |
517 | msr_addr = MSR_AMD64_SMCA_MCx_DEADDR(bank); | |
518 | } | |
519 | ||
520 | rdmsrl(msr_status, status); | |
521 | ||
afdf344e AG |
522 | if (!(status & MCI_STATUS_VAL)) |
523 | return; | |
524 | ||
525 | mce_setup(&m); | |
526 | ||
527 | m.status = status; | |
528 | m.bank = bank; | |
6e6e746e | 529 | |
afdf344e AG |
530 | if (threshold_err) |
531 | m.misc = misc; | |
532 | ||
6e6e746e | 533 | if (m.status & MCI_STATUS_ADDRV) |
34102009 | 534 | rdmsrl(msr_addr, m.addr); |
afdf344e | 535 | |
db819d60 YG |
536 | if (mce_flags.smca && (m.status & MCI_STATUS_SYNDV)) |
537 | rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd); | |
538 | ||
6e6e746e | 539 | mce_log(&m); |
34102009 YG |
540 | |
541 | wrmsrl(msr_status, 0); | |
afdf344e AG |
542 | } |
543 | ||
24fd78a8 AG |
544 | static inline void __smp_deferred_error_interrupt(void) |
545 | { | |
546 | inc_irq_stat(irq_deferred_error_count); | |
547 | deferred_error_int_vector(); | |
548 | } | |
549 | ||
550 | asmlinkage __visible void smp_deferred_error_interrupt(void) | |
551 | { | |
552 | entering_irq(); | |
553 | __smp_deferred_error_interrupt(); | |
554 | exiting_ack_irq(); | |
555 | } | |
556 | ||
557 | asmlinkage __visible void smp_trace_deferred_error_interrupt(void) | |
558 | { | |
559 | entering_irq(); | |
560 | trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR); | |
561 | __smp_deferred_error_interrupt(); | |
562 | trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR); | |
563 | exiting_ack_irq(); | |
564 | } | |
565 | ||
566 | /* APIC interrupt handler for deferred errors */ | |
567 | static void amd_deferred_error_interrupt(void) | |
568 | { | |
24fd78a8 | 569 | unsigned int bank; |
34102009 YG |
570 | u32 msr_status; |
571 | u64 status; | |
24fd78a8 AG |
572 | |
573 | for (bank = 0; bank < mca_cfg.banks; ++bank) { | |
34102009 YG |
574 | msr_status = (mce_flags.smca) ? MSR_AMD64_SMCA_MCx_DESTAT(bank) |
575 | : msr_ops.status(bank); | |
576 | ||
577 | rdmsrl(msr_status, status); | |
24fd78a8 AG |
578 | |
579 | if (!(status & MCI_STATUS_VAL) || | |
580 | !(status & MCI_STATUS_DEFERRED)) | |
581 | continue; | |
582 | ||
34102009 | 583 | __log_error(bank, true, false, 0); |
24fd78a8 AG |
584 | break; |
585 | } | |
586 | } | |
587 | ||
89b831ef JS |
588 | /* |
589 | * APIC Interrupt Handler | |
590 | */ | |
591 | ||
592 | /* | |
593 | * threshold interrupt handler will service THRESHOLD_APIC_VECTOR. | |
594 | * the interrupt goes off when error_count reaches threshold_limit. | |
595 | * the handler will simply log mcelog w/ software defined bank number. | |
596 | */ | |
afdf344e | 597 | |
b2762686 | 598 | static void amd_threshold_interrupt(void) |
89b831ef | 599 | { |
1cb2a8e1 | 600 | u32 low = 0, high = 0, address = 0; |
cfee4f6f | 601 | unsigned int bank, block, cpu = smp_processor_id(); |
89b831ef | 602 | |
89b831ef | 603 | /* assume first bank caused it */ |
bafcdd3b | 604 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
44612a3a | 605 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
24ce0e96 | 606 | continue; |
95268664 | 607 | for (block = 0; block < NR_BLOCKS; ++block) { |
cfee4f6f | 608 | address = get_block_address(cpu, address, low, high, bank, block); |
8dd1e17a AG |
609 | if (!address) |
610 | break; | |
95268664 JS |
611 | |
612 | if (rdmsr_safe(address, &low, &high)) | |
24ce0e96 | 613 | break; |
95268664 JS |
614 | |
615 | if (!(high & MASK_VALID_HI)) { | |
616 | if (block) | |
617 | continue; | |
618 | else | |
619 | break; | |
620 | } | |
621 | ||
24ce0e96 JB |
622 | if (!(high & MASK_CNTP_HI) || |
623 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
624 | continue; |
625 | ||
1cb2a8e1 IM |
626 | /* |
627 | * Log the machine check that caused the threshold | |
628 | * event. | |
629 | */ | |
44612a3a CY |
630 | if (high & MASK_OVERFLOW_HI) |
631 | goto log; | |
89b831ef JS |
632 | } |
633 | } | |
44612a3a CY |
634 | return; |
635 | ||
636 | log: | |
34102009 | 637 | __log_error(bank, false, true, ((u64)high << 32) | low); |
89b831ef JS |
638 | } |
639 | ||
640 | /* | |
641 | * Sysfs Interface | |
642 | */ | |
643 | ||
89b831ef | 644 | struct threshold_attr { |
2903ee85 | 645 | struct attribute attr; |
1cb2a8e1 IM |
646 | ssize_t (*show) (struct threshold_block *, char *); |
647 | ssize_t (*store) (struct threshold_block *, const char *, size_t count); | |
89b831ef JS |
648 | }; |
649 | ||
1cb2a8e1 IM |
650 | #define SHOW_FIELDS(name) \ |
651 | static ssize_t show_ ## name(struct threshold_block *b, char *buf) \ | |
652 | { \ | |
18c20f37 | 653 | return sprintf(buf, "%lu\n", (unsigned long) b->name); \ |
2903ee85 | 654 | } |
89b831ef JS |
655 | SHOW_FIELDS(interrupt_enable) |
656 | SHOW_FIELDS(threshold_limit) | |
657 | ||
1cb2a8e1 | 658 | static ssize_t |
9319cec8 | 659 | store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size) |
89b831ef | 660 | { |
4cd4601d | 661 | struct thresh_restart tr; |
1cb2a8e1 | 662 | unsigned long new; |
1cb2a8e1 | 663 | |
f227d430 BP |
664 | if (!b->interrupt_capable) |
665 | return -EINVAL; | |
666 | ||
164109e3 | 667 | if (kstrtoul(buf, 0, &new) < 0) |
89b831ef | 668 | return -EINVAL; |
1cb2a8e1 | 669 | |
89b831ef JS |
670 | b->interrupt_enable = !!new; |
671 | ||
9c37c9d8 | 672 | memset(&tr, 0, sizeof(tr)); |
1cb2a8e1 | 673 | tr.b = b; |
1cb2a8e1 | 674 | |
a6b6a14e | 675 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef | 676 | |
9319cec8 | 677 | return size; |
89b831ef JS |
678 | } |
679 | ||
1cb2a8e1 | 680 | static ssize_t |
9319cec8 | 681 | store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) |
89b831ef | 682 | { |
4cd4601d | 683 | struct thresh_restart tr; |
1cb2a8e1 | 684 | unsigned long new; |
1cb2a8e1 | 685 | |
164109e3 | 686 | if (kstrtoul(buf, 0, &new) < 0) |
89b831ef | 687 | return -EINVAL; |
1cb2a8e1 | 688 | |
89b831ef JS |
689 | if (new > THRESHOLD_MAX) |
690 | new = THRESHOLD_MAX; | |
691 | if (new < 1) | |
692 | new = 1; | |
1cb2a8e1 | 693 | |
9c37c9d8 | 694 | memset(&tr, 0, sizeof(tr)); |
4cd4601d | 695 | tr.old_limit = b->threshold_limit; |
89b831ef | 696 | b->threshold_limit = new; |
4cd4601d | 697 | tr.b = b; |
89b831ef | 698 | |
a6b6a14e | 699 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef | 700 | |
9319cec8 | 701 | return size; |
89b831ef JS |
702 | } |
703 | ||
4cd4601d MT |
704 | static ssize_t show_error_count(struct threshold_block *b, char *buf) |
705 | { | |
2c9c42fa BP |
706 | u32 lo, hi; |
707 | ||
708 | rdmsr_on_cpu(b->cpu, b->address, &lo, &hi); | |
a6b6a14e | 709 | |
2c9c42fa BP |
710 | return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - |
711 | (THRESHOLD_MAX - b->threshold_limit))); | |
89b831ef JS |
712 | } |
713 | ||
6e927361 BP |
714 | static struct threshold_attr error_count = { |
715 | .attr = {.name = __stringify(error_count), .mode = 0444 }, | |
716 | .show = show_error_count, | |
717 | }; | |
89b831ef | 718 | |
34fa1967 HS |
719 | #define RW_ATTR(val) \ |
720 | static struct threshold_attr val = { \ | |
721 | .attr = {.name = __stringify(val), .mode = 0644 }, \ | |
722 | .show = show_## val, \ | |
723 | .store = store_## val, \ | |
89b831ef JS |
724 | }; |
725 | ||
2903ee85 JS |
726 | RW_ATTR(interrupt_enable); |
727 | RW_ATTR(threshold_limit); | |
89b831ef JS |
728 | |
729 | static struct attribute *default_attrs[] = { | |
89b831ef JS |
730 | &threshold_limit.attr, |
731 | &error_count.attr, | |
d26ecc48 BP |
732 | NULL, /* possibly interrupt_enable if supported, see below */ |
733 | NULL, | |
89b831ef JS |
734 | }; |
735 | ||
1cb2a8e1 IM |
736 | #define to_block(k) container_of(k, struct threshold_block, kobj) |
737 | #define to_attr(a) container_of(a, struct threshold_attr, attr) | |
89b831ef JS |
738 | |
739 | static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) | |
740 | { | |
95268664 | 741 | struct threshold_block *b = to_block(kobj); |
89b831ef JS |
742 | struct threshold_attr *a = to_attr(attr); |
743 | ssize_t ret; | |
1cb2a8e1 | 744 | |
89b831ef | 745 | ret = a->show ? a->show(b, buf) : -EIO; |
1cb2a8e1 | 746 | |
89b831ef JS |
747 | return ret; |
748 | } | |
749 | ||
750 | static ssize_t store(struct kobject *kobj, struct attribute *attr, | |
751 | const char *buf, size_t count) | |
752 | { | |
95268664 | 753 | struct threshold_block *b = to_block(kobj); |
89b831ef JS |
754 | struct threshold_attr *a = to_attr(attr); |
755 | ssize_t ret; | |
1cb2a8e1 | 756 | |
89b831ef | 757 | ret = a->store ? a->store(b, buf, count) : -EIO; |
1cb2a8e1 | 758 | |
89b831ef JS |
759 | return ret; |
760 | } | |
761 | ||
52cf25d0 | 762 | static const struct sysfs_ops threshold_ops = { |
1cb2a8e1 IM |
763 | .show = show, |
764 | .store = store, | |
89b831ef JS |
765 | }; |
766 | ||
767 | static struct kobj_type threshold_ktype = { | |
1cb2a8e1 IM |
768 | .sysfs_ops = &threshold_ops, |
769 | .default_attrs = default_attrs, | |
89b831ef JS |
770 | }; |
771 | ||
148f9bb8 PG |
772 | static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank, |
773 | unsigned int block, u32 address) | |
95268664 | 774 | { |
95268664 | 775 | struct threshold_block *b = NULL; |
1cb2a8e1 IM |
776 | u32 low, high; |
777 | int err; | |
95268664 | 778 | |
bafcdd3b | 779 | if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS)) |
95268664 JS |
780 | return 0; |
781 | ||
a6b6a14e | 782 | if (rdmsr_safe_on_cpu(cpu, address, &low, &high)) |
24ce0e96 | 783 | return 0; |
95268664 JS |
784 | |
785 | if (!(high & MASK_VALID_HI)) { | |
786 | if (block) | |
787 | goto recurse; | |
788 | else | |
789 | return 0; | |
790 | } | |
791 | ||
24ce0e96 JB |
792 | if (!(high & MASK_CNTP_HI) || |
793 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
794 | goto recurse; |
795 | ||
796 | b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL); | |
797 | if (!b) | |
798 | return -ENOMEM; | |
95268664 | 799 | |
1cb2a8e1 IM |
800 | b->block = block; |
801 | b->bank = bank; | |
802 | b->cpu = cpu; | |
803 | b->address = address; | |
804 | b->interrupt_enable = 0; | |
f227d430 | 805 | b->interrupt_capable = lvt_interrupt_supported(bank, high); |
1cb2a8e1 | 806 | b->threshold_limit = THRESHOLD_MAX; |
95268664 | 807 | |
d79f931f | 808 | if (b->interrupt_capable) { |
d26ecc48 | 809 | threshold_ktype.default_attrs[2] = &interrupt_enable.attr; |
d79f931f AG |
810 | b->interrupt_enable = 1; |
811 | } else { | |
d26ecc48 | 812 | threshold_ktype.default_attrs[2] = NULL; |
d79f931f | 813 | } |
d26ecc48 | 814 | |
95268664 JS |
815 | INIT_LIST_HEAD(&b->miscj); |
816 | ||
1cb2a8e1 | 817 | if (per_cpu(threshold_banks, cpu)[bank]->blocks) { |
95268664 JS |
818 | list_add(&b->miscj, |
819 | &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj); | |
1cb2a8e1 | 820 | } else { |
95268664 | 821 | per_cpu(threshold_banks, cpu)[bank]->blocks = b; |
1cb2a8e1 | 822 | } |
95268664 | 823 | |
542eb75a GKH |
824 | err = kobject_init_and_add(&b->kobj, &threshold_ktype, |
825 | per_cpu(threshold_banks, cpu)[bank]->kobj, | |
336d335a | 826 | (bank == 4 ? bank4_names(b) : th_names[bank])); |
95268664 JS |
827 | if (err) |
828 | goto out_free; | |
829 | recurse: | |
cfee4f6f | 830 | address = get_block_address(cpu, address, low, high, bank, ++block); |
8dd1e17a AG |
831 | if (!address) |
832 | return 0; | |
95268664 | 833 | |
8dd1e17a | 834 | err = allocate_threshold_blocks(cpu, bank, block, address); |
95268664 JS |
835 | if (err) |
836 | goto out_free; | |
837 | ||
213eca7f GKH |
838 | if (b) |
839 | kobject_uevent(&b->kobj, KOBJ_ADD); | |
542eb75a | 840 | |
95268664 JS |
841 | return err; |
842 | ||
843 | out_free: | |
844 | if (b) { | |
38a382ae | 845 | kobject_put(&b->kobj); |
d9a5ac9e | 846 | list_del(&b->miscj); |
95268664 JS |
847 | kfree(b); |
848 | } | |
849 | return err; | |
850 | } | |
851 | ||
148f9bb8 | 852 | static int __threshold_add_blocks(struct threshold_bank *b) |
019f34fc BP |
853 | { |
854 | struct list_head *head = &b->blocks->miscj; | |
855 | struct threshold_block *pos = NULL; | |
856 | struct threshold_block *tmp = NULL; | |
857 | int err = 0; | |
858 | ||
859 | err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name); | |
860 | if (err) | |
861 | return err; | |
862 | ||
863 | list_for_each_entry_safe(pos, tmp, head, miscj) { | |
864 | ||
865 | err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name); | |
866 | if (err) { | |
867 | list_for_each_entry_safe_reverse(pos, tmp, head, miscj) | |
868 | kobject_del(&pos->kobj); | |
869 | ||
870 | return err; | |
871 | } | |
872 | } | |
873 | return err; | |
874 | } | |
875 | ||
148f9bb8 | 876 | static int threshold_create_bank(unsigned int cpu, unsigned int bank) |
89b831ef | 877 | { |
d6126ef5 | 878 | struct device *dev = per_cpu(mce_device, cpu); |
019f34fc | 879 | struct amd_northbridge *nb = NULL; |
92e26e2a | 880 | struct threshold_bank *b = NULL; |
336d335a | 881 | const char *name = th_names[bank]; |
92e26e2a | 882 | int err = 0; |
95268664 | 883 | |
c76e8164 | 884 | if (is_shared_bank(bank)) { |
019f34fc | 885 | nb = node_to_amd_nb(amd_get_nb_id(cpu)); |
019f34fc BP |
886 | |
887 | /* threshold descriptor already initialized on this node? */ | |
21c5e50e | 888 | if (nb && nb->bank4) { |
019f34fc BP |
889 | /* yes, use it */ |
890 | b = nb->bank4; | |
891 | err = kobject_add(b->kobj, &dev->kobj, name); | |
892 | if (err) | |
893 | goto out; | |
894 | ||
895 | per_cpu(threshold_banks, cpu)[bank] = b; | |
896 | atomic_inc(&b->cpus); | |
897 | ||
898 | err = __threshold_add_blocks(b); | |
899 | ||
900 | goto out; | |
901 | } | |
902 | } | |
903 | ||
95268664 | 904 | b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL); |
89b831ef JS |
905 | if (!b) { |
906 | err = -ENOMEM; | |
907 | goto out; | |
908 | } | |
89b831ef | 909 | |
e032d807 | 910 | b->kobj = kobject_create_and_add(name, &dev->kobj); |
92e26e2a BP |
911 | if (!b->kobj) { |
912 | err = -EINVAL; | |
a521cf20 | 913 | goto out_free; |
92e26e2a | 914 | } |
95268664 | 915 | |
89b831ef | 916 | per_cpu(threshold_banks, cpu)[bank] = b; |
95268664 | 917 | |
c76e8164 | 918 | if (is_shared_bank(bank)) { |
019f34fc BP |
919 | atomic_set(&b->cpus, 1); |
920 | ||
921 | /* nb is already initialized, see above */ | |
21c5e50e DB |
922 | if (nb) { |
923 | WARN_ON(nb->bank4); | |
924 | nb->bank4 = b; | |
925 | } | |
019f34fc BP |
926 | } |
927 | ||
74ab0e7a | 928 | err = allocate_threshold_blocks(cpu, bank, 0, msr_ops.misc(bank)); |
92e26e2a BP |
929 | if (!err) |
930 | goto out; | |
95268664 | 931 | |
019f34fc | 932 | out_free: |
95268664 | 933 | kfree(b); |
019f34fc BP |
934 | |
935 | out: | |
89b831ef JS |
936 | return err; |
937 | } | |
938 | ||
939 | /* create dir/files for all valid threshold banks */ | |
148f9bb8 | 940 | static int threshold_create_device(unsigned int cpu) |
89b831ef | 941 | { |
2903ee85 | 942 | unsigned int bank; |
bafcdd3b | 943 | struct threshold_bank **bp; |
89b831ef JS |
944 | int err = 0; |
945 | ||
bafcdd3b BO |
946 | bp = kzalloc(sizeof(struct threshold_bank *) * mca_cfg.banks, |
947 | GFP_KERNEL); | |
948 | if (!bp) | |
949 | return -ENOMEM; | |
950 | ||
951 | per_cpu(threshold_banks, cpu) = bp; | |
952 | ||
953 | for (bank = 0; bank < mca_cfg.banks; ++bank) { | |
5a96f4a5 | 954 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
89b831ef JS |
955 | continue; |
956 | err = threshold_create_bank(cpu, bank); | |
957 | if (err) | |
0a17941e | 958 | return err; |
89b831ef | 959 | } |
0a17941e | 960 | |
89b831ef JS |
961 | return err; |
962 | } | |
963 | ||
be6b5a35 | 964 | static void deallocate_threshold_block(unsigned int cpu, |
95268664 JS |
965 | unsigned int bank) |
966 | { | |
967 | struct threshold_block *pos = NULL; | |
968 | struct threshold_block *tmp = NULL; | |
969 | struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank]; | |
970 | ||
971 | if (!head) | |
972 | return; | |
973 | ||
974 | list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) { | |
38a382ae | 975 | kobject_put(&pos->kobj); |
95268664 JS |
976 | list_del(&pos->miscj); |
977 | kfree(pos); | |
978 | } | |
979 | ||
980 | kfree(per_cpu(threshold_banks, cpu)[bank]->blocks); | |
981 | per_cpu(threshold_banks, cpu)[bank]->blocks = NULL; | |
982 | } | |
983 | ||
019f34fc BP |
984 | static void __threshold_remove_blocks(struct threshold_bank *b) |
985 | { | |
986 | struct threshold_block *pos = NULL; | |
987 | struct threshold_block *tmp = NULL; | |
988 | ||
989 | kobject_del(b->kobj); | |
990 | ||
991 | list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj) | |
992 | kobject_del(&pos->kobj); | |
993 | } | |
994 | ||
be6b5a35 | 995 | static void threshold_remove_bank(unsigned int cpu, int bank) |
89b831ef | 996 | { |
019f34fc | 997 | struct amd_northbridge *nb; |
89b831ef | 998 | struct threshold_bank *b; |
89b831ef JS |
999 | |
1000 | b = per_cpu(threshold_banks, cpu)[bank]; | |
1001 | if (!b) | |
1002 | return; | |
019f34fc | 1003 | |
95268664 JS |
1004 | if (!b->blocks) |
1005 | goto free_out; | |
1006 | ||
c76e8164 | 1007 | if (is_shared_bank(bank)) { |
019f34fc BP |
1008 | if (!atomic_dec_and_test(&b->cpus)) { |
1009 | __threshold_remove_blocks(b); | |
1010 | per_cpu(threshold_banks, cpu)[bank] = NULL; | |
1011 | return; | |
1012 | } else { | |
1013 | /* | |
1014 | * the last CPU on this node using the shared bank is | |
1015 | * going away, remove that bank now. | |
1016 | */ | |
1017 | nb = node_to_amd_nb(amd_get_nb_id(cpu)); | |
1018 | nb->bank4 = NULL; | |
1019 | } | |
1020 | } | |
1021 | ||
95268664 JS |
1022 | deallocate_threshold_block(cpu, bank); |
1023 | ||
1024 | free_out: | |
8735728e | 1025 | kobject_del(b->kobj); |
38a382ae | 1026 | kobject_put(b->kobj); |
95268664 JS |
1027 | kfree(b); |
1028 | per_cpu(threshold_banks, cpu)[bank] = NULL; | |
89b831ef JS |
1029 | } |
1030 | ||
be6b5a35 | 1031 | static void threshold_remove_device(unsigned int cpu) |
89b831ef | 1032 | { |
2903ee85 | 1033 | unsigned int bank; |
89b831ef | 1034 | |
bafcdd3b | 1035 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
5a96f4a5 | 1036 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
89b831ef JS |
1037 | continue; |
1038 | threshold_remove_bank(cpu, bank); | |
1039 | } | |
bafcdd3b | 1040 | kfree(per_cpu(threshold_banks, cpu)); |
89b831ef JS |
1041 | } |
1042 | ||
89b831ef | 1043 | /* get notified when a cpu comes on/off */ |
148f9bb8 | 1044 | static void |
1cb2a8e1 | 1045 | amd_64_threshold_cpu_callback(unsigned long action, unsigned int cpu) |
89b831ef | 1046 | { |
89b831ef JS |
1047 | switch (action) { |
1048 | case CPU_ONLINE: | |
8bb78442 | 1049 | case CPU_ONLINE_FROZEN: |
89b831ef | 1050 | threshold_create_device(cpu); |
89b831ef JS |
1051 | break; |
1052 | case CPU_DEAD: | |
8bb78442 | 1053 | case CPU_DEAD_FROZEN: |
89b831ef JS |
1054 | threshold_remove_device(cpu); |
1055 | break; | |
1056 | default: | |
1057 | break; | |
1058 | } | |
89b831ef JS |
1059 | } |
1060 | ||
89b831ef JS |
1061 | static __init int threshold_init_device(void) |
1062 | { | |
2903ee85 | 1063 | unsigned lcpu = 0; |
89b831ef | 1064 | |
89b831ef JS |
1065 | /* to hit CPUs online before the notifier is up */ |
1066 | for_each_online_cpu(lcpu) { | |
fff2e89f | 1067 | int err = threshold_create_device(lcpu); |
1cb2a8e1 | 1068 | |
89b831ef | 1069 | if (err) |
fff2e89f | 1070 | return err; |
89b831ef | 1071 | } |
8735728e | 1072 | threshold_cpu_callback = amd_64_threshold_cpu_callback; |
1cb2a8e1 | 1073 | |
fff2e89f | 1074 | return 0; |
89b831ef | 1075 | } |
a8fccdb0 LJ |
1076 | /* |
1077 | * there are 3 funcs which need to be _initcalled in a logic sequence: | |
1078 | * 1. xen_late_init_mcelog | |
1079 | * 2. mcheck_init_device | |
1080 | * 3. threshold_init_device | |
1081 | * | |
1082 | * xen_late_init_mcelog must register xen_mce_chrdev_device before | |
1083 | * native mce_chrdev_device registration if running under xen platform; | |
1084 | * | |
1085 | * mcheck_init_device should be inited before threshold_init_device to | |
1086 | * initialize mce_device, otherwise a NULL ptr dereference will cause panic. | |
1087 | * | |
1088 | * so we use following _initcalls | |
1089 | * 1. device_initcall(xen_late_init_mcelog); | |
1090 | * 2. device_initcall_sync(mcheck_init_device); | |
1091 | * 3. late_initcall(threshold_init_device); | |
1092 | * | |
1093 | * when running under xen, the initcall order is 1,2,3; | |
1094 | * on baremetal, we skip 1 and we do only 2 and 3. | |
1095 | */ | |
1096 | late_initcall(threshold_init_device); |