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Commit | Line | Data |
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89b831ef | 1 | /* |
ea2ca36b | 2 | * (c) 2005-2016 Advanced Micro Devices, Inc. |
89b831ef JS |
3 | * Your use of this code is subject to the terms and conditions of the |
4 | * GNU general public license version 2. See "COPYING" or | |
5 | * http://www.gnu.org/licenses/gpl.html | |
6 | * | |
7 | * Written by Jacob Shin - AMD, Inc. | |
e6d41e8c | 8 | * Maintained by: Borislav Petkov <bp@alien8.de> |
89b831ef | 9 | * |
3490c0e4 | 10 | * All MC4_MISCi registers are shared between cores on a node. |
89b831ef | 11 | */ |
89b831ef | 12 | #include <linux/interrupt.h> |
89b831ef | 13 | #include <linux/notifier.h> |
1cb2a8e1 | 14 | #include <linux/kobject.h> |
34fa1967 | 15 | #include <linux/percpu.h> |
1cb2a8e1 IM |
16 | #include <linux/errno.h> |
17 | #include <linux/sched.h> | |
89b831ef | 18 | #include <linux/sysfs.h> |
5a0e3ad6 | 19 | #include <linux/slab.h> |
1cb2a8e1 IM |
20 | #include <linux/init.h> |
21 | #include <linux/cpu.h> | |
22 | #include <linux/smp.h> | |
87a6d409 | 23 | #include <linux/string.h> |
1cb2a8e1 | 24 | |
019f34fc | 25 | #include <asm/amd_nb.h> |
89b831ef | 26 | #include <asm/apic.h> |
1cb2a8e1 | 27 | #include <asm/idle.h> |
89b831ef JS |
28 | #include <asm/mce.h> |
29 | #include <asm/msr.h> | |
24fd78a8 | 30 | #include <asm/trace/irq_vectors.h> |
89b831ef | 31 | |
60f116fc | 32 | #define NR_BLOCKS 5 |
2903ee85 JS |
33 | #define THRESHOLD_MAX 0xFFF |
34 | #define INT_TYPE_APIC 0x00020000 | |
35 | #define MASK_VALID_HI 0x80000000 | |
24ce0e96 JB |
36 | #define MASK_CNTP_HI 0x40000000 |
37 | #define MASK_LOCKED_HI 0x20000000 | |
2903ee85 JS |
38 | #define MASK_LVTOFF_HI 0x00F00000 |
39 | #define MASK_COUNT_EN_HI 0x00080000 | |
40 | #define MASK_INT_TYPE_HI 0x00060000 | |
41 | #define MASK_OVERFLOW_HI 0x00010000 | |
89b831ef | 42 | #define MASK_ERR_COUNT_HI 0x00000FFF |
95268664 JS |
43 | #define MASK_BLKPTR_LO 0xFF000000 |
44 | #define MCG_XBLK_ADDR 0xC0000400 | |
89b831ef | 45 | |
24fd78a8 AG |
46 | /* Deferred error settings */ |
47 | #define MSR_CU_DEF_ERR 0xC0000410 | |
48 | #define MASK_DEF_LVTOFF 0x000000F0 | |
49 | #define MASK_DEF_INT_TYPE 0x00000006 | |
50 | #define DEF_LVT_OFF 0x2 | |
51 | #define DEF_INT_TYPE_APIC 0x2 | |
52 | ||
f57a1f3c AG |
53 | /* Scalable MCA: */ |
54 | ||
55 | /* Threshold LVT offset is at MSR0xC0000410[15:12] */ | |
56 | #define SMCA_THR_LVT_OFF 0xF000 | |
57 | ||
336d335a BP |
58 | static const char * const th_names[] = { |
59 | "load_store", | |
60 | "insn_fetch", | |
61 | "combined_unit", | |
62 | "", | |
63 | "northbridge", | |
64 | "execution_unit", | |
65 | }; | |
66 | ||
87a6d409 YG |
67 | static const char * const smca_umc_block_names[] = { |
68 | "dram_ecc", | |
69 | "misc_umc" | |
70 | }; | |
71 | ||
5896820e YG |
72 | struct smca_bank_name smca_bank_names[] = { |
73 | [SMCA_LS] = { "load_store", "Load Store Unit" }, | |
74 | [SMCA_IF] = { "insn_fetch", "Instruction Fetch Unit" }, | |
75 | [SMCA_L2_CACHE] = { "l2_cache", "L2 Cache" }, | |
76 | [SMCA_DE] = { "decode_unit", "Decode Unit" }, | |
77 | [SMCA_EX] = { "execution_unit", "Execution Unit" }, | |
78 | [SMCA_FP] = { "floating_point", "Floating Point Unit" }, | |
79 | [SMCA_L3_CACHE] = { "l3_cache", "L3 Cache" }, | |
80 | [SMCA_CS] = { "coherent_slave", "Coherent Slave" }, | |
81 | [SMCA_PIE] = { "pie", "Power, Interrupts, etc." }, | |
82 | [SMCA_UMC] = { "umc", "Unified Memory Controller" }, | |
83 | [SMCA_PB] = { "param_block", "Parameter Block" }, | |
84 | [SMCA_PSP] = { "psp", "Platform Security Processor" }, | |
85 | [SMCA_SMU] = { "smu", "System Management Unit" }, | |
be0aec23 | 86 | }; |
5896820e YG |
87 | EXPORT_SYMBOL_GPL(smca_bank_names); |
88 | ||
89 | static struct smca_hwid_mcatype smca_hwid_mcatypes[] = { | |
90 | /* { bank_type, hwid_mcatype, xec_bitmap } */ | |
91 | ||
92 | /* ZN Core (HWID=0xB0) MCA types */ | |
93 | { SMCA_LS, HWID_MCATYPE(0xB0, 0x0), 0x1FFFEF }, | |
94 | { SMCA_IF, HWID_MCATYPE(0xB0, 0x1), 0x3FFF }, | |
95 | { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2), 0xF }, | |
96 | { SMCA_DE, HWID_MCATYPE(0xB0, 0x3), 0x1FF }, | |
97 | /* HWID 0xB0 MCATYPE 0x4 is Reserved */ | |
98 | { SMCA_EX, HWID_MCATYPE(0xB0, 0x5), 0x7FF }, | |
99 | { SMCA_FP, HWID_MCATYPE(0xB0, 0x6), 0x7F }, | |
100 | { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7), 0xFF }, | |
101 | ||
102 | /* Data Fabric MCA types */ | |
103 | { SMCA_CS, HWID_MCATYPE(0x2E, 0x0), 0x1FF }, | |
104 | { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1), 0xF }, | |
105 | ||
106 | /* Unified Memory Controller MCA type */ | |
107 | { SMCA_UMC, HWID_MCATYPE(0x96, 0x0), 0x3F }, | |
108 | ||
109 | /* Parameter Block MCA type */ | |
110 | { SMCA_PB, HWID_MCATYPE(0x05, 0x0), 0x1 }, | |
be0aec23 | 111 | |
5896820e YG |
112 | /* Platform Security Processor MCA type */ |
113 | { SMCA_PSP, HWID_MCATYPE(0xFF, 0x0), 0x1 }, | |
114 | ||
115 | /* System Management Unit MCA type */ | |
116 | { SMCA_SMU, HWID_MCATYPE(0x01, 0x0), 0x1 }, | |
be0aec23 | 117 | }; |
5896820e YG |
118 | |
119 | struct smca_bank_info smca_banks[MAX_NR_BANKS]; | |
120 | EXPORT_SYMBOL_GPL(smca_banks); | |
be0aec23 | 121 | |
87a6d409 YG |
122 | /* |
123 | * In SMCA enabled processors, we can have multiple banks for a given IP type. | |
124 | * So to define a unique name for each bank, we use a temp c-string to append | |
125 | * the MCA_IPID[InstanceId] to type's name in get_name(). | |
126 | * | |
127 | * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN | |
128 | * is greater than 8 plus 1 (for underscore) plus length of longest type name. | |
129 | */ | |
130 | #define MAX_MCATYPE_NAME_LEN 30 | |
131 | static char buf_mcatype[MAX_MCATYPE_NAME_LEN]; | |
132 | ||
bafcdd3b | 133 | static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks); |
955d1427 | 134 | static DEFINE_PER_CPU(unsigned int, bank_map); /* see which banks are on */ |
89b831ef | 135 | |
b2762686 | 136 | static void amd_threshold_interrupt(void); |
24fd78a8 AG |
137 | static void amd_deferred_error_interrupt(void); |
138 | ||
139 | static void default_deferred_error_interrupt(void) | |
140 | { | |
141 | pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR); | |
142 | } | |
143 | void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; | |
b2762686 | 144 | |
89b831ef JS |
145 | /* |
146 | * CPU Initialization | |
147 | */ | |
148 | ||
5896820e YG |
149 | static void get_smca_bank_info(unsigned int bank) |
150 | { | |
151 | unsigned int i, hwid_mcatype, cpu = smp_processor_id(); | |
152 | struct smca_hwid_mcatype *type; | |
153 | u32 high, instanceId; | |
154 | u16 hwid, mcatype; | |
155 | ||
156 | /* Collect bank_info using CPU 0 for now. */ | |
157 | if (cpu) | |
158 | return; | |
159 | ||
160 | if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_IPID(bank), &instanceId, &high)) { | |
161 | pr_warn("Failed to read MCA_IPID for bank %d\n", bank); | |
162 | return; | |
163 | } | |
164 | ||
165 | hwid = high & MCI_IPID_HWID; | |
166 | mcatype = (high & MCI_IPID_MCATYPE) >> 16; | |
167 | hwid_mcatype = HWID_MCATYPE(hwid, mcatype); | |
168 | ||
169 | for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) { | |
170 | type = &smca_hwid_mcatypes[i]; | |
171 | if (hwid_mcatype == type->hwid_mcatype) { | |
172 | smca_banks[bank].type = type; | |
173 | smca_banks[bank].type_instance = instanceId; | |
174 | break; | |
175 | } | |
176 | } | |
177 | } | |
178 | ||
4cd4601d | 179 | struct thresh_restart { |
1cb2a8e1 IM |
180 | struct threshold_block *b; |
181 | int reset; | |
9c37c9d8 RR |
182 | int set_lvt_off; |
183 | int lvt_off; | |
1cb2a8e1 | 184 | u16 old_limit; |
4cd4601d MT |
185 | }; |
186 | ||
c76e8164 BO |
187 | static inline bool is_shared_bank(int bank) |
188 | { | |
284b965c AG |
189 | /* |
190 | * Scalable MCA provides for only one core to have access to the MSRs of | |
191 | * a shared bank. | |
192 | */ | |
193 | if (mce_flags.smca) | |
194 | return false; | |
195 | ||
c76e8164 BO |
196 | /* Bank 4 is for northbridge reporting and is thus shared */ |
197 | return (bank == 4); | |
198 | } | |
199 | ||
2cd4c303 | 200 | static const char *bank4_names(const struct threshold_block *b) |
336d335a BP |
201 | { |
202 | switch (b->address) { | |
203 | /* MSR4_MISC0 */ | |
204 | case 0x00000413: | |
205 | return "dram"; | |
206 | ||
207 | case 0xc0000408: | |
208 | return "ht_links"; | |
209 | ||
210 | case 0xc0000409: | |
211 | return "l3_cache"; | |
212 | ||
213 | default: | |
214 | WARN(1, "Funny MSR: 0x%08x\n", b->address); | |
215 | return ""; | |
216 | } | |
217 | }; | |
218 | ||
219 | ||
f227d430 BP |
220 | static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) |
221 | { | |
222 | /* | |
223 | * bank 4 supports APIC LVT interrupts implicitly since forever. | |
224 | */ | |
225 | if (bank == 4) | |
226 | return true; | |
227 | ||
228 | /* | |
229 | * IntP: interrupt present; if this bit is set, the thresholding | |
230 | * bank can generate APIC LVT interrupts | |
231 | */ | |
232 | return msr_high_bits & BIT(28); | |
233 | } | |
234 | ||
bbaff08d RR |
235 | static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) |
236 | { | |
237 | int msr = (hi & MASK_LVTOFF_HI) >> 20; | |
238 | ||
239 | if (apic < 0) { | |
240 | pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " | |
241 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, | |
242 | b->bank, b->block, b->address, hi, lo); | |
243 | return 0; | |
244 | } | |
245 | ||
246 | if (apic != msr) { | |
f57a1f3c AG |
247 | /* |
248 | * On SMCA CPUs, LVT offset is programmed at a different MSR, and | |
249 | * the BIOS provides the value. The original field where LVT offset | |
250 | * was set is reserved. Return early here: | |
251 | */ | |
252 | if (mce_flags.smca) | |
253 | return 0; | |
254 | ||
bbaff08d RR |
255 | pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " |
256 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n", | |
257 | b->cpu, apic, b->bank, b->block, b->address, hi, lo); | |
258 | return 0; | |
259 | } | |
260 | ||
261 | return 1; | |
262 | }; | |
263 | ||
ea2ca36b | 264 | /* Reprogram MCx_MISC MSR behind this threshold bank. */ |
a6b6a14e | 265 | static void threshold_restart_bank(void *_tr) |
89b831ef | 266 | { |
4cd4601d | 267 | struct thresh_restart *tr = _tr; |
7203a049 | 268 | u32 hi, lo; |
89b831ef | 269 | |
7203a049 | 270 | rdmsr(tr->b->address, lo, hi); |
89b831ef | 271 | |
7203a049 | 272 | if (tr->b->threshold_limit < (hi & THRESHOLD_MAX)) |
4cd4601d | 273 | tr->reset = 1; /* limit cannot be lower than err count */ |
89b831ef | 274 | |
4cd4601d | 275 | if (tr->reset) { /* reset err count and overflow bit */ |
7203a049 RR |
276 | hi = |
277 | (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) | | |
4cd4601d MT |
278 | (THRESHOLD_MAX - tr->b->threshold_limit); |
279 | } else if (tr->old_limit) { /* change limit w/o reset */ | |
7203a049 | 280 | int new_count = (hi & THRESHOLD_MAX) + |
4cd4601d | 281 | (tr->old_limit - tr->b->threshold_limit); |
1cb2a8e1 | 282 | |
7203a049 | 283 | hi = (hi & ~MASK_ERR_COUNT_HI) | |
89b831ef JS |
284 | (new_count & THRESHOLD_MAX); |
285 | } | |
286 | ||
f227d430 BP |
287 | /* clear IntType */ |
288 | hi &= ~MASK_INT_TYPE_HI; | |
289 | ||
290 | if (!tr->b->interrupt_capable) | |
291 | goto done; | |
292 | ||
9c37c9d8 | 293 | if (tr->set_lvt_off) { |
bbaff08d RR |
294 | if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) { |
295 | /* set new lvt offset */ | |
296 | hi &= ~MASK_LVTOFF_HI; | |
297 | hi |= tr->lvt_off << 20; | |
298 | } | |
9c37c9d8 RR |
299 | } |
300 | ||
f227d430 BP |
301 | if (tr->b->interrupt_enable) |
302 | hi |= INT_TYPE_APIC; | |
303 | ||
304 | done: | |
89b831ef | 305 | |
7203a049 RR |
306 | hi |= MASK_COUNT_EN_HI; |
307 | wrmsr(tr->b->address, lo, hi); | |
89b831ef JS |
308 | } |
309 | ||
9c37c9d8 RR |
310 | static void mce_threshold_block_init(struct threshold_block *b, int offset) |
311 | { | |
312 | struct thresh_restart tr = { | |
313 | .b = b, | |
314 | .set_lvt_off = 1, | |
315 | .lvt_off = offset, | |
316 | }; | |
317 | ||
318 | b->threshold_limit = THRESHOLD_MAX; | |
319 | threshold_restart_bank(&tr); | |
320 | }; | |
321 | ||
868c00bb | 322 | static int setup_APIC_mce_threshold(int reserved, int new) |
bbaff08d RR |
323 | { |
324 | if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR, | |
325 | APIC_EILVT_MSG_FIX, 0)) | |
326 | return new; | |
327 | ||
328 | return reserved; | |
329 | } | |
330 | ||
24fd78a8 AG |
331 | static int setup_APIC_deferred_error(int reserved, int new) |
332 | { | |
333 | if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR, | |
334 | APIC_EILVT_MSG_FIX, 0)) | |
335 | return new; | |
336 | ||
337 | return reserved; | |
338 | } | |
339 | ||
340 | static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) | |
341 | { | |
342 | u32 low = 0, high = 0; | |
343 | int def_offset = -1, def_new; | |
344 | ||
345 | if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) | |
346 | return; | |
347 | ||
348 | def_new = (low & MASK_DEF_LVTOFF) >> 4; | |
349 | if (!(low & MASK_DEF_LVTOFF)) { | |
350 | pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n"); | |
351 | def_new = DEF_LVT_OFF; | |
352 | low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4); | |
353 | } | |
354 | ||
355 | def_offset = setup_APIC_deferred_error(def_offset, def_new); | |
356 | if ((def_offset == def_new) && | |
357 | (deferred_error_int_vector != amd_deferred_error_interrupt)) | |
358 | deferred_error_int_vector = amd_deferred_error_interrupt; | |
359 | ||
360 | low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; | |
361 | wrmsr(MSR_CU_DEF_ERR, low, high); | |
362 | } | |
363 | ||
cfee4f6f | 364 | static u32 get_block_address(unsigned int cpu, u32 current_addr, u32 low, u32 high, |
8dd1e17a AG |
365 | unsigned int bank, unsigned int block) |
366 | { | |
367 | u32 addr = 0, offset = 0; | |
368 | ||
369 | if (mce_flags.smca) { | |
370 | if (!block) { | |
371 | addr = MSR_AMD64_SMCA_MCx_MISC(bank); | |
372 | } else { | |
373 | /* | |
374 | * For SMCA enabled processors, BLKPTR field of the | |
375 | * first MISC register (MCx_MISC0) indicates presence of | |
376 | * additional MISC register set (MISC1-4). | |
377 | */ | |
378 | u32 low, high; | |
379 | ||
cfee4f6f | 380 | if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) |
8dd1e17a AG |
381 | return addr; |
382 | ||
383 | if (!(low & MCI_CONFIG_MCAX)) | |
384 | return addr; | |
385 | ||
cfee4f6f | 386 | if (!rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) && |
8dd1e17a AG |
387 | (low & MASK_BLKPTR_LO)) |
388 | addr = MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); | |
389 | } | |
390 | return addr; | |
391 | } | |
392 | ||
393 | /* Fall back to method we used for older processors: */ | |
394 | switch (block) { | |
395 | case 0: | |
d9d73fcc | 396 | addr = msr_ops.misc(bank); |
8dd1e17a AG |
397 | break; |
398 | case 1: | |
399 | offset = ((low & MASK_BLKPTR_LO) >> 21); | |
400 | if (offset) | |
401 | addr = MCG_XBLK_ADDR + offset; | |
402 | break; | |
403 | default: | |
404 | addr = ++current_addr; | |
405 | } | |
406 | return addr; | |
407 | } | |
408 | ||
429893b1 BP |
409 | static int |
410 | prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, | |
411 | int offset, u32 misc_high) | |
412 | { | |
413 | unsigned int cpu = smp_processor_id(); | |
e128b4f4 | 414 | u32 smca_low, smca_high, smca_addr; |
429893b1 BP |
415 | struct threshold_block b; |
416 | int new; | |
417 | ||
418 | if (!block) | |
419 | per_cpu(bank_map, cpu) |= (1 << bank); | |
420 | ||
421 | memset(&b, 0, sizeof(b)); | |
422 | b.cpu = cpu; | |
423 | b.bank = bank; | |
424 | b.block = block; | |
425 | b.address = addr; | |
426 | b.interrupt_capable = lvt_interrupt_supported(bank, misc_high); | |
427 | ||
428 | if (!b.interrupt_capable) | |
429 | goto done; | |
430 | ||
431 | b.interrupt_enable = 1; | |
432 | ||
e128b4f4 BP |
433 | if (!mce_flags.smca) { |
434 | new = (misc_high & MASK_LVTOFF_HI) >> 20; | |
435 | goto set_offset; | |
436 | } | |
32544f06 | 437 | |
e128b4f4 | 438 | smca_addr = MSR_AMD64_SMCA_MCx_CONFIG(bank); |
32544f06 | 439 | |
e128b4f4 BP |
440 | if (!rdmsr_safe(smca_addr, &smca_low, &smca_high)) { |
441 | /* | |
442 | * OS is required to set the MCAX bit to acknowledge that it is | |
443 | * now using the new MSR ranges and new registers under each | |
444 | * bank. It also means that the OS will configure deferred | |
445 | * errors in the new MCx_CONFIG register. If the bit is not set, | |
446 | * uncorrectable errors will cause a system panic. | |
447 | * | |
448 | * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.) | |
449 | */ | |
450 | smca_high |= BIT(0); | |
429893b1 | 451 | |
e128b4f4 BP |
452 | /* |
453 | * SMCA logs Deferred Error information in MCA_DE{STAT,ADDR} | |
454 | * registers with the option of additionally logging to | |
455 | * MCA_{STATUS,ADDR} if MCA_CONFIG[LogDeferredInMcaStat] is set. | |
456 | * | |
457 | * This bit is usually set by BIOS to retain the old behavior | |
458 | * for OSes that don't use the new registers. Linux supports the | |
459 | * new registers so let's disable that additional logging here. | |
460 | * | |
461 | * MCA_CONFIG[LogDeferredInMcaStat] is bit 34 (bit 2 in the high | |
462 | * portion of the MSR). | |
463 | */ | |
464 | smca_high &= ~BIT(2); | |
429893b1 | 465 | |
66ef269d YG |
466 | /* |
467 | * SMCA sets the Deferred Error Interrupt type per bank. | |
468 | * | |
469 | * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us | |
470 | * if the DeferredIntType bit field is available. | |
471 | * | |
472 | * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the | |
473 | * high portion of the MSR). OS should set this to 0x1 to enable | |
474 | * APIC based interrupt. First, check that no interrupt has been | |
475 | * set. | |
476 | */ | |
477 | if ((smca_low & BIT(5)) && !((smca_high >> 5) & 0x3)) | |
478 | smca_high |= BIT(5); | |
479 | ||
e128b4f4 | 480 | wrmsr(smca_addr, smca_low, smca_high); |
429893b1 BP |
481 | } |
482 | ||
e128b4f4 BP |
483 | /* Gather LVT offset for thresholding: */ |
484 | if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high)) | |
485 | goto out; | |
486 | ||
487 | new = (smca_low & SMCA_THR_LVT_OFF) >> 12; | |
488 | ||
489 | set_offset: | |
429893b1 BP |
490 | offset = setup_APIC_mce_threshold(offset, new); |
491 | ||
492 | if ((offset == new) && (mce_threshold_vector != amd_threshold_interrupt)) | |
493 | mce_threshold_vector = amd_threshold_interrupt; | |
494 | ||
495 | done: | |
496 | mce_threshold_block_init(&b, offset); | |
497 | ||
498 | out: | |
499 | return offset; | |
500 | } | |
501 | ||
95268664 | 502 | /* cpu init entry point, called from mce.c with preempt off */ |
cc3ca220 | 503 | void mce_amd_feature_init(struct cpuinfo_x86 *c) |
89b831ef | 504 | { |
95268664 | 505 | u32 low = 0, high = 0, address = 0; |
cfee4f6f | 506 | unsigned int bank, block, cpu = smp_processor_id(); |
429893b1 | 507 | int offset = -1; |
89b831ef | 508 | |
bafcdd3b | 509 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
5896820e YG |
510 | if (mce_flags.smca) |
511 | get_smca_bank_info(bank); | |
512 | ||
95268664 | 513 | for (block = 0; block < NR_BLOCKS; ++block) { |
cfee4f6f | 514 | address = get_block_address(cpu, address, low, high, bank, block); |
8dd1e17a AG |
515 | if (!address) |
516 | break; | |
95268664 JS |
517 | |
518 | if (rdmsr_safe(address, &low, &high)) | |
24ce0e96 | 519 | break; |
95268664 | 520 | |
6dcbfe4f BP |
521 | if (!(high & MASK_VALID_HI)) |
522 | continue; | |
95268664 | 523 | |
24ce0e96 JB |
524 | if (!(high & MASK_CNTP_HI) || |
525 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
526 | continue; |
527 | ||
429893b1 | 528 | offset = prepare_threshold_block(bank, block, address, offset, high); |
95268664 | 529 | } |
89b831ef | 530 | } |
24fd78a8 AG |
531 | |
532 | if (mce_flags.succor) | |
533 | deferred_error_interrupt_enable(c); | |
89b831ef JS |
534 | } |
535 | ||
34102009 YG |
536 | static void |
537 | __log_error(unsigned int bank, bool deferred_err, bool threshold_err, u64 misc) | |
afdf344e | 538 | { |
34102009 YG |
539 | u32 msr_status = msr_ops.status(bank); |
540 | u32 msr_addr = msr_ops.addr(bank); | |
afdf344e AG |
541 | struct mce m; |
542 | u64 status; | |
543 | ||
34102009 YG |
544 | WARN_ON_ONCE(deferred_err && threshold_err); |
545 | ||
546 | if (deferred_err && mce_flags.smca) { | |
547 | msr_status = MSR_AMD64_SMCA_MCx_DESTAT(bank); | |
548 | msr_addr = MSR_AMD64_SMCA_MCx_DEADDR(bank); | |
549 | } | |
550 | ||
551 | rdmsrl(msr_status, status); | |
552 | ||
afdf344e AG |
553 | if (!(status & MCI_STATUS_VAL)) |
554 | return; | |
555 | ||
556 | mce_setup(&m); | |
557 | ||
558 | m.status = status; | |
559 | m.bank = bank; | |
6e6e746e | 560 | |
afdf344e AG |
561 | if (threshold_err) |
562 | m.misc = misc; | |
563 | ||
6e6e746e | 564 | if (m.status & MCI_STATUS_ADDRV) |
34102009 | 565 | rdmsrl(msr_addr, m.addr); |
afdf344e | 566 | |
db819d60 YG |
567 | if (mce_flags.smca && (m.status & MCI_STATUS_SYNDV)) |
568 | rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd); | |
569 | ||
6e6e746e | 570 | mce_log(&m); |
34102009 YG |
571 | |
572 | wrmsrl(msr_status, 0); | |
afdf344e AG |
573 | } |
574 | ||
24fd78a8 AG |
575 | static inline void __smp_deferred_error_interrupt(void) |
576 | { | |
577 | inc_irq_stat(irq_deferred_error_count); | |
578 | deferred_error_int_vector(); | |
579 | } | |
580 | ||
581 | asmlinkage __visible void smp_deferred_error_interrupt(void) | |
582 | { | |
583 | entering_irq(); | |
584 | __smp_deferred_error_interrupt(); | |
585 | exiting_ack_irq(); | |
586 | } | |
587 | ||
588 | asmlinkage __visible void smp_trace_deferred_error_interrupt(void) | |
589 | { | |
590 | entering_irq(); | |
591 | trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR); | |
592 | __smp_deferred_error_interrupt(); | |
593 | trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR); | |
594 | exiting_ack_irq(); | |
595 | } | |
596 | ||
597 | /* APIC interrupt handler for deferred errors */ | |
598 | static void amd_deferred_error_interrupt(void) | |
599 | { | |
24fd78a8 | 600 | unsigned int bank; |
34102009 YG |
601 | u32 msr_status; |
602 | u64 status; | |
24fd78a8 AG |
603 | |
604 | for (bank = 0; bank < mca_cfg.banks; ++bank) { | |
34102009 YG |
605 | msr_status = (mce_flags.smca) ? MSR_AMD64_SMCA_MCx_DESTAT(bank) |
606 | : msr_ops.status(bank); | |
607 | ||
608 | rdmsrl(msr_status, status); | |
24fd78a8 AG |
609 | |
610 | if (!(status & MCI_STATUS_VAL) || | |
611 | !(status & MCI_STATUS_DEFERRED)) | |
612 | continue; | |
613 | ||
34102009 | 614 | __log_error(bank, true, false, 0); |
24fd78a8 AG |
615 | break; |
616 | } | |
617 | } | |
618 | ||
89b831ef JS |
619 | /* |
620 | * APIC Interrupt Handler | |
621 | */ | |
622 | ||
623 | /* | |
624 | * threshold interrupt handler will service THRESHOLD_APIC_VECTOR. | |
625 | * the interrupt goes off when error_count reaches threshold_limit. | |
626 | * the handler will simply log mcelog w/ software defined bank number. | |
627 | */ | |
afdf344e | 628 | |
b2762686 | 629 | static void amd_threshold_interrupt(void) |
89b831ef | 630 | { |
1cb2a8e1 | 631 | u32 low = 0, high = 0, address = 0; |
cfee4f6f | 632 | unsigned int bank, block, cpu = smp_processor_id(); |
89b831ef | 633 | |
89b831ef | 634 | /* assume first bank caused it */ |
bafcdd3b | 635 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
44612a3a | 636 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
24ce0e96 | 637 | continue; |
95268664 | 638 | for (block = 0; block < NR_BLOCKS; ++block) { |
cfee4f6f | 639 | address = get_block_address(cpu, address, low, high, bank, block); |
8dd1e17a AG |
640 | if (!address) |
641 | break; | |
95268664 JS |
642 | |
643 | if (rdmsr_safe(address, &low, &high)) | |
24ce0e96 | 644 | break; |
95268664 JS |
645 | |
646 | if (!(high & MASK_VALID_HI)) { | |
647 | if (block) | |
648 | continue; | |
649 | else | |
650 | break; | |
651 | } | |
652 | ||
24ce0e96 JB |
653 | if (!(high & MASK_CNTP_HI) || |
654 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
655 | continue; |
656 | ||
1cb2a8e1 IM |
657 | /* |
658 | * Log the machine check that caused the threshold | |
659 | * event. | |
660 | */ | |
44612a3a CY |
661 | if (high & MASK_OVERFLOW_HI) |
662 | goto log; | |
89b831ef JS |
663 | } |
664 | } | |
44612a3a CY |
665 | return; |
666 | ||
667 | log: | |
34102009 | 668 | __log_error(bank, false, true, ((u64)high << 32) | low); |
89b831ef JS |
669 | } |
670 | ||
671 | /* | |
672 | * Sysfs Interface | |
673 | */ | |
674 | ||
89b831ef | 675 | struct threshold_attr { |
2903ee85 | 676 | struct attribute attr; |
1cb2a8e1 IM |
677 | ssize_t (*show) (struct threshold_block *, char *); |
678 | ssize_t (*store) (struct threshold_block *, const char *, size_t count); | |
89b831ef JS |
679 | }; |
680 | ||
1cb2a8e1 IM |
681 | #define SHOW_FIELDS(name) \ |
682 | static ssize_t show_ ## name(struct threshold_block *b, char *buf) \ | |
683 | { \ | |
18c20f37 | 684 | return sprintf(buf, "%lu\n", (unsigned long) b->name); \ |
2903ee85 | 685 | } |
89b831ef JS |
686 | SHOW_FIELDS(interrupt_enable) |
687 | SHOW_FIELDS(threshold_limit) | |
688 | ||
1cb2a8e1 | 689 | static ssize_t |
9319cec8 | 690 | store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size) |
89b831ef | 691 | { |
4cd4601d | 692 | struct thresh_restart tr; |
1cb2a8e1 | 693 | unsigned long new; |
1cb2a8e1 | 694 | |
f227d430 BP |
695 | if (!b->interrupt_capable) |
696 | return -EINVAL; | |
697 | ||
164109e3 | 698 | if (kstrtoul(buf, 0, &new) < 0) |
89b831ef | 699 | return -EINVAL; |
1cb2a8e1 | 700 | |
89b831ef JS |
701 | b->interrupt_enable = !!new; |
702 | ||
9c37c9d8 | 703 | memset(&tr, 0, sizeof(tr)); |
1cb2a8e1 | 704 | tr.b = b; |
1cb2a8e1 | 705 | |
a6b6a14e | 706 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef | 707 | |
9319cec8 | 708 | return size; |
89b831ef JS |
709 | } |
710 | ||
1cb2a8e1 | 711 | static ssize_t |
9319cec8 | 712 | store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) |
89b831ef | 713 | { |
4cd4601d | 714 | struct thresh_restart tr; |
1cb2a8e1 | 715 | unsigned long new; |
1cb2a8e1 | 716 | |
164109e3 | 717 | if (kstrtoul(buf, 0, &new) < 0) |
89b831ef | 718 | return -EINVAL; |
1cb2a8e1 | 719 | |
89b831ef JS |
720 | if (new > THRESHOLD_MAX) |
721 | new = THRESHOLD_MAX; | |
722 | if (new < 1) | |
723 | new = 1; | |
1cb2a8e1 | 724 | |
9c37c9d8 | 725 | memset(&tr, 0, sizeof(tr)); |
4cd4601d | 726 | tr.old_limit = b->threshold_limit; |
89b831ef | 727 | b->threshold_limit = new; |
4cd4601d | 728 | tr.b = b; |
89b831ef | 729 | |
a6b6a14e | 730 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef | 731 | |
9319cec8 | 732 | return size; |
89b831ef JS |
733 | } |
734 | ||
4cd4601d MT |
735 | static ssize_t show_error_count(struct threshold_block *b, char *buf) |
736 | { | |
2c9c42fa BP |
737 | u32 lo, hi; |
738 | ||
739 | rdmsr_on_cpu(b->cpu, b->address, &lo, &hi); | |
a6b6a14e | 740 | |
2c9c42fa BP |
741 | return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - |
742 | (THRESHOLD_MAX - b->threshold_limit))); | |
89b831ef JS |
743 | } |
744 | ||
6e927361 BP |
745 | static struct threshold_attr error_count = { |
746 | .attr = {.name = __stringify(error_count), .mode = 0444 }, | |
747 | .show = show_error_count, | |
748 | }; | |
89b831ef | 749 | |
34fa1967 HS |
750 | #define RW_ATTR(val) \ |
751 | static struct threshold_attr val = { \ | |
752 | .attr = {.name = __stringify(val), .mode = 0644 }, \ | |
753 | .show = show_## val, \ | |
754 | .store = store_## val, \ | |
89b831ef JS |
755 | }; |
756 | ||
2903ee85 JS |
757 | RW_ATTR(interrupt_enable); |
758 | RW_ATTR(threshold_limit); | |
89b831ef JS |
759 | |
760 | static struct attribute *default_attrs[] = { | |
89b831ef JS |
761 | &threshold_limit.attr, |
762 | &error_count.attr, | |
d26ecc48 BP |
763 | NULL, /* possibly interrupt_enable if supported, see below */ |
764 | NULL, | |
89b831ef JS |
765 | }; |
766 | ||
1cb2a8e1 IM |
767 | #define to_block(k) container_of(k, struct threshold_block, kobj) |
768 | #define to_attr(a) container_of(a, struct threshold_attr, attr) | |
89b831ef JS |
769 | |
770 | static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) | |
771 | { | |
95268664 | 772 | struct threshold_block *b = to_block(kobj); |
89b831ef JS |
773 | struct threshold_attr *a = to_attr(attr); |
774 | ssize_t ret; | |
1cb2a8e1 | 775 | |
89b831ef | 776 | ret = a->show ? a->show(b, buf) : -EIO; |
1cb2a8e1 | 777 | |
89b831ef JS |
778 | return ret; |
779 | } | |
780 | ||
781 | static ssize_t store(struct kobject *kobj, struct attribute *attr, | |
782 | const char *buf, size_t count) | |
783 | { | |
95268664 | 784 | struct threshold_block *b = to_block(kobj); |
89b831ef JS |
785 | struct threshold_attr *a = to_attr(attr); |
786 | ssize_t ret; | |
1cb2a8e1 | 787 | |
89b831ef | 788 | ret = a->store ? a->store(b, buf, count) : -EIO; |
1cb2a8e1 | 789 | |
89b831ef JS |
790 | return ret; |
791 | } | |
792 | ||
52cf25d0 | 793 | static const struct sysfs_ops threshold_ops = { |
1cb2a8e1 IM |
794 | .show = show, |
795 | .store = store, | |
89b831ef JS |
796 | }; |
797 | ||
798 | static struct kobj_type threshold_ktype = { | |
1cb2a8e1 IM |
799 | .sysfs_ops = &threshold_ops, |
800 | .default_attrs = default_attrs, | |
89b831ef JS |
801 | }; |
802 | ||
87a6d409 YG |
803 | static const char *get_name(unsigned int bank, struct threshold_block *b) |
804 | { | |
805 | unsigned int bank_type; | |
806 | ||
807 | if (!mce_flags.smca) { | |
808 | if (b && bank == 4) | |
809 | return bank4_names(b); | |
810 | ||
811 | return th_names[bank]; | |
812 | } | |
813 | ||
814 | if (!smca_banks[bank].type) | |
815 | return NULL; | |
816 | ||
817 | bank_type = smca_banks[bank].type->bank_type; | |
818 | ||
819 | if (b && bank_type == SMCA_UMC) { | |
820 | if (b->block < ARRAY_SIZE(smca_umc_block_names)) | |
821 | return smca_umc_block_names[b->block]; | |
822 | return NULL; | |
823 | } | |
824 | ||
825 | snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN, | |
826 | "%s_%x", smca_bank_names[bank_type].name, | |
827 | smca_banks[bank].type_instance); | |
828 | return buf_mcatype; | |
829 | } | |
830 | ||
148f9bb8 PG |
831 | static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank, |
832 | unsigned int block, u32 address) | |
95268664 | 833 | { |
95268664 | 834 | struct threshold_block *b = NULL; |
1cb2a8e1 IM |
835 | u32 low, high; |
836 | int err; | |
95268664 | 837 | |
bafcdd3b | 838 | if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS)) |
95268664 JS |
839 | return 0; |
840 | ||
a6b6a14e | 841 | if (rdmsr_safe_on_cpu(cpu, address, &low, &high)) |
24ce0e96 | 842 | return 0; |
95268664 JS |
843 | |
844 | if (!(high & MASK_VALID_HI)) { | |
845 | if (block) | |
846 | goto recurse; | |
847 | else | |
848 | return 0; | |
849 | } | |
850 | ||
24ce0e96 JB |
851 | if (!(high & MASK_CNTP_HI) || |
852 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
853 | goto recurse; |
854 | ||
855 | b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL); | |
856 | if (!b) | |
857 | return -ENOMEM; | |
95268664 | 858 | |
1cb2a8e1 IM |
859 | b->block = block; |
860 | b->bank = bank; | |
861 | b->cpu = cpu; | |
862 | b->address = address; | |
863 | b->interrupt_enable = 0; | |
f227d430 | 864 | b->interrupt_capable = lvt_interrupt_supported(bank, high); |
1cb2a8e1 | 865 | b->threshold_limit = THRESHOLD_MAX; |
95268664 | 866 | |
d79f931f | 867 | if (b->interrupt_capable) { |
d26ecc48 | 868 | threshold_ktype.default_attrs[2] = &interrupt_enable.attr; |
d79f931f AG |
869 | b->interrupt_enable = 1; |
870 | } else { | |
d26ecc48 | 871 | threshold_ktype.default_attrs[2] = NULL; |
d79f931f | 872 | } |
d26ecc48 | 873 | |
95268664 JS |
874 | INIT_LIST_HEAD(&b->miscj); |
875 | ||
1cb2a8e1 | 876 | if (per_cpu(threshold_banks, cpu)[bank]->blocks) { |
95268664 JS |
877 | list_add(&b->miscj, |
878 | &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj); | |
1cb2a8e1 | 879 | } else { |
95268664 | 880 | per_cpu(threshold_banks, cpu)[bank]->blocks = b; |
1cb2a8e1 | 881 | } |
95268664 | 882 | |
542eb75a GKH |
883 | err = kobject_init_and_add(&b->kobj, &threshold_ktype, |
884 | per_cpu(threshold_banks, cpu)[bank]->kobj, | |
87a6d409 | 885 | get_name(bank, b)); |
95268664 JS |
886 | if (err) |
887 | goto out_free; | |
888 | recurse: | |
cfee4f6f | 889 | address = get_block_address(cpu, address, low, high, bank, ++block); |
8dd1e17a AG |
890 | if (!address) |
891 | return 0; | |
95268664 | 892 | |
8dd1e17a | 893 | err = allocate_threshold_blocks(cpu, bank, block, address); |
95268664 JS |
894 | if (err) |
895 | goto out_free; | |
896 | ||
213eca7f GKH |
897 | if (b) |
898 | kobject_uevent(&b->kobj, KOBJ_ADD); | |
542eb75a | 899 | |
95268664 JS |
900 | return err; |
901 | ||
902 | out_free: | |
903 | if (b) { | |
38a382ae | 904 | kobject_put(&b->kobj); |
d9a5ac9e | 905 | list_del(&b->miscj); |
95268664 JS |
906 | kfree(b); |
907 | } | |
908 | return err; | |
909 | } | |
910 | ||
148f9bb8 | 911 | static int __threshold_add_blocks(struct threshold_bank *b) |
019f34fc BP |
912 | { |
913 | struct list_head *head = &b->blocks->miscj; | |
914 | struct threshold_block *pos = NULL; | |
915 | struct threshold_block *tmp = NULL; | |
916 | int err = 0; | |
917 | ||
918 | err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name); | |
919 | if (err) | |
920 | return err; | |
921 | ||
922 | list_for_each_entry_safe(pos, tmp, head, miscj) { | |
923 | ||
924 | err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name); | |
925 | if (err) { | |
926 | list_for_each_entry_safe_reverse(pos, tmp, head, miscj) | |
927 | kobject_del(&pos->kobj); | |
928 | ||
929 | return err; | |
930 | } | |
931 | } | |
932 | return err; | |
933 | } | |
934 | ||
148f9bb8 | 935 | static int threshold_create_bank(unsigned int cpu, unsigned int bank) |
89b831ef | 936 | { |
d6126ef5 | 937 | struct device *dev = per_cpu(mce_device, cpu); |
019f34fc | 938 | struct amd_northbridge *nb = NULL; |
92e26e2a | 939 | struct threshold_bank *b = NULL; |
87a6d409 | 940 | const char *name = get_name(bank, NULL); |
92e26e2a | 941 | int err = 0; |
95268664 | 942 | |
c76e8164 | 943 | if (is_shared_bank(bank)) { |
019f34fc | 944 | nb = node_to_amd_nb(amd_get_nb_id(cpu)); |
019f34fc BP |
945 | |
946 | /* threshold descriptor already initialized on this node? */ | |
21c5e50e | 947 | if (nb && nb->bank4) { |
019f34fc BP |
948 | /* yes, use it */ |
949 | b = nb->bank4; | |
950 | err = kobject_add(b->kobj, &dev->kobj, name); | |
951 | if (err) | |
952 | goto out; | |
953 | ||
954 | per_cpu(threshold_banks, cpu)[bank] = b; | |
955 | atomic_inc(&b->cpus); | |
956 | ||
957 | err = __threshold_add_blocks(b); | |
958 | ||
959 | goto out; | |
960 | } | |
961 | } | |
962 | ||
95268664 | 963 | b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL); |
89b831ef JS |
964 | if (!b) { |
965 | err = -ENOMEM; | |
966 | goto out; | |
967 | } | |
89b831ef | 968 | |
e032d807 | 969 | b->kobj = kobject_create_and_add(name, &dev->kobj); |
92e26e2a BP |
970 | if (!b->kobj) { |
971 | err = -EINVAL; | |
a521cf20 | 972 | goto out_free; |
92e26e2a | 973 | } |
95268664 | 974 | |
89b831ef | 975 | per_cpu(threshold_banks, cpu)[bank] = b; |
95268664 | 976 | |
c76e8164 | 977 | if (is_shared_bank(bank)) { |
019f34fc BP |
978 | atomic_set(&b->cpus, 1); |
979 | ||
980 | /* nb is already initialized, see above */ | |
21c5e50e DB |
981 | if (nb) { |
982 | WARN_ON(nb->bank4); | |
983 | nb->bank4 = b; | |
984 | } | |
019f34fc BP |
985 | } |
986 | ||
74ab0e7a | 987 | err = allocate_threshold_blocks(cpu, bank, 0, msr_ops.misc(bank)); |
92e26e2a BP |
988 | if (!err) |
989 | goto out; | |
95268664 | 990 | |
019f34fc | 991 | out_free: |
95268664 | 992 | kfree(b); |
019f34fc BP |
993 | |
994 | out: | |
89b831ef JS |
995 | return err; |
996 | } | |
997 | ||
998 | /* create dir/files for all valid threshold banks */ | |
148f9bb8 | 999 | static int threshold_create_device(unsigned int cpu) |
89b831ef | 1000 | { |
2903ee85 | 1001 | unsigned int bank; |
bafcdd3b | 1002 | struct threshold_bank **bp; |
89b831ef JS |
1003 | int err = 0; |
1004 | ||
bafcdd3b BO |
1005 | bp = kzalloc(sizeof(struct threshold_bank *) * mca_cfg.banks, |
1006 | GFP_KERNEL); | |
1007 | if (!bp) | |
1008 | return -ENOMEM; | |
1009 | ||
1010 | per_cpu(threshold_banks, cpu) = bp; | |
1011 | ||
1012 | for (bank = 0; bank < mca_cfg.banks; ++bank) { | |
5a96f4a5 | 1013 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
89b831ef JS |
1014 | continue; |
1015 | err = threshold_create_bank(cpu, bank); | |
1016 | if (err) | |
0a17941e | 1017 | return err; |
89b831ef | 1018 | } |
0a17941e | 1019 | |
89b831ef JS |
1020 | return err; |
1021 | } | |
1022 | ||
be6b5a35 | 1023 | static void deallocate_threshold_block(unsigned int cpu, |
95268664 JS |
1024 | unsigned int bank) |
1025 | { | |
1026 | struct threshold_block *pos = NULL; | |
1027 | struct threshold_block *tmp = NULL; | |
1028 | struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank]; | |
1029 | ||
1030 | if (!head) | |
1031 | return; | |
1032 | ||
1033 | list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) { | |
38a382ae | 1034 | kobject_put(&pos->kobj); |
95268664 JS |
1035 | list_del(&pos->miscj); |
1036 | kfree(pos); | |
1037 | } | |
1038 | ||
1039 | kfree(per_cpu(threshold_banks, cpu)[bank]->blocks); | |
1040 | per_cpu(threshold_banks, cpu)[bank]->blocks = NULL; | |
1041 | } | |
1042 | ||
019f34fc BP |
1043 | static void __threshold_remove_blocks(struct threshold_bank *b) |
1044 | { | |
1045 | struct threshold_block *pos = NULL; | |
1046 | struct threshold_block *tmp = NULL; | |
1047 | ||
1048 | kobject_del(b->kobj); | |
1049 | ||
1050 | list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj) | |
1051 | kobject_del(&pos->kobj); | |
1052 | } | |
1053 | ||
be6b5a35 | 1054 | static void threshold_remove_bank(unsigned int cpu, int bank) |
89b831ef | 1055 | { |
019f34fc | 1056 | struct amd_northbridge *nb; |
89b831ef | 1057 | struct threshold_bank *b; |
89b831ef JS |
1058 | |
1059 | b = per_cpu(threshold_banks, cpu)[bank]; | |
1060 | if (!b) | |
1061 | return; | |
019f34fc | 1062 | |
95268664 JS |
1063 | if (!b->blocks) |
1064 | goto free_out; | |
1065 | ||
c76e8164 | 1066 | if (is_shared_bank(bank)) { |
019f34fc BP |
1067 | if (!atomic_dec_and_test(&b->cpus)) { |
1068 | __threshold_remove_blocks(b); | |
1069 | per_cpu(threshold_banks, cpu)[bank] = NULL; | |
1070 | return; | |
1071 | } else { | |
1072 | /* | |
1073 | * the last CPU on this node using the shared bank is | |
1074 | * going away, remove that bank now. | |
1075 | */ | |
1076 | nb = node_to_amd_nb(amd_get_nb_id(cpu)); | |
1077 | nb->bank4 = NULL; | |
1078 | } | |
1079 | } | |
1080 | ||
95268664 JS |
1081 | deallocate_threshold_block(cpu, bank); |
1082 | ||
1083 | free_out: | |
8735728e | 1084 | kobject_del(b->kobj); |
38a382ae | 1085 | kobject_put(b->kobj); |
95268664 JS |
1086 | kfree(b); |
1087 | per_cpu(threshold_banks, cpu)[bank] = NULL; | |
89b831ef JS |
1088 | } |
1089 | ||
be6b5a35 | 1090 | static void threshold_remove_device(unsigned int cpu) |
89b831ef | 1091 | { |
2903ee85 | 1092 | unsigned int bank; |
89b831ef | 1093 | |
bafcdd3b | 1094 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
5a96f4a5 | 1095 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
89b831ef JS |
1096 | continue; |
1097 | threshold_remove_bank(cpu, bank); | |
1098 | } | |
bafcdd3b | 1099 | kfree(per_cpu(threshold_banks, cpu)); |
89b831ef JS |
1100 | } |
1101 | ||
89b831ef | 1102 | /* get notified when a cpu comes on/off */ |
148f9bb8 | 1103 | static void |
1cb2a8e1 | 1104 | amd_64_threshold_cpu_callback(unsigned long action, unsigned int cpu) |
89b831ef | 1105 | { |
89b831ef JS |
1106 | switch (action) { |
1107 | case CPU_ONLINE: | |
8bb78442 | 1108 | case CPU_ONLINE_FROZEN: |
89b831ef | 1109 | threshold_create_device(cpu); |
89b831ef JS |
1110 | break; |
1111 | case CPU_DEAD: | |
8bb78442 | 1112 | case CPU_DEAD_FROZEN: |
89b831ef JS |
1113 | threshold_remove_device(cpu); |
1114 | break; | |
1115 | default: | |
1116 | break; | |
1117 | } | |
89b831ef JS |
1118 | } |
1119 | ||
89b831ef JS |
1120 | static __init int threshold_init_device(void) |
1121 | { | |
2903ee85 | 1122 | unsigned lcpu = 0; |
89b831ef | 1123 | |
89b831ef JS |
1124 | /* to hit CPUs online before the notifier is up */ |
1125 | for_each_online_cpu(lcpu) { | |
fff2e89f | 1126 | int err = threshold_create_device(lcpu); |
1cb2a8e1 | 1127 | |
89b831ef | 1128 | if (err) |
fff2e89f | 1129 | return err; |
89b831ef | 1130 | } |
8735728e | 1131 | threshold_cpu_callback = amd_64_threshold_cpu_callback; |
1cb2a8e1 | 1132 | |
fff2e89f | 1133 | return 0; |
89b831ef | 1134 | } |
a8fccdb0 LJ |
1135 | /* |
1136 | * there are 3 funcs which need to be _initcalled in a logic sequence: | |
1137 | * 1. xen_late_init_mcelog | |
1138 | * 2. mcheck_init_device | |
1139 | * 3. threshold_init_device | |
1140 | * | |
1141 | * xen_late_init_mcelog must register xen_mce_chrdev_device before | |
1142 | * native mce_chrdev_device registration if running under xen platform; | |
1143 | * | |
1144 | * mcheck_init_device should be inited before threshold_init_device to | |
1145 | * initialize mce_device, otherwise a NULL ptr dereference will cause panic. | |
1146 | * | |
1147 | * so we use following _initcalls | |
1148 | * 1. device_initcall(xen_late_init_mcelog); | |
1149 | * 2. device_initcall_sync(mcheck_init_device); | |
1150 | * 3. late_initcall(threshold_init_device); | |
1151 | * | |
1152 | * when running under xen, the initcall order is 1,2,3; | |
1153 | * on baremetal, we skip 1 and we do only 2 and 3. | |
1154 | */ | |
1155 | late_initcall(threshold_init_device); |