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Commit | Line | Data |
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89b831ef | 1 | /* |
ea2ca36b | 2 | * (c) 2005-2016 Advanced Micro Devices, Inc. |
89b831ef JS |
3 | * Your use of this code is subject to the terms and conditions of the |
4 | * GNU general public license version 2. See "COPYING" or | |
5 | * http://www.gnu.org/licenses/gpl.html | |
6 | * | |
7 | * Written by Jacob Shin - AMD, Inc. | |
e6d41e8c | 8 | * Maintained by: Borislav Petkov <bp@alien8.de> |
89b831ef | 9 | * |
3490c0e4 | 10 | * All MC4_MISCi registers are shared between cores on a node. |
89b831ef | 11 | */ |
89b831ef | 12 | #include <linux/interrupt.h> |
89b831ef | 13 | #include <linux/notifier.h> |
1cb2a8e1 | 14 | #include <linux/kobject.h> |
34fa1967 | 15 | #include <linux/percpu.h> |
1cb2a8e1 IM |
16 | #include <linux/errno.h> |
17 | #include <linux/sched.h> | |
89b831ef | 18 | #include <linux/sysfs.h> |
5a0e3ad6 | 19 | #include <linux/slab.h> |
1cb2a8e1 IM |
20 | #include <linux/init.h> |
21 | #include <linux/cpu.h> | |
22 | #include <linux/smp.h> | |
87a6d409 | 23 | #include <linux/string.h> |
1cb2a8e1 | 24 | |
019f34fc | 25 | #include <asm/amd_nb.h> |
89b831ef JS |
26 | #include <asm/apic.h> |
27 | #include <asm/mce.h> | |
28 | #include <asm/msr.h> | |
24fd78a8 | 29 | #include <asm/trace/irq_vectors.h> |
89b831ef | 30 | |
262e6811 BP |
31 | #include "mce-internal.h" |
32 | ||
60f116fc | 33 | #define NR_BLOCKS 5 |
2903ee85 JS |
34 | #define THRESHOLD_MAX 0xFFF |
35 | #define INT_TYPE_APIC 0x00020000 | |
36 | #define MASK_VALID_HI 0x80000000 | |
24ce0e96 JB |
37 | #define MASK_CNTP_HI 0x40000000 |
38 | #define MASK_LOCKED_HI 0x20000000 | |
2903ee85 JS |
39 | #define MASK_LVTOFF_HI 0x00F00000 |
40 | #define MASK_COUNT_EN_HI 0x00080000 | |
41 | #define MASK_INT_TYPE_HI 0x00060000 | |
42 | #define MASK_OVERFLOW_HI 0x00010000 | |
89b831ef | 43 | #define MASK_ERR_COUNT_HI 0x00000FFF |
95268664 JS |
44 | #define MASK_BLKPTR_LO 0xFF000000 |
45 | #define MCG_XBLK_ADDR 0xC0000400 | |
89b831ef | 46 | |
24fd78a8 AG |
47 | /* Deferred error settings */ |
48 | #define MSR_CU_DEF_ERR 0xC0000410 | |
49 | #define MASK_DEF_LVTOFF 0x000000F0 | |
50 | #define MASK_DEF_INT_TYPE 0x00000006 | |
51 | #define DEF_LVT_OFF 0x2 | |
52 | #define DEF_INT_TYPE_APIC 0x2 | |
53 | ||
f57a1f3c AG |
54 | /* Scalable MCA: */ |
55 | ||
56 | /* Threshold LVT offset is at MSR0xC0000410[15:12] */ | |
57 | #define SMCA_THR_LVT_OFF 0xF000 | |
58 | ||
4d7b02d5 SAS |
59 | static bool thresholding_en; |
60 | ||
336d335a BP |
61 | static const char * const th_names[] = { |
62 | "load_store", | |
63 | "insn_fetch", | |
64 | "combined_unit", | |
29f72ce3 | 65 | "decode_unit", |
336d335a BP |
66 | "northbridge", |
67 | "execution_unit", | |
68 | }; | |
69 | ||
87a6d409 YG |
70 | static const char * const smca_umc_block_names[] = { |
71 | "dram_ecc", | |
72 | "misc_umc" | |
73 | }; | |
74 | ||
c09a8c40 BP |
75 | struct smca_bank_name { |
76 | const char *name; /* Short name for sysfs */ | |
77 | const char *long_name; /* Long name for pretty-printing */ | |
78 | }; | |
79 | ||
80 | static struct smca_bank_name smca_names[] = { | |
5896820e YG |
81 | [SMCA_LS] = { "load_store", "Load Store Unit" }, |
82 | [SMCA_IF] = { "insn_fetch", "Instruction Fetch Unit" }, | |
83 | [SMCA_L2_CACHE] = { "l2_cache", "L2 Cache" }, | |
84 | [SMCA_DE] = { "decode_unit", "Decode Unit" }, | |
68627a69 | 85 | [SMCA_RESERVED] = { "reserved", "Reserved" }, |
5896820e YG |
86 | [SMCA_EX] = { "execution_unit", "Execution Unit" }, |
87 | [SMCA_FP] = { "floating_point", "Floating Point Unit" }, | |
88 | [SMCA_L3_CACHE] = { "l3_cache", "L3 Cache" }, | |
89 | [SMCA_CS] = { "coherent_slave", "Coherent Slave" }, | |
90 | [SMCA_PIE] = { "pie", "Power, Interrupts, etc." }, | |
91 | [SMCA_UMC] = { "umc", "Unified Memory Controller" }, | |
92 | [SMCA_PB] = { "param_block", "Parameter Block" }, | |
93 | [SMCA_PSP] = { "psp", "Platform Security Processor" }, | |
94 | [SMCA_SMU] = { "smu", "System Management Unit" }, | |
be0aec23 | 95 | }; |
c09a8c40 BP |
96 | |
97 | const char *smca_get_name(enum smca_bank_types t) | |
98 | { | |
99 | if (t >= N_SMCA_BANK_TYPES) | |
100 | return NULL; | |
101 | ||
102 | return smca_names[t].name; | |
103 | } | |
104 | ||
105 | const char *smca_get_long_name(enum smca_bank_types t) | |
106 | { | |
107 | if (t >= N_SMCA_BANK_TYPES) | |
108 | return NULL; | |
109 | ||
110 | return smca_names[t].long_name; | |
111 | } | |
112 | EXPORT_SYMBOL_GPL(smca_get_long_name); | |
5896820e | 113 | |
e5d6a126 | 114 | static enum smca_bank_types smca_get_bank_type(unsigned int bank) |
11cf8877 YG |
115 | { |
116 | struct smca_bank *b; | |
117 | ||
e5d6a126 | 118 | if (bank >= MAX_NR_BANKS) |
11cf8877 YG |
119 | return N_SMCA_BANK_TYPES; |
120 | ||
e5d6a126 | 121 | b = &smca_banks[bank]; |
11cf8877 YG |
122 | if (!b->hwid) |
123 | return N_SMCA_BANK_TYPES; | |
124 | ||
125 | return b->hwid->bank_type; | |
126 | } | |
127 | ||
1ce9cd7f | 128 | static struct smca_hwid smca_hwid_mcatypes[] = { |
5896820e YG |
129 | /* { bank_type, hwid_mcatype, xec_bitmap } */ |
130 | ||
68627a69 YG |
131 | /* Reserved type */ |
132 | { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0), 0x0 }, | |
133 | ||
5896820e YG |
134 | /* ZN Core (HWID=0xB0) MCA types */ |
135 | { SMCA_LS, HWID_MCATYPE(0xB0, 0x0), 0x1FFFEF }, | |
136 | { SMCA_IF, HWID_MCATYPE(0xB0, 0x1), 0x3FFF }, | |
137 | { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2), 0xF }, | |
138 | { SMCA_DE, HWID_MCATYPE(0xB0, 0x3), 0x1FF }, | |
139 | /* HWID 0xB0 MCATYPE 0x4 is Reserved */ | |
140 | { SMCA_EX, HWID_MCATYPE(0xB0, 0x5), 0x7FF }, | |
141 | { SMCA_FP, HWID_MCATYPE(0xB0, 0x6), 0x7F }, | |
142 | { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7), 0xFF }, | |
143 | ||
144 | /* Data Fabric MCA types */ | |
145 | { SMCA_CS, HWID_MCATYPE(0x2E, 0x0), 0x1FF }, | |
146 | { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1), 0xF }, | |
147 | ||
148 | /* Unified Memory Controller MCA type */ | |
149 | { SMCA_UMC, HWID_MCATYPE(0x96, 0x0), 0x3F }, | |
150 | ||
151 | /* Parameter Block MCA type */ | |
152 | { SMCA_PB, HWID_MCATYPE(0x05, 0x0), 0x1 }, | |
be0aec23 | 153 | |
5896820e YG |
154 | /* Platform Security Processor MCA type */ |
155 | { SMCA_PSP, HWID_MCATYPE(0xFF, 0x0), 0x1 }, | |
156 | ||
157 | /* System Management Unit MCA type */ | |
158 | { SMCA_SMU, HWID_MCATYPE(0x01, 0x0), 0x1 }, | |
be0aec23 | 159 | }; |
5896820e | 160 | |
79349f52 | 161 | struct smca_bank smca_banks[MAX_NR_BANKS]; |
5896820e | 162 | EXPORT_SYMBOL_GPL(smca_banks); |
be0aec23 | 163 | |
87a6d409 YG |
164 | /* |
165 | * In SMCA enabled processors, we can have multiple banks for a given IP type. | |
166 | * So to define a unique name for each bank, we use a temp c-string to append | |
167 | * the MCA_IPID[InstanceId] to type's name in get_name(). | |
168 | * | |
169 | * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN | |
170 | * is greater than 8 plus 1 (for underscore) plus length of longest type name. | |
171 | */ | |
172 | #define MAX_MCATYPE_NAME_LEN 30 | |
173 | static char buf_mcatype[MAX_MCATYPE_NAME_LEN]; | |
174 | ||
bafcdd3b | 175 | static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks); |
955d1427 | 176 | static DEFINE_PER_CPU(unsigned int, bank_map); /* see which banks are on */ |
89b831ef | 177 | |
b2762686 | 178 | static void amd_threshold_interrupt(void); |
24fd78a8 AG |
179 | static void amd_deferred_error_interrupt(void); |
180 | ||
181 | static void default_deferred_error_interrupt(void) | |
182 | { | |
183 | pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR); | |
184 | } | |
185 | void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; | |
b2762686 | 186 | |
84bcc1d5 | 187 | static void smca_configure(unsigned int bank, unsigned int cpu) |
5896820e | 188 | { |
84bcc1d5 | 189 | unsigned int i, hwid_mcatype; |
1ce9cd7f | 190 | struct smca_hwid *s_hwid; |
84bcc1d5 YG |
191 | u32 high, low; |
192 | u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); | |
193 | ||
194 | /* Set appropriate bits in MCA_CONFIG */ | |
195 | if (!rdmsr_safe(smca_config, &low, &high)) { | |
196 | /* | |
197 | * OS is required to set the MCAX bit to acknowledge that it is | |
198 | * now using the new MSR ranges and new registers under each | |
199 | * bank. It also means that the OS will configure deferred | |
200 | * errors in the new MCx_CONFIG register. If the bit is not set, | |
201 | * uncorrectable errors will cause a system panic. | |
202 | * | |
203 | * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.) | |
204 | */ | |
205 | high |= BIT(0); | |
206 | ||
207 | /* | |
208 | * SMCA sets the Deferred Error Interrupt type per bank. | |
209 | * | |
210 | * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us | |
211 | * if the DeferredIntType bit field is available. | |
212 | * | |
213 | * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the | |
214 | * high portion of the MSR). OS should set this to 0x1 to enable | |
215 | * APIC based interrupt. First, check that no interrupt has been | |
216 | * set. | |
217 | */ | |
218 | if ((low & BIT(5)) && !((high >> 5) & 0x3)) | |
219 | high |= BIT(5); | |
220 | ||
221 | wrmsr(smca_config, low, high); | |
222 | } | |
5896820e | 223 | |
9662d43f YG |
224 | /* Return early if this bank was already initialized. */ |
225 | if (smca_banks[bank].hwid) | |
5896820e YG |
226 | return; |
227 | ||
84bcc1d5 | 228 | if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) { |
5896820e YG |
229 | pr_warn("Failed to read MCA_IPID for bank %d\n", bank); |
230 | return; | |
231 | } | |
232 | ||
1ce9cd7f BP |
233 | hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID, |
234 | (high & MCI_IPID_MCATYPE) >> 16); | |
5896820e YG |
235 | |
236 | for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) { | |
1ce9cd7f BP |
237 | s_hwid = &smca_hwid_mcatypes[i]; |
238 | if (hwid_mcatype == s_hwid->hwid_mcatype) { | |
239 | smca_banks[bank].hwid = s_hwid; | |
84bcc1d5 | 240 | smca_banks[bank].id = low; |
0b737a9c | 241 | smca_banks[bank].sysfs_id = s_hwid->count++; |
5896820e YG |
242 | break; |
243 | } | |
244 | } | |
245 | } | |
246 | ||
4cd4601d | 247 | struct thresh_restart { |
1cb2a8e1 IM |
248 | struct threshold_block *b; |
249 | int reset; | |
9c37c9d8 RR |
250 | int set_lvt_off; |
251 | int lvt_off; | |
1cb2a8e1 | 252 | u16 old_limit; |
4cd4601d MT |
253 | }; |
254 | ||
c76e8164 BO |
255 | static inline bool is_shared_bank(int bank) |
256 | { | |
284b965c AG |
257 | /* |
258 | * Scalable MCA provides for only one core to have access to the MSRs of | |
259 | * a shared bank. | |
260 | */ | |
261 | if (mce_flags.smca) | |
262 | return false; | |
263 | ||
c76e8164 BO |
264 | /* Bank 4 is for northbridge reporting and is thus shared */ |
265 | return (bank == 4); | |
266 | } | |
267 | ||
2cd4c303 | 268 | static const char *bank4_names(const struct threshold_block *b) |
336d335a BP |
269 | { |
270 | switch (b->address) { | |
271 | /* MSR4_MISC0 */ | |
272 | case 0x00000413: | |
273 | return "dram"; | |
274 | ||
275 | case 0xc0000408: | |
276 | return "ht_links"; | |
277 | ||
278 | case 0xc0000409: | |
279 | return "l3_cache"; | |
280 | ||
281 | default: | |
282 | WARN(1, "Funny MSR: 0x%08x\n", b->address); | |
283 | return ""; | |
284 | } | |
285 | }; | |
286 | ||
287 | ||
f227d430 BP |
288 | static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) |
289 | { | |
290 | /* | |
291 | * bank 4 supports APIC LVT interrupts implicitly since forever. | |
292 | */ | |
293 | if (bank == 4) | |
294 | return true; | |
295 | ||
296 | /* | |
297 | * IntP: interrupt present; if this bit is set, the thresholding | |
298 | * bank can generate APIC LVT interrupts | |
299 | */ | |
300 | return msr_high_bits & BIT(28); | |
301 | } | |
302 | ||
bbaff08d RR |
303 | static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) |
304 | { | |
305 | int msr = (hi & MASK_LVTOFF_HI) >> 20; | |
306 | ||
307 | if (apic < 0) { | |
308 | pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " | |
309 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, | |
310 | b->bank, b->block, b->address, hi, lo); | |
311 | return 0; | |
312 | } | |
313 | ||
314 | if (apic != msr) { | |
f57a1f3c AG |
315 | /* |
316 | * On SMCA CPUs, LVT offset is programmed at a different MSR, and | |
317 | * the BIOS provides the value. The original field where LVT offset | |
318 | * was set is reserved. Return early here: | |
319 | */ | |
320 | if (mce_flags.smca) | |
321 | return 0; | |
322 | ||
bbaff08d RR |
323 | pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " |
324 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n", | |
325 | b->cpu, apic, b->bank, b->block, b->address, hi, lo); | |
326 | return 0; | |
327 | } | |
328 | ||
329 | return 1; | |
330 | }; | |
331 | ||
ea2ca36b | 332 | /* Reprogram MCx_MISC MSR behind this threshold bank. */ |
a6b6a14e | 333 | static void threshold_restart_bank(void *_tr) |
89b831ef | 334 | { |
4cd4601d | 335 | struct thresh_restart *tr = _tr; |
7203a049 | 336 | u32 hi, lo; |
89b831ef | 337 | |
7203a049 | 338 | rdmsr(tr->b->address, lo, hi); |
89b831ef | 339 | |
7203a049 | 340 | if (tr->b->threshold_limit < (hi & THRESHOLD_MAX)) |
4cd4601d | 341 | tr->reset = 1; /* limit cannot be lower than err count */ |
89b831ef | 342 | |
4cd4601d | 343 | if (tr->reset) { /* reset err count and overflow bit */ |
7203a049 RR |
344 | hi = |
345 | (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) | | |
4cd4601d MT |
346 | (THRESHOLD_MAX - tr->b->threshold_limit); |
347 | } else if (tr->old_limit) { /* change limit w/o reset */ | |
7203a049 | 348 | int new_count = (hi & THRESHOLD_MAX) + |
4cd4601d | 349 | (tr->old_limit - tr->b->threshold_limit); |
1cb2a8e1 | 350 | |
7203a049 | 351 | hi = (hi & ~MASK_ERR_COUNT_HI) | |
89b831ef JS |
352 | (new_count & THRESHOLD_MAX); |
353 | } | |
354 | ||
f227d430 BP |
355 | /* clear IntType */ |
356 | hi &= ~MASK_INT_TYPE_HI; | |
357 | ||
358 | if (!tr->b->interrupt_capable) | |
359 | goto done; | |
360 | ||
9c37c9d8 | 361 | if (tr->set_lvt_off) { |
bbaff08d RR |
362 | if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) { |
363 | /* set new lvt offset */ | |
364 | hi &= ~MASK_LVTOFF_HI; | |
365 | hi |= tr->lvt_off << 20; | |
366 | } | |
9c37c9d8 RR |
367 | } |
368 | ||
f227d430 BP |
369 | if (tr->b->interrupt_enable) |
370 | hi |= INT_TYPE_APIC; | |
371 | ||
372 | done: | |
89b831ef | 373 | |
7203a049 RR |
374 | hi |= MASK_COUNT_EN_HI; |
375 | wrmsr(tr->b->address, lo, hi); | |
89b831ef JS |
376 | } |
377 | ||
9c37c9d8 RR |
378 | static void mce_threshold_block_init(struct threshold_block *b, int offset) |
379 | { | |
380 | struct thresh_restart tr = { | |
381 | .b = b, | |
382 | .set_lvt_off = 1, | |
383 | .lvt_off = offset, | |
384 | }; | |
385 | ||
386 | b->threshold_limit = THRESHOLD_MAX; | |
387 | threshold_restart_bank(&tr); | |
388 | }; | |
389 | ||
868c00bb | 390 | static int setup_APIC_mce_threshold(int reserved, int new) |
bbaff08d RR |
391 | { |
392 | if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR, | |
393 | APIC_EILVT_MSG_FIX, 0)) | |
394 | return new; | |
395 | ||
396 | return reserved; | |
397 | } | |
398 | ||
24fd78a8 AG |
399 | static int setup_APIC_deferred_error(int reserved, int new) |
400 | { | |
401 | if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR, | |
402 | APIC_EILVT_MSG_FIX, 0)) | |
403 | return new; | |
404 | ||
405 | return reserved; | |
406 | } | |
407 | ||
408 | static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) | |
409 | { | |
410 | u32 low = 0, high = 0; | |
411 | int def_offset = -1, def_new; | |
412 | ||
413 | if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) | |
414 | return; | |
415 | ||
416 | def_new = (low & MASK_DEF_LVTOFF) >> 4; | |
417 | if (!(low & MASK_DEF_LVTOFF)) { | |
418 | pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n"); | |
419 | def_new = DEF_LVT_OFF; | |
420 | low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4); | |
421 | } | |
422 | ||
423 | def_offset = setup_APIC_deferred_error(def_offset, def_new); | |
424 | if ((def_offset == def_new) && | |
425 | (deferred_error_int_vector != amd_deferred_error_interrupt)) | |
426 | deferred_error_int_vector = amd_deferred_error_interrupt; | |
427 | ||
c8a4364c YG |
428 | if (!mce_flags.smca) |
429 | low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; | |
430 | ||
24fd78a8 AG |
431 | wrmsr(MSR_CU_DEF_ERR, low, high); |
432 | } | |
433 | ||
cfee4f6f | 434 | static u32 get_block_address(unsigned int cpu, u32 current_addr, u32 low, u32 high, |
8dd1e17a AG |
435 | unsigned int bank, unsigned int block) |
436 | { | |
437 | u32 addr = 0, offset = 0; | |
438 | ||
439 | if (mce_flags.smca) { | |
68627a69 YG |
440 | if (smca_get_bank_type(bank) == SMCA_RESERVED) |
441 | return addr; | |
442 | ||
8dd1e17a AG |
443 | if (!block) { |
444 | addr = MSR_AMD64_SMCA_MCx_MISC(bank); | |
445 | } else { | |
446 | /* | |
447 | * For SMCA enabled processors, BLKPTR field of the | |
448 | * first MISC register (MCx_MISC0) indicates presence of | |
449 | * additional MISC register set (MISC1-4). | |
450 | */ | |
451 | u32 low, high; | |
452 | ||
cfee4f6f | 453 | if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) |
8dd1e17a AG |
454 | return addr; |
455 | ||
456 | if (!(low & MCI_CONFIG_MCAX)) | |
457 | return addr; | |
458 | ||
cfee4f6f | 459 | if (!rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) && |
8dd1e17a AG |
460 | (low & MASK_BLKPTR_LO)) |
461 | addr = MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); | |
462 | } | |
463 | return addr; | |
464 | } | |
465 | ||
466 | /* Fall back to method we used for older processors: */ | |
467 | switch (block) { | |
468 | case 0: | |
d9d73fcc | 469 | addr = msr_ops.misc(bank); |
8dd1e17a AG |
470 | break; |
471 | case 1: | |
472 | offset = ((low & MASK_BLKPTR_LO) >> 21); | |
473 | if (offset) | |
474 | addr = MCG_XBLK_ADDR + offset; | |
475 | break; | |
476 | default: | |
477 | addr = ++current_addr; | |
478 | } | |
479 | return addr; | |
480 | } | |
481 | ||
429893b1 BP |
482 | static int |
483 | prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, | |
484 | int offset, u32 misc_high) | |
485 | { | |
486 | unsigned int cpu = smp_processor_id(); | |
84bcc1d5 | 487 | u32 smca_low, smca_high; |
429893b1 BP |
488 | struct threshold_block b; |
489 | int new; | |
490 | ||
491 | if (!block) | |
492 | per_cpu(bank_map, cpu) |= (1 << bank); | |
493 | ||
494 | memset(&b, 0, sizeof(b)); | |
495 | b.cpu = cpu; | |
496 | b.bank = bank; | |
497 | b.block = block; | |
498 | b.address = addr; | |
499 | b.interrupt_capable = lvt_interrupt_supported(bank, misc_high); | |
500 | ||
501 | if (!b.interrupt_capable) | |
502 | goto done; | |
503 | ||
504 | b.interrupt_enable = 1; | |
505 | ||
e128b4f4 BP |
506 | if (!mce_flags.smca) { |
507 | new = (misc_high & MASK_LVTOFF_HI) >> 20; | |
508 | goto set_offset; | |
509 | } | |
32544f06 | 510 | |
e128b4f4 BP |
511 | /* Gather LVT offset for thresholding: */ |
512 | if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high)) | |
513 | goto out; | |
514 | ||
515 | new = (smca_low & SMCA_THR_LVT_OFF) >> 12; | |
516 | ||
517 | set_offset: | |
429893b1 BP |
518 | offset = setup_APIC_mce_threshold(offset, new); |
519 | ||
520 | if ((offset == new) && (mce_threshold_vector != amd_threshold_interrupt)) | |
521 | mce_threshold_vector = amd_threshold_interrupt; | |
522 | ||
523 | done: | |
524 | mce_threshold_block_init(&b, offset); | |
525 | ||
526 | out: | |
527 | return offset; | |
528 | } | |
529 | ||
95268664 | 530 | /* cpu init entry point, called from mce.c with preempt off */ |
cc3ca220 | 531 | void mce_amd_feature_init(struct cpuinfo_x86 *c) |
89b831ef | 532 | { |
95268664 | 533 | u32 low = 0, high = 0, address = 0; |
cfee4f6f | 534 | unsigned int bank, block, cpu = smp_processor_id(); |
429893b1 | 535 | int offset = -1; |
89b831ef | 536 | |
bafcdd3b | 537 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
5896820e | 538 | if (mce_flags.smca) |
84bcc1d5 | 539 | smca_configure(bank, cpu); |
5896820e | 540 | |
95268664 | 541 | for (block = 0; block < NR_BLOCKS; ++block) { |
cfee4f6f | 542 | address = get_block_address(cpu, address, low, high, bank, block); |
8dd1e17a AG |
543 | if (!address) |
544 | break; | |
95268664 JS |
545 | |
546 | if (rdmsr_safe(address, &low, &high)) | |
24ce0e96 | 547 | break; |
95268664 | 548 | |
6dcbfe4f BP |
549 | if (!(high & MASK_VALID_HI)) |
550 | continue; | |
95268664 | 551 | |
24ce0e96 JB |
552 | if (!(high & MASK_CNTP_HI) || |
553 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
554 | continue; |
555 | ||
429893b1 | 556 | offset = prepare_threshold_block(bank, block, address, offset, high); |
95268664 | 557 | } |
89b831ef | 558 | } |
24fd78a8 AG |
559 | |
560 | if (mce_flags.succor) | |
561 | deferred_error_interrupt_enable(c); | |
89b831ef JS |
562 | } |
563 | ||
f5382de9 YG |
564 | int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) |
565 | { | |
566 | u64 dram_base_addr, dram_limit_addr, dram_hole_base; | |
567 | /* We start from the normalized address */ | |
568 | u64 ret_addr = norm_addr; | |
569 | ||
570 | u32 tmp; | |
571 | ||
572 | u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; | |
573 | u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; | |
574 | u8 intlv_addr_sel, intlv_addr_bit; | |
575 | u8 num_intlv_bits, hashed_bit; | |
576 | u8 lgcy_mmio_hole_en, base = 0; | |
577 | u8 cs_mask, cs_id = 0; | |
578 | bool hash_enabled = false; | |
579 | ||
580 | /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */ | |
581 | if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp)) | |
582 | goto out_err; | |
583 | ||
584 | /* Remove HiAddrOffset from normalized address, if enabled: */ | |
585 | if (tmp & BIT(0)) { | |
586 | u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8; | |
587 | ||
588 | if (norm_addr >= hi_addr_offset) { | |
589 | ret_addr -= hi_addr_offset; | |
590 | base = 1; | |
591 | } | |
592 | } | |
593 | ||
594 | /* Read D18F0x110 (DramBaseAddress). */ | |
595 | if (amd_df_indirect_read(nid, 0, 0x110 + (8 * base), umc, &tmp)) | |
596 | goto out_err; | |
597 | ||
598 | /* Check if address range is valid. */ | |
599 | if (!(tmp & BIT(0))) { | |
600 | pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n", | |
601 | __func__, tmp); | |
602 | goto out_err; | |
603 | } | |
604 | ||
605 | lgcy_mmio_hole_en = tmp & BIT(1); | |
606 | intlv_num_chan = (tmp >> 4) & 0xF; | |
607 | intlv_addr_sel = (tmp >> 8) & 0x7; | |
608 | dram_base_addr = (tmp & GENMASK_ULL(31, 12)) << 16; | |
609 | ||
610 | /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ | |
611 | if (intlv_addr_sel > 3) { | |
612 | pr_err("%s: Invalid interleave address select %d.\n", | |
613 | __func__, intlv_addr_sel); | |
614 | goto out_err; | |
615 | } | |
616 | ||
617 | /* Read D18F0x114 (DramLimitAddress). */ | |
618 | if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp)) | |
619 | goto out_err; | |
620 | ||
621 | intlv_num_sockets = (tmp >> 8) & 0x1; | |
622 | intlv_num_dies = (tmp >> 10) & 0x3; | |
623 | dram_limit_addr = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); | |
624 | ||
625 | intlv_addr_bit = intlv_addr_sel + 8; | |
626 | ||
627 | /* Re-use intlv_num_chan by setting it equal to log2(#channels) */ | |
628 | switch (intlv_num_chan) { | |
629 | case 0: intlv_num_chan = 0; break; | |
630 | case 1: intlv_num_chan = 1; break; | |
631 | case 3: intlv_num_chan = 2; break; | |
632 | case 5: intlv_num_chan = 3; break; | |
633 | case 7: intlv_num_chan = 4; break; | |
634 | ||
635 | case 8: intlv_num_chan = 1; | |
636 | hash_enabled = true; | |
637 | break; | |
638 | default: | |
639 | pr_err("%s: Invalid number of interleaved channels %d.\n", | |
640 | __func__, intlv_num_chan); | |
641 | goto out_err; | |
642 | } | |
643 | ||
644 | num_intlv_bits = intlv_num_chan; | |
645 | ||
646 | if (intlv_num_dies > 2) { | |
647 | pr_err("%s: Invalid number of interleaved nodes/dies %d.\n", | |
648 | __func__, intlv_num_dies); | |
649 | goto out_err; | |
650 | } | |
651 | ||
652 | num_intlv_bits += intlv_num_dies; | |
653 | ||
654 | /* Add a bit if sockets are interleaved. */ | |
655 | num_intlv_bits += intlv_num_sockets; | |
656 | ||
657 | /* Assert num_intlv_bits <= 4 */ | |
658 | if (num_intlv_bits > 4) { | |
659 | pr_err("%s: Invalid interleave bits %d.\n", | |
660 | __func__, num_intlv_bits); | |
661 | goto out_err; | |
662 | } | |
663 | ||
664 | if (num_intlv_bits > 0) { | |
665 | u64 temp_addr_x, temp_addr_i, temp_addr_y; | |
666 | u8 die_id_bit, sock_id_bit, cs_fabric_id; | |
667 | ||
668 | /* | |
669 | * Read FabricBlockInstanceInformation3_CS[BlockFabricID]. | |
670 | * This is the fabric id for this coherent slave. Use | |
671 | * umc/channel# as instance id of the coherent slave | |
672 | * for FICAA. | |
673 | */ | |
674 | if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp)) | |
675 | goto out_err; | |
676 | ||
677 | cs_fabric_id = (tmp >> 8) & 0xFF; | |
678 | die_id_bit = 0; | |
679 | ||
680 | /* If interleaved over more than 1 channel: */ | |
681 | if (intlv_num_chan) { | |
682 | die_id_bit = intlv_num_chan; | |
683 | cs_mask = (1 << die_id_bit) - 1; | |
684 | cs_id = cs_fabric_id & cs_mask; | |
685 | } | |
686 | ||
687 | sock_id_bit = die_id_bit; | |
688 | ||
689 | /* Read D18F1x208 (SystemFabricIdMask). */ | |
690 | if (intlv_num_dies || intlv_num_sockets) | |
691 | if (amd_df_indirect_read(nid, 1, 0x208, umc, &tmp)) | |
692 | goto out_err; | |
693 | ||
694 | /* If interleaved over more than 1 die. */ | |
695 | if (intlv_num_dies) { | |
696 | sock_id_bit = die_id_bit + intlv_num_dies; | |
697 | die_id_shift = (tmp >> 24) & 0xF; | |
698 | die_id_mask = (tmp >> 8) & 0xFF; | |
699 | ||
700 | cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; | |
701 | } | |
702 | ||
703 | /* If interleaved over more than 1 socket. */ | |
704 | if (intlv_num_sockets) { | |
705 | socket_id_shift = (tmp >> 28) & 0xF; | |
706 | socket_id_mask = (tmp >> 16) & 0xFF; | |
707 | ||
708 | cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit; | |
709 | } | |
710 | ||
711 | /* | |
712 | * The pre-interleaved address consists of XXXXXXIIIYYYYY | |
713 | * where III is the ID for this CS, and XXXXXXYYYYY are the | |
714 | * address bits from the post-interleaved address. | |
715 | * "num_intlv_bits" has been calculated to tell us how many "I" | |
716 | * bits there are. "intlv_addr_bit" tells us how many "Y" bits | |
717 | * there are (where "I" starts). | |
718 | */ | |
719 | temp_addr_y = ret_addr & GENMASK_ULL(intlv_addr_bit-1, 0); | |
720 | temp_addr_i = (cs_id << intlv_addr_bit); | |
721 | temp_addr_x = (ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits; | |
722 | ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; | |
723 | } | |
724 | ||
725 | /* Add dram base address */ | |
726 | ret_addr += dram_base_addr; | |
727 | ||
728 | /* If legacy MMIO hole enabled */ | |
729 | if (lgcy_mmio_hole_en) { | |
730 | if (amd_df_indirect_read(nid, 0, 0x104, umc, &tmp)) | |
731 | goto out_err; | |
732 | ||
733 | dram_hole_base = tmp & GENMASK(31, 24); | |
734 | if (ret_addr >= dram_hole_base) | |
735 | ret_addr += (BIT_ULL(32) - dram_hole_base); | |
736 | } | |
737 | ||
738 | if (hash_enabled) { | |
739 | /* Save some parentheses and grab ls-bit at the end. */ | |
740 | hashed_bit = (ret_addr >> 12) ^ | |
741 | (ret_addr >> 18) ^ | |
742 | (ret_addr >> 21) ^ | |
743 | (ret_addr >> 30) ^ | |
744 | cs_id; | |
745 | ||
746 | hashed_bit &= BIT(0); | |
747 | ||
748 | if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0))) | |
749 | ret_addr ^= BIT(intlv_addr_bit); | |
750 | } | |
751 | ||
752 | /* Is calculated system address is above DRAM limit address? */ | |
753 | if (ret_addr > dram_limit_addr) | |
754 | goto out_err; | |
755 | ||
756 | *sys_addr = ret_addr; | |
757 | return 0; | |
758 | ||
759 | out_err: | |
760 | return -EINVAL; | |
761 | } | |
762 | EXPORT_SYMBOL_GPL(umc_normaddr_to_sysaddr); | |
763 | ||
c6708d50 YG |
764 | bool amd_mce_is_memory_error(struct mce *m) |
765 | { | |
766 | /* ErrCodeExt[20:16] */ | |
767 | u8 xec = (m->status >> 16) & 0x1f; | |
768 | ||
769 | if (mce_flags.smca) | |
e5d6a126 | 770 | return smca_get_bank_type(m->bank) == SMCA_UMC && xec == 0x0; |
c6708d50 YG |
771 | |
772 | return m->bank == 4 && xec == 0x8; | |
773 | } | |
774 | ||
37d43acf | 775 | static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) |
afdf344e AG |
776 | { |
777 | struct mce m; | |
afdf344e AG |
778 | |
779 | mce_setup(&m); | |
780 | ||
781 | m.status = status; | |
37d43acf | 782 | m.misc = misc; |
669c00f0 BP |
783 | m.bank = bank; |
784 | m.tsc = rdtsc(); | |
6e6e746e | 785 | |
4f29b73b | 786 | if (m.status & MCI_STATUS_ADDRV) { |
37d43acf | 787 | m.addr = addr; |
afdf344e | 788 | |
4f29b73b YG |
789 | /* |
790 | * Extract [55:<lsb>] where lsb is the least significant | |
791 | * *valid* bit of the address bits. | |
792 | */ | |
793 | if (mce_flags.smca) { | |
794 | u8 lsb = (m.addr >> 56) & 0x3f; | |
795 | ||
796 | m.addr &= GENMASK_ULL(55, lsb); | |
797 | } | |
798 | } | |
799 | ||
5828c46f YG |
800 | if (mce_flags.smca) { |
801 | rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid); | |
802 | ||
803 | if (m.status & MCI_STATUS_SYNDV) | |
804 | rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd); | |
805 | } | |
db819d60 | 806 | |
6e6e746e | 807 | mce_log(&m); |
afdf344e AG |
808 | } |
809 | ||
c4158ff5 | 810 | asmlinkage __visible void __irq_entry smp_deferred_error_interrupt(void) |
24fd78a8 AG |
811 | { |
812 | entering_irq(); | |
813 | trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR); | |
0f42ae28 TG |
814 | inc_irq_stat(irq_deferred_error_count); |
815 | deferred_error_int_vector(); | |
24fd78a8 AG |
816 | trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR); |
817 | exiting_ack_irq(); | |
818 | } | |
819 | ||
37d43acf YG |
820 | /* |
821 | * Returns true if the logged error is deferred. False, otherwise. | |
822 | */ | |
823 | static inline bool | |
824 | _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc) | |
24fd78a8 | 825 | { |
37d43acf | 826 | u64 status, addr = 0; |
24fd78a8 | 827 | |
37d43acf YG |
828 | rdmsrl(msr_stat, status); |
829 | if (!(status & MCI_STATUS_VAL)) | |
830 | return false; | |
34102009 | 831 | |
37d43acf YG |
832 | if (status & MCI_STATUS_ADDRV) |
833 | rdmsrl(msr_addr, addr); | |
24fd78a8 | 834 | |
37d43acf | 835 | __log_error(bank, status, addr, misc); |
24fd78a8 | 836 | |
a24b8c34 | 837 | wrmsrl(msr_stat, 0); |
37d43acf YG |
838 | |
839 | return status & MCI_STATUS_DEFERRED; | |
24fd78a8 AG |
840 | } |
841 | ||
89b831ef | 842 | /* |
37d43acf YG |
843 | * We have three scenarios for checking for Deferred errors: |
844 | * | |
845 | * 1) Non-SMCA systems check MCA_STATUS and log error if found. | |
846 | * 2) SMCA systems check MCA_STATUS. If error is found then log it and also | |
847 | * clear MCA_DESTAT. | |
848 | * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and | |
849 | * log it. | |
89b831ef | 850 | */ |
37d43acf YG |
851 | static void log_error_deferred(unsigned int bank) |
852 | { | |
853 | bool defrd; | |
854 | ||
855 | defrd = _log_error_bank(bank, msr_ops.status(bank), | |
856 | msr_ops.addr(bank), 0); | |
857 | ||
858 | if (!mce_flags.smca) | |
859 | return; | |
860 | ||
861 | /* Clear MCA_DESTAT if we logged the deferred error from MCA_STATUS. */ | |
862 | if (defrd) { | |
863 | wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0); | |
864 | return; | |
865 | } | |
866 | ||
867 | /* | |
868 | * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check | |
869 | * for a valid error. | |
870 | */ | |
871 | _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank), | |
872 | MSR_AMD64_SMCA_MCx_DEADDR(bank), 0); | |
873 | } | |
874 | ||
875 | /* APIC interrupt handler for deferred errors */ | |
876 | static void amd_deferred_error_interrupt(void) | |
877 | { | |
878 | unsigned int bank; | |
879 | ||
880 | for (bank = 0; bank < mca_cfg.banks; ++bank) | |
881 | log_error_deferred(bank); | |
882 | } | |
883 | ||
884 | static void log_error_thresholding(unsigned int bank, u64 misc) | |
885 | { | |
886 | _log_error_bank(bank, msr_ops.status(bank), msr_ops.addr(bank), misc); | |
887 | } | |
89b831ef | 888 | |
17ef4af0 YG |
889 | static void log_and_reset_block(struct threshold_block *block) |
890 | { | |
891 | struct thresh_restart tr; | |
892 | u32 low = 0, high = 0; | |
893 | ||
894 | if (!block) | |
895 | return; | |
896 | ||
897 | if (rdmsr_safe(block->address, &low, &high)) | |
898 | return; | |
899 | ||
900 | if (!(high & MASK_OVERFLOW_HI)) | |
901 | return; | |
902 | ||
903 | /* Log the MCE which caused the threshold event. */ | |
904 | log_error_thresholding(block->bank, ((u64)high << 32) | low); | |
905 | ||
906 | /* Reset threshold block after logging error. */ | |
907 | memset(&tr, 0, sizeof(tr)); | |
908 | tr.b = block; | |
909 | threshold_restart_bank(&tr); | |
910 | } | |
911 | ||
89b831ef | 912 | /* |
37d43acf YG |
913 | * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt |
914 | * goes off when error_count reaches threshold_limit. | |
89b831ef | 915 | */ |
b2762686 | 916 | static void amd_threshold_interrupt(void) |
89b831ef | 917 | { |
17ef4af0 YG |
918 | struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL; |
919 | unsigned int bank, cpu = smp_processor_id(); | |
89b831ef | 920 | |
bafcdd3b | 921 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
44612a3a | 922 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
24ce0e96 | 923 | continue; |
44612a3a | 924 | |
17ef4af0 YG |
925 | first_block = per_cpu(threshold_banks, cpu)[bank]->blocks; |
926 | if (!first_block) | |
927 | continue; | |
18807ddb | 928 | |
17ef4af0 YG |
929 | /* |
930 | * The first block is also the head of the list. Check it first | |
931 | * before iterating over the rest. | |
932 | */ | |
933 | log_and_reset_block(first_block); | |
934 | list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj) | |
935 | log_and_reset_block(block); | |
37d43acf | 936 | } |
89b831ef JS |
937 | } |
938 | ||
939 | /* | |
940 | * Sysfs Interface | |
941 | */ | |
942 | ||
89b831ef | 943 | struct threshold_attr { |
2903ee85 | 944 | struct attribute attr; |
1cb2a8e1 IM |
945 | ssize_t (*show) (struct threshold_block *, char *); |
946 | ssize_t (*store) (struct threshold_block *, const char *, size_t count); | |
89b831ef JS |
947 | }; |
948 | ||
1cb2a8e1 IM |
949 | #define SHOW_FIELDS(name) \ |
950 | static ssize_t show_ ## name(struct threshold_block *b, char *buf) \ | |
951 | { \ | |
18c20f37 | 952 | return sprintf(buf, "%lu\n", (unsigned long) b->name); \ |
2903ee85 | 953 | } |
89b831ef JS |
954 | SHOW_FIELDS(interrupt_enable) |
955 | SHOW_FIELDS(threshold_limit) | |
956 | ||
1cb2a8e1 | 957 | static ssize_t |
9319cec8 | 958 | store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size) |
89b831ef | 959 | { |
4cd4601d | 960 | struct thresh_restart tr; |
1cb2a8e1 | 961 | unsigned long new; |
1cb2a8e1 | 962 | |
f227d430 BP |
963 | if (!b->interrupt_capable) |
964 | return -EINVAL; | |
965 | ||
164109e3 | 966 | if (kstrtoul(buf, 0, &new) < 0) |
89b831ef | 967 | return -EINVAL; |
1cb2a8e1 | 968 | |
89b831ef JS |
969 | b->interrupt_enable = !!new; |
970 | ||
9c37c9d8 | 971 | memset(&tr, 0, sizeof(tr)); |
1cb2a8e1 | 972 | tr.b = b; |
1cb2a8e1 | 973 | |
a6b6a14e | 974 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef | 975 | |
9319cec8 | 976 | return size; |
89b831ef JS |
977 | } |
978 | ||
1cb2a8e1 | 979 | static ssize_t |
9319cec8 | 980 | store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) |
89b831ef | 981 | { |
4cd4601d | 982 | struct thresh_restart tr; |
1cb2a8e1 | 983 | unsigned long new; |
1cb2a8e1 | 984 | |
164109e3 | 985 | if (kstrtoul(buf, 0, &new) < 0) |
89b831ef | 986 | return -EINVAL; |
1cb2a8e1 | 987 | |
89b831ef JS |
988 | if (new > THRESHOLD_MAX) |
989 | new = THRESHOLD_MAX; | |
990 | if (new < 1) | |
991 | new = 1; | |
1cb2a8e1 | 992 | |
9c37c9d8 | 993 | memset(&tr, 0, sizeof(tr)); |
4cd4601d | 994 | tr.old_limit = b->threshold_limit; |
89b831ef | 995 | b->threshold_limit = new; |
4cd4601d | 996 | tr.b = b; |
89b831ef | 997 | |
a6b6a14e | 998 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef | 999 | |
9319cec8 | 1000 | return size; |
89b831ef JS |
1001 | } |
1002 | ||
4cd4601d MT |
1003 | static ssize_t show_error_count(struct threshold_block *b, char *buf) |
1004 | { | |
2c9c42fa BP |
1005 | u32 lo, hi; |
1006 | ||
1007 | rdmsr_on_cpu(b->cpu, b->address, &lo, &hi); | |
a6b6a14e | 1008 | |
2c9c42fa BP |
1009 | return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - |
1010 | (THRESHOLD_MAX - b->threshold_limit))); | |
89b831ef JS |
1011 | } |
1012 | ||
6e927361 BP |
1013 | static struct threshold_attr error_count = { |
1014 | .attr = {.name = __stringify(error_count), .mode = 0444 }, | |
1015 | .show = show_error_count, | |
1016 | }; | |
89b831ef | 1017 | |
34fa1967 HS |
1018 | #define RW_ATTR(val) \ |
1019 | static struct threshold_attr val = { \ | |
1020 | .attr = {.name = __stringify(val), .mode = 0644 }, \ | |
1021 | .show = show_## val, \ | |
1022 | .store = store_## val, \ | |
89b831ef JS |
1023 | }; |
1024 | ||
2903ee85 JS |
1025 | RW_ATTR(interrupt_enable); |
1026 | RW_ATTR(threshold_limit); | |
89b831ef JS |
1027 | |
1028 | static struct attribute *default_attrs[] = { | |
89b831ef JS |
1029 | &threshold_limit.attr, |
1030 | &error_count.attr, | |
d26ecc48 BP |
1031 | NULL, /* possibly interrupt_enable if supported, see below */ |
1032 | NULL, | |
89b831ef JS |
1033 | }; |
1034 | ||
1cb2a8e1 IM |
1035 | #define to_block(k) container_of(k, struct threshold_block, kobj) |
1036 | #define to_attr(a) container_of(a, struct threshold_attr, attr) | |
89b831ef JS |
1037 | |
1038 | static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) | |
1039 | { | |
95268664 | 1040 | struct threshold_block *b = to_block(kobj); |
89b831ef JS |
1041 | struct threshold_attr *a = to_attr(attr); |
1042 | ssize_t ret; | |
1cb2a8e1 | 1043 | |
89b831ef | 1044 | ret = a->show ? a->show(b, buf) : -EIO; |
1cb2a8e1 | 1045 | |
89b831ef JS |
1046 | return ret; |
1047 | } | |
1048 | ||
1049 | static ssize_t store(struct kobject *kobj, struct attribute *attr, | |
1050 | const char *buf, size_t count) | |
1051 | { | |
95268664 | 1052 | struct threshold_block *b = to_block(kobj); |
89b831ef JS |
1053 | struct threshold_attr *a = to_attr(attr); |
1054 | ssize_t ret; | |
1cb2a8e1 | 1055 | |
89b831ef | 1056 | ret = a->store ? a->store(b, buf, count) : -EIO; |
1cb2a8e1 | 1057 | |
89b831ef JS |
1058 | return ret; |
1059 | } | |
1060 | ||
52cf25d0 | 1061 | static const struct sysfs_ops threshold_ops = { |
1cb2a8e1 IM |
1062 | .show = show, |
1063 | .store = store, | |
89b831ef JS |
1064 | }; |
1065 | ||
1066 | static struct kobj_type threshold_ktype = { | |
1cb2a8e1 IM |
1067 | .sysfs_ops = &threshold_ops, |
1068 | .default_attrs = default_attrs, | |
89b831ef JS |
1069 | }; |
1070 | ||
87a6d409 YG |
1071 | static const char *get_name(unsigned int bank, struct threshold_block *b) |
1072 | { | |
e5d6a126 | 1073 | enum smca_bank_types bank_type; |
87a6d409 YG |
1074 | |
1075 | if (!mce_flags.smca) { | |
1076 | if (b && bank == 4) | |
1077 | return bank4_names(b); | |
1078 | ||
1079 | return th_names[bank]; | |
1080 | } | |
1081 | ||
e5d6a126 YG |
1082 | bank_type = smca_get_bank_type(bank); |
1083 | if (bank_type >= N_SMCA_BANK_TYPES) | |
87a6d409 YG |
1084 | return NULL; |
1085 | ||
87a6d409 YG |
1086 | if (b && bank_type == SMCA_UMC) { |
1087 | if (b->block < ARRAY_SIZE(smca_umc_block_names)) | |
1088 | return smca_umc_block_names[b->block]; | |
1089 | return NULL; | |
1090 | } | |
1091 | ||
0b737a9c YG |
1092 | if (smca_banks[bank].hwid->count == 1) |
1093 | return smca_get_name(bank_type); | |
1094 | ||
87a6d409 | 1095 | snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN, |
c09a8c40 | 1096 | "%s_%x", smca_get_name(bank_type), |
0b737a9c | 1097 | smca_banks[bank].sysfs_id); |
87a6d409 YG |
1098 | return buf_mcatype; |
1099 | } | |
1100 | ||
148f9bb8 PG |
1101 | static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank, |
1102 | unsigned int block, u32 address) | |
95268664 | 1103 | { |
95268664 | 1104 | struct threshold_block *b = NULL; |
1cb2a8e1 IM |
1105 | u32 low, high; |
1106 | int err; | |
95268664 | 1107 | |
bafcdd3b | 1108 | if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS)) |
95268664 JS |
1109 | return 0; |
1110 | ||
a6b6a14e | 1111 | if (rdmsr_safe_on_cpu(cpu, address, &low, &high)) |
24ce0e96 | 1112 | return 0; |
95268664 JS |
1113 | |
1114 | if (!(high & MASK_VALID_HI)) { | |
1115 | if (block) | |
1116 | goto recurse; | |
1117 | else | |
1118 | return 0; | |
1119 | } | |
1120 | ||
24ce0e96 JB |
1121 | if (!(high & MASK_CNTP_HI) || |
1122 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
1123 | goto recurse; |
1124 | ||
1125 | b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL); | |
1126 | if (!b) | |
1127 | return -ENOMEM; | |
95268664 | 1128 | |
1cb2a8e1 IM |
1129 | b->block = block; |
1130 | b->bank = bank; | |
1131 | b->cpu = cpu; | |
1132 | b->address = address; | |
1133 | b->interrupt_enable = 0; | |
f227d430 | 1134 | b->interrupt_capable = lvt_interrupt_supported(bank, high); |
1cb2a8e1 | 1135 | b->threshold_limit = THRESHOLD_MAX; |
95268664 | 1136 | |
d79f931f | 1137 | if (b->interrupt_capable) { |
d26ecc48 | 1138 | threshold_ktype.default_attrs[2] = &interrupt_enable.attr; |
d79f931f AG |
1139 | b->interrupt_enable = 1; |
1140 | } else { | |
d26ecc48 | 1141 | threshold_ktype.default_attrs[2] = NULL; |
d79f931f | 1142 | } |
d26ecc48 | 1143 | |
95268664 JS |
1144 | INIT_LIST_HEAD(&b->miscj); |
1145 | ||
1cb2a8e1 | 1146 | if (per_cpu(threshold_banks, cpu)[bank]->blocks) { |
95268664 JS |
1147 | list_add(&b->miscj, |
1148 | &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj); | |
1cb2a8e1 | 1149 | } else { |
95268664 | 1150 | per_cpu(threshold_banks, cpu)[bank]->blocks = b; |
1cb2a8e1 | 1151 | } |
95268664 | 1152 | |
542eb75a GKH |
1153 | err = kobject_init_and_add(&b->kobj, &threshold_ktype, |
1154 | per_cpu(threshold_banks, cpu)[bank]->kobj, | |
87a6d409 | 1155 | get_name(bank, b)); |
95268664 JS |
1156 | if (err) |
1157 | goto out_free; | |
1158 | recurse: | |
cfee4f6f | 1159 | address = get_block_address(cpu, address, low, high, bank, ++block); |
8dd1e17a AG |
1160 | if (!address) |
1161 | return 0; | |
95268664 | 1162 | |
8dd1e17a | 1163 | err = allocate_threshold_blocks(cpu, bank, block, address); |
95268664 JS |
1164 | if (err) |
1165 | goto out_free; | |
1166 | ||
213eca7f GKH |
1167 | if (b) |
1168 | kobject_uevent(&b->kobj, KOBJ_ADD); | |
542eb75a | 1169 | |
95268664 JS |
1170 | return err; |
1171 | ||
1172 | out_free: | |
1173 | if (b) { | |
38a382ae | 1174 | kobject_put(&b->kobj); |
d9a5ac9e | 1175 | list_del(&b->miscj); |
95268664 JS |
1176 | kfree(b); |
1177 | } | |
1178 | return err; | |
1179 | } | |
1180 | ||
148f9bb8 | 1181 | static int __threshold_add_blocks(struct threshold_bank *b) |
019f34fc BP |
1182 | { |
1183 | struct list_head *head = &b->blocks->miscj; | |
1184 | struct threshold_block *pos = NULL; | |
1185 | struct threshold_block *tmp = NULL; | |
1186 | int err = 0; | |
1187 | ||
1188 | err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name); | |
1189 | if (err) | |
1190 | return err; | |
1191 | ||
1192 | list_for_each_entry_safe(pos, tmp, head, miscj) { | |
1193 | ||
1194 | err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name); | |
1195 | if (err) { | |
1196 | list_for_each_entry_safe_reverse(pos, tmp, head, miscj) | |
1197 | kobject_del(&pos->kobj); | |
1198 | ||
1199 | return err; | |
1200 | } | |
1201 | } | |
1202 | return err; | |
1203 | } | |
1204 | ||
148f9bb8 | 1205 | static int threshold_create_bank(unsigned int cpu, unsigned int bank) |
89b831ef | 1206 | { |
d6126ef5 | 1207 | struct device *dev = per_cpu(mce_device, cpu); |
019f34fc | 1208 | struct amd_northbridge *nb = NULL; |
92e26e2a | 1209 | struct threshold_bank *b = NULL; |
87a6d409 | 1210 | const char *name = get_name(bank, NULL); |
92e26e2a | 1211 | int err = 0; |
95268664 | 1212 | |
0dad3a30 TG |
1213 | if (!dev) |
1214 | return -ENODEV; | |
1215 | ||
c76e8164 | 1216 | if (is_shared_bank(bank)) { |
019f34fc | 1217 | nb = node_to_amd_nb(amd_get_nb_id(cpu)); |
019f34fc BP |
1218 | |
1219 | /* threshold descriptor already initialized on this node? */ | |
21c5e50e | 1220 | if (nb && nb->bank4) { |
019f34fc BP |
1221 | /* yes, use it */ |
1222 | b = nb->bank4; | |
1223 | err = kobject_add(b->kobj, &dev->kobj, name); | |
1224 | if (err) | |
1225 | goto out; | |
1226 | ||
1227 | per_cpu(threshold_banks, cpu)[bank] = b; | |
473e90b2 | 1228 | refcount_inc(&b->cpus); |
019f34fc BP |
1229 | |
1230 | err = __threshold_add_blocks(b); | |
1231 | ||
1232 | goto out; | |
1233 | } | |
1234 | } | |
1235 | ||
95268664 | 1236 | b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL); |
89b831ef JS |
1237 | if (!b) { |
1238 | err = -ENOMEM; | |
1239 | goto out; | |
1240 | } | |
89b831ef | 1241 | |
e032d807 | 1242 | b->kobj = kobject_create_and_add(name, &dev->kobj); |
92e26e2a BP |
1243 | if (!b->kobj) { |
1244 | err = -EINVAL; | |
a521cf20 | 1245 | goto out_free; |
92e26e2a | 1246 | } |
95268664 | 1247 | |
89b831ef | 1248 | per_cpu(threshold_banks, cpu)[bank] = b; |
95268664 | 1249 | |
c76e8164 | 1250 | if (is_shared_bank(bank)) { |
473e90b2 | 1251 | refcount_set(&b->cpus, 1); |
019f34fc BP |
1252 | |
1253 | /* nb is already initialized, see above */ | |
21c5e50e DB |
1254 | if (nb) { |
1255 | WARN_ON(nb->bank4); | |
1256 | nb->bank4 = b; | |
1257 | } | |
019f34fc BP |
1258 | } |
1259 | ||
74ab0e7a | 1260 | err = allocate_threshold_blocks(cpu, bank, 0, msr_ops.misc(bank)); |
92e26e2a BP |
1261 | if (!err) |
1262 | goto out; | |
95268664 | 1263 | |
019f34fc | 1264 | out_free: |
95268664 | 1265 | kfree(b); |
019f34fc BP |
1266 | |
1267 | out: | |
89b831ef JS |
1268 | return err; |
1269 | } | |
1270 | ||
be6b5a35 | 1271 | static void deallocate_threshold_block(unsigned int cpu, |
95268664 JS |
1272 | unsigned int bank) |
1273 | { | |
1274 | struct threshold_block *pos = NULL; | |
1275 | struct threshold_block *tmp = NULL; | |
1276 | struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank]; | |
1277 | ||
1278 | if (!head) | |
1279 | return; | |
1280 | ||
1281 | list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) { | |
38a382ae | 1282 | kobject_put(&pos->kobj); |
95268664 JS |
1283 | list_del(&pos->miscj); |
1284 | kfree(pos); | |
1285 | } | |
1286 | ||
1287 | kfree(per_cpu(threshold_banks, cpu)[bank]->blocks); | |
1288 | per_cpu(threshold_banks, cpu)[bank]->blocks = NULL; | |
1289 | } | |
1290 | ||
019f34fc BP |
1291 | static void __threshold_remove_blocks(struct threshold_bank *b) |
1292 | { | |
1293 | struct threshold_block *pos = NULL; | |
1294 | struct threshold_block *tmp = NULL; | |
1295 | ||
1296 | kobject_del(b->kobj); | |
1297 | ||
1298 | list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj) | |
1299 | kobject_del(&pos->kobj); | |
1300 | } | |
1301 | ||
be6b5a35 | 1302 | static void threshold_remove_bank(unsigned int cpu, int bank) |
89b831ef | 1303 | { |
019f34fc | 1304 | struct amd_northbridge *nb; |
89b831ef | 1305 | struct threshold_bank *b; |
89b831ef JS |
1306 | |
1307 | b = per_cpu(threshold_banks, cpu)[bank]; | |
1308 | if (!b) | |
1309 | return; | |
019f34fc | 1310 | |
95268664 JS |
1311 | if (!b->blocks) |
1312 | goto free_out; | |
1313 | ||
c76e8164 | 1314 | if (is_shared_bank(bank)) { |
473e90b2 | 1315 | if (!refcount_dec_and_test(&b->cpus)) { |
019f34fc BP |
1316 | __threshold_remove_blocks(b); |
1317 | per_cpu(threshold_banks, cpu)[bank] = NULL; | |
1318 | return; | |
1319 | } else { | |
1320 | /* | |
1321 | * the last CPU on this node using the shared bank is | |
1322 | * going away, remove that bank now. | |
1323 | */ | |
1324 | nb = node_to_amd_nb(amd_get_nb_id(cpu)); | |
1325 | nb->bank4 = NULL; | |
1326 | } | |
1327 | } | |
1328 | ||
95268664 JS |
1329 | deallocate_threshold_block(cpu, bank); |
1330 | ||
1331 | free_out: | |
8735728e | 1332 | kobject_del(b->kobj); |
38a382ae | 1333 | kobject_put(b->kobj); |
95268664 JS |
1334 | kfree(b); |
1335 | per_cpu(threshold_banks, cpu)[bank] = NULL; | |
89b831ef JS |
1336 | } |
1337 | ||
4d7b02d5 | 1338 | int mce_threshold_remove_device(unsigned int cpu) |
89b831ef | 1339 | { |
2903ee85 | 1340 | unsigned int bank; |
89b831ef | 1341 | |
4d7b02d5 SAS |
1342 | if (!thresholding_en) |
1343 | return 0; | |
1344 | ||
bafcdd3b | 1345 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
5a96f4a5 | 1346 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
89b831ef JS |
1347 | continue; |
1348 | threshold_remove_bank(cpu, bank); | |
1349 | } | |
bafcdd3b | 1350 | kfree(per_cpu(threshold_banks, cpu)); |
ec553abb | 1351 | per_cpu(threshold_banks, cpu) = NULL; |
4d7b02d5 | 1352 | return 0; |
89b831ef JS |
1353 | } |
1354 | ||
09436372 | 1355 | /* create dir/files for all valid threshold banks */ |
4d7b02d5 | 1356 | int mce_threshold_create_device(unsigned int cpu) |
89b831ef | 1357 | { |
09436372 SAS |
1358 | unsigned int bank; |
1359 | struct threshold_bank **bp; | |
1360 | int err = 0; | |
1361 | ||
4d7b02d5 SAS |
1362 | if (!thresholding_en) |
1363 | return 0; | |
1364 | ||
7f34b935 SAS |
1365 | bp = per_cpu(threshold_banks, cpu); |
1366 | if (bp) | |
1367 | return 0; | |
1368 | ||
09436372 SAS |
1369 | bp = kzalloc(sizeof(struct threshold_bank *) * mca_cfg.banks, |
1370 | GFP_KERNEL); | |
1371 | if (!bp) | |
1372 | return -ENOMEM; | |
1373 | ||
1374 | per_cpu(threshold_banks, cpu) = bp; | |
1375 | ||
1376 | for (bank = 0; bank < mca_cfg.banks; ++bank) { | |
1377 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) | |
1378 | continue; | |
1379 | err = threshold_create_bank(cpu, bank); | |
1380 | if (err) | |
ec553abb | 1381 | goto err; |
89b831ef | 1382 | } |
ec553abb SAS |
1383 | return err; |
1384 | err: | |
4d7b02d5 | 1385 | mce_threshold_remove_device(cpu); |
09436372 | 1386 | return err; |
89b831ef JS |
1387 | } |
1388 | ||
89b831ef JS |
1389 | static __init int threshold_init_device(void) |
1390 | { | |
2903ee85 | 1391 | unsigned lcpu = 0; |
89b831ef | 1392 | |
254fe9c7 BP |
1393 | if (mce_threshold_vector == amd_threshold_interrupt) |
1394 | thresholding_en = true; | |
1395 | ||
89b831ef JS |
1396 | /* to hit CPUs online before the notifier is up */ |
1397 | for_each_online_cpu(lcpu) { | |
4d7b02d5 | 1398 | int err = mce_threshold_create_device(lcpu); |
1cb2a8e1 | 1399 | |
89b831ef | 1400 | if (err) |
fff2e89f | 1401 | return err; |
89b831ef | 1402 | } |
1cb2a8e1 | 1403 | |
fff2e89f | 1404 | return 0; |
89b831ef | 1405 | } |
a8fccdb0 LJ |
1406 | /* |
1407 | * there are 3 funcs which need to be _initcalled in a logic sequence: | |
1408 | * 1. xen_late_init_mcelog | |
1409 | * 2. mcheck_init_device | |
1410 | * 3. threshold_init_device | |
1411 | * | |
1412 | * xen_late_init_mcelog must register xen_mce_chrdev_device before | |
1413 | * native mce_chrdev_device registration if running under xen platform; | |
1414 | * | |
1415 | * mcheck_init_device should be inited before threshold_init_device to | |
1416 | * initialize mce_device, otherwise a NULL ptr dereference will cause panic. | |
1417 | * | |
1418 | * so we use following _initcalls | |
1419 | * 1. device_initcall(xen_late_init_mcelog); | |
1420 | * 2. device_initcall_sync(mcheck_init_device); | |
1421 | * 3. late_initcall(threshold_init_device); | |
1422 | * | |
1423 | * when running under xen, the initcall order is 1,2,3; | |
1424 | * on baremetal, we skip 1 and we do only 2 and 3. | |
1425 | */ | |
1426 | late_initcall(threshold_init_device); |