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Commit | Line | Data |
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89b831ef | 1 | /* |
ea2ca36b | 2 | * (c) 2005-2016 Advanced Micro Devices, Inc. |
89b831ef JS |
3 | * Your use of this code is subject to the terms and conditions of the |
4 | * GNU general public license version 2. See "COPYING" or | |
5 | * http://www.gnu.org/licenses/gpl.html | |
6 | * | |
7 | * Written by Jacob Shin - AMD, Inc. | |
e6d41e8c | 8 | * Maintained by: Borislav Petkov <bp@alien8.de> |
89b831ef | 9 | * |
3490c0e4 | 10 | * All MC4_MISCi registers are shared between cores on a node. |
89b831ef | 11 | */ |
89b831ef | 12 | #include <linux/interrupt.h> |
89b831ef | 13 | #include <linux/notifier.h> |
1cb2a8e1 | 14 | #include <linux/kobject.h> |
34fa1967 | 15 | #include <linux/percpu.h> |
1cb2a8e1 IM |
16 | #include <linux/errno.h> |
17 | #include <linux/sched.h> | |
89b831ef | 18 | #include <linux/sysfs.h> |
5a0e3ad6 | 19 | #include <linux/slab.h> |
1cb2a8e1 IM |
20 | #include <linux/init.h> |
21 | #include <linux/cpu.h> | |
22 | #include <linux/smp.h> | |
87a6d409 | 23 | #include <linux/string.h> |
1cb2a8e1 | 24 | |
019f34fc | 25 | #include <asm/amd_nb.h> |
89b831ef | 26 | #include <asm/apic.h> |
1cb2a8e1 | 27 | #include <asm/idle.h> |
89b831ef JS |
28 | #include <asm/mce.h> |
29 | #include <asm/msr.h> | |
24fd78a8 | 30 | #include <asm/trace/irq_vectors.h> |
89b831ef | 31 | |
60f116fc | 32 | #define NR_BLOCKS 5 |
2903ee85 JS |
33 | #define THRESHOLD_MAX 0xFFF |
34 | #define INT_TYPE_APIC 0x00020000 | |
35 | #define MASK_VALID_HI 0x80000000 | |
24ce0e96 JB |
36 | #define MASK_CNTP_HI 0x40000000 |
37 | #define MASK_LOCKED_HI 0x20000000 | |
2903ee85 JS |
38 | #define MASK_LVTOFF_HI 0x00F00000 |
39 | #define MASK_COUNT_EN_HI 0x00080000 | |
40 | #define MASK_INT_TYPE_HI 0x00060000 | |
41 | #define MASK_OVERFLOW_HI 0x00010000 | |
89b831ef | 42 | #define MASK_ERR_COUNT_HI 0x00000FFF |
95268664 JS |
43 | #define MASK_BLKPTR_LO 0xFF000000 |
44 | #define MCG_XBLK_ADDR 0xC0000400 | |
89b831ef | 45 | |
24fd78a8 AG |
46 | /* Deferred error settings */ |
47 | #define MSR_CU_DEF_ERR 0xC0000410 | |
48 | #define MASK_DEF_LVTOFF 0x000000F0 | |
49 | #define MASK_DEF_INT_TYPE 0x00000006 | |
50 | #define DEF_LVT_OFF 0x2 | |
51 | #define DEF_INT_TYPE_APIC 0x2 | |
52 | ||
f57a1f3c AG |
53 | /* Scalable MCA: */ |
54 | ||
55 | /* Threshold LVT offset is at MSR0xC0000410[15:12] */ | |
56 | #define SMCA_THR_LVT_OFF 0xF000 | |
57 | ||
336d335a BP |
58 | static const char * const th_names[] = { |
59 | "load_store", | |
60 | "insn_fetch", | |
61 | "combined_unit", | |
62 | "", | |
63 | "northbridge", | |
64 | "execution_unit", | |
65 | }; | |
66 | ||
87a6d409 YG |
67 | static const char * const smca_umc_block_names[] = { |
68 | "dram_ecc", | |
69 | "misc_umc" | |
70 | }; | |
71 | ||
c09a8c40 BP |
72 | struct smca_bank_name { |
73 | const char *name; /* Short name for sysfs */ | |
74 | const char *long_name; /* Long name for pretty-printing */ | |
75 | }; | |
76 | ||
77 | static struct smca_bank_name smca_names[] = { | |
5896820e YG |
78 | [SMCA_LS] = { "load_store", "Load Store Unit" }, |
79 | [SMCA_IF] = { "insn_fetch", "Instruction Fetch Unit" }, | |
80 | [SMCA_L2_CACHE] = { "l2_cache", "L2 Cache" }, | |
81 | [SMCA_DE] = { "decode_unit", "Decode Unit" }, | |
82 | [SMCA_EX] = { "execution_unit", "Execution Unit" }, | |
83 | [SMCA_FP] = { "floating_point", "Floating Point Unit" }, | |
84 | [SMCA_L3_CACHE] = { "l3_cache", "L3 Cache" }, | |
85 | [SMCA_CS] = { "coherent_slave", "Coherent Slave" }, | |
86 | [SMCA_PIE] = { "pie", "Power, Interrupts, etc." }, | |
87 | [SMCA_UMC] = { "umc", "Unified Memory Controller" }, | |
88 | [SMCA_PB] = { "param_block", "Parameter Block" }, | |
89 | [SMCA_PSP] = { "psp", "Platform Security Processor" }, | |
90 | [SMCA_SMU] = { "smu", "System Management Unit" }, | |
be0aec23 | 91 | }; |
c09a8c40 BP |
92 | |
93 | const char *smca_get_name(enum smca_bank_types t) | |
94 | { | |
95 | if (t >= N_SMCA_BANK_TYPES) | |
96 | return NULL; | |
97 | ||
98 | return smca_names[t].name; | |
99 | } | |
100 | ||
101 | const char *smca_get_long_name(enum smca_bank_types t) | |
102 | { | |
103 | if (t >= N_SMCA_BANK_TYPES) | |
104 | return NULL; | |
105 | ||
106 | return smca_names[t].long_name; | |
107 | } | |
108 | EXPORT_SYMBOL_GPL(smca_get_long_name); | |
5896820e | 109 | |
1ce9cd7f | 110 | static struct smca_hwid smca_hwid_mcatypes[] = { |
5896820e YG |
111 | /* { bank_type, hwid_mcatype, xec_bitmap } */ |
112 | ||
113 | /* ZN Core (HWID=0xB0) MCA types */ | |
114 | { SMCA_LS, HWID_MCATYPE(0xB0, 0x0), 0x1FFFEF }, | |
115 | { SMCA_IF, HWID_MCATYPE(0xB0, 0x1), 0x3FFF }, | |
116 | { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2), 0xF }, | |
117 | { SMCA_DE, HWID_MCATYPE(0xB0, 0x3), 0x1FF }, | |
118 | /* HWID 0xB0 MCATYPE 0x4 is Reserved */ | |
119 | { SMCA_EX, HWID_MCATYPE(0xB0, 0x5), 0x7FF }, | |
120 | { SMCA_FP, HWID_MCATYPE(0xB0, 0x6), 0x7F }, | |
121 | { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7), 0xFF }, | |
122 | ||
123 | /* Data Fabric MCA types */ | |
124 | { SMCA_CS, HWID_MCATYPE(0x2E, 0x0), 0x1FF }, | |
125 | { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1), 0xF }, | |
126 | ||
127 | /* Unified Memory Controller MCA type */ | |
128 | { SMCA_UMC, HWID_MCATYPE(0x96, 0x0), 0x3F }, | |
129 | ||
130 | /* Parameter Block MCA type */ | |
131 | { SMCA_PB, HWID_MCATYPE(0x05, 0x0), 0x1 }, | |
be0aec23 | 132 | |
5896820e YG |
133 | /* Platform Security Processor MCA type */ |
134 | { SMCA_PSP, HWID_MCATYPE(0xFF, 0x0), 0x1 }, | |
135 | ||
136 | /* System Management Unit MCA type */ | |
137 | { SMCA_SMU, HWID_MCATYPE(0x01, 0x0), 0x1 }, | |
be0aec23 | 138 | }; |
5896820e | 139 | |
79349f52 | 140 | struct smca_bank smca_banks[MAX_NR_BANKS]; |
5896820e | 141 | EXPORT_SYMBOL_GPL(smca_banks); |
be0aec23 | 142 | |
87a6d409 YG |
143 | /* |
144 | * In SMCA enabled processors, we can have multiple banks for a given IP type. | |
145 | * So to define a unique name for each bank, we use a temp c-string to append | |
146 | * the MCA_IPID[InstanceId] to type's name in get_name(). | |
147 | * | |
148 | * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN | |
149 | * is greater than 8 plus 1 (for underscore) plus length of longest type name. | |
150 | */ | |
151 | #define MAX_MCATYPE_NAME_LEN 30 | |
152 | static char buf_mcatype[MAX_MCATYPE_NAME_LEN]; | |
153 | ||
bafcdd3b | 154 | static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks); |
955d1427 | 155 | static DEFINE_PER_CPU(unsigned int, bank_map); /* see which banks are on */ |
89b831ef | 156 | |
b2762686 | 157 | static void amd_threshold_interrupt(void); |
24fd78a8 AG |
158 | static void amd_deferred_error_interrupt(void); |
159 | ||
160 | static void default_deferred_error_interrupt(void) | |
161 | { | |
162 | pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR); | |
163 | } | |
164 | void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; | |
b2762686 | 165 | |
5896820e YG |
166 | static void get_smca_bank_info(unsigned int bank) |
167 | { | |
168 | unsigned int i, hwid_mcatype, cpu = smp_processor_id(); | |
1ce9cd7f | 169 | struct smca_hwid *s_hwid; |
79349f52 | 170 | u32 high, instance_id; |
5896820e YG |
171 | |
172 | /* Collect bank_info using CPU 0 for now. */ | |
173 | if (cpu) | |
174 | return; | |
175 | ||
79349f52 | 176 | if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_IPID(bank), &instance_id, &high)) { |
5896820e YG |
177 | pr_warn("Failed to read MCA_IPID for bank %d\n", bank); |
178 | return; | |
179 | } | |
180 | ||
1ce9cd7f BP |
181 | hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID, |
182 | (high & MCI_IPID_MCATYPE) >> 16); | |
5896820e YG |
183 | |
184 | for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) { | |
1ce9cd7f BP |
185 | s_hwid = &smca_hwid_mcatypes[i]; |
186 | if (hwid_mcatype == s_hwid->hwid_mcatype) { | |
c09a8c40 BP |
187 | |
188 | WARN(smca_banks[bank].hwid, | |
189 | "Bank %s already initialized!\n", | |
190 | smca_get_name(s_hwid->bank_type)); | |
191 | ||
1ce9cd7f | 192 | smca_banks[bank].hwid = s_hwid; |
79349f52 | 193 | smca_banks[bank].id = instance_id; |
5896820e YG |
194 | break; |
195 | } | |
196 | } | |
197 | } | |
198 | ||
4cd4601d | 199 | struct thresh_restart { |
1cb2a8e1 IM |
200 | struct threshold_block *b; |
201 | int reset; | |
9c37c9d8 RR |
202 | int set_lvt_off; |
203 | int lvt_off; | |
1cb2a8e1 | 204 | u16 old_limit; |
4cd4601d MT |
205 | }; |
206 | ||
c76e8164 BO |
207 | static inline bool is_shared_bank(int bank) |
208 | { | |
284b965c AG |
209 | /* |
210 | * Scalable MCA provides for only one core to have access to the MSRs of | |
211 | * a shared bank. | |
212 | */ | |
213 | if (mce_flags.smca) | |
214 | return false; | |
215 | ||
c76e8164 BO |
216 | /* Bank 4 is for northbridge reporting and is thus shared */ |
217 | return (bank == 4); | |
218 | } | |
219 | ||
2cd4c303 | 220 | static const char *bank4_names(const struct threshold_block *b) |
336d335a BP |
221 | { |
222 | switch (b->address) { | |
223 | /* MSR4_MISC0 */ | |
224 | case 0x00000413: | |
225 | return "dram"; | |
226 | ||
227 | case 0xc0000408: | |
228 | return "ht_links"; | |
229 | ||
230 | case 0xc0000409: | |
231 | return "l3_cache"; | |
232 | ||
233 | default: | |
234 | WARN(1, "Funny MSR: 0x%08x\n", b->address); | |
235 | return ""; | |
236 | } | |
237 | }; | |
238 | ||
239 | ||
f227d430 BP |
240 | static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) |
241 | { | |
242 | /* | |
243 | * bank 4 supports APIC LVT interrupts implicitly since forever. | |
244 | */ | |
245 | if (bank == 4) | |
246 | return true; | |
247 | ||
248 | /* | |
249 | * IntP: interrupt present; if this bit is set, the thresholding | |
250 | * bank can generate APIC LVT interrupts | |
251 | */ | |
252 | return msr_high_bits & BIT(28); | |
253 | } | |
254 | ||
bbaff08d RR |
255 | static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) |
256 | { | |
257 | int msr = (hi & MASK_LVTOFF_HI) >> 20; | |
258 | ||
259 | if (apic < 0) { | |
260 | pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " | |
261 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, | |
262 | b->bank, b->block, b->address, hi, lo); | |
263 | return 0; | |
264 | } | |
265 | ||
266 | if (apic != msr) { | |
f57a1f3c AG |
267 | /* |
268 | * On SMCA CPUs, LVT offset is programmed at a different MSR, and | |
269 | * the BIOS provides the value. The original field where LVT offset | |
270 | * was set is reserved. Return early here: | |
271 | */ | |
272 | if (mce_flags.smca) | |
273 | return 0; | |
274 | ||
bbaff08d RR |
275 | pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " |
276 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n", | |
277 | b->cpu, apic, b->bank, b->block, b->address, hi, lo); | |
278 | return 0; | |
279 | } | |
280 | ||
281 | return 1; | |
282 | }; | |
283 | ||
ea2ca36b | 284 | /* Reprogram MCx_MISC MSR behind this threshold bank. */ |
a6b6a14e | 285 | static void threshold_restart_bank(void *_tr) |
89b831ef | 286 | { |
4cd4601d | 287 | struct thresh_restart *tr = _tr; |
7203a049 | 288 | u32 hi, lo; |
89b831ef | 289 | |
7203a049 | 290 | rdmsr(tr->b->address, lo, hi); |
89b831ef | 291 | |
7203a049 | 292 | if (tr->b->threshold_limit < (hi & THRESHOLD_MAX)) |
4cd4601d | 293 | tr->reset = 1; /* limit cannot be lower than err count */ |
89b831ef | 294 | |
4cd4601d | 295 | if (tr->reset) { /* reset err count and overflow bit */ |
7203a049 RR |
296 | hi = |
297 | (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) | | |
4cd4601d MT |
298 | (THRESHOLD_MAX - tr->b->threshold_limit); |
299 | } else if (tr->old_limit) { /* change limit w/o reset */ | |
7203a049 | 300 | int new_count = (hi & THRESHOLD_MAX) + |
4cd4601d | 301 | (tr->old_limit - tr->b->threshold_limit); |
1cb2a8e1 | 302 | |
7203a049 | 303 | hi = (hi & ~MASK_ERR_COUNT_HI) | |
89b831ef JS |
304 | (new_count & THRESHOLD_MAX); |
305 | } | |
306 | ||
f227d430 BP |
307 | /* clear IntType */ |
308 | hi &= ~MASK_INT_TYPE_HI; | |
309 | ||
310 | if (!tr->b->interrupt_capable) | |
311 | goto done; | |
312 | ||
9c37c9d8 | 313 | if (tr->set_lvt_off) { |
bbaff08d RR |
314 | if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) { |
315 | /* set new lvt offset */ | |
316 | hi &= ~MASK_LVTOFF_HI; | |
317 | hi |= tr->lvt_off << 20; | |
318 | } | |
9c37c9d8 RR |
319 | } |
320 | ||
f227d430 BP |
321 | if (tr->b->interrupt_enable) |
322 | hi |= INT_TYPE_APIC; | |
323 | ||
324 | done: | |
89b831ef | 325 | |
7203a049 RR |
326 | hi |= MASK_COUNT_EN_HI; |
327 | wrmsr(tr->b->address, lo, hi); | |
89b831ef JS |
328 | } |
329 | ||
9c37c9d8 RR |
330 | static void mce_threshold_block_init(struct threshold_block *b, int offset) |
331 | { | |
332 | struct thresh_restart tr = { | |
333 | .b = b, | |
334 | .set_lvt_off = 1, | |
335 | .lvt_off = offset, | |
336 | }; | |
337 | ||
338 | b->threshold_limit = THRESHOLD_MAX; | |
339 | threshold_restart_bank(&tr); | |
340 | }; | |
341 | ||
868c00bb | 342 | static int setup_APIC_mce_threshold(int reserved, int new) |
bbaff08d RR |
343 | { |
344 | if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR, | |
345 | APIC_EILVT_MSG_FIX, 0)) | |
346 | return new; | |
347 | ||
348 | return reserved; | |
349 | } | |
350 | ||
24fd78a8 AG |
351 | static int setup_APIC_deferred_error(int reserved, int new) |
352 | { | |
353 | if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR, | |
354 | APIC_EILVT_MSG_FIX, 0)) | |
355 | return new; | |
356 | ||
357 | return reserved; | |
358 | } | |
359 | ||
360 | static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) | |
361 | { | |
362 | u32 low = 0, high = 0; | |
363 | int def_offset = -1, def_new; | |
364 | ||
365 | if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) | |
366 | return; | |
367 | ||
368 | def_new = (low & MASK_DEF_LVTOFF) >> 4; | |
369 | if (!(low & MASK_DEF_LVTOFF)) { | |
370 | pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n"); | |
371 | def_new = DEF_LVT_OFF; | |
372 | low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4); | |
373 | } | |
374 | ||
375 | def_offset = setup_APIC_deferred_error(def_offset, def_new); | |
376 | if ((def_offset == def_new) && | |
377 | (deferred_error_int_vector != amd_deferred_error_interrupt)) | |
378 | deferred_error_int_vector = amd_deferred_error_interrupt; | |
379 | ||
380 | low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; | |
381 | wrmsr(MSR_CU_DEF_ERR, low, high); | |
382 | } | |
383 | ||
cfee4f6f | 384 | static u32 get_block_address(unsigned int cpu, u32 current_addr, u32 low, u32 high, |
8dd1e17a AG |
385 | unsigned int bank, unsigned int block) |
386 | { | |
387 | u32 addr = 0, offset = 0; | |
388 | ||
389 | if (mce_flags.smca) { | |
390 | if (!block) { | |
391 | addr = MSR_AMD64_SMCA_MCx_MISC(bank); | |
392 | } else { | |
393 | /* | |
394 | * For SMCA enabled processors, BLKPTR field of the | |
395 | * first MISC register (MCx_MISC0) indicates presence of | |
396 | * additional MISC register set (MISC1-4). | |
397 | */ | |
398 | u32 low, high; | |
399 | ||
cfee4f6f | 400 | if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) |
8dd1e17a AG |
401 | return addr; |
402 | ||
403 | if (!(low & MCI_CONFIG_MCAX)) | |
404 | return addr; | |
405 | ||
cfee4f6f | 406 | if (!rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) && |
8dd1e17a AG |
407 | (low & MASK_BLKPTR_LO)) |
408 | addr = MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); | |
409 | } | |
410 | return addr; | |
411 | } | |
412 | ||
413 | /* Fall back to method we used for older processors: */ | |
414 | switch (block) { | |
415 | case 0: | |
d9d73fcc | 416 | addr = msr_ops.misc(bank); |
8dd1e17a AG |
417 | break; |
418 | case 1: | |
419 | offset = ((low & MASK_BLKPTR_LO) >> 21); | |
420 | if (offset) | |
421 | addr = MCG_XBLK_ADDR + offset; | |
422 | break; | |
423 | default: | |
424 | addr = ++current_addr; | |
425 | } | |
426 | return addr; | |
427 | } | |
428 | ||
429893b1 BP |
429 | static int |
430 | prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, | |
431 | int offset, u32 misc_high) | |
432 | { | |
433 | unsigned int cpu = smp_processor_id(); | |
e128b4f4 | 434 | u32 smca_low, smca_high, smca_addr; |
429893b1 BP |
435 | struct threshold_block b; |
436 | int new; | |
437 | ||
438 | if (!block) | |
439 | per_cpu(bank_map, cpu) |= (1 << bank); | |
440 | ||
441 | memset(&b, 0, sizeof(b)); | |
442 | b.cpu = cpu; | |
443 | b.bank = bank; | |
444 | b.block = block; | |
445 | b.address = addr; | |
446 | b.interrupt_capable = lvt_interrupt_supported(bank, misc_high); | |
447 | ||
448 | if (!b.interrupt_capable) | |
449 | goto done; | |
450 | ||
451 | b.interrupt_enable = 1; | |
452 | ||
e128b4f4 BP |
453 | if (!mce_flags.smca) { |
454 | new = (misc_high & MASK_LVTOFF_HI) >> 20; | |
455 | goto set_offset; | |
456 | } | |
32544f06 | 457 | |
e128b4f4 | 458 | smca_addr = MSR_AMD64_SMCA_MCx_CONFIG(bank); |
32544f06 | 459 | |
e128b4f4 BP |
460 | if (!rdmsr_safe(smca_addr, &smca_low, &smca_high)) { |
461 | /* | |
462 | * OS is required to set the MCAX bit to acknowledge that it is | |
463 | * now using the new MSR ranges and new registers under each | |
464 | * bank. It also means that the OS will configure deferred | |
465 | * errors in the new MCx_CONFIG register. If the bit is not set, | |
466 | * uncorrectable errors will cause a system panic. | |
467 | * | |
468 | * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.) | |
469 | */ | |
470 | smca_high |= BIT(0); | |
429893b1 | 471 | |
e128b4f4 BP |
472 | /* |
473 | * SMCA logs Deferred Error information in MCA_DE{STAT,ADDR} | |
474 | * registers with the option of additionally logging to | |
475 | * MCA_{STATUS,ADDR} if MCA_CONFIG[LogDeferredInMcaStat] is set. | |
476 | * | |
477 | * This bit is usually set by BIOS to retain the old behavior | |
478 | * for OSes that don't use the new registers. Linux supports the | |
479 | * new registers so let's disable that additional logging here. | |
480 | * | |
481 | * MCA_CONFIG[LogDeferredInMcaStat] is bit 34 (bit 2 in the high | |
482 | * portion of the MSR). | |
483 | */ | |
484 | smca_high &= ~BIT(2); | |
429893b1 | 485 | |
66ef269d YG |
486 | /* |
487 | * SMCA sets the Deferred Error Interrupt type per bank. | |
488 | * | |
489 | * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us | |
490 | * if the DeferredIntType bit field is available. | |
491 | * | |
492 | * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the | |
493 | * high portion of the MSR). OS should set this to 0x1 to enable | |
494 | * APIC based interrupt. First, check that no interrupt has been | |
495 | * set. | |
496 | */ | |
497 | if ((smca_low & BIT(5)) && !((smca_high >> 5) & 0x3)) | |
498 | smca_high |= BIT(5); | |
499 | ||
e128b4f4 | 500 | wrmsr(smca_addr, smca_low, smca_high); |
429893b1 BP |
501 | } |
502 | ||
e128b4f4 BP |
503 | /* Gather LVT offset for thresholding: */ |
504 | if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high)) | |
505 | goto out; | |
506 | ||
507 | new = (smca_low & SMCA_THR_LVT_OFF) >> 12; | |
508 | ||
509 | set_offset: | |
429893b1 BP |
510 | offset = setup_APIC_mce_threshold(offset, new); |
511 | ||
512 | if ((offset == new) && (mce_threshold_vector != amd_threshold_interrupt)) | |
513 | mce_threshold_vector = amd_threshold_interrupt; | |
514 | ||
515 | done: | |
516 | mce_threshold_block_init(&b, offset); | |
517 | ||
518 | out: | |
519 | return offset; | |
520 | } | |
521 | ||
95268664 | 522 | /* cpu init entry point, called from mce.c with preempt off */ |
cc3ca220 | 523 | void mce_amd_feature_init(struct cpuinfo_x86 *c) |
89b831ef | 524 | { |
95268664 | 525 | u32 low = 0, high = 0, address = 0; |
cfee4f6f | 526 | unsigned int bank, block, cpu = smp_processor_id(); |
429893b1 | 527 | int offset = -1; |
89b831ef | 528 | |
bafcdd3b | 529 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
5896820e YG |
530 | if (mce_flags.smca) |
531 | get_smca_bank_info(bank); | |
532 | ||
95268664 | 533 | for (block = 0; block < NR_BLOCKS; ++block) { |
cfee4f6f | 534 | address = get_block_address(cpu, address, low, high, bank, block); |
8dd1e17a AG |
535 | if (!address) |
536 | break; | |
95268664 JS |
537 | |
538 | if (rdmsr_safe(address, &low, &high)) | |
24ce0e96 | 539 | break; |
95268664 | 540 | |
6dcbfe4f BP |
541 | if (!(high & MASK_VALID_HI)) |
542 | continue; | |
95268664 | 543 | |
24ce0e96 JB |
544 | if (!(high & MASK_CNTP_HI) || |
545 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
546 | continue; |
547 | ||
429893b1 | 548 | offset = prepare_threshold_block(bank, block, address, offset, high); |
95268664 | 549 | } |
89b831ef | 550 | } |
24fd78a8 AG |
551 | |
552 | if (mce_flags.succor) | |
553 | deferred_error_interrupt_enable(c); | |
89b831ef JS |
554 | } |
555 | ||
34102009 YG |
556 | static void |
557 | __log_error(unsigned int bank, bool deferred_err, bool threshold_err, u64 misc) | |
afdf344e | 558 | { |
34102009 YG |
559 | u32 msr_status = msr_ops.status(bank); |
560 | u32 msr_addr = msr_ops.addr(bank); | |
afdf344e AG |
561 | struct mce m; |
562 | u64 status; | |
563 | ||
34102009 YG |
564 | WARN_ON_ONCE(deferred_err && threshold_err); |
565 | ||
566 | if (deferred_err && mce_flags.smca) { | |
567 | msr_status = MSR_AMD64_SMCA_MCx_DESTAT(bank); | |
568 | msr_addr = MSR_AMD64_SMCA_MCx_DEADDR(bank); | |
569 | } | |
570 | ||
571 | rdmsrl(msr_status, status); | |
572 | ||
afdf344e AG |
573 | if (!(status & MCI_STATUS_VAL)) |
574 | return; | |
575 | ||
576 | mce_setup(&m); | |
577 | ||
578 | m.status = status; | |
579 | m.bank = bank; | |
6e6e746e | 580 | |
afdf344e AG |
581 | if (threshold_err) |
582 | m.misc = misc; | |
583 | ||
4f29b73b | 584 | if (m.status & MCI_STATUS_ADDRV) { |
34102009 | 585 | rdmsrl(msr_addr, m.addr); |
afdf344e | 586 | |
4f29b73b YG |
587 | /* |
588 | * Extract [55:<lsb>] where lsb is the least significant | |
589 | * *valid* bit of the address bits. | |
590 | */ | |
591 | if (mce_flags.smca) { | |
592 | u8 lsb = (m.addr >> 56) & 0x3f; | |
593 | ||
594 | m.addr &= GENMASK_ULL(55, lsb); | |
595 | } | |
596 | } | |
597 | ||
5828c46f YG |
598 | if (mce_flags.smca) { |
599 | rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid); | |
600 | ||
601 | if (m.status & MCI_STATUS_SYNDV) | |
602 | rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd); | |
603 | } | |
db819d60 | 604 | |
6e6e746e | 605 | mce_log(&m); |
34102009 YG |
606 | |
607 | wrmsrl(msr_status, 0); | |
afdf344e AG |
608 | } |
609 | ||
24fd78a8 AG |
610 | static inline void __smp_deferred_error_interrupt(void) |
611 | { | |
612 | inc_irq_stat(irq_deferred_error_count); | |
613 | deferred_error_int_vector(); | |
614 | } | |
615 | ||
616 | asmlinkage __visible void smp_deferred_error_interrupt(void) | |
617 | { | |
618 | entering_irq(); | |
619 | __smp_deferred_error_interrupt(); | |
620 | exiting_ack_irq(); | |
621 | } | |
622 | ||
623 | asmlinkage __visible void smp_trace_deferred_error_interrupt(void) | |
624 | { | |
625 | entering_irq(); | |
626 | trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR); | |
627 | __smp_deferred_error_interrupt(); | |
628 | trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR); | |
629 | exiting_ack_irq(); | |
630 | } | |
631 | ||
632 | /* APIC interrupt handler for deferred errors */ | |
633 | static void amd_deferred_error_interrupt(void) | |
634 | { | |
24fd78a8 | 635 | unsigned int bank; |
34102009 YG |
636 | u32 msr_status; |
637 | u64 status; | |
24fd78a8 AG |
638 | |
639 | for (bank = 0; bank < mca_cfg.banks; ++bank) { | |
34102009 YG |
640 | msr_status = (mce_flags.smca) ? MSR_AMD64_SMCA_MCx_DESTAT(bank) |
641 | : msr_ops.status(bank); | |
642 | ||
643 | rdmsrl(msr_status, status); | |
24fd78a8 AG |
644 | |
645 | if (!(status & MCI_STATUS_VAL) || | |
646 | !(status & MCI_STATUS_DEFERRED)) | |
647 | continue; | |
648 | ||
34102009 | 649 | __log_error(bank, true, false, 0); |
24fd78a8 AG |
650 | break; |
651 | } | |
652 | } | |
653 | ||
89b831ef JS |
654 | /* |
655 | * APIC Interrupt Handler | |
656 | */ | |
657 | ||
658 | /* | |
659 | * threshold interrupt handler will service THRESHOLD_APIC_VECTOR. | |
660 | * the interrupt goes off when error_count reaches threshold_limit. | |
661 | * the handler will simply log mcelog w/ software defined bank number. | |
662 | */ | |
afdf344e | 663 | |
b2762686 | 664 | static void amd_threshold_interrupt(void) |
89b831ef | 665 | { |
1cb2a8e1 | 666 | u32 low = 0, high = 0, address = 0; |
cfee4f6f | 667 | unsigned int bank, block, cpu = smp_processor_id(); |
89b831ef | 668 | |
89b831ef | 669 | /* assume first bank caused it */ |
bafcdd3b | 670 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
44612a3a | 671 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
24ce0e96 | 672 | continue; |
95268664 | 673 | for (block = 0; block < NR_BLOCKS; ++block) { |
cfee4f6f | 674 | address = get_block_address(cpu, address, low, high, bank, block); |
8dd1e17a AG |
675 | if (!address) |
676 | break; | |
95268664 JS |
677 | |
678 | if (rdmsr_safe(address, &low, &high)) | |
24ce0e96 | 679 | break; |
95268664 JS |
680 | |
681 | if (!(high & MASK_VALID_HI)) { | |
682 | if (block) | |
683 | continue; | |
684 | else | |
685 | break; | |
686 | } | |
687 | ||
24ce0e96 JB |
688 | if (!(high & MASK_CNTP_HI) || |
689 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
690 | continue; |
691 | ||
1cb2a8e1 IM |
692 | /* |
693 | * Log the machine check that caused the threshold | |
694 | * event. | |
695 | */ | |
44612a3a CY |
696 | if (high & MASK_OVERFLOW_HI) |
697 | goto log; | |
89b831ef JS |
698 | } |
699 | } | |
44612a3a CY |
700 | return; |
701 | ||
702 | log: | |
34102009 | 703 | __log_error(bank, false, true, ((u64)high << 32) | low); |
89b831ef JS |
704 | } |
705 | ||
706 | /* | |
707 | * Sysfs Interface | |
708 | */ | |
709 | ||
89b831ef | 710 | struct threshold_attr { |
2903ee85 | 711 | struct attribute attr; |
1cb2a8e1 IM |
712 | ssize_t (*show) (struct threshold_block *, char *); |
713 | ssize_t (*store) (struct threshold_block *, const char *, size_t count); | |
89b831ef JS |
714 | }; |
715 | ||
1cb2a8e1 IM |
716 | #define SHOW_FIELDS(name) \ |
717 | static ssize_t show_ ## name(struct threshold_block *b, char *buf) \ | |
718 | { \ | |
18c20f37 | 719 | return sprintf(buf, "%lu\n", (unsigned long) b->name); \ |
2903ee85 | 720 | } |
89b831ef JS |
721 | SHOW_FIELDS(interrupt_enable) |
722 | SHOW_FIELDS(threshold_limit) | |
723 | ||
1cb2a8e1 | 724 | static ssize_t |
9319cec8 | 725 | store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size) |
89b831ef | 726 | { |
4cd4601d | 727 | struct thresh_restart tr; |
1cb2a8e1 | 728 | unsigned long new; |
1cb2a8e1 | 729 | |
f227d430 BP |
730 | if (!b->interrupt_capable) |
731 | return -EINVAL; | |
732 | ||
164109e3 | 733 | if (kstrtoul(buf, 0, &new) < 0) |
89b831ef | 734 | return -EINVAL; |
1cb2a8e1 | 735 | |
89b831ef JS |
736 | b->interrupt_enable = !!new; |
737 | ||
9c37c9d8 | 738 | memset(&tr, 0, sizeof(tr)); |
1cb2a8e1 | 739 | tr.b = b; |
1cb2a8e1 | 740 | |
a6b6a14e | 741 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef | 742 | |
9319cec8 | 743 | return size; |
89b831ef JS |
744 | } |
745 | ||
1cb2a8e1 | 746 | static ssize_t |
9319cec8 | 747 | store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) |
89b831ef | 748 | { |
4cd4601d | 749 | struct thresh_restart tr; |
1cb2a8e1 | 750 | unsigned long new; |
1cb2a8e1 | 751 | |
164109e3 | 752 | if (kstrtoul(buf, 0, &new) < 0) |
89b831ef | 753 | return -EINVAL; |
1cb2a8e1 | 754 | |
89b831ef JS |
755 | if (new > THRESHOLD_MAX) |
756 | new = THRESHOLD_MAX; | |
757 | if (new < 1) | |
758 | new = 1; | |
1cb2a8e1 | 759 | |
9c37c9d8 | 760 | memset(&tr, 0, sizeof(tr)); |
4cd4601d | 761 | tr.old_limit = b->threshold_limit; |
89b831ef | 762 | b->threshold_limit = new; |
4cd4601d | 763 | tr.b = b; |
89b831ef | 764 | |
a6b6a14e | 765 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef | 766 | |
9319cec8 | 767 | return size; |
89b831ef JS |
768 | } |
769 | ||
4cd4601d MT |
770 | static ssize_t show_error_count(struct threshold_block *b, char *buf) |
771 | { | |
2c9c42fa BP |
772 | u32 lo, hi; |
773 | ||
774 | rdmsr_on_cpu(b->cpu, b->address, &lo, &hi); | |
a6b6a14e | 775 | |
2c9c42fa BP |
776 | return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - |
777 | (THRESHOLD_MAX - b->threshold_limit))); | |
89b831ef JS |
778 | } |
779 | ||
6e927361 BP |
780 | static struct threshold_attr error_count = { |
781 | .attr = {.name = __stringify(error_count), .mode = 0444 }, | |
782 | .show = show_error_count, | |
783 | }; | |
89b831ef | 784 | |
34fa1967 HS |
785 | #define RW_ATTR(val) \ |
786 | static struct threshold_attr val = { \ | |
787 | .attr = {.name = __stringify(val), .mode = 0644 }, \ | |
788 | .show = show_## val, \ | |
789 | .store = store_## val, \ | |
89b831ef JS |
790 | }; |
791 | ||
2903ee85 JS |
792 | RW_ATTR(interrupt_enable); |
793 | RW_ATTR(threshold_limit); | |
89b831ef JS |
794 | |
795 | static struct attribute *default_attrs[] = { | |
89b831ef JS |
796 | &threshold_limit.attr, |
797 | &error_count.attr, | |
d26ecc48 BP |
798 | NULL, /* possibly interrupt_enable if supported, see below */ |
799 | NULL, | |
89b831ef JS |
800 | }; |
801 | ||
1cb2a8e1 IM |
802 | #define to_block(k) container_of(k, struct threshold_block, kobj) |
803 | #define to_attr(a) container_of(a, struct threshold_attr, attr) | |
89b831ef JS |
804 | |
805 | static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) | |
806 | { | |
95268664 | 807 | struct threshold_block *b = to_block(kobj); |
89b831ef JS |
808 | struct threshold_attr *a = to_attr(attr); |
809 | ssize_t ret; | |
1cb2a8e1 | 810 | |
89b831ef | 811 | ret = a->show ? a->show(b, buf) : -EIO; |
1cb2a8e1 | 812 | |
89b831ef JS |
813 | return ret; |
814 | } | |
815 | ||
816 | static ssize_t store(struct kobject *kobj, struct attribute *attr, | |
817 | const char *buf, size_t count) | |
818 | { | |
95268664 | 819 | struct threshold_block *b = to_block(kobj); |
89b831ef JS |
820 | struct threshold_attr *a = to_attr(attr); |
821 | ssize_t ret; | |
1cb2a8e1 | 822 | |
89b831ef | 823 | ret = a->store ? a->store(b, buf, count) : -EIO; |
1cb2a8e1 | 824 | |
89b831ef JS |
825 | return ret; |
826 | } | |
827 | ||
52cf25d0 | 828 | static const struct sysfs_ops threshold_ops = { |
1cb2a8e1 IM |
829 | .show = show, |
830 | .store = store, | |
89b831ef JS |
831 | }; |
832 | ||
833 | static struct kobj_type threshold_ktype = { | |
1cb2a8e1 IM |
834 | .sysfs_ops = &threshold_ops, |
835 | .default_attrs = default_attrs, | |
89b831ef JS |
836 | }; |
837 | ||
87a6d409 YG |
838 | static const char *get_name(unsigned int bank, struct threshold_block *b) |
839 | { | |
840 | unsigned int bank_type; | |
841 | ||
842 | if (!mce_flags.smca) { | |
843 | if (b && bank == 4) | |
844 | return bank4_names(b); | |
845 | ||
846 | return th_names[bank]; | |
847 | } | |
848 | ||
1ce9cd7f | 849 | if (!smca_banks[bank].hwid) |
87a6d409 YG |
850 | return NULL; |
851 | ||
1ce9cd7f | 852 | bank_type = smca_banks[bank].hwid->bank_type; |
87a6d409 YG |
853 | |
854 | if (b && bank_type == SMCA_UMC) { | |
855 | if (b->block < ARRAY_SIZE(smca_umc_block_names)) | |
856 | return smca_umc_block_names[b->block]; | |
857 | return NULL; | |
858 | } | |
859 | ||
860 | snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN, | |
c09a8c40 | 861 | "%s_%x", smca_get_name(bank_type), |
79349f52 | 862 | smca_banks[bank].id); |
87a6d409 YG |
863 | return buf_mcatype; |
864 | } | |
865 | ||
148f9bb8 PG |
866 | static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank, |
867 | unsigned int block, u32 address) | |
95268664 | 868 | { |
95268664 | 869 | struct threshold_block *b = NULL; |
1cb2a8e1 IM |
870 | u32 low, high; |
871 | int err; | |
95268664 | 872 | |
bafcdd3b | 873 | if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS)) |
95268664 JS |
874 | return 0; |
875 | ||
a6b6a14e | 876 | if (rdmsr_safe_on_cpu(cpu, address, &low, &high)) |
24ce0e96 | 877 | return 0; |
95268664 JS |
878 | |
879 | if (!(high & MASK_VALID_HI)) { | |
880 | if (block) | |
881 | goto recurse; | |
882 | else | |
883 | return 0; | |
884 | } | |
885 | ||
24ce0e96 JB |
886 | if (!(high & MASK_CNTP_HI) || |
887 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
888 | goto recurse; |
889 | ||
890 | b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL); | |
891 | if (!b) | |
892 | return -ENOMEM; | |
95268664 | 893 | |
1cb2a8e1 IM |
894 | b->block = block; |
895 | b->bank = bank; | |
896 | b->cpu = cpu; | |
897 | b->address = address; | |
898 | b->interrupt_enable = 0; | |
f227d430 | 899 | b->interrupt_capable = lvt_interrupt_supported(bank, high); |
1cb2a8e1 | 900 | b->threshold_limit = THRESHOLD_MAX; |
95268664 | 901 | |
d79f931f | 902 | if (b->interrupt_capable) { |
d26ecc48 | 903 | threshold_ktype.default_attrs[2] = &interrupt_enable.attr; |
d79f931f AG |
904 | b->interrupt_enable = 1; |
905 | } else { | |
d26ecc48 | 906 | threshold_ktype.default_attrs[2] = NULL; |
d79f931f | 907 | } |
d26ecc48 | 908 | |
95268664 JS |
909 | INIT_LIST_HEAD(&b->miscj); |
910 | ||
1cb2a8e1 | 911 | if (per_cpu(threshold_banks, cpu)[bank]->blocks) { |
95268664 JS |
912 | list_add(&b->miscj, |
913 | &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj); | |
1cb2a8e1 | 914 | } else { |
95268664 | 915 | per_cpu(threshold_banks, cpu)[bank]->blocks = b; |
1cb2a8e1 | 916 | } |
95268664 | 917 | |
542eb75a GKH |
918 | err = kobject_init_and_add(&b->kobj, &threshold_ktype, |
919 | per_cpu(threshold_banks, cpu)[bank]->kobj, | |
87a6d409 | 920 | get_name(bank, b)); |
95268664 JS |
921 | if (err) |
922 | goto out_free; | |
923 | recurse: | |
cfee4f6f | 924 | address = get_block_address(cpu, address, low, high, bank, ++block); |
8dd1e17a AG |
925 | if (!address) |
926 | return 0; | |
95268664 | 927 | |
8dd1e17a | 928 | err = allocate_threshold_blocks(cpu, bank, block, address); |
95268664 JS |
929 | if (err) |
930 | goto out_free; | |
931 | ||
213eca7f GKH |
932 | if (b) |
933 | kobject_uevent(&b->kobj, KOBJ_ADD); | |
542eb75a | 934 | |
95268664 JS |
935 | return err; |
936 | ||
937 | out_free: | |
938 | if (b) { | |
38a382ae | 939 | kobject_put(&b->kobj); |
d9a5ac9e | 940 | list_del(&b->miscj); |
95268664 JS |
941 | kfree(b); |
942 | } | |
943 | return err; | |
944 | } | |
945 | ||
148f9bb8 | 946 | static int __threshold_add_blocks(struct threshold_bank *b) |
019f34fc BP |
947 | { |
948 | struct list_head *head = &b->blocks->miscj; | |
949 | struct threshold_block *pos = NULL; | |
950 | struct threshold_block *tmp = NULL; | |
951 | int err = 0; | |
952 | ||
953 | err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name); | |
954 | if (err) | |
955 | return err; | |
956 | ||
957 | list_for_each_entry_safe(pos, tmp, head, miscj) { | |
958 | ||
959 | err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name); | |
960 | if (err) { | |
961 | list_for_each_entry_safe_reverse(pos, tmp, head, miscj) | |
962 | kobject_del(&pos->kobj); | |
963 | ||
964 | return err; | |
965 | } | |
966 | } | |
967 | return err; | |
968 | } | |
969 | ||
148f9bb8 | 970 | static int threshold_create_bank(unsigned int cpu, unsigned int bank) |
89b831ef | 971 | { |
d6126ef5 | 972 | struct device *dev = per_cpu(mce_device, cpu); |
019f34fc | 973 | struct amd_northbridge *nb = NULL; |
92e26e2a | 974 | struct threshold_bank *b = NULL; |
87a6d409 | 975 | const char *name = get_name(bank, NULL); |
92e26e2a | 976 | int err = 0; |
95268664 | 977 | |
c76e8164 | 978 | if (is_shared_bank(bank)) { |
019f34fc | 979 | nb = node_to_amd_nb(amd_get_nb_id(cpu)); |
019f34fc BP |
980 | |
981 | /* threshold descriptor already initialized on this node? */ | |
21c5e50e | 982 | if (nb && nb->bank4) { |
019f34fc BP |
983 | /* yes, use it */ |
984 | b = nb->bank4; | |
985 | err = kobject_add(b->kobj, &dev->kobj, name); | |
986 | if (err) | |
987 | goto out; | |
988 | ||
989 | per_cpu(threshold_banks, cpu)[bank] = b; | |
990 | atomic_inc(&b->cpus); | |
991 | ||
992 | err = __threshold_add_blocks(b); | |
993 | ||
994 | goto out; | |
995 | } | |
996 | } | |
997 | ||
95268664 | 998 | b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL); |
89b831ef JS |
999 | if (!b) { |
1000 | err = -ENOMEM; | |
1001 | goto out; | |
1002 | } | |
89b831ef | 1003 | |
e032d807 | 1004 | b->kobj = kobject_create_and_add(name, &dev->kobj); |
92e26e2a BP |
1005 | if (!b->kobj) { |
1006 | err = -EINVAL; | |
a521cf20 | 1007 | goto out_free; |
92e26e2a | 1008 | } |
95268664 | 1009 | |
89b831ef | 1010 | per_cpu(threshold_banks, cpu)[bank] = b; |
95268664 | 1011 | |
c76e8164 | 1012 | if (is_shared_bank(bank)) { |
019f34fc BP |
1013 | atomic_set(&b->cpus, 1); |
1014 | ||
1015 | /* nb is already initialized, see above */ | |
21c5e50e DB |
1016 | if (nb) { |
1017 | WARN_ON(nb->bank4); | |
1018 | nb->bank4 = b; | |
1019 | } | |
019f34fc BP |
1020 | } |
1021 | ||
74ab0e7a | 1022 | err = allocate_threshold_blocks(cpu, bank, 0, msr_ops.misc(bank)); |
92e26e2a BP |
1023 | if (!err) |
1024 | goto out; | |
95268664 | 1025 | |
019f34fc | 1026 | out_free: |
95268664 | 1027 | kfree(b); |
019f34fc BP |
1028 | |
1029 | out: | |
89b831ef JS |
1030 | return err; |
1031 | } | |
1032 | ||
1033 | /* create dir/files for all valid threshold banks */ | |
148f9bb8 | 1034 | static int threshold_create_device(unsigned int cpu) |
89b831ef | 1035 | { |
2903ee85 | 1036 | unsigned int bank; |
bafcdd3b | 1037 | struct threshold_bank **bp; |
89b831ef JS |
1038 | int err = 0; |
1039 | ||
bafcdd3b BO |
1040 | bp = kzalloc(sizeof(struct threshold_bank *) * mca_cfg.banks, |
1041 | GFP_KERNEL); | |
1042 | if (!bp) | |
1043 | return -ENOMEM; | |
1044 | ||
1045 | per_cpu(threshold_banks, cpu) = bp; | |
1046 | ||
1047 | for (bank = 0; bank < mca_cfg.banks; ++bank) { | |
5a96f4a5 | 1048 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
89b831ef JS |
1049 | continue; |
1050 | err = threshold_create_bank(cpu, bank); | |
1051 | if (err) | |
0a17941e | 1052 | return err; |
89b831ef | 1053 | } |
0a17941e | 1054 | |
89b831ef JS |
1055 | return err; |
1056 | } | |
1057 | ||
be6b5a35 | 1058 | static void deallocate_threshold_block(unsigned int cpu, |
95268664 JS |
1059 | unsigned int bank) |
1060 | { | |
1061 | struct threshold_block *pos = NULL; | |
1062 | struct threshold_block *tmp = NULL; | |
1063 | struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank]; | |
1064 | ||
1065 | if (!head) | |
1066 | return; | |
1067 | ||
1068 | list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) { | |
38a382ae | 1069 | kobject_put(&pos->kobj); |
95268664 JS |
1070 | list_del(&pos->miscj); |
1071 | kfree(pos); | |
1072 | } | |
1073 | ||
1074 | kfree(per_cpu(threshold_banks, cpu)[bank]->blocks); | |
1075 | per_cpu(threshold_banks, cpu)[bank]->blocks = NULL; | |
1076 | } | |
1077 | ||
019f34fc BP |
1078 | static void __threshold_remove_blocks(struct threshold_bank *b) |
1079 | { | |
1080 | struct threshold_block *pos = NULL; | |
1081 | struct threshold_block *tmp = NULL; | |
1082 | ||
1083 | kobject_del(b->kobj); | |
1084 | ||
1085 | list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj) | |
1086 | kobject_del(&pos->kobj); | |
1087 | } | |
1088 | ||
be6b5a35 | 1089 | static void threshold_remove_bank(unsigned int cpu, int bank) |
89b831ef | 1090 | { |
019f34fc | 1091 | struct amd_northbridge *nb; |
89b831ef | 1092 | struct threshold_bank *b; |
89b831ef JS |
1093 | |
1094 | b = per_cpu(threshold_banks, cpu)[bank]; | |
1095 | if (!b) | |
1096 | return; | |
019f34fc | 1097 | |
95268664 JS |
1098 | if (!b->blocks) |
1099 | goto free_out; | |
1100 | ||
c76e8164 | 1101 | if (is_shared_bank(bank)) { |
019f34fc BP |
1102 | if (!atomic_dec_and_test(&b->cpus)) { |
1103 | __threshold_remove_blocks(b); | |
1104 | per_cpu(threshold_banks, cpu)[bank] = NULL; | |
1105 | return; | |
1106 | } else { | |
1107 | /* | |
1108 | * the last CPU on this node using the shared bank is | |
1109 | * going away, remove that bank now. | |
1110 | */ | |
1111 | nb = node_to_amd_nb(amd_get_nb_id(cpu)); | |
1112 | nb->bank4 = NULL; | |
1113 | } | |
1114 | } | |
1115 | ||
95268664 JS |
1116 | deallocate_threshold_block(cpu, bank); |
1117 | ||
1118 | free_out: | |
8735728e | 1119 | kobject_del(b->kobj); |
38a382ae | 1120 | kobject_put(b->kobj); |
95268664 JS |
1121 | kfree(b); |
1122 | per_cpu(threshold_banks, cpu)[bank] = NULL; | |
89b831ef JS |
1123 | } |
1124 | ||
be6b5a35 | 1125 | static void threshold_remove_device(unsigned int cpu) |
89b831ef | 1126 | { |
2903ee85 | 1127 | unsigned int bank; |
89b831ef | 1128 | |
bafcdd3b | 1129 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
5a96f4a5 | 1130 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
89b831ef JS |
1131 | continue; |
1132 | threshold_remove_bank(cpu, bank); | |
1133 | } | |
bafcdd3b | 1134 | kfree(per_cpu(threshold_banks, cpu)); |
89b831ef JS |
1135 | } |
1136 | ||
89b831ef | 1137 | /* get notified when a cpu comes on/off */ |
148f9bb8 | 1138 | static void |
1cb2a8e1 | 1139 | amd_64_threshold_cpu_callback(unsigned long action, unsigned int cpu) |
89b831ef | 1140 | { |
89b831ef JS |
1141 | switch (action) { |
1142 | case CPU_ONLINE: | |
8bb78442 | 1143 | case CPU_ONLINE_FROZEN: |
89b831ef | 1144 | threshold_create_device(cpu); |
89b831ef JS |
1145 | break; |
1146 | case CPU_DEAD: | |
8bb78442 | 1147 | case CPU_DEAD_FROZEN: |
89b831ef JS |
1148 | threshold_remove_device(cpu); |
1149 | break; | |
1150 | default: | |
1151 | break; | |
1152 | } | |
89b831ef JS |
1153 | } |
1154 | ||
89b831ef JS |
1155 | static __init int threshold_init_device(void) |
1156 | { | |
2903ee85 | 1157 | unsigned lcpu = 0; |
89b831ef | 1158 | |
89b831ef JS |
1159 | /* to hit CPUs online before the notifier is up */ |
1160 | for_each_online_cpu(lcpu) { | |
fff2e89f | 1161 | int err = threshold_create_device(lcpu); |
1cb2a8e1 | 1162 | |
89b831ef | 1163 | if (err) |
fff2e89f | 1164 | return err; |
89b831ef | 1165 | } |
8735728e | 1166 | threshold_cpu_callback = amd_64_threshold_cpu_callback; |
1cb2a8e1 | 1167 | |
fff2e89f | 1168 | return 0; |
89b831ef | 1169 | } |
a8fccdb0 LJ |
1170 | /* |
1171 | * there are 3 funcs which need to be _initcalled in a logic sequence: | |
1172 | * 1. xen_late_init_mcelog | |
1173 | * 2. mcheck_init_device | |
1174 | * 3. threshold_init_device | |
1175 | * | |
1176 | * xen_late_init_mcelog must register xen_mce_chrdev_device before | |
1177 | * native mce_chrdev_device registration if running under xen platform; | |
1178 | * | |
1179 | * mcheck_init_device should be inited before threshold_init_device to | |
1180 | * initialize mce_device, otherwise a NULL ptr dereference will cause panic. | |
1181 | * | |
1182 | * so we use following _initcalls | |
1183 | * 1. device_initcall(xen_late_init_mcelog); | |
1184 | * 2. device_initcall_sync(mcheck_init_device); | |
1185 | * 3. late_initcall(threshold_init_device); | |
1186 | * | |
1187 | * when running under xen, the initcall order is 1,2,3; | |
1188 | * on baremetal, we skip 1 and we do only 2 and 3. | |
1189 | */ | |
1190 | late_initcall(threshold_init_device); |