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Commit | Line | Data |
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89b831ef | 1 | /* |
ea2ca36b | 2 | * (c) 2005-2016 Advanced Micro Devices, Inc. |
89b831ef JS |
3 | * Your use of this code is subject to the terms and conditions of the |
4 | * GNU general public license version 2. See "COPYING" or | |
5 | * http://www.gnu.org/licenses/gpl.html | |
6 | * | |
7 | * Written by Jacob Shin - AMD, Inc. | |
e6d41e8c | 8 | * Maintained by: Borislav Petkov <bp@alien8.de> |
89b831ef | 9 | * |
3490c0e4 | 10 | * All MC4_MISCi registers are shared between cores on a node. |
89b831ef | 11 | */ |
89b831ef | 12 | #include <linux/interrupt.h> |
89b831ef | 13 | #include <linux/notifier.h> |
1cb2a8e1 | 14 | #include <linux/kobject.h> |
34fa1967 | 15 | #include <linux/percpu.h> |
1cb2a8e1 IM |
16 | #include <linux/errno.h> |
17 | #include <linux/sched.h> | |
89b831ef | 18 | #include <linux/sysfs.h> |
5a0e3ad6 | 19 | #include <linux/slab.h> |
1cb2a8e1 IM |
20 | #include <linux/init.h> |
21 | #include <linux/cpu.h> | |
22 | #include <linux/smp.h> | |
87a6d409 | 23 | #include <linux/string.h> |
1cb2a8e1 | 24 | |
019f34fc | 25 | #include <asm/amd_nb.h> |
7b1312ce | 26 | #include <asm/traps.h> |
89b831ef JS |
27 | #include <asm/apic.h> |
28 | #include <asm/mce.h> | |
29 | #include <asm/msr.h> | |
24fd78a8 | 30 | #include <asm/trace/irq_vectors.h> |
89b831ef | 31 | |
262e6811 BP |
32 | #include "mce-internal.h" |
33 | ||
60f116fc | 34 | #define NR_BLOCKS 5 |
2903ee85 JS |
35 | #define THRESHOLD_MAX 0xFFF |
36 | #define INT_TYPE_APIC 0x00020000 | |
37 | #define MASK_VALID_HI 0x80000000 | |
24ce0e96 JB |
38 | #define MASK_CNTP_HI 0x40000000 |
39 | #define MASK_LOCKED_HI 0x20000000 | |
2903ee85 JS |
40 | #define MASK_LVTOFF_HI 0x00F00000 |
41 | #define MASK_COUNT_EN_HI 0x00080000 | |
42 | #define MASK_INT_TYPE_HI 0x00060000 | |
43 | #define MASK_OVERFLOW_HI 0x00010000 | |
89b831ef | 44 | #define MASK_ERR_COUNT_HI 0x00000FFF |
95268664 JS |
45 | #define MASK_BLKPTR_LO 0xFF000000 |
46 | #define MCG_XBLK_ADDR 0xC0000400 | |
89b831ef | 47 | |
24fd78a8 AG |
48 | /* Deferred error settings */ |
49 | #define MSR_CU_DEF_ERR 0xC0000410 | |
50 | #define MASK_DEF_LVTOFF 0x000000F0 | |
51 | #define MASK_DEF_INT_TYPE 0x00000006 | |
52 | #define DEF_LVT_OFF 0x2 | |
53 | #define DEF_INT_TYPE_APIC 0x2 | |
54 | ||
f57a1f3c AG |
55 | /* Scalable MCA: */ |
56 | ||
57 | /* Threshold LVT offset is at MSR0xC0000410[15:12] */ | |
58 | #define SMCA_THR_LVT_OFF 0xF000 | |
59 | ||
628cf0d4 | 60 | static bool thresholding_irq_en; |
4d7b02d5 | 61 | |
336d335a BP |
62 | static const char * const th_names[] = { |
63 | "load_store", | |
64 | "insn_fetch", | |
65 | "combined_unit", | |
29f72ce3 | 66 | "decode_unit", |
336d335a BP |
67 | "northbridge", |
68 | "execution_unit", | |
69 | }; | |
70 | ||
87a6d409 YG |
71 | static const char * const smca_umc_block_names[] = { |
72 | "dram_ecc", | |
73 | "misc_umc" | |
74 | }; | |
75 | ||
c09a8c40 BP |
76 | struct smca_bank_name { |
77 | const char *name; /* Short name for sysfs */ | |
78 | const char *long_name; /* Long name for pretty-printing */ | |
79 | }; | |
80 | ||
81 | static struct smca_bank_name smca_names[] = { | |
5896820e YG |
82 | [SMCA_LS] = { "load_store", "Load Store Unit" }, |
83 | [SMCA_IF] = { "insn_fetch", "Instruction Fetch Unit" }, | |
84 | [SMCA_L2_CACHE] = { "l2_cache", "L2 Cache" }, | |
85 | [SMCA_DE] = { "decode_unit", "Decode Unit" }, | |
df15bd16 | 86 | [SMCA_RESERVED] = { "reserved", "Reserved" }, |
5896820e YG |
87 | [SMCA_EX] = { "execution_unit", "Execution Unit" }, |
88 | [SMCA_FP] = { "floating_point", "Floating Point Unit" }, | |
89 | [SMCA_L3_CACHE] = { "l3_cache", "L3 Cache" }, | |
90 | [SMCA_CS] = { "coherent_slave", "Coherent Slave" }, | |
91 | [SMCA_PIE] = { "pie", "Power, Interrupts, etc." }, | |
92 | [SMCA_UMC] = { "umc", "Unified Memory Controller" }, | |
93 | [SMCA_PB] = { "param_block", "Parameter Block" }, | |
94 | [SMCA_PSP] = { "psp", "Platform Security Processor" }, | |
95 | [SMCA_SMU] = { "smu", "System Management Unit" }, | |
be0aec23 | 96 | }; |
c09a8c40 | 97 | |
262a85e7 BP |
98 | static u32 smca_bank_addrs[MAX_NR_BANKS][NR_BLOCKS] __ro_after_init = |
99 | { | |
100 | [0 ... MAX_NR_BANKS - 1] = { [0 ... NR_BLOCKS - 1] = -1 } | |
101 | }; | |
102 | ||
7b1312ce | 103 | static const char *smca_get_name(enum smca_bank_types t) |
c09a8c40 BP |
104 | { |
105 | if (t >= N_SMCA_BANK_TYPES) | |
106 | return NULL; | |
107 | ||
108 | return smca_names[t].name; | |
109 | } | |
110 | ||
111 | const char *smca_get_long_name(enum smca_bank_types t) | |
112 | { | |
113 | if (t >= N_SMCA_BANK_TYPES) | |
114 | return NULL; | |
115 | ||
116 | return smca_names[t].long_name; | |
117 | } | |
118 | EXPORT_SYMBOL_GPL(smca_get_long_name); | |
5896820e | 119 | |
42cac853 | 120 | static enum smca_bank_types smca_get_bank_type(unsigned int bank) |
dd78f0be YG |
121 | { |
122 | struct smca_bank *b; | |
123 | ||
42cac853 | 124 | if (bank >= MAX_NR_BANKS) |
dd78f0be YG |
125 | return N_SMCA_BANK_TYPES; |
126 | ||
42cac853 | 127 | b = &smca_banks[bank]; |
dd78f0be YG |
128 | if (!b->hwid) |
129 | return N_SMCA_BANK_TYPES; | |
130 | ||
131 | return b->hwid->bank_type; | |
132 | } | |
133 | ||
1ce9cd7f | 134 | static struct smca_hwid smca_hwid_mcatypes[] = { |
5896820e YG |
135 | /* { bank_type, hwid_mcatype, xec_bitmap } */ |
136 | ||
df15bd16 YG |
137 | /* Reserved type */ |
138 | { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0), 0x0 }, | |
139 | ||
5896820e YG |
140 | /* ZN Core (HWID=0xB0) MCA types */ |
141 | { SMCA_LS, HWID_MCATYPE(0xB0, 0x0), 0x1FFFEF }, | |
142 | { SMCA_IF, HWID_MCATYPE(0xB0, 0x1), 0x3FFF }, | |
143 | { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2), 0xF }, | |
144 | { SMCA_DE, HWID_MCATYPE(0xB0, 0x3), 0x1FF }, | |
145 | /* HWID 0xB0 MCATYPE 0x4 is Reserved */ | |
146 | { SMCA_EX, HWID_MCATYPE(0xB0, 0x5), 0x7FF }, | |
147 | { SMCA_FP, HWID_MCATYPE(0xB0, 0x6), 0x7F }, | |
148 | { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7), 0xFF }, | |
149 | ||
150 | /* Data Fabric MCA types */ | |
151 | { SMCA_CS, HWID_MCATYPE(0x2E, 0x0), 0x1FF }, | |
152 | { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1), 0xF }, | |
153 | ||
154 | /* Unified Memory Controller MCA type */ | |
155 | { SMCA_UMC, HWID_MCATYPE(0x96, 0x0), 0x3F }, | |
156 | ||
157 | /* Parameter Block MCA type */ | |
158 | { SMCA_PB, HWID_MCATYPE(0x05, 0x0), 0x1 }, | |
be0aec23 | 159 | |
5896820e YG |
160 | /* Platform Security Processor MCA type */ |
161 | { SMCA_PSP, HWID_MCATYPE(0xFF, 0x0), 0x1 }, | |
162 | ||
163 | /* System Management Unit MCA type */ | |
164 | { SMCA_SMU, HWID_MCATYPE(0x01, 0x0), 0x1 }, | |
be0aec23 | 165 | }; |
5896820e | 166 | |
79349f52 | 167 | struct smca_bank smca_banks[MAX_NR_BANKS]; |
5896820e | 168 | EXPORT_SYMBOL_GPL(smca_banks); |
be0aec23 | 169 | |
87a6d409 YG |
170 | /* |
171 | * In SMCA enabled processors, we can have multiple banks for a given IP type. | |
172 | * So to define a unique name for each bank, we use a temp c-string to append | |
173 | * the MCA_IPID[InstanceId] to type's name in get_name(). | |
174 | * | |
175 | * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN | |
176 | * is greater than 8 plus 1 (for underscore) plus length of longest type name. | |
177 | */ | |
178 | #define MAX_MCATYPE_NAME_LEN 30 | |
179 | static char buf_mcatype[MAX_MCATYPE_NAME_LEN]; | |
180 | ||
bafcdd3b | 181 | static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks); |
955d1427 | 182 | static DEFINE_PER_CPU(unsigned int, bank_map); /* see which banks are on */ |
89b831ef | 183 | |
b2762686 | 184 | static void amd_threshold_interrupt(void); |
24fd78a8 AG |
185 | static void amd_deferred_error_interrupt(void); |
186 | ||
187 | static void default_deferred_error_interrupt(void) | |
188 | { | |
189 | pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR); | |
190 | } | |
191 | void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; | |
b2762686 | 192 | |
84bcc1d5 | 193 | static void smca_configure(unsigned int bank, unsigned int cpu) |
5896820e | 194 | { |
84bcc1d5 | 195 | unsigned int i, hwid_mcatype; |
1ce9cd7f | 196 | struct smca_hwid *s_hwid; |
84bcc1d5 YG |
197 | u32 high, low; |
198 | u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); | |
199 | ||
200 | /* Set appropriate bits in MCA_CONFIG */ | |
201 | if (!rdmsr_safe(smca_config, &low, &high)) { | |
202 | /* | |
203 | * OS is required to set the MCAX bit to acknowledge that it is | |
204 | * now using the new MSR ranges and new registers under each | |
205 | * bank. It also means that the OS will configure deferred | |
206 | * errors in the new MCx_CONFIG register. If the bit is not set, | |
207 | * uncorrectable errors will cause a system panic. | |
208 | * | |
209 | * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.) | |
210 | */ | |
211 | high |= BIT(0); | |
212 | ||
213 | /* | |
214 | * SMCA sets the Deferred Error Interrupt type per bank. | |
215 | * | |
216 | * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us | |
217 | * if the DeferredIntType bit field is available. | |
218 | * | |
219 | * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the | |
220 | * high portion of the MSR). OS should set this to 0x1 to enable | |
221 | * APIC based interrupt. First, check that no interrupt has been | |
222 | * set. | |
223 | */ | |
224 | if ((low & BIT(5)) && !((high >> 5) & 0x3)) | |
225 | high |= BIT(5); | |
226 | ||
227 | wrmsr(smca_config, low, high); | |
228 | } | |
5896820e | 229 | |
9662d43f | 230 | /* Return early if this bank was already initialized. */ |
b8b11676 | 231 | if (smca_banks[bank].hwid && smca_banks[bank].hwid->hwid_mcatype != 0) |
5896820e YG |
232 | return; |
233 | ||
eea55c14 | 234 | if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) { |
5896820e YG |
235 | pr_warn("Failed to read MCA_IPID for bank %d\n", bank); |
236 | return; | |
237 | } | |
238 | ||
1ce9cd7f BP |
239 | hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID, |
240 | (high & MCI_IPID_MCATYPE) >> 16); | |
5896820e YG |
241 | |
242 | for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) { | |
1ce9cd7f BP |
243 | s_hwid = &smca_hwid_mcatypes[i]; |
244 | if (hwid_mcatype == s_hwid->hwid_mcatype) { | |
245 | smca_banks[bank].hwid = s_hwid; | |
84bcc1d5 | 246 | smca_banks[bank].id = low; |
0b737a9c | 247 | smca_banks[bank].sysfs_id = s_hwid->count++; |
5896820e YG |
248 | break; |
249 | } | |
250 | } | |
251 | } | |
252 | ||
4cd4601d | 253 | struct thresh_restart { |
1cb2a8e1 IM |
254 | struct threshold_block *b; |
255 | int reset; | |
9c37c9d8 RR |
256 | int set_lvt_off; |
257 | int lvt_off; | |
1cb2a8e1 | 258 | u16 old_limit; |
4cd4601d MT |
259 | }; |
260 | ||
c76e8164 BO |
261 | static inline bool is_shared_bank(int bank) |
262 | { | |
284b965c AG |
263 | /* |
264 | * Scalable MCA provides for only one core to have access to the MSRs of | |
265 | * a shared bank. | |
266 | */ | |
267 | if (mce_flags.smca) | |
268 | return false; | |
269 | ||
c76e8164 BO |
270 | /* Bank 4 is for northbridge reporting and is thus shared */ |
271 | return (bank == 4); | |
272 | } | |
273 | ||
2cd4c303 | 274 | static const char *bank4_names(const struct threshold_block *b) |
336d335a BP |
275 | { |
276 | switch (b->address) { | |
277 | /* MSR4_MISC0 */ | |
278 | case 0x00000413: | |
279 | return "dram"; | |
280 | ||
281 | case 0xc0000408: | |
282 | return "ht_links"; | |
283 | ||
284 | case 0xc0000409: | |
285 | return "l3_cache"; | |
286 | ||
287 | default: | |
288 | WARN(1, "Funny MSR: 0x%08x\n", b->address); | |
289 | return ""; | |
290 | } | |
291 | }; | |
292 | ||
293 | ||
f227d430 BP |
294 | static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) |
295 | { | |
296 | /* | |
297 | * bank 4 supports APIC LVT interrupts implicitly since forever. | |
298 | */ | |
299 | if (bank == 4) | |
300 | return true; | |
301 | ||
302 | /* | |
303 | * IntP: interrupt present; if this bit is set, the thresholding | |
304 | * bank can generate APIC LVT interrupts | |
305 | */ | |
306 | return msr_high_bits & BIT(28); | |
307 | } | |
308 | ||
bbaff08d RR |
309 | static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) |
310 | { | |
311 | int msr = (hi & MASK_LVTOFF_HI) >> 20; | |
312 | ||
313 | if (apic < 0) { | |
314 | pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " | |
315 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, | |
316 | b->bank, b->block, b->address, hi, lo); | |
317 | return 0; | |
318 | } | |
319 | ||
320 | if (apic != msr) { | |
f57a1f3c AG |
321 | /* |
322 | * On SMCA CPUs, LVT offset is programmed at a different MSR, and | |
323 | * the BIOS provides the value. The original field where LVT offset | |
324 | * was set is reserved. Return early here: | |
325 | */ | |
326 | if (mce_flags.smca) | |
327 | return 0; | |
328 | ||
bbaff08d RR |
329 | pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " |
330 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n", | |
331 | b->cpu, apic, b->bank, b->block, b->address, hi, lo); | |
332 | return 0; | |
333 | } | |
334 | ||
335 | return 1; | |
336 | }; | |
337 | ||
ea2ca36b | 338 | /* Reprogram MCx_MISC MSR behind this threshold bank. */ |
a6b6a14e | 339 | static void threshold_restart_bank(void *_tr) |
89b831ef | 340 | { |
4cd4601d | 341 | struct thresh_restart *tr = _tr; |
7203a049 | 342 | u32 hi, lo; |
89b831ef | 343 | |
7203a049 | 344 | rdmsr(tr->b->address, lo, hi); |
89b831ef | 345 | |
7203a049 | 346 | if (tr->b->threshold_limit < (hi & THRESHOLD_MAX)) |
4cd4601d | 347 | tr->reset = 1; /* limit cannot be lower than err count */ |
89b831ef | 348 | |
4cd4601d | 349 | if (tr->reset) { /* reset err count and overflow bit */ |
7203a049 RR |
350 | hi = |
351 | (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) | | |
4cd4601d MT |
352 | (THRESHOLD_MAX - tr->b->threshold_limit); |
353 | } else if (tr->old_limit) { /* change limit w/o reset */ | |
7203a049 | 354 | int new_count = (hi & THRESHOLD_MAX) + |
4cd4601d | 355 | (tr->old_limit - tr->b->threshold_limit); |
1cb2a8e1 | 356 | |
7203a049 | 357 | hi = (hi & ~MASK_ERR_COUNT_HI) | |
89b831ef JS |
358 | (new_count & THRESHOLD_MAX); |
359 | } | |
360 | ||
f227d430 BP |
361 | /* clear IntType */ |
362 | hi &= ~MASK_INT_TYPE_HI; | |
363 | ||
364 | if (!tr->b->interrupt_capable) | |
365 | goto done; | |
366 | ||
9c37c9d8 | 367 | if (tr->set_lvt_off) { |
bbaff08d RR |
368 | if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) { |
369 | /* set new lvt offset */ | |
370 | hi &= ~MASK_LVTOFF_HI; | |
371 | hi |= tr->lvt_off << 20; | |
372 | } | |
9c37c9d8 RR |
373 | } |
374 | ||
f227d430 BP |
375 | if (tr->b->interrupt_enable) |
376 | hi |= INT_TYPE_APIC; | |
377 | ||
378 | done: | |
89b831ef | 379 | |
7203a049 RR |
380 | hi |= MASK_COUNT_EN_HI; |
381 | wrmsr(tr->b->address, lo, hi); | |
89b831ef JS |
382 | } |
383 | ||
9c37c9d8 RR |
384 | static void mce_threshold_block_init(struct threshold_block *b, int offset) |
385 | { | |
386 | struct thresh_restart tr = { | |
387 | .b = b, | |
388 | .set_lvt_off = 1, | |
389 | .lvt_off = offset, | |
390 | }; | |
391 | ||
392 | b->threshold_limit = THRESHOLD_MAX; | |
393 | threshold_restart_bank(&tr); | |
394 | }; | |
395 | ||
868c00bb | 396 | static int setup_APIC_mce_threshold(int reserved, int new) |
bbaff08d RR |
397 | { |
398 | if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR, | |
399 | APIC_EILVT_MSG_FIX, 0)) | |
400 | return new; | |
401 | ||
402 | return reserved; | |
403 | } | |
404 | ||
24fd78a8 AG |
405 | static int setup_APIC_deferred_error(int reserved, int new) |
406 | { | |
407 | if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR, | |
408 | APIC_EILVT_MSG_FIX, 0)) | |
409 | return new; | |
410 | ||
411 | return reserved; | |
412 | } | |
413 | ||
414 | static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) | |
415 | { | |
416 | u32 low = 0, high = 0; | |
417 | int def_offset = -1, def_new; | |
418 | ||
419 | if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) | |
420 | return; | |
421 | ||
422 | def_new = (low & MASK_DEF_LVTOFF) >> 4; | |
423 | if (!(low & MASK_DEF_LVTOFF)) { | |
424 | pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n"); | |
425 | def_new = DEF_LVT_OFF; | |
426 | low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4); | |
427 | } | |
428 | ||
429 | def_offset = setup_APIC_deferred_error(def_offset, def_new); | |
430 | if ((def_offset == def_new) && | |
431 | (deferred_error_int_vector != amd_deferred_error_interrupt)) | |
432 | deferred_error_int_vector = amd_deferred_error_interrupt; | |
433 | ||
434 | low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; | |
435 | wrmsr(MSR_CU_DEF_ERR, low, high); | |
436 | } | |
437 | ||
280e79a1 YG |
438 | static u32 smca_get_block_address(unsigned int cpu, unsigned int bank, |
439 | unsigned int block) | |
440 | { | |
441 | u32 low, high; | |
442 | u32 addr = 0; | |
443 | ||
444 | if (smca_get_bank_type(bank) == SMCA_RESERVED) | |
445 | return addr; | |
446 | ||
447 | if (!block) | |
448 | return MSR_AMD64_SMCA_MCx_MISC(bank); | |
449 | ||
262a85e7 BP |
450 | /* Check our cache first: */ |
451 | if (smca_bank_addrs[bank][block] != -1) | |
452 | return smca_bank_addrs[bank][block]; | |
453 | ||
280e79a1 YG |
454 | /* |
455 | * For SMCA enabled processors, BLKPTR field of the first MISC register | |
456 | * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4). | |
457 | */ | |
458 | if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) | |
262a85e7 | 459 | goto out; |
280e79a1 YG |
460 | |
461 | if (!(low & MCI_CONFIG_MCAX)) | |
262a85e7 | 462 | goto out; |
280e79a1 YG |
463 | |
464 | if (!rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) && | |
465 | (low & MASK_BLKPTR_LO)) | |
262a85e7 | 466 | addr = MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); |
280e79a1 | 467 | |
262a85e7 BP |
468 | out: |
469 | smca_bank_addrs[bank][block] = addr; | |
280e79a1 YG |
470 | return addr; |
471 | } | |
472 | ||
cfee4f6f | 473 | static u32 get_block_address(unsigned int cpu, u32 current_addr, u32 low, u32 high, |
8dd1e17a AG |
474 | unsigned int bank, unsigned int block) |
475 | { | |
476 | u32 addr = 0, offset = 0; | |
477 | ||
9243a5be YG |
478 | if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS)) |
479 | return addr; | |
480 | ||
280e79a1 YG |
481 | if (mce_flags.smca) |
482 | return smca_get_block_address(cpu, bank, block); | |
8dd1e17a AG |
483 | |
484 | /* Fall back to method we used for older processors: */ | |
485 | switch (block) { | |
486 | case 0: | |
d9d73fcc | 487 | addr = msr_ops.misc(bank); |
8dd1e17a AG |
488 | break; |
489 | case 1: | |
490 | offset = ((low & MASK_BLKPTR_LO) >> 21); | |
491 | if (offset) | |
492 | addr = MCG_XBLK_ADDR + offset; | |
493 | break; | |
494 | default: | |
495 | addr = ++current_addr; | |
496 | } | |
497 | return addr; | |
498 | } | |
499 | ||
429893b1 BP |
500 | static int |
501 | prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, | |
502 | int offset, u32 misc_high) | |
503 | { | |
504 | unsigned int cpu = smp_processor_id(); | |
84bcc1d5 | 505 | u32 smca_low, smca_high; |
429893b1 BP |
506 | struct threshold_block b; |
507 | int new; | |
508 | ||
509 | if (!block) | |
510 | per_cpu(bank_map, cpu) |= (1 << bank); | |
511 | ||
512 | memset(&b, 0, sizeof(b)); | |
513 | b.cpu = cpu; | |
514 | b.bank = bank; | |
515 | b.block = block; | |
516 | b.address = addr; | |
517 | b.interrupt_capable = lvt_interrupt_supported(bank, misc_high); | |
518 | ||
519 | if (!b.interrupt_capable) | |
520 | goto done; | |
521 | ||
522 | b.interrupt_enable = 1; | |
523 | ||
e128b4f4 BP |
524 | if (!mce_flags.smca) { |
525 | new = (misc_high & MASK_LVTOFF_HI) >> 20; | |
526 | goto set_offset; | |
527 | } | |
32544f06 | 528 | |
e128b4f4 BP |
529 | /* Gather LVT offset for thresholding: */ |
530 | if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high)) | |
531 | goto out; | |
532 | ||
533 | new = (smca_low & SMCA_THR_LVT_OFF) >> 12; | |
534 | ||
535 | set_offset: | |
429893b1 | 536 | offset = setup_APIC_mce_threshold(offset, new); |
628cf0d4 BP |
537 | if (offset == new) |
538 | thresholding_irq_en = true; | |
429893b1 BP |
539 | |
540 | done: | |
541 | mce_threshold_block_init(&b, offset); | |
542 | ||
543 | out: | |
544 | return offset; | |
545 | } | |
546 | ||
624d9eb3 YG |
547 | bool amd_filter_mce(struct mce *m) |
548 | { | |
549 | enum smca_bank_types bank_type = smca_get_bank_type(m->bank); | |
550 | struct cpuinfo_x86 *c = &boot_cpu_data; | |
551 | u8 xec = (m->status >> 16) & 0x3F; | |
552 | ||
553 | /* See Family 17h Models 10h-2Fh Erratum #1114. */ | |
554 | if (c->x86 == 0x17 && | |
555 | c->x86_model >= 0x10 && c->x86_model <= 0x2F && | |
556 | bank_type == SMCA_IF && xec == 10) | |
557 | return true; | |
558 | ||
559 | return false; | |
560 | } | |
561 | ||
c7b3c935 | 562 | /* |
624d9eb3 YG |
563 | * Turn off thresholding banks for the following conditions: |
564 | * - MC4_MISC thresholding is not supported on Family 0x15. | |
565 | * - Prevent possible spurious interrupts from the IF bank on Family 0x17 | |
566 | * Models 0x10-0x2F due to Erratum #1114. | |
c7b3c935 | 567 | */ |
624d9eb3 | 568 | void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank) |
c7b3c935 | 569 | { |
624d9eb3 | 570 | int i, num_msrs; |
c7b3c935 S |
571 | u64 hwcr; |
572 | bool need_toggle; | |
624d9eb3 | 573 | u32 msrs[NR_BLOCKS]; |
c7b3c935 | 574 | |
624d9eb3 YG |
575 | if (c->x86 == 0x15 && bank == 4) { |
576 | msrs[0] = 0x00000413; /* MC4_MISC0 */ | |
577 | msrs[1] = 0xc0000408; /* MC4_MISC1 */ | |
578 | num_msrs = 2; | |
579 | } else if (c->x86 == 0x17 && | |
580 | (c->x86_model >= 0x10 && c->x86_model <= 0x2F)) { | |
581 | ||
582 | if (smca_get_bank_type(bank) != SMCA_IF) | |
583 | return; | |
584 | ||
585 | msrs[0] = MSR_AMD64_SMCA_MCx_MISC(bank); | |
586 | num_msrs = 1; | |
587 | } else { | |
c7b3c935 | 588 | return; |
624d9eb3 | 589 | } |
c7b3c935 S |
590 | |
591 | rdmsrl(MSR_K7_HWCR, hwcr); | |
592 | ||
593 | /* McStatusWrEn has to be set */ | |
594 | need_toggle = !(hwcr & BIT(18)); | |
c7b3c935 S |
595 | if (need_toggle) |
596 | wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); | |
597 | ||
598 | /* Clear CntP bit safely */ | |
624d9eb3 | 599 | for (i = 0; i < num_msrs; i++) |
c7b3c935 S |
600 | msr_clear_bit(msrs[i], 62); |
601 | ||
602 | /* restore old settings */ | |
603 | if (need_toggle) | |
604 | wrmsrl(MSR_K7_HWCR, hwcr); | |
605 | } | |
606 | ||
95268664 | 607 | /* cpu init entry point, called from mce.c with preempt off */ |
cc3ca220 | 608 | void mce_amd_feature_init(struct cpuinfo_x86 *c) |
89b831ef | 609 | { |
95268664 | 610 | u32 low = 0, high = 0, address = 0; |
cfee4f6f | 611 | unsigned int bank, block, cpu = smp_processor_id(); |
429893b1 | 612 | int offset = -1; |
89b831ef | 613 | |
bafcdd3b | 614 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
5896820e | 615 | if (mce_flags.smca) |
84bcc1d5 | 616 | smca_configure(bank, cpu); |
5896820e | 617 | |
624d9eb3 YG |
618 | disable_err_thresholding(c, bank); |
619 | ||
95268664 | 620 | for (block = 0; block < NR_BLOCKS; ++block) { |
cfee4f6f | 621 | address = get_block_address(cpu, address, low, high, bank, block); |
8dd1e17a AG |
622 | if (!address) |
623 | break; | |
95268664 JS |
624 | |
625 | if (rdmsr_safe(address, &low, &high)) | |
24ce0e96 | 626 | break; |
95268664 | 627 | |
6dcbfe4f BP |
628 | if (!(high & MASK_VALID_HI)) |
629 | continue; | |
95268664 | 630 | |
24ce0e96 JB |
631 | if (!(high & MASK_CNTP_HI) || |
632 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
633 | continue; |
634 | ||
429893b1 | 635 | offset = prepare_threshold_block(bank, block, address, offset, high); |
95268664 | 636 | } |
89b831ef | 637 | } |
24fd78a8 AG |
638 | |
639 | if (mce_flags.succor) | |
640 | deferred_error_interrupt_enable(c); | |
89b831ef JS |
641 | } |
642 | ||
f5382de9 YG |
643 | int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) |
644 | { | |
645 | u64 dram_base_addr, dram_limit_addr, dram_hole_base; | |
646 | /* We start from the normalized address */ | |
647 | u64 ret_addr = norm_addr; | |
648 | ||
649 | u32 tmp; | |
650 | ||
651 | u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; | |
652 | u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; | |
653 | u8 intlv_addr_sel, intlv_addr_bit; | |
654 | u8 num_intlv_bits, hashed_bit; | |
655 | u8 lgcy_mmio_hole_en, base = 0; | |
656 | u8 cs_mask, cs_id = 0; | |
657 | bool hash_enabled = false; | |
658 | ||
659 | /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */ | |
660 | if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp)) | |
661 | goto out_err; | |
662 | ||
663 | /* Remove HiAddrOffset from normalized address, if enabled: */ | |
664 | if (tmp & BIT(0)) { | |
665 | u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8; | |
666 | ||
667 | if (norm_addr >= hi_addr_offset) { | |
668 | ret_addr -= hi_addr_offset; | |
669 | base = 1; | |
670 | } | |
671 | } | |
672 | ||
673 | /* Read D18F0x110 (DramBaseAddress). */ | |
674 | if (amd_df_indirect_read(nid, 0, 0x110 + (8 * base), umc, &tmp)) | |
675 | goto out_err; | |
676 | ||
677 | /* Check if address range is valid. */ | |
678 | if (!(tmp & BIT(0))) { | |
679 | pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n", | |
680 | __func__, tmp); | |
681 | goto out_err; | |
682 | } | |
683 | ||
684 | lgcy_mmio_hole_en = tmp & BIT(1); | |
685 | intlv_num_chan = (tmp >> 4) & 0xF; | |
686 | intlv_addr_sel = (tmp >> 8) & 0x7; | |
687 | dram_base_addr = (tmp & GENMASK_ULL(31, 12)) << 16; | |
688 | ||
689 | /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ | |
690 | if (intlv_addr_sel > 3) { | |
691 | pr_err("%s: Invalid interleave address select %d.\n", | |
692 | __func__, intlv_addr_sel); | |
693 | goto out_err; | |
694 | } | |
695 | ||
696 | /* Read D18F0x114 (DramLimitAddress). */ | |
697 | if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp)) | |
698 | goto out_err; | |
699 | ||
700 | intlv_num_sockets = (tmp >> 8) & 0x1; | |
701 | intlv_num_dies = (tmp >> 10) & 0x3; | |
702 | dram_limit_addr = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); | |
703 | ||
704 | intlv_addr_bit = intlv_addr_sel + 8; | |
705 | ||
706 | /* Re-use intlv_num_chan by setting it equal to log2(#channels) */ | |
707 | switch (intlv_num_chan) { | |
708 | case 0: intlv_num_chan = 0; break; | |
709 | case 1: intlv_num_chan = 1; break; | |
710 | case 3: intlv_num_chan = 2; break; | |
711 | case 5: intlv_num_chan = 3; break; | |
712 | case 7: intlv_num_chan = 4; break; | |
713 | ||
714 | case 8: intlv_num_chan = 1; | |
715 | hash_enabled = true; | |
716 | break; | |
717 | default: | |
718 | pr_err("%s: Invalid number of interleaved channels %d.\n", | |
719 | __func__, intlv_num_chan); | |
720 | goto out_err; | |
721 | } | |
722 | ||
723 | num_intlv_bits = intlv_num_chan; | |
724 | ||
725 | if (intlv_num_dies > 2) { | |
726 | pr_err("%s: Invalid number of interleaved nodes/dies %d.\n", | |
727 | __func__, intlv_num_dies); | |
728 | goto out_err; | |
729 | } | |
730 | ||
731 | num_intlv_bits += intlv_num_dies; | |
732 | ||
733 | /* Add a bit if sockets are interleaved. */ | |
734 | num_intlv_bits += intlv_num_sockets; | |
735 | ||
736 | /* Assert num_intlv_bits <= 4 */ | |
737 | if (num_intlv_bits > 4) { | |
738 | pr_err("%s: Invalid interleave bits %d.\n", | |
739 | __func__, num_intlv_bits); | |
740 | goto out_err; | |
741 | } | |
742 | ||
743 | if (num_intlv_bits > 0) { | |
744 | u64 temp_addr_x, temp_addr_i, temp_addr_y; | |
745 | u8 die_id_bit, sock_id_bit, cs_fabric_id; | |
746 | ||
747 | /* | |
748 | * Read FabricBlockInstanceInformation3_CS[BlockFabricID]. | |
749 | * This is the fabric id for this coherent slave. Use | |
750 | * umc/channel# as instance id of the coherent slave | |
751 | * for FICAA. | |
752 | */ | |
753 | if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp)) | |
754 | goto out_err; | |
755 | ||
756 | cs_fabric_id = (tmp >> 8) & 0xFF; | |
757 | die_id_bit = 0; | |
758 | ||
759 | /* If interleaved over more than 1 channel: */ | |
760 | if (intlv_num_chan) { | |
761 | die_id_bit = intlv_num_chan; | |
762 | cs_mask = (1 << die_id_bit) - 1; | |
763 | cs_id = cs_fabric_id & cs_mask; | |
764 | } | |
765 | ||
766 | sock_id_bit = die_id_bit; | |
767 | ||
768 | /* Read D18F1x208 (SystemFabricIdMask). */ | |
769 | if (intlv_num_dies || intlv_num_sockets) | |
770 | if (amd_df_indirect_read(nid, 1, 0x208, umc, &tmp)) | |
771 | goto out_err; | |
772 | ||
773 | /* If interleaved over more than 1 die. */ | |
774 | if (intlv_num_dies) { | |
775 | sock_id_bit = die_id_bit + intlv_num_dies; | |
776 | die_id_shift = (tmp >> 24) & 0xF; | |
777 | die_id_mask = (tmp >> 8) & 0xFF; | |
778 | ||
779 | cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; | |
780 | } | |
781 | ||
782 | /* If interleaved over more than 1 socket. */ | |
783 | if (intlv_num_sockets) { | |
784 | socket_id_shift = (tmp >> 28) & 0xF; | |
785 | socket_id_mask = (tmp >> 16) & 0xFF; | |
786 | ||
787 | cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit; | |
788 | } | |
789 | ||
790 | /* | |
791 | * The pre-interleaved address consists of XXXXXXIIIYYYYY | |
792 | * where III is the ID for this CS, and XXXXXXYYYYY are the | |
793 | * address bits from the post-interleaved address. | |
794 | * "num_intlv_bits" has been calculated to tell us how many "I" | |
795 | * bits there are. "intlv_addr_bit" tells us how many "Y" bits | |
796 | * there are (where "I" starts). | |
797 | */ | |
798 | temp_addr_y = ret_addr & GENMASK_ULL(intlv_addr_bit-1, 0); | |
799 | temp_addr_i = (cs_id << intlv_addr_bit); | |
800 | temp_addr_x = (ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits; | |
801 | ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; | |
802 | } | |
803 | ||
804 | /* Add dram base address */ | |
805 | ret_addr += dram_base_addr; | |
806 | ||
807 | /* If legacy MMIO hole enabled */ | |
808 | if (lgcy_mmio_hole_en) { | |
809 | if (amd_df_indirect_read(nid, 0, 0x104, umc, &tmp)) | |
810 | goto out_err; | |
811 | ||
812 | dram_hole_base = tmp & GENMASK(31, 24); | |
813 | if (ret_addr >= dram_hole_base) | |
814 | ret_addr += (BIT_ULL(32) - dram_hole_base); | |
815 | } | |
816 | ||
817 | if (hash_enabled) { | |
818 | /* Save some parentheses and grab ls-bit at the end. */ | |
819 | hashed_bit = (ret_addr >> 12) ^ | |
820 | (ret_addr >> 18) ^ | |
821 | (ret_addr >> 21) ^ | |
822 | (ret_addr >> 30) ^ | |
823 | cs_id; | |
824 | ||
825 | hashed_bit &= BIT(0); | |
826 | ||
827 | if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0))) | |
828 | ret_addr ^= BIT(intlv_addr_bit); | |
829 | } | |
830 | ||
831 | /* Is calculated system address is above DRAM limit address? */ | |
832 | if (ret_addr > dram_limit_addr) | |
833 | goto out_err; | |
834 | ||
835 | *sys_addr = ret_addr; | |
836 | return 0; | |
837 | ||
838 | out_err: | |
839 | return -EINVAL; | |
840 | } | |
841 | EXPORT_SYMBOL_GPL(umc_normaddr_to_sysaddr); | |
842 | ||
37d43acf | 843 | static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) |
afdf344e AG |
844 | { |
845 | struct mce m; | |
afdf344e AG |
846 | |
847 | mce_setup(&m); | |
848 | ||
849 | m.status = status; | |
37d43acf | 850 | m.misc = misc; |
669c00f0 BP |
851 | m.bank = bank; |
852 | m.tsc = rdtsc(); | |
6e6e746e | 853 | |
4f29b73b | 854 | if (m.status & MCI_STATUS_ADDRV) { |
37d43acf | 855 | m.addr = addr; |
afdf344e | 856 | |
4f29b73b YG |
857 | /* |
858 | * Extract [55:<lsb>] where lsb is the least significant | |
859 | * *valid* bit of the address bits. | |
860 | */ | |
861 | if (mce_flags.smca) { | |
862 | u8 lsb = (m.addr >> 56) & 0x3f; | |
863 | ||
864 | m.addr &= GENMASK_ULL(55, lsb); | |
865 | } | |
866 | } | |
867 | ||
5828c46f YG |
868 | if (mce_flags.smca) { |
869 | rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid); | |
870 | ||
871 | if (m.status & MCI_STATUS_SYNDV) | |
872 | rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd); | |
873 | } | |
db819d60 | 874 | |
6e6e746e | 875 | mce_log(&m); |
afdf344e AG |
876 | } |
877 | ||
7b1312ce | 878 | asmlinkage __visible void __irq_entry smp_deferred_error_interrupt(struct pt_regs *regs) |
24fd78a8 AG |
879 | { |
880 | entering_irq(); | |
881 | trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR); | |
0f42ae28 TG |
882 | inc_irq_stat(irq_deferred_error_count); |
883 | deferred_error_int_vector(); | |
24fd78a8 AG |
884 | trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR); |
885 | exiting_ack_irq(); | |
886 | } | |
887 | ||
37d43acf YG |
888 | /* |
889 | * Returns true if the logged error is deferred. False, otherwise. | |
890 | */ | |
891 | static inline bool | |
892 | _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc) | |
24fd78a8 | 893 | { |
37d43acf | 894 | u64 status, addr = 0; |
24fd78a8 | 895 | |
37d43acf YG |
896 | rdmsrl(msr_stat, status); |
897 | if (!(status & MCI_STATUS_VAL)) | |
898 | return false; | |
34102009 | 899 | |
37d43acf YG |
900 | if (status & MCI_STATUS_ADDRV) |
901 | rdmsrl(msr_addr, addr); | |
24fd78a8 | 902 | |
37d43acf | 903 | __log_error(bank, status, addr, misc); |
24fd78a8 | 904 | |
a24b8c34 | 905 | wrmsrl(msr_stat, 0); |
37d43acf YG |
906 | |
907 | return status & MCI_STATUS_DEFERRED; | |
24fd78a8 AG |
908 | } |
909 | ||
89b831ef | 910 | /* |
37d43acf YG |
911 | * We have three scenarios for checking for Deferred errors: |
912 | * | |
913 | * 1) Non-SMCA systems check MCA_STATUS and log error if found. | |
914 | * 2) SMCA systems check MCA_STATUS. If error is found then log it and also | |
915 | * clear MCA_DESTAT. | |
916 | * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and | |
917 | * log it. | |
89b831ef | 918 | */ |
37d43acf YG |
919 | static void log_error_deferred(unsigned int bank) |
920 | { | |
921 | bool defrd; | |
922 | ||
923 | defrd = _log_error_bank(bank, msr_ops.status(bank), | |
924 | msr_ops.addr(bank), 0); | |
925 | ||
926 | if (!mce_flags.smca) | |
927 | return; | |
928 | ||
929 | /* Clear MCA_DESTAT if we logged the deferred error from MCA_STATUS. */ | |
930 | if (defrd) { | |
931 | wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0); | |
932 | return; | |
933 | } | |
934 | ||
935 | /* | |
936 | * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check | |
937 | * for a valid error. | |
938 | */ | |
939 | _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank), | |
940 | MSR_AMD64_SMCA_MCx_DEADDR(bank), 0); | |
941 | } | |
942 | ||
943 | /* APIC interrupt handler for deferred errors */ | |
944 | static void amd_deferred_error_interrupt(void) | |
945 | { | |
946 | unsigned int bank; | |
947 | ||
948 | for (bank = 0; bank < mca_cfg.banks; ++bank) | |
949 | log_error_deferred(bank); | |
950 | } | |
951 | ||
952 | static void log_error_thresholding(unsigned int bank, u64 misc) | |
953 | { | |
954 | _log_error_bank(bank, msr_ops.status(bank), msr_ops.addr(bank), misc); | |
955 | } | |
89b831ef | 956 | |
17ef4af0 YG |
957 | static void log_and_reset_block(struct threshold_block *block) |
958 | { | |
959 | struct thresh_restart tr; | |
960 | u32 low = 0, high = 0; | |
961 | ||
962 | if (!block) | |
963 | return; | |
964 | ||
965 | if (rdmsr_safe(block->address, &low, &high)) | |
966 | return; | |
967 | ||
968 | if (!(high & MASK_OVERFLOW_HI)) | |
969 | return; | |
970 | ||
971 | /* Log the MCE which caused the threshold event. */ | |
972 | log_error_thresholding(block->bank, ((u64)high << 32) | low); | |
973 | ||
974 | /* Reset threshold block after logging error. */ | |
975 | memset(&tr, 0, sizeof(tr)); | |
976 | tr.b = block; | |
977 | threshold_restart_bank(&tr); | |
978 | } | |
979 | ||
89b831ef | 980 | /* |
37d43acf YG |
981 | * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt |
982 | * goes off when error_count reaches threshold_limit. | |
89b831ef | 983 | */ |
b2762686 | 984 | static void amd_threshold_interrupt(void) |
89b831ef | 985 | { |
17ef4af0 YG |
986 | struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL; |
987 | unsigned int bank, cpu = smp_processor_id(); | |
89b831ef | 988 | |
bafcdd3b | 989 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
44612a3a | 990 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
24ce0e96 | 991 | continue; |
44612a3a | 992 | |
17ef4af0 YG |
993 | first_block = per_cpu(threshold_banks, cpu)[bank]->blocks; |
994 | if (!first_block) | |
995 | continue; | |
18807ddb | 996 | |
17ef4af0 YG |
997 | /* |
998 | * The first block is also the head of the list. Check it first | |
999 | * before iterating over the rest. | |
1000 | */ | |
1001 | log_and_reset_block(first_block); | |
1002 | list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj) | |
1003 | log_and_reset_block(block); | |
37d43acf | 1004 | } |
89b831ef JS |
1005 | } |
1006 | ||
1007 | /* | |
1008 | * Sysfs Interface | |
1009 | */ | |
1010 | ||
89b831ef | 1011 | struct threshold_attr { |
2903ee85 | 1012 | struct attribute attr; |
1cb2a8e1 IM |
1013 | ssize_t (*show) (struct threshold_block *, char *); |
1014 | ssize_t (*store) (struct threshold_block *, const char *, size_t count); | |
89b831ef JS |
1015 | }; |
1016 | ||
1cb2a8e1 IM |
1017 | #define SHOW_FIELDS(name) \ |
1018 | static ssize_t show_ ## name(struct threshold_block *b, char *buf) \ | |
1019 | { \ | |
18c20f37 | 1020 | return sprintf(buf, "%lu\n", (unsigned long) b->name); \ |
2903ee85 | 1021 | } |
89b831ef JS |
1022 | SHOW_FIELDS(interrupt_enable) |
1023 | SHOW_FIELDS(threshold_limit) | |
1024 | ||
1cb2a8e1 | 1025 | static ssize_t |
9319cec8 | 1026 | store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size) |
89b831ef | 1027 | { |
4cd4601d | 1028 | struct thresh_restart tr; |
1cb2a8e1 | 1029 | unsigned long new; |
1cb2a8e1 | 1030 | |
f227d430 BP |
1031 | if (!b->interrupt_capable) |
1032 | return -EINVAL; | |
1033 | ||
164109e3 | 1034 | if (kstrtoul(buf, 0, &new) < 0) |
89b831ef | 1035 | return -EINVAL; |
1cb2a8e1 | 1036 | |
89b831ef JS |
1037 | b->interrupt_enable = !!new; |
1038 | ||
9c37c9d8 | 1039 | memset(&tr, 0, sizeof(tr)); |
1cb2a8e1 | 1040 | tr.b = b; |
1cb2a8e1 | 1041 | |
a6b6a14e | 1042 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef | 1043 | |
9319cec8 | 1044 | return size; |
89b831ef JS |
1045 | } |
1046 | ||
1cb2a8e1 | 1047 | static ssize_t |
9319cec8 | 1048 | store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) |
89b831ef | 1049 | { |
4cd4601d | 1050 | struct thresh_restart tr; |
1cb2a8e1 | 1051 | unsigned long new; |
1cb2a8e1 | 1052 | |
164109e3 | 1053 | if (kstrtoul(buf, 0, &new) < 0) |
89b831ef | 1054 | return -EINVAL; |
1cb2a8e1 | 1055 | |
89b831ef JS |
1056 | if (new > THRESHOLD_MAX) |
1057 | new = THRESHOLD_MAX; | |
1058 | if (new < 1) | |
1059 | new = 1; | |
1cb2a8e1 | 1060 | |
9c37c9d8 | 1061 | memset(&tr, 0, sizeof(tr)); |
4cd4601d | 1062 | tr.old_limit = b->threshold_limit; |
89b831ef | 1063 | b->threshold_limit = new; |
4cd4601d | 1064 | tr.b = b; |
89b831ef | 1065 | |
a6b6a14e | 1066 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef | 1067 | |
9319cec8 | 1068 | return size; |
89b831ef JS |
1069 | } |
1070 | ||
4cd4601d MT |
1071 | static ssize_t show_error_count(struct threshold_block *b, char *buf) |
1072 | { | |
2c9c42fa BP |
1073 | u32 lo, hi; |
1074 | ||
1075 | rdmsr_on_cpu(b->cpu, b->address, &lo, &hi); | |
a6b6a14e | 1076 | |
2c9c42fa BP |
1077 | return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - |
1078 | (THRESHOLD_MAX - b->threshold_limit))); | |
89b831ef JS |
1079 | } |
1080 | ||
6e927361 BP |
1081 | static struct threshold_attr error_count = { |
1082 | .attr = {.name = __stringify(error_count), .mode = 0444 }, | |
1083 | .show = show_error_count, | |
1084 | }; | |
89b831ef | 1085 | |
34fa1967 HS |
1086 | #define RW_ATTR(val) \ |
1087 | static struct threshold_attr val = { \ | |
1088 | .attr = {.name = __stringify(val), .mode = 0644 }, \ | |
1089 | .show = show_## val, \ | |
1090 | .store = store_## val, \ | |
89b831ef JS |
1091 | }; |
1092 | ||
2903ee85 JS |
1093 | RW_ATTR(interrupt_enable); |
1094 | RW_ATTR(threshold_limit); | |
89b831ef JS |
1095 | |
1096 | static struct attribute *default_attrs[] = { | |
89b831ef JS |
1097 | &threshold_limit.attr, |
1098 | &error_count.attr, | |
d26ecc48 BP |
1099 | NULL, /* possibly interrupt_enable if supported, see below */ |
1100 | NULL, | |
89b831ef JS |
1101 | }; |
1102 | ||
1cb2a8e1 IM |
1103 | #define to_block(k) container_of(k, struct threshold_block, kobj) |
1104 | #define to_attr(a) container_of(a, struct threshold_attr, attr) | |
89b831ef JS |
1105 | |
1106 | static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) | |
1107 | { | |
95268664 | 1108 | struct threshold_block *b = to_block(kobj); |
89b831ef JS |
1109 | struct threshold_attr *a = to_attr(attr); |
1110 | ssize_t ret; | |
1cb2a8e1 | 1111 | |
89b831ef | 1112 | ret = a->show ? a->show(b, buf) : -EIO; |
1cb2a8e1 | 1113 | |
89b831ef JS |
1114 | return ret; |
1115 | } | |
1116 | ||
1117 | static ssize_t store(struct kobject *kobj, struct attribute *attr, | |
1118 | const char *buf, size_t count) | |
1119 | { | |
95268664 | 1120 | struct threshold_block *b = to_block(kobj); |
89b831ef JS |
1121 | struct threshold_attr *a = to_attr(attr); |
1122 | ssize_t ret; | |
1cb2a8e1 | 1123 | |
89b831ef | 1124 | ret = a->store ? a->store(b, buf, count) : -EIO; |
1cb2a8e1 | 1125 | |
89b831ef JS |
1126 | return ret; |
1127 | } | |
1128 | ||
52cf25d0 | 1129 | static const struct sysfs_ops threshold_ops = { |
1cb2a8e1 IM |
1130 | .show = show, |
1131 | .store = store, | |
89b831ef JS |
1132 | }; |
1133 | ||
1134 | static struct kobj_type threshold_ktype = { | |
1cb2a8e1 IM |
1135 | .sysfs_ops = &threshold_ops, |
1136 | .default_attrs = default_attrs, | |
89b831ef JS |
1137 | }; |
1138 | ||
87a6d409 YG |
1139 | static const char *get_name(unsigned int bank, struct threshold_block *b) |
1140 | { | |
42cac853 | 1141 | enum smca_bank_types bank_type; |
87a6d409 YG |
1142 | |
1143 | if (!mce_flags.smca) { | |
1144 | if (b && bank == 4) | |
1145 | return bank4_names(b); | |
1146 | ||
1147 | return th_names[bank]; | |
1148 | } | |
1149 | ||
42cac853 YG |
1150 | bank_type = smca_get_bank_type(bank); |
1151 | if (bank_type >= N_SMCA_BANK_TYPES) | |
87a6d409 YG |
1152 | return NULL; |
1153 | ||
87a6d409 YG |
1154 | if (b && bank_type == SMCA_UMC) { |
1155 | if (b->block < ARRAY_SIZE(smca_umc_block_names)) | |
1156 | return smca_umc_block_names[b->block]; | |
1157 | return NULL; | |
1158 | } | |
1159 | ||
0b737a9c YG |
1160 | if (smca_banks[bank].hwid->count == 1) |
1161 | return smca_get_name(bank_type); | |
1162 | ||
87a6d409 | 1163 | snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN, |
c09a8c40 | 1164 | "%s_%x", smca_get_name(bank_type), |
0b737a9c | 1165 | smca_banks[bank].sysfs_id); |
87a6d409 YG |
1166 | return buf_mcatype; |
1167 | } | |
1168 | ||
148f9bb8 PG |
1169 | static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank, |
1170 | unsigned int block, u32 address) | |
95268664 | 1171 | { |
95268664 | 1172 | struct threshold_block *b = NULL; |
1cb2a8e1 IM |
1173 | u32 low, high; |
1174 | int err; | |
95268664 | 1175 | |
bafcdd3b | 1176 | if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS)) |
95268664 JS |
1177 | return 0; |
1178 | ||
a6b6a14e | 1179 | if (rdmsr_safe_on_cpu(cpu, address, &low, &high)) |
24ce0e96 | 1180 | return 0; |
95268664 JS |
1181 | |
1182 | if (!(high & MASK_VALID_HI)) { | |
1183 | if (block) | |
1184 | goto recurse; | |
1185 | else | |
1186 | return 0; | |
1187 | } | |
1188 | ||
24ce0e96 JB |
1189 | if (!(high & MASK_CNTP_HI) || |
1190 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
1191 | goto recurse; |
1192 | ||
1193 | b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL); | |
1194 | if (!b) | |
1195 | return -ENOMEM; | |
95268664 | 1196 | |
1cb2a8e1 IM |
1197 | b->block = block; |
1198 | b->bank = bank; | |
1199 | b->cpu = cpu; | |
1200 | b->address = address; | |
1201 | b->interrupt_enable = 0; | |
f227d430 | 1202 | b->interrupt_capable = lvt_interrupt_supported(bank, high); |
1cb2a8e1 | 1203 | b->threshold_limit = THRESHOLD_MAX; |
95268664 | 1204 | |
d79f931f | 1205 | if (b->interrupt_capable) { |
d26ecc48 | 1206 | threshold_ktype.default_attrs[2] = &interrupt_enable.attr; |
d79f931f AG |
1207 | b->interrupt_enable = 1; |
1208 | } else { | |
d26ecc48 | 1209 | threshold_ktype.default_attrs[2] = NULL; |
d79f931f | 1210 | } |
d26ecc48 | 1211 | |
95268664 JS |
1212 | INIT_LIST_HEAD(&b->miscj); |
1213 | ||
1cb2a8e1 | 1214 | if (per_cpu(threshold_banks, cpu)[bank]->blocks) { |
95268664 JS |
1215 | list_add(&b->miscj, |
1216 | &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj); | |
1cb2a8e1 | 1217 | } else { |
95268664 | 1218 | per_cpu(threshold_banks, cpu)[bank]->blocks = b; |
1cb2a8e1 | 1219 | } |
95268664 | 1220 | |
542eb75a GKH |
1221 | err = kobject_init_and_add(&b->kobj, &threshold_ktype, |
1222 | per_cpu(threshold_banks, cpu)[bank]->kobj, | |
87a6d409 | 1223 | get_name(bank, b)); |
95268664 JS |
1224 | if (err) |
1225 | goto out_free; | |
1226 | recurse: | |
cfee4f6f | 1227 | address = get_block_address(cpu, address, low, high, bank, ++block); |
8dd1e17a AG |
1228 | if (!address) |
1229 | return 0; | |
95268664 | 1230 | |
8dd1e17a | 1231 | err = allocate_threshold_blocks(cpu, bank, block, address); |
95268664 JS |
1232 | if (err) |
1233 | goto out_free; | |
1234 | ||
213eca7f GKH |
1235 | if (b) |
1236 | kobject_uevent(&b->kobj, KOBJ_ADD); | |
542eb75a | 1237 | |
95268664 JS |
1238 | return err; |
1239 | ||
1240 | out_free: | |
1241 | if (b) { | |
38a382ae | 1242 | kobject_put(&b->kobj); |
d9a5ac9e | 1243 | list_del(&b->miscj); |
95268664 JS |
1244 | kfree(b); |
1245 | } | |
1246 | return err; | |
1247 | } | |
1248 | ||
148f9bb8 | 1249 | static int __threshold_add_blocks(struct threshold_bank *b) |
019f34fc BP |
1250 | { |
1251 | struct list_head *head = &b->blocks->miscj; | |
1252 | struct threshold_block *pos = NULL; | |
1253 | struct threshold_block *tmp = NULL; | |
1254 | int err = 0; | |
1255 | ||
1256 | err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name); | |
1257 | if (err) | |
1258 | return err; | |
1259 | ||
1260 | list_for_each_entry_safe(pos, tmp, head, miscj) { | |
1261 | ||
1262 | err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name); | |
1263 | if (err) { | |
1264 | list_for_each_entry_safe_reverse(pos, tmp, head, miscj) | |
1265 | kobject_del(&pos->kobj); | |
1266 | ||
1267 | return err; | |
1268 | } | |
1269 | } | |
1270 | return err; | |
1271 | } | |
1272 | ||
148f9bb8 | 1273 | static int threshold_create_bank(unsigned int cpu, unsigned int bank) |
89b831ef | 1274 | { |
d6126ef5 | 1275 | struct device *dev = per_cpu(mce_device, cpu); |
019f34fc | 1276 | struct amd_northbridge *nb = NULL; |
92e26e2a | 1277 | struct threshold_bank *b = NULL; |
87a6d409 | 1278 | const char *name = get_name(bank, NULL); |
92e26e2a | 1279 | int err = 0; |
95268664 | 1280 | |
0dad3a30 TG |
1281 | if (!dev) |
1282 | return -ENODEV; | |
1283 | ||
c76e8164 | 1284 | if (is_shared_bank(bank)) { |
019f34fc | 1285 | nb = node_to_amd_nb(amd_get_nb_id(cpu)); |
019f34fc BP |
1286 | |
1287 | /* threshold descriptor already initialized on this node? */ | |
21c5e50e | 1288 | if (nb && nb->bank4) { |
019f34fc BP |
1289 | /* yes, use it */ |
1290 | b = nb->bank4; | |
1291 | err = kobject_add(b->kobj, &dev->kobj, name); | |
1292 | if (err) | |
1293 | goto out; | |
1294 | ||
1295 | per_cpu(threshold_banks, cpu)[bank] = b; | |
473e90b2 | 1296 | refcount_inc(&b->cpus); |
019f34fc BP |
1297 | |
1298 | err = __threshold_add_blocks(b); | |
1299 | ||
1300 | goto out; | |
1301 | } | |
1302 | } | |
1303 | ||
95268664 | 1304 | b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL); |
89b831ef JS |
1305 | if (!b) { |
1306 | err = -ENOMEM; | |
1307 | goto out; | |
1308 | } | |
89b831ef | 1309 | |
e032d807 | 1310 | b->kobj = kobject_create_and_add(name, &dev->kobj); |
92e26e2a BP |
1311 | if (!b->kobj) { |
1312 | err = -EINVAL; | |
a521cf20 | 1313 | goto out_free; |
92e26e2a | 1314 | } |
95268664 | 1315 | |
89b831ef | 1316 | per_cpu(threshold_banks, cpu)[bank] = b; |
95268664 | 1317 | |
c76e8164 | 1318 | if (is_shared_bank(bank)) { |
473e90b2 | 1319 | refcount_set(&b->cpus, 1); |
019f34fc BP |
1320 | |
1321 | /* nb is already initialized, see above */ | |
21c5e50e DB |
1322 | if (nb) { |
1323 | WARN_ON(nb->bank4); | |
1324 | nb->bank4 = b; | |
1325 | } | |
019f34fc BP |
1326 | } |
1327 | ||
74ab0e7a | 1328 | err = allocate_threshold_blocks(cpu, bank, 0, msr_ops.misc(bank)); |
92e26e2a BP |
1329 | if (!err) |
1330 | goto out; | |
95268664 | 1331 | |
019f34fc | 1332 | out_free: |
95268664 | 1333 | kfree(b); |
019f34fc BP |
1334 | |
1335 | out: | |
89b831ef JS |
1336 | return err; |
1337 | } | |
1338 | ||
be6b5a35 | 1339 | static void deallocate_threshold_block(unsigned int cpu, |
95268664 JS |
1340 | unsigned int bank) |
1341 | { | |
1342 | struct threshold_block *pos = NULL; | |
1343 | struct threshold_block *tmp = NULL; | |
1344 | struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank]; | |
1345 | ||
1346 | if (!head) | |
1347 | return; | |
1348 | ||
1349 | list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) { | |
38a382ae | 1350 | kobject_put(&pos->kobj); |
95268664 JS |
1351 | list_del(&pos->miscj); |
1352 | kfree(pos); | |
1353 | } | |
1354 | ||
1355 | kfree(per_cpu(threshold_banks, cpu)[bank]->blocks); | |
1356 | per_cpu(threshold_banks, cpu)[bank]->blocks = NULL; | |
1357 | } | |
1358 | ||
019f34fc BP |
1359 | static void __threshold_remove_blocks(struct threshold_bank *b) |
1360 | { | |
1361 | struct threshold_block *pos = NULL; | |
1362 | struct threshold_block *tmp = NULL; | |
1363 | ||
1364 | kobject_del(b->kobj); | |
1365 | ||
1366 | list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj) | |
1367 | kobject_del(&pos->kobj); | |
1368 | } | |
1369 | ||
be6b5a35 | 1370 | static void threshold_remove_bank(unsigned int cpu, int bank) |
89b831ef | 1371 | { |
019f34fc | 1372 | struct amd_northbridge *nb; |
89b831ef | 1373 | struct threshold_bank *b; |
89b831ef JS |
1374 | |
1375 | b = per_cpu(threshold_banks, cpu)[bank]; | |
1376 | if (!b) | |
1377 | return; | |
019f34fc | 1378 | |
95268664 JS |
1379 | if (!b->blocks) |
1380 | goto free_out; | |
1381 | ||
c76e8164 | 1382 | if (is_shared_bank(bank)) { |
473e90b2 | 1383 | if (!refcount_dec_and_test(&b->cpus)) { |
019f34fc BP |
1384 | __threshold_remove_blocks(b); |
1385 | per_cpu(threshold_banks, cpu)[bank] = NULL; | |
1386 | return; | |
1387 | } else { | |
1388 | /* | |
1389 | * the last CPU on this node using the shared bank is | |
1390 | * going away, remove that bank now. | |
1391 | */ | |
1392 | nb = node_to_amd_nb(amd_get_nb_id(cpu)); | |
1393 | nb->bank4 = NULL; | |
1394 | } | |
1395 | } | |
1396 | ||
95268664 JS |
1397 | deallocate_threshold_block(cpu, bank); |
1398 | ||
1399 | free_out: | |
8735728e | 1400 | kobject_del(b->kobj); |
38a382ae | 1401 | kobject_put(b->kobj); |
95268664 JS |
1402 | kfree(b); |
1403 | per_cpu(threshold_banks, cpu)[bank] = NULL; | |
89b831ef JS |
1404 | } |
1405 | ||
4d7b02d5 | 1406 | int mce_threshold_remove_device(unsigned int cpu) |
89b831ef | 1407 | { |
2903ee85 | 1408 | unsigned int bank; |
89b831ef | 1409 | |
bafcdd3b | 1410 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
5a96f4a5 | 1411 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
89b831ef JS |
1412 | continue; |
1413 | threshold_remove_bank(cpu, bank); | |
1414 | } | |
bafcdd3b | 1415 | kfree(per_cpu(threshold_banks, cpu)); |
ec553abb | 1416 | per_cpu(threshold_banks, cpu) = NULL; |
4d7b02d5 | 1417 | return 0; |
89b831ef JS |
1418 | } |
1419 | ||
09436372 | 1420 | /* create dir/files for all valid threshold banks */ |
4d7b02d5 | 1421 | int mce_threshold_create_device(unsigned int cpu) |
89b831ef | 1422 | { |
09436372 SAS |
1423 | unsigned int bank; |
1424 | struct threshold_bank **bp; | |
1425 | int err = 0; | |
1426 | ||
7f34b935 SAS |
1427 | bp = per_cpu(threshold_banks, cpu); |
1428 | if (bp) | |
1429 | return 0; | |
1430 | ||
09436372 SAS |
1431 | bp = kzalloc(sizeof(struct threshold_bank *) * mca_cfg.banks, |
1432 | GFP_KERNEL); | |
1433 | if (!bp) | |
1434 | return -ENOMEM; | |
1435 | ||
1436 | per_cpu(threshold_banks, cpu) = bp; | |
1437 | ||
1438 | for (bank = 0; bank < mca_cfg.banks; ++bank) { | |
1439 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) | |
1440 | continue; | |
1441 | err = threshold_create_bank(cpu, bank); | |
1442 | if (err) | |
ec553abb | 1443 | goto err; |
89b831ef | 1444 | } |
ec553abb SAS |
1445 | return err; |
1446 | err: | |
4d7b02d5 | 1447 | mce_threshold_remove_device(cpu); |
09436372 | 1448 | return err; |
89b831ef JS |
1449 | } |
1450 | ||
89b831ef JS |
1451 | static __init int threshold_init_device(void) |
1452 | { | |
2903ee85 | 1453 | unsigned lcpu = 0; |
89b831ef | 1454 | |
89b831ef JS |
1455 | /* to hit CPUs online before the notifier is up */ |
1456 | for_each_online_cpu(lcpu) { | |
4d7b02d5 | 1457 | int err = mce_threshold_create_device(lcpu); |
1cb2a8e1 | 1458 | |
89b831ef | 1459 | if (err) |
fff2e89f | 1460 | return err; |
89b831ef | 1461 | } |
1cb2a8e1 | 1462 | |
628cf0d4 BP |
1463 | if (thresholding_irq_en) |
1464 | mce_threshold_vector = amd_threshold_interrupt; | |
1465 | ||
fff2e89f | 1466 | return 0; |
89b831ef | 1467 | } |
a8fccdb0 LJ |
1468 | /* |
1469 | * there are 3 funcs which need to be _initcalled in a logic sequence: | |
1470 | * 1. xen_late_init_mcelog | |
1471 | * 2. mcheck_init_device | |
1472 | * 3. threshold_init_device | |
1473 | * | |
1474 | * xen_late_init_mcelog must register xen_mce_chrdev_device before | |
1475 | * native mce_chrdev_device registration if running under xen platform; | |
1476 | * | |
1477 | * mcheck_init_device should be inited before threshold_init_device to | |
1478 | * initialize mce_device, otherwise a NULL ptr dereference will cause panic. | |
1479 | * | |
1480 | * so we use following _initcalls | |
1481 | * 1. device_initcall(xen_late_init_mcelog); | |
1482 | * 2. device_initcall_sync(mcheck_init_device); | |
1483 | * 3. late_initcall(threshold_init_device); | |
1484 | * | |
1485 | * when running under xen, the initcall order is 1,2,3; | |
1486 | * on baremetal, we skip 1 and we do only 2 and 3. | |
1487 | */ | |
1488 | late_initcall(threshold_init_device); |