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Commit | Line | Data |
---|---|---|
89b831ef | 1 | /* |
95268664 | 2 | * (c) 2005, 2006 Advanced Micro Devices, Inc. |
89b831ef JS |
3 | * Your use of this code is subject to the terms and conditions of the |
4 | * GNU general public license version 2. See "COPYING" or | |
5 | * http://www.gnu.org/licenses/gpl.html | |
6 | * | |
7 | * Written by Jacob Shin - AMD, Inc. | |
8 | * | |
9 | * Support : jacob.shin@amd.com | |
10 | * | |
95268664 JS |
11 | * April 2006 |
12 | * - added support for AMD Family 0x10 processors | |
89b831ef | 13 | * |
95268664 | 14 | * All MC4_MISCi registers are shared between multi-cores |
89b831ef | 15 | */ |
89b831ef | 16 | #include <linux/interrupt.h> |
89b831ef | 17 | #include <linux/notifier.h> |
1cb2a8e1 | 18 | #include <linux/kobject.h> |
89b831ef | 19 | #include <linux/sysdev.h> |
1cb2a8e1 IM |
20 | #include <linux/errno.h> |
21 | #include <linux/sched.h> | |
89b831ef | 22 | #include <linux/sysfs.h> |
1cb2a8e1 IM |
23 | #include <linux/init.h> |
24 | #include <linux/cpu.h> | |
25 | #include <linux/smp.h> | |
26 | ||
27 | #include <asm/percpu.h> | |
89b831ef | 28 | #include <asm/apic.h> |
1cb2a8e1 | 29 | #include <asm/idle.h> |
89b831ef JS |
30 | #include <asm/mce.h> |
31 | #include <asm/msr.h> | |
89b831ef | 32 | |
2903ee85 JS |
33 | #define PFX "mce_threshold: " |
34 | #define VERSION "version 1.1.1" | |
35 | #define NR_BANKS 6 | |
36 | #define NR_BLOCKS 9 | |
37 | #define THRESHOLD_MAX 0xFFF | |
38 | #define INT_TYPE_APIC 0x00020000 | |
39 | #define MASK_VALID_HI 0x80000000 | |
24ce0e96 JB |
40 | #define MASK_CNTP_HI 0x40000000 |
41 | #define MASK_LOCKED_HI 0x20000000 | |
2903ee85 JS |
42 | #define MASK_LVTOFF_HI 0x00F00000 |
43 | #define MASK_COUNT_EN_HI 0x00080000 | |
44 | #define MASK_INT_TYPE_HI 0x00060000 | |
45 | #define MASK_OVERFLOW_HI 0x00010000 | |
89b831ef | 46 | #define MASK_ERR_COUNT_HI 0x00000FFF |
95268664 JS |
47 | #define MASK_BLKPTR_LO 0xFF000000 |
48 | #define MCG_XBLK_ADDR 0xC0000400 | |
89b831ef | 49 | |
95268664 | 50 | struct threshold_block { |
1cb2a8e1 IM |
51 | unsigned int block; |
52 | unsigned int bank; | |
53 | unsigned int cpu; | |
54 | u32 address; | |
55 | u16 interrupt_enable; | |
56 | u16 threshold_limit; | |
57 | struct kobject kobj; | |
58 | struct list_head miscj; | |
89b831ef JS |
59 | }; |
60 | ||
95268664 JS |
61 | /* defaults used early on boot */ |
62 | static struct threshold_block threshold_defaults = { | |
1cb2a8e1 IM |
63 | .interrupt_enable = 0, |
64 | .threshold_limit = THRESHOLD_MAX, | |
89b831ef JS |
65 | }; |
66 | ||
95268664 | 67 | struct threshold_bank { |
1cb2a8e1 IM |
68 | struct kobject *kobj; |
69 | struct threshold_block *blocks; | |
70 | cpumask_var_t cpus; | |
95268664 JS |
71 | }; |
72 | static DEFINE_PER_CPU(struct threshold_bank *, threshold_banks[NR_BANKS]); | |
73 | ||
89b831ef JS |
74 | #ifdef CONFIG_SMP |
75 | static unsigned char shared_bank[NR_BANKS] = { | |
76 | 0, 0, 0, 0, 1 | |
77 | }; | |
78 | #endif | |
79 | ||
80 | static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */ | |
81 | ||
b2762686 AK |
82 | static void amd_threshold_interrupt(void); |
83 | ||
89b831ef JS |
84 | /* |
85 | * CPU Initialization | |
86 | */ | |
87 | ||
4cd4601d | 88 | struct thresh_restart { |
1cb2a8e1 IM |
89 | struct threshold_block *b; |
90 | int reset; | |
91 | u16 old_limit; | |
4cd4601d MT |
92 | }; |
93 | ||
89b831ef | 94 | /* must be called with correct cpu affinity */ |
a6b6a14e AM |
95 | /* Called via smp_call_function_single() */ |
96 | static void threshold_restart_bank(void *_tr) | |
89b831ef | 97 | { |
4cd4601d | 98 | struct thresh_restart *tr = _tr; |
89b831ef JS |
99 | u32 mci_misc_hi, mci_misc_lo; |
100 | ||
4cd4601d | 101 | rdmsr(tr->b->address, mci_misc_lo, mci_misc_hi); |
89b831ef | 102 | |
4cd4601d MT |
103 | if (tr->b->threshold_limit < (mci_misc_hi & THRESHOLD_MAX)) |
104 | tr->reset = 1; /* limit cannot be lower than err count */ | |
89b831ef | 105 | |
4cd4601d | 106 | if (tr->reset) { /* reset err count and overflow bit */ |
89b831ef JS |
107 | mci_misc_hi = |
108 | (mci_misc_hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) | | |
4cd4601d MT |
109 | (THRESHOLD_MAX - tr->b->threshold_limit); |
110 | } else if (tr->old_limit) { /* change limit w/o reset */ | |
89b831ef | 111 | int new_count = (mci_misc_hi & THRESHOLD_MAX) + |
4cd4601d | 112 | (tr->old_limit - tr->b->threshold_limit); |
1cb2a8e1 | 113 | |
89b831ef JS |
114 | mci_misc_hi = (mci_misc_hi & ~MASK_ERR_COUNT_HI) | |
115 | (new_count & THRESHOLD_MAX); | |
116 | } | |
117 | ||
4cd4601d | 118 | tr->b->interrupt_enable ? |
89b831ef JS |
119 | (mci_misc_hi = (mci_misc_hi & ~MASK_INT_TYPE_HI) | INT_TYPE_APIC) : |
120 | (mci_misc_hi &= ~MASK_INT_TYPE_HI); | |
121 | ||
122 | mci_misc_hi |= MASK_COUNT_EN_HI; | |
4cd4601d | 123 | wrmsr(tr->b->address, mci_misc_lo, mci_misc_hi); |
89b831ef JS |
124 | } |
125 | ||
95268664 | 126 | /* cpu init entry point, called from mce.c with preempt off */ |
cc3ca220 | 127 | void mce_amd_feature_init(struct cpuinfo_x86 *c) |
89b831ef | 128 | { |
89b831ef | 129 | unsigned int cpu = smp_processor_id(); |
95268664 | 130 | u32 low = 0, high = 0, address = 0; |
1cb2a8e1 | 131 | unsigned int bank, block; |
4cd4601d | 132 | struct thresh_restart tr; |
1cb2a8e1 | 133 | u8 lvt_off; |
89b831ef JS |
134 | |
135 | for (bank = 0; bank < NR_BANKS; ++bank) { | |
95268664 JS |
136 | for (block = 0; block < NR_BLOCKS; ++block) { |
137 | if (block == 0) | |
138 | address = MSR_IA32_MC0_MISC + bank * 4; | |
24ce0e96 JB |
139 | else if (block == 1) { |
140 | address = (low & MASK_BLKPTR_LO) >> 21; | |
141 | if (!address) | |
142 | break; | |
143 | address += MCG_XBLK_ADDR; | |
1cb2a8e1 | 144 | } else |
95268664 JS |
145 | ++address; |
146 | ||
147 | if (rdmsr_safe(address, &low, &high)) | |
24ce0e96 | 148 | break; |
95268664 JS |
149 | |
150 | if (!(high & MASK_VALID_HI)) { | |
151 | if (block) | |
152 | continue; | |
153 | else | |
154 | break; | |
155 | } | |
156 | ||
24ce0e96 JB |
157 | if (!(high & MASK_CNTP_HI) || |
158 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
159 | continue; |
160 | ||
161 | if (!block) | |
162 | per_cpu(bank_map, cpu) |= (1 << bank); | |
89b831ef | 163 | #ifdef CONFIG_SMP |
95268664 JS |
164 | if (shared_bank[bank] && c->cpu_core_id) |
165 | break; | |
89b831ef | 166 | #endif |
7b83dae7 RR |
167 | lvt_off = setup_APIC_eilvt_mce(THRESHOLD_APIC_VECTOR, |
168 | APIC_EILVT_MSG_FIX, 0); | |
169 | ||
95268664 | 170 | high &= ~MASK_LVTOFF_HI; |
7b83dae7 | 171 | high |= lvt_off << 20; |
95268664 JS |
172 | wrmsr(address, low, high); |
173 | ||
95268664 | 174 | threshold_defaults.address = address; |
4cd4601d MT |
175 | tr.b = &threshold_defaults; |
176 | tr.reset = 0; | |
177 | tr.old_limit = 0; | |
178 | threshold_restart_bank(&tr); | |
b2762686 AK |
179 | |
180 | mce_threshold_vector = amd_threshold_interrupt; | |
95268664 | 181 | } |
89b831ef JS |
182 | } |
183 | } | |
184 | ||
185 | /* | |
186 | * APIC Interrupt Handler | |
187 | */ | |
188 | ||
189 | /* | |
190 | * threshold interrupt handler will service THRESHOLD_APIC_VECTOR. | |
191 | * the interrupt goes off when error_count reaches threshold_limit. | |
192 | * the handler will simply log mcelog w/ software defined bank number. | |
193 | */ | |
b2762686 | 194 | static void amd_threshold_interrupt(void) |
89b831ef | 195 | { |
1cb2a8e1 | 196 | u32 low = 0, high = 0, address = 0; |
95268664 | 197 | unsigned int bank, block; |
89b831ef JS |
198 | struct mce m; |
199 | ||
b5f2fa4e | 200 | mce_setup(&m); |
89b831ef JS |
201 | |
202 | /* assume first bank caused it */ | |
203 | for (bank = 0; bank < NR_BANKS; ++bank) { | |
24ce0e96 JB |
204 | if (!(per_cpu(bank_map, m.cpu) & (1 << bank))) |
205 | continue; | |
95268664 | 206 | for (block = 0; block < NR_BLOCKS; ++block) { |
1cb2a8e1 | 207 | if (block == 0) { |
95268664 | 208 | address = MSR_IA32_MC0_MISC + bank * 4; |
1cb2a8e1 | 209 | } else if (block == 1) { |
24ce0e96 JB |
210 | address = (low & MASK_BLKPTR_LO) >> 21; |
211 | if (!address) | |
212 | break; | |
213 | address += MCG_XBLK_ADDR; | |
1cb2a8e1 | 214 | } else { |
95268664 | 215 | ++address; |
1cb2a8e1 | 216 | } |
95268664 JS |
217 | |
218 | if (rdmsr_safe(address, &low, &high)) | |
24ce0e96 | 219 | break; |
95268664 JS |
220 | |
221 | if (!(high & MASK_VALID_HI)) { | |
222 | if (block) | |
223 | continue; | |
224 | else | |
225 | break; | |
226 | } | |
227 | ||
24ce0e96 JB |
228 | if (!(high & MASK_CNTP_HI) || |
229 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
230 | continue; |
231 | ||
1cb2a8e1 IM |
232 | /* |
233 | * Log the machine check that caused the threshold | |
234 | * event. | |
235 | */ | |
ee031c31 AK |
236 | machine_check_poll(MCP_TIMESTAMP, |
237 | &__get_cpu_var(mce_poll_banks)); | |
a98f0dd3 | 238 | |
95268664 JS |
239 | if (high & MASK_OVERFLOW_HI) { |
240 | rdmsrl(address, m.misc); | |
241 | rdmsrl(MSR_IA32_MC0_STATUS + bank * 4, | |
242 | m.status); | |
243 | m.bank = K8_MCE_THRESHOLD_BASE | |
244 | + bank * NR_BLOCKS | |
245 | + block; | |
246 | mce_log(&m); | |
b2762686 | 247 | return; |
95268664 | 248 | } |
89b831ef JS |
249 | } |
250 | } | |
89b831ef JS |
251 | } |
252 | ||
253 | /* | |
254 | * Sysfs Interface | |
255 | */ | |
256 | ||
89b831ef | 257 | struct threshold_attr { |
2903ee85 | 258 | struct attribute attr; |
1cb2a8e1 IM |
259 | ssize_t (*show) (struct threshold_block *, char *); |
260 | ssize_t (*store) (struct threshold_block *, const char *, size_t count); | |
89b831ef JS |
261 | }; |
262 | ||
1cb2a8e1 IM |
263 | #define SHOW_FIELDS(name) \ |
264 | static ssize_t show_ ## name(struct threshold_block *b, char *buf) \ | |
265 | { \ | |
266 | return sprintf(buf, "%lx\n", (unsigned long) b->name); \ | |
2903ee85 | 267 | } |
89b831ef JS |
268 | SHOW_FIELDS(interrupt_enable) |
269 | SHOW_FIELDS(threshold_limit) | |
270 | ||
1cb2a8e1 | 271 | static ssize_t |
9319cec8 | 272 | store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size) |
89b831ef | 273 | { |
4cd4601d | 274 | struct thresh_restart tr; |
1cb2a8e1 | 275 | unsigned long new; |
1cb2a8e1 | 276 | |
9319cec8 | 277 | if (strict_strtoul(buf, 0, &new) < 0) |
89b831ef | 278 | return -EINVAL; |
1cb2a8e1 | 279 | |
89b831ef JS |
280 | b->interrupt_enable = !!new; |
281 | ||
1cb2a8e1 IM |
282 | tr.b = b; |
283 | tr.reset = 0; | |
284 | tr.old_limit = 0; | |
285 | ||
a6b6a14e | 286 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef | 287 | |
9319cec8 | 288 | return size; |
89b831ef JS |
289 | } |
290 | ||
1cb2a8e1 | 291 | static ssize_t |
9319cec8 | 292 | store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) |
89b831ef | 293 | { |
4cd4601d | 294 | struct thresh_restart tr; |
1cb2a8e1 | 295 | unsigned long new; |
1cb2a8e1 | 296 | |
9319cec8 | 297 | if (strict_strtoul(buf, 0, &new) < 0) |
89b831ef | 298 | return -EINVAL; |
1cb2a8e1 | 299 | |
89b831ef JS |
300 | if (new > THRESHOLD_MAX) |
301 | new = THRESHOLD_MAX; | |
302 | if (new < 1) | |
303 | new = 1; | |
1cb2a8e1 | 304 | |
4cd4601d | 305 | tr.old_limit = b->threshold_limit; |
89b831ef | 306 | b->threshold_limit = new; |
4cd4601d MT |
307 | tr.b = b; |
308 | tr.reset = 0; | |
89b831ef | 309 | |
a6b6a14e | 310 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef | 311 | |
9319cec8 | 312 | return size; |
89b831ef JS |
313 | } |
314 | ||
a6b6a14e | 315 | struct threshold_block_cross_cpu { |
1cb2a8e1 IM |
316 | struct threshold_block *tb; |
317 | long retval; | |
a6b6a14e AM |
318 | }; |
319 | ||
320 | static void local_error_count_handler(void *_tbcc) | |
89b831ef | 321 | { |
a6b6a14e AM |
322 | struct threshold_block_cross_cpu *tbcc = _tbcc; |
323 | struct threshold_block *b = tbcc->tb; | |
4cd4601d MT |
324 | u32 low, high; |
325 | ||
95268664 | 326 | rdmsr(b->address, low, high); |
a6b6a14e | 327 | tbcc->retval = (high & 0xFFF) - (THRESHOLD_MAX - b->threshold_limit); |
4cd4601d MT |
328 | } |
329 | ||
330 | static ssize_t show_error_count(struct threshold_block *b, char *buf) | |
331 | { | |
a6b6a14e AM |
332 | struct threshold_block_cross_cpu tbcc = { .tb = b, }; |
333 | ||
334 | smp_call_function_single(b->cpu, local_error_count_handler, &tbcc, 1); | |
335 | return sprintf(buf, "%lx\n", tbcc.retval); | |
89b831ef JS |
336 | } |
337 | ||
95268664 | 338 | static ssize_t store_error_count(struct threshold_block *b, |
89b831ef JS |
339 | const char *buf, size_t count) |
340 | { | |
4cd4601d MT |
341 | struct thresh_restart tr = { .b = b, .reset = 1, .old_limit = 0 }; |
342 | ||
a6b6a14e | 343 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef JS |
344 | return 1; |
345 | } | |
346 | ||
1cb2a8e1 IM |
347 | #define THRESHOLD_ATTR(_name, _mode, _show, _store) \ |
348 | { \ | |
349 | .attr = {.name = __stringify(_name), .mode = _mode }, \ | |
350 | .show = _show, \ | |
351 | .store = _store, \ | |
89b831ef JS |
352 | }; |
353 | ||
1cb2a8e1 IM |
354 | #define RW_ATTR(name) \ |
355 | static struct threshold_attr name = \ | |
356 | THRESHOLD_ATTR(name, 0644, show_## name, store_## name) | |
89b831ef | 357 | |
2903ee85 JS |
358 | RW_ATTR(interrupt_enable); |
359 | RW_ATTR(threshold_limit); | |
360 | RW_ATTR(error_count); | |
89b831ef JS |
361 | |
362 | static struct attribute *default_attrs[] = { | |
363 | &interrupt_enable.attr, | |
364 | &threshold_limit.attr, | |
365 | &error_count.attr, | |
366 | NULL | |
367 | }; | |
368 | ||
1cb2a8e1 IM |
369 | #define to_block(k) container_of(k, struct threshold_block, kobj) |
370 | #define to_attr(a) container_of(a, struct threshold_attr, attr) | |
89b831ef JS |
371 | |
372 | static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) | |
373 | { | |
95268664 | 374 | struct threshold_block *b = to_block(kobj); |
89b831ef JS |
375 | struct threshold_attr *a = to_attr(attr); |
376 | ssize_t ret; | |
1cb2a8e1 | 377 | |
89b831ef | 378 | ret = a->show ? a->show(b, buf) : -EIO; |
1cb2a8e1 | 379 | |
89b831ef JS |
380 | return ret; |
381 | } | |
382 | ||
383 | static ssize_t store(struct kobject *kobj, struct attribute *attr, | |
384 | const char *buf, size_t count) | |
385 | { | |
95268664 | 386 | struct threshold_block *b = to_block(kobj); |
89b831ef JS |
387 | struct threshold_attr *a = to_attr(attr); |
388 | ssize_t ret; | |
1cb2a8e1 | 389 | |
89b831ef | 390 | ret = a->store ? a->store(b, buf, count) : -EIO; |
1cb2a8e1 | 391 | |
89b831ef JS |
392 | return ret; |
393 | } | |
394 | ||
395 | static struct sysfs_ops threshold_ops = { | |
1cb2a8e1 IM |
396 | .show = show, |
397 | .store = store, | |
89b831ef JS |
398 | }; |
399 | ||
400 | static struct kobj_type threshold_ktype = { | |
1cb2a8e1 IM |
401 | .sysfs_ops = &threshold_ops, |
402 | .default_attrs = default_attrs, | |
89b831ef JS |
403 | }; |
404 | ||
95268664 JS |
405 | static __cpuinit int allocate_threshold_blocks(unsigned int cpu, |
406 | unsigned int bank, | |
407 | unsigned int block, | |
408 | u32 address) | |
409 | { | |
95268664 | 410 | struct threshold_block *b = NULL; |
1cb2a8e1 IM |
411 | u32 low, high; |
412 | int err; | |
95268664 JS |
413 | |
414 | if ((bank >= NR_BANKS) || (block >= NR_BLOCKS)) | |
415 | return 0; | |
416 | ||
a6b6a14e | 417 | if (rdmsr_safe_on_cpu(cpu, address, &low, &high)) |
24ce0e96 | 418 | return 0; |
95268664 JS |
419 | |
420 | if (!(high & MASK_VALID_HI)) { | |
421 | if (block) | |
422 | goto recurse; | |
423 | else | |
424 | return 0; | |
425 | } | |
426 | ||
24ce0e96 JB |
427 | if (!(high & MASK_CNTP_HI) || |
428 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
429 | goto recurse; |
430 | ||
431 | b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL); | |
432 | if (!b) | |
433 | return -ENOMEM; | |
95268664 | 434 | |
1cb2a8e1 IM |
435 | b->block = block; |
436 | b->bank = bank; | |
437 | b->cpu = cpu; | |
438 | b->address = address; | |
439 | b->interrupt_enable = 0; | |
440 | b->threshold_limit = THRESHOLD_MAX; | |
95268664 JS |
441 | |
442 | INIT_LIST_HEAD(&b->miscj); | |
443 | ||
1cb2a8e1 | 444 | if (per_cpu(threshold_banks, cpu)[bank]->blocks) { |
95268664 JS |
445 | list_add(&b->miscj, |
446 | &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj); | |
1cb2a8e1 | 447 | } else { |
95268664 | 448 | per_cpu(threshold_banks, cpu)[bank]->blocks = b; |
1cb2a8e1 | 449 | } |
95268664 | 450 | |
542eb75a GKH |
451 | err = kobject_init_and_add(&b->kobj, &threshold_ktype, |
452 | per_cpu(threshold_banks, cpu)[bank]->kobj, | |
453 | "misc%i", block); | |
95268664 JS |
454 | if (err) |
455 | goto out_free; | |
456 | recurse: | |
457 | if (!block) { | |
458 | address = (low & MASK_BLKPTR_LO) >> 21; | |
459 | if (!address) | |
460 | return 0; | |
461 | address += MCG_XBLK_ADDR; | |
1cb2a8e1 | 462 | } else { |
95268664 | 463 | ++address; |
1cb2a8e1 | 464 | } |
95268664 JS |
465 | |
466 | err = allocate_threshold_blocks(cpu, bank, ++block, address); | |
467 | if (err) | |
468 | goto out_free; | |
469 | ||
213eca7f GKH |
470 | if (b) |
471 | kobject_uevent(&b->kobj, KOBJ_ADD); | |
542eb75a | 472 | |
95268664 JS |
473 | return err; |
474 | ||
475 | out_free: | |
476 | if (b) { | |
38a382ae | 477 | kobject_put(&b->kobj); |
95268664 JS |
478 | kfree(b); |
479 | } | |
480 | return err; | |
481 | } | |
482 | ||
a6b6a14e AM |
483 | static __cpuinit long |
484 | local_allocate_threshold_blocks(int cpu, unsigned int bank) | |
4cd4601d | 485 | { |
a6b6a14e AM |
486 | return allocate_threshold_blocks(cpu, bank, 0, |
487 | MSR_IA32_MC0_MISC + bank * 4); | |
4cd4601d MT |
488 | } |
489 | ||
89b831ef | 490 | /* symlinks sibling shared banks to first core. first core owns dir/files. */ |
95268664 | 491 | static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank) |
89b831ef | 492 | { |
95268664 | 493 | int i, err = 0; |
68209407 | 494 | struct threshold_bank *b = NULL; |
95268664 JS |
495 | char name[32]; |
496 | ||
497 | sprintf(name, "threshold_bank%i", bank); | |
89b831ef JS |
498 | |
499 | #ifdef CONFIG_SMP | |
92cb7612 | 500 | if (cpu_data(cpu).cpu_core_id && shared_bank[bank]) { /* symlink */ |
7ad728f9 | 501 | i = cpumask_first(cpu_core_mask(cpu)); |
95268664 JS |
502 | |
503 | /* first core not up yet */ | |
92cb7612 | 504 | if (cpu_data(i).cpu_core_id) |
95268664 JS |
505 | goto out; |
506 | ||
507 | /* already linked */ | |
508 | if (per_cpu(threshold_banks, cpu)[bank]) | |
509 | goto out; | |
510 | ||
511 | b = per_cpu(threshold_banks, i)[bank]; | |
89b831ef | 512 | |
89b831ef JS |
513 | if (!b) |
514 | goto out; | |
95268664 | 515 | |
cb491fca | 516 | err = sysfs_create_link(&per_cpu(mce_dev, cpu).kobj, |
a521cf20 | 517 | b->kobj, name); |
89b831ef JS |
518 | if (err) |
519 | goto out; | |
95268664 | 520 | |
7ad728f9 | 521 | cpumask_copy(b->cpus, cpu_core_mask(cpu)); |
89b831ef | 522 | per_cpu(threshold_banks, cpu)[bank] = b; |
1cb2a8e1 | 523 | |
89b831ef JS |
524 | goto out; |
525 | } | |
526 | #endif | |
527 | ||
95268664 | 528 | b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL); |
89b831ef JS |
529 | if (!b) { |
530 | err = -ENOMEM; | |
531 | goto out; | |
532 | } | |
a1c33bbe MT |
533 | if (!alloc_cpumask_var(&b->cpus, GFP_KERNEL)) { |
534 | kfree(b); | |
535 | err = -ENOMEM; | |
536 | goto out; | |
537 | } | |
89b831ef | 538 | |
cb491fca | 539 | b->kobj = kobject_create_and_add(name, &per_cpu(mce_dev, cpu).kobj); |
a521cf20 GKH |
540 | if (!b->kobj) |
541 | goto out_free; | |
542 | ||
95268664 | 543 | #ifndef CONFIG_SMP |
a1c33bbe | 544 | cpumask_setall(b->cpus); |
95268664 | 545 | #else |
7ad728f9 | 546 | cpumask_copy(b->cpus, cpu_core_mask(cpu)); |
95268664 | 547 | #endif |
95268664 | 548 | |
89b831ef | 549 | per_cpu(threshold_banks, cpu)[bank] = b; |
95268664 | 550 | |
a6b6a14e | 551 | err = local_allocate_threshold_blocks(cpu, bank); |
95268664 JS |
552 | if (err) |
553 | goto out_free; | |
554 | ||
a1c33bbe | 555 | for_each_cpu(i, b->cpus) { |
95268664 JS |
556 | if (i == cpu) |
557 | continue; | |
558 | ||
cb491fca | 559 | err = sysfs_create_link(&per_cpu(mce_dev, i).kobj, |
a521cf20 | 560 | b->kobj, name); |
95268664 JS |
561 | if (err) |
562 | goto out; | |
563 | ||
564 | per_cpu(threshold_banks, i)[bank] = b; | |
565 | } | |
566 | ||
567 | goto out; | |
568 | ||
569 | out_free: | |
570 | per_cpu(threshold_banks, cpu)[bank] = NULL; | |
a1c33bbe | 571 | free_cpumask_var(b->cpus); |
95268664 | 572 | kfree(b); |
2903ee85 | 573 | out: |
89b831ef JS |
574 | return err; |
575 | } | |
576 | ||
577 | /* create dir/files for all valid threshold banks */ | |
578 | static __cpuinit int threshold_create_device(unsigned int cpu) | |
579 | { | |
2903ee85 | 580 | unsigned int bank; |
89b831ef JS |
581 | int err = 0; |
582 | ||
89b831ef | 583 | for (bank = 0; bank < NR_BANKS; ++bank) { |
5a96f4a5 | 584 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
89b831ef JS |
585 | continue; |
586 | err = threshold_create_bank(cpu, bank); | |
587 | if (err) | |
588 | goto out; | |
589 | } | |
2903ee85 | 590 | out: |
89b831ef JS |
591 | return err; |
592 | } | |
593 | ||
89b831ef JS |
594 | /* |
595 | * let's be hotplug friendly. | |
596 | * in case of multiple core processors, the first core always takes ownership | |
597 | * of shared sysfs dir/files, and rest of the cores will be symlinked to it. | |
598 | */ | |
599 | ||
be6b5a35 | 600 | static void deallocate_threshold_block(unsigned int cpu, |
95268664 JS |
601 | unsigned int bank) |
602 | { | |
603 | struct threshold_block *pos = NULL; | |
604 | struct threshold_block *tmp = NULL; | |
605 | struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank]; | |
606 | ||
607 | if (!head) | |
608 | return; | |
609 | ||
610 | list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) { | |
38a382ae | 611 | kobject_put(&pos->kobj); |
95268664 JS |
612 | list_del(&pos->miscj); |
613 | kfree(pos); | |
614 | } | |
615 | ||
616 | kfree(per_cpu(threshold_banks, cpu)[bank]->blocks); | |
617 | per_cpu(threshold_banks, cpu)[bank]->blocks = NULL; | |
618 | } | |
619 | ||
be6b5a35 | 620 | static void threshold_remove_bank(unsigned int cpu, int bank) |
89b831ef JS |
621 | { |
622 | struct threshold_bank *b; | |
95268664 | 623 | char name[32]; |
1cb2a8e1 | 624 | int i = 0; |
89b831ef JS |
625 | |
626 | b = per_cpu(threshold_banks, cpu)[bank]; | |
627 | if (!b) | |
628 | return; | |
95268664 JS |
629 | if (!b->blocks) |
630 | goto free_out; | |
631 | ||
632 | sprintf(name, "threshold_bank%i", bank); | |
633 | ||
02316067 | 634 | #ifdef CONFIG_SMP |
95268664 JS |
635 | /* sibling symlink */ |
636 | if (shared_bank[bank] && b->blocks->cpu != cpu) { | |
cb491fca | 637 | sysfs_remove_link(&per_cpu(mce_dev, cpu).kobj, name); |
0d2caebd | 638 | per_cpu(threshold_banks, cpu)[bank] = NULL; |
1cb2a8e1 | 639 | |
95268664 | 640 | return; |
89b831ef | 641 | } |
02316067 | 642 | #endif |
95268664 JS |
643 | |
644 | /* remove all sibling symlinks before unregistering */ | |
a1c33bbe | 645 | for_each_cpu(i, b->cpus) { |
95268664 JS |
646 | if (i == cpu) |
647 | continue; | |
648 | ||
cb491fca | 649 | sysfs_remove_link(&per_cpu(mce_dev, i).kobj, name); |
95268664 JS |
650 | per_cpu(threshold_banks, i)[bank] = NULL; |
651 | } | |
652 | ||
653 | deallocate_threshold_block(cpu, bank); | |
654 | ||
655 | free_out: | |
8735728e | 656 | kobject_del(b->kobj); |
38a382ae | 657 | kobject_put(b->kobj); |
a1c33bbe | 658 | free_cpumask_var(b->cpus); |
95268664 JS |
659 | kfree(b); |
660 | per_cpu(threshold_banks, cpu)[bank] = NULL; | |
89b831ef JS |
661 | } |
662 | ||
be6b5a35 | 663 | static void threshold_remove_device(unsigned int cpu) |
89b831ef | 664 | { |
2903ee85 | 665 | unsigned int bank; |
89b831ef JS |
666 | |
667 | for (bank = 0; bank < NR_BANKS; ++bank) { | |
5a96f4a5 | 668 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
89b831ef JS |
669 | continue; |
670 | threshold_remove_bank(cpu, bank); | |
671 | } | |
89b831ef JS |
672 | } |
673 | ||
89b831ef | 674 | /* get notified when a cpu comes on/off */ |
1cb2a8e1 IM |
675 | static void __cpuinit |
676 | amd_64_threshold_cpu_callback(unsigned long action, unsigned int cpu) | |
89b831ef | 677 | { |
89b831ef | 678 | if (cpu >= NR_CPUS) |
8735728e | 679 | return; |
89b831ef JS |
680 | |
681 | switch (action) { | |
682 | case CPU_ONLINE: | |
8bb78442 | 683 | case CPU_ONLINE_FROZEN: |
89b831ef | 684 | threshold_create_device(cpu); |
89b831ef JS |
685 | break; |
686 | case CPU_DEAD: | |
8bb78442 | 687 | case CPU_DEAD_FROZEN: |
89b831ef JS |
688 | threshold_remove_device(cpu); |
689 | break; | |
690 | default: | |
691 | break; | |
692 | } | |
89b831ef JS |
693 | } |
694 | ||
89b831ef JS |
695 | static __init int threshold_init_device(void) |
696 | { | |
2903ee85 | 697 | unsigned lcpu = 0; |
89b831ef | 698 | |
89b831ef JS |
699 | /* to hit CPUs online before the notifier is up */ |
700 | for_each_online_cpu(lcpu) { | |
fff2e89f | 701 | int err = threshold_create_device(lcpu); |
1cb2a8e1 | 702 | |
89b831ef | 703 | if (err) |
fff2e89f | 704 | return err; |
89b831ef | 705 | } |
8735728e | 706 | threshold_cpu_callback = amd_64_threshold_cpu_callback; |
1cb2a8e1 | 707 | |
fff2e89f | 708 | return 0; |
89b831ef | 709 | } |
89b831ef | 710 | device_initcall(threshold_init_device); |