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Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 LT |
2 | /* |
3 | * P5 specific Machine Check Exception Reporting | |
87c6fe26 | 4 | * (C) Copyright 2002 Alan Cox <alan@lxorguk.ukuu.org.uk> |
1da177e4 | 5 | */ |
1da177e4 | 6 | #include <linux/interrupt.h> |
ed8bc7ed IM |
7 | #include <linux/kernel.h> |
8 | #include <linux/types.h> | |
1da177e4 LT |
9 | #include <linux/smp.h> |
10 | ||
15777205 | 11 | #include <asm/processor.h> |
95927475 | 12 | #include <asm/traps.h> |
375074cc | 13 | #include <asm/tlbflush.h> |
9e55e44e | 14 | #include <asm/mce.h> |
1da177e4 LT |
15 | #include <asm/msr.h> |
16 | ||
4efc0670 | 17 | /* By default disabled */ |
c6978369 | 18 | int mce_p5_enabled __read_mostly; |
4efc0670 | 19 | |
ed8bc7ed | 20 | /* Machine check handler for Pentium class Intel CPUs: */ |
15777205 | 21 | static void pentium_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 LT |
22 | { |
23 | u32 loaddr, hi, lotype; | |
ed8bc7ed | 24 | |
8c84014f | 25 | ist_enter(regs); |
95927475 | 26 | |
1da177e4 LT |
27 | rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi); |
28 | rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi); | |
ed8bc7ed | 29 | |
1b74dde7 CY |
30 | pr_emerg("CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n", |
31 | smp_processor_id(), loaddr, lotype); | |
ed8bc7ed IM |
32 | |
33 | if (lotype & (1<<5)) { | |
1b74dde7 CY |
34 | pr_emerg("CPU#%d: Possible thermal failure (CPU on fire ?).\n", |
35 | smp_processor_id()); | |
ed8bc7ed IM |
36 | } |
37 | ||
373d4d09 | 38 | add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); |
95927475 | 39 | |
8c84014f | 40 | ist_exit(regs); |
1da177e4 LT |
41 | } |
42 | ||
ed8bc7ed | 43 | /* Set up machine check reporting for processors with Intel style MCE: */ |
31ab269a | 44 | void intel_p5_mcheck_init(struct cpuinfo_x86 *c) |
1da177e4 LT |
45 | { |
46 | u32 l, h; | |
15777205 | 47 | |
c6978369 HS |
48 | /* Default P5 to off as its often misconnected: */ |
49 | if (!mce_p5_enabled) | |
15777205 | 50 | return; |
1da177e4 | 51 | |
c6978369 HS |
52 | /* Check for MCE support: */ |
53 | if (!cpu_has(c, X86_FEATURE_MCE)) | |
1da177e4 | 54 | return; |
ed8bc7ed | 55 | |
1da177e4 | 56 | machine_check_vector = pentium_machine_check; |
ed8bc7ed | 57 | /* Make sure the vector pointer is visible before we enable MCEs: */ |
1da177e4 LT |
58 | wmb(); |
59 | ||
ed8bc7ed | 60 | /* Read registers before enabling: */ |
1da177e4 LT |
61 | rdmsr(MSR_IA32_P5_MC_ADDR, l, h); |
62 | rdmsr(MSR_IA32_P5_MC_TYPE, l, h); | |
1b74dde7 | 63 | pr_info("Intel old style machine check architecture supported.\n"); |
1da177e4 | 64 | |
ed8bc7ed | 65 | /* Enable MCE: */ |
375074cc | 66 | cr4_set_bits(X86_CR4_MCE); |
1b74dde7 CY |
67 | pr_info("Intel old style machine check reporting enabled on CPU#%d.\n", |
68 | smp_processor_id()); | |
1da177e4 | 69 | } |