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Commit | Line | Data |
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15d5f839 | 1 | /* |
3222b36f DZ |
2 | * Thermal throttle event support code (such as syslog messaging and rate |
3 | * limiting) that was factored out from x86_64 (mce_intel.c) and i386 (p4.c). | |
cb6f3c15 | 4 | * |
3222b36f DZ |
5 | * This allows consistent reporting of CPU thermal throttle events. |
6 | * | |
7 | * Maintains a counter in /sys that keeps track of the number of thermal | |
8 | * events, such that the user knows how bad the thermal problem might be | |
9 | * (since the logging to syslog and mcelog is rate limited). | |
15d5f839 DZ |
10 | * |
11 | * Author: Dmitriy Zavin (dmitriyz@google.com) | |
12 | * | |
13 | * Credits: Adapted from Zwane Mwaikambo's original code in mce_intel.c. | |
3222b36f | 14 | * Inspired by Ross Biro's and Al Borchers' counter code. |
15d5f839 | 15 | */ |
a65c88dd | 16 | #include <linux/interrupt.h> |
cb6f3c15 IM |
17 | #include <linux/notifier.h> |
18 | #include <linux/jiffies.h> | |
895287c0 | 19 | #include <linux/kernel.h> |
15d5f839 | 20 | #include <linux/percpu.h> |
69c60c88 | 21 | #include <linux/export.h> |
895287c0 HS |
22 | #include <linux/types.h> |
23 | #include <linux/init.h> | |
24 | #include <linux/smp.h> | |
15d5f839 | 25 | #include <linux/cpu.h> |
cb6f3c15 | 26 | |
895287c0 | 27 | #include <asm/processor.h> |
895287c0 | 28 | #include <asm/apic.h> |
a65c88dd HS |
29 | #include <asm/idle.h> |
30 | #include <asm/mce.h> | |
895287c0 | 31 | #include <asm/msr.h> |
cf910e83 | 32 | #include <asm/trace/irq_vectors.h> |
15d5f839 DZ |
33 | |
34 | /* How long to wait between reporting thermal events */ | |
cb6f3c15 | 35 | #define CHECK_INTERVAL (300 * HZ) |
15d5f839 | 36 | |
0199114c FY |
37 | #define THERMAL_THROTTLING_EVENT 0 |
38 | #define POWER_LIMIT_EVENT 1 | |
39 | ||
39676840 | 40 | /* |
0199114c | 41 | * Current thermal event state: |
39676840 | 42 | */ |
55d435a2 | 43 | struct _thermal_state { |
0199114c FY |
44 | bool new_event; |
45 | int event; | |
39676840 | 46 | u64 next_check; |
0199114c FY |
47 | unsigned long count; |
48 | unsigned long last_count; | |
39676840 | 49 | }; |
cb6f3c15 | 50 | |
55d435a2 | 51 | struct thermal_state { |
0199114c FY |
52 | struct _thermal_state core_throttle; |
53 | struct _thermal_state core_power_limit; | |
54 | struct _thermal_state package_throttle; | |
55 | struct _thermal_state package_power_limit; | |
9e76a97e D |
56 | struct _thermal_state core_thresh0; |
57 | struct _thermal_state core_thresh1; | |
25cdce17 SP |
58 | struct _thermal_state pkg_thresh0; |
59 | struct _thermal_state pkg_thresh1; | |
55d435a2 FY |
60 | }; |
61 | ||
9e76a97e D |
62 | /* Callback to handle core threshold interrupts */ |
63 | int (*platform_thermal_notify)(__u64 msr_val); | |
f21bbec9 | 64 | EXPORT_SYMBOL(platform_thermal_notify); |
9e76a97e | 65 | |
25cdce17 SP |
66 | /* Callback to handle core package threshold_interrupts */ |
67 | int (*platform_thermal_package_notify)(__u64 msr_val); | |
68 | EXPORT_SYMBOL_GPL(platform_thermal_package_notify); | |
69 | ||
70 | /* Callback support of rate control, return true, if | |
71 | * callback has rate control */ | |
72 | bool (*platform_thermal_package_rate_control)(void); | |
73 | EXPORT_SYMBOL_GPL(platform_thermal_package_rate_control); | |
74 | ||
75 | ||
39676840 IM |
76 | static DEFINE_PER_CPU(struct thermal_state, thermal_state); |
77 | ||
78 | static atomic_t therm_throt_en = ATOMIC_INIT(0); | |
3222b36f | 79 | |
a2202aa2 YW |
80 | static u32 lvtthmr_init __read_mostly; |
81 | ||
3222b36f | 82 | #ifdef CONFIG_SYSFS |
8a25a2fd KS |
83 | #define define_therm_throt_device_one_ro(_name) \ |
84 | static DEVICE_ATTR(_name, 0444, \ | |
85 | therm_throt_device_show_##_name, \ | |
55d435a2 | 86 | NULL) \ |
cb6f3c15 | 87 | |
8a25a2fd | 88 | #define define_therm_throt_device_show_func(event, name) \ |
39676840 | 89 | \ |
8a25a2fd KS |
90 | static ssize_t therm_throt_device_show_##event##_##name( \ |
91 | struct device *dev, \ | |
92 | struct device_attribute *attr, \ | |
39676840 | 93 | char *buf) \ |
cb6f3c15 IM |
94 | { \ |
95 | unsigned int cpu = dev->id; \ | |
96 | ssize_t ret; \ | |
97 | \ | |
98 | preempt_disable(); /* CPU hotplug */ \ | |
55d435a2 | 99 | if (cpu_online(cpu)) { \ |
cb6f3c15 | 100 | ret = sprintf(buf, "%lu\n", \ |
0199114c | 101 | per_cpu(thermal_state, cpu).event.name); \ |
55d435a2 | 102 | } else \ |
cb6f3c15 IM |
103 | ret = 0; \ |
104 | preempt_enable(); \ | |
105 | \ | |
106 | return ret; \ | |
3222b36f DZ |
107 | } |
108 | ||
8a25a2fd KS |
109 | define_therm_throt_device_show_func(core_throttle, count); |
110 | define_therm_throt_device_one_ro(core_throttle_count); | |
55d435a2 | 111 | |
8a25a2fd KS |
112 | define_therm_throt_device_show_func(core_power_limit, count); |
113 | define_therm_throt_device_one_ro(core_power_limit_count); | |
0199114c | 114 | |
8a25a2fd KS |
115 | define_therm_throt_device_show_func(package_throttle, count); |
116 | define_therm_throt_device_one_ro(package_throttle_count); | |
3222b36f | 117 | |
8a25a2fd KS |
118 | define_therm_throt_device_show_func(package_power_limit, count); |
119 | define_therm_throt_device_one_ro(package_power_limit_count); | |
0199114c | 120 | |
3222b36f | 121 | static struct attribute *thermal_throttle_attrs[] = { |
8a25a2fd | 122 | &dev_attr_core_throttle_count.attr, |
3222b36f DZ |
123 | NULL |
124 | }; | |
125 | ||
0199114c | 126 | static struct attribute_group thermal_attr_group = { |
cb6f3c15 IM |
127 | .attrs = thermal_throttle_attrs, |
128 | .name = "thermal_throttle" | |
3222b36f DZ |
129 | }; |
130 | #endif /* CONFIG_SYSFS */ | |
15d5f839 | 131 | |
0199114c FY |
132 | #define CORE_LEVEL 0 |
133 | #define PACKAGE_LEVEL 1 | |
134 | ||
15d5f839 | 135 | /*** |
3222b36f | 136 | * therm_throt_process - Process thermal throttling event from interrupt |
15d5f839 DZ |
137 | * @curr: Whether the condition is current or not (boolean), since the |
138 | * thermal interrupt normally gets called both when the thermal | |
139 | * event begins and once the event has ended. | |
140 | * | |
3222b36f | 141 | * This function is called by the thermal interrupt after the |
15d5f839 DZ |
142 | * IRQ has been acknowledged. |
143 | * | |
144 | * It will take care of rate limiting and printing messages to the syslog. | |
145 | * | |
146 | * Returns: 0 : Event should NOT be further logged, i.e. still in | |
147 | * "timeout" from previous log message. | |
148 | * 1 : Event should be logged further, and a message has been | |
149 | * printed to the syslog. | |
150 | */ | |
0199114c | 151 | static int therm_throt_process(bool new_event, int event, int level) |
15d5f839 | 152 | { |
55d435a2 | 153 | struct _thermal_state *state; |
0199114c FY |
154 | unsigned int this_cpu = smp_processor_id(); |
155 | bool old_event; | |
39676840 | 156 | u64 now; |
0199114c | 157 | struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu); |
39676840 | 158 | |
39676840 | 159 | now = get_jiffies_64(); |
0199114c FY |
160 | if (level == CORE_LEVEL) { |
161 | if (event == THERMAL_THROTTLING_EVENT) | |
162 | state = &pstate->core_throttle; | |
163 | else if (event == POWER_LIMIT_EVENT) | |
164 | state = &pstate->core_power_limit; | |
165 | else | |
166 | return 0; | |
167 | } else if (level == PACKAGE_LEVEL) { | |
168 | if (event == THERMAL_THROTTLING_EVENT) | |
169 | state = &pstate->package_throttle; | |
170 | else if (event == POWER_LIMIT_EVENT) | |
171 | state = &pstate->package_power_limit; | |
172 | else | |
173 | return 0; | |
174 | } else | |
175 | return 0; | |
39676840 | 176 | |
0199114c FY |
177 | old_event = state->new_event; |
178 | state->new_event = new_event; | |
15d5f839 | 179 | |
0199114c FY |
180 | if (new_event) |
181 | state->count++; | |
3222b36f | 182 | |
b417c9fd | 183 | if (time_before64(now, state->next_check) && |
0199114c | 184 | state->count != state->last_count) |
15d5f839 DZ |
185 | return 0; |
186 | ||
39676840 | 187 | state->next_check = now + CHECK_INTERVAL; |
0199114c | 188 | state->last_count = state->count; |
15d5f839 DZ |
189 | |
190 | /* if we just entered the thermal event */ | |
0199114c FY |
191 | if (new_event) { |
192 | if (event == THERMAL_THROTTLING_EVENT) | |
1b74dde7 | 193 | pr_crit("CPU%d: %s temperature above threshold, cpu clock throttled (total events = %lu)\n", |
0199114c FY |
194 | this_cpu, |
195 | level == CORE_LEVEL ? "Core" : "Package", | |
196 | state->count); | |
4e5c25d4 HD |
197 | return 1; |
198 | } | |
0199114c FY |
199 | if (old_event) { |
200 | if (event == THERMAL_THROTTLING_EVENT) | |
1b74dde7 | 201 | pr_info("CPU%d: %s temperature/speed normal\n", this_cpu, |
0199114c | 202 | level == CORE_LEVEL ? "Core" : "Package"); |
4e5c25d4 | 203 | return 1; |
15d5f839 DZ |
204 | } |
205 | ||
4e5c25d4 | 206 | return 0; |
15d5f839 | 207 | } |
3222b36f | 208 | |
25cdce17 | 209 | static int thresh_event_valid(int level, int event) |
9e76a97e D |
210 | { |
211 | struct _thermal_state *state; | |
212 | unsigned int this_cpu = smp_processor_id(); | |
213 | struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu); | |
214 | u64 now = get_jiffies_64(); | |
215 | ||
25cdce17 SP |
216 | if (level == PACKAGE_LEVEL) |
217 | state = (event == 0) ? &pstate->pkg_thresh0 : | |
218 | &pstate->pkg_thresh1; | |
219 | else | |
220 | state = (event == 0) ? &pstate->core_thresh0 : | |
221 | &pstate->core_thresh1; | |
9e76a97e D |
222 | |
223 | if (time_before64(now, state->next_check)) | |
224 | return 0; | |
225 | ||
226 | state->next_check = now + CHECK_INTERVAL; | |
25cdce17 | 227 | |
9e76a97e D |
228 | return 1; |
229 | } | |
230 | ||
6bb2ff84 FY |
231 | static bool int_pln_enable; |
232 | static int __init int_pln_enable_setup(char *s) | |
233 | { | |
234 | int_pln_enable = true; | |
235 | ||
236 | return 1; | |
237 | } | |
238 | __setup("int_pln_enable", int_pln_enable_setup); | |
239 | ||
3222b36f | 240 | #ifdef CONFIG_SYSFS |
cb6f3c15 | 241 | /* Add/Remove thermal_throttle interface for CPU device: */ |
148f9bb8 | 242 | static int thermal_throttle_add_dev(struct device *dev, unsigned int cpu) |
3222b36f | 243 | { |
55d435a2 | 244 | int err; |
51e3c1b5 | 245 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
55d435a2 | 246 | |
8a25a2fd | 247 | err = sysfs_create_group(&dev->kobj, &thermal_attr_group); |
55d435a2 FY |
248 | if (err) |
249 | return err; | |
250 | ||
6bb2ff84 | 251 | if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable) |
8a25a2fd KS |
252 | err = sysfs_add_file_to_group(&dev->kobj, |
253 | &dev_attr_core_power_limit_count.attr, | |
0199114c | 254 | thermal_attr_group.name); |
b62be8ea | 255 | if (cpu_has(c, X86_FEATURE_PTS)) { |
8a25a2fd KS |
256 | err = sysfs_add_file_to_group(&dev->kobj, |
257 | &dev_attr_package_throttle_count.attr, | |
0199114c | 258 | thermal_attr_group.name); |
6bb2ff84 | 259 | if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable) |
8a25a2fd KS |
260 | err = sysfs_add_file_to_group(&dev->kobj, |
261 | &dev_attr_package_power_limit_count.attr, | |
0199114c | 262 | thermal_attr_group.name); |
b62be8ea | 263 | } |
55d435a2 FY |
264 | |
265 | return err; | |
3222b36f DZ |
266 | } |
267 | ||
148f9bb8 | 268 | static void thermal_throttle_remove_dev(struct device *dev) |
3222b36f | 269 | { |
8a25a2fd | 270 | sysfs_remove_group(&dev->kobj, &thermal_attr_group); |
3222b36f DZ |
271 | } |
272 | ||
3222b36f | 273 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
148f9bb8 | 274 | static int |
cb6f3c15 IM |
275 | thermal_throttle_cpu_callback(struct notifier_block *nfb, |
276 | unsigned long action, | |
277 | void *hcpu) | |
3222b36f DZ |
278 | { |
279 | unsigned int cpu = (unsigned long)hcpu; | |
8a25a2fd | 280 | struct device *dev; |
c7e38a9c | 281 | int err = 0; |
3222b36f | 282 | |
8a25a2fd | 283 | dev = get_cpu_device(cpu); |
cb6f3c15 | 284 | |
3222b36f | 285 | switch (action) { |
c7e38a9c AM |
286 | case CPU_UP_PREPARE: |
287 | case CPU_UP_PREPARE_FROZEN: | |
8a25a2fd | 288 | err = thermal_throttle_add_dev(dev, cpu); |
6569345a | 289 | WARN_ON(err); |
3222b36f | 290 | break; |
c7e38a9c AM |
291 | case CPU_UP_CANCELED: |
292 | case CPU_UP_CANCELED_FROZEN: | |
3222b36f | 293 | case CPU_DEAD: |
8bb78442 | 294 | case CPU_DEAD_FROZEN: |
8a25a2fd | 295 | thermal_throttle_remove_dev(dev); |
3222b36f DZ |
296 | break; |
297 | } | |
a94247e7 | 298 | return notifier_from_errno(err); |
3222b36f DZ |
299 | } |
300 | ||
148f9bb8 | 301 | static struct notifier_block thermal_throttle_cpu_notifier = |
3222b36f DZ |
302 | { |
303 | .notifier_call = thermal_throttle_cpu_callback, | |
304 | }; | |
3222b36f DZ |
305 | |
306 | static __init int thermal_throttle_init_device(void) | |
307 | { | |
308 | unsigned int cpu = 0; | |
6569345a | 309 | int err; |
3222b36f DZ |
310 | |
311 | if (!atomic_read(&therm_throt_en)) | |
312 | return 0; | |
313 | ||
4e6192bb | 314 | cpu_notifier_register_begin(); |
3222b36f | 315 | |
3222b36f | 316 | /* connect live CPUs to sysfs */ |
6569345a | 317 | for_each_online_cpu(cpu) { |
8a25a2fd | 318 | err = thermal_throttle_add_dev(get_cpu_device(cpu), cpu); |
6569345a SH |
319 | WARN_ON(err); |
320 | } | |
3222b36f | 321 | |
4e6192bb SB |
322 | __register_hotcpu_notifier(&thermal_throttle_cpu_notifier); |
323 | cpu_notifier_register_done(); | |
324 | ||
3222b36f DZ |
325 | return 0; |
326 | } | |
3222b36f | 327 | device_initcall(thermal_throttle_init_device); |
a65c88dd | 328 | |
3222b36f | 329 | #endif /* CONFIG_SYSFS */ |
a65c88dd | 330 | |
25cdce17 SP |
331 | static void notify_package_thresholds(__u64 msr_val) |
332 | { | |
333 | bool notify_thres_0 = false; | |
334 | bool notify_thres_1 = false; | |
335 | ||
336 | if (!platform_thermal_package_notify) | |
337 | return; | |
338 | ||
339 | /* lower threshold check */ | |
340 | if (msr_val & THERM_LOG_THRESHOLD0) | |
341 | notify_thres_0 = true; | |
342 | /* higher threshold check */ | |
343 | if (msr_val & THERM_LOG_THRESHOLD1) | |
344 | notify_thres_1 = true; | |
345 | ||
346 | if (!notify_thres_0 && !notify_thres_1) | |
347 | return; | |
348 | ||
349 | if (platform_thermal_package_rate_control && | |
350 | platform_thermal_package_rate_control()) { | |
351 | /* Rate control is implemented in callback */ | |
352 | platform_thermal_package_notify(msr_val); | |
353 | return; | |
354 | } | |
355 | ||
356 | /* lower threshold reached */ | |
357 | if (notify_thres_0 && thresh_event_valid(PACKAGE_LEVEL, 0)) | |
358 | platform_thermal_package_notify(msr_val); | |
359 | /* higher threshold reached */ | |
360 | if (notify_thres_1 && thresh_event_valid(PACKAGE_LEVEL, 1)) | |
361 | platform_thermal_package_notify(msr_val); | |
362 | } | |
363 | ||
9e76a97e D |
364 | static void notify_thresholds(__u64 msr_val) |
365 | { | |
366 | /* check whether the interrupt handler is defined; | |
367 | * otherwise simply return | |
368 | */ | |
369 | if (!platform_thermal_notify) | |
370 | return; | |
371 | ||
372 | /* lower threshold reached */ | |
25cdce17 SP |
373 | if ((msr_val & THERM_LOG_THRESHOLD0) && |
374 | thresh_event_valid(CORE_LEVEL, 0)) | |
9e76a97e D |
375 | platform_thermal_notify(msr_val); |
376 | /* higher threshold reached */ | |
25cdce17 SP |
377 | if ((msr_val & THERM_LOG_THRESHOLD1) && |
378 | thresh_event_valid(CORE_LEVEL, 1)) | |
9e76a97e D |
379 | platform_thermal_notify(msr_val); |
380 | } | |
381 | ||
a65c88dd | 382 | /* Thermal transition interrupt handler */ |
8363fc82 | 383 | static void intel_thermal_interrupt(void) |
a65c88dd HS |
384 | { |
385 | __u64 msr_val; | |
386 | ||
387 | rdmsrl(MSR_IA32_THERM_STATUS, msr_val); | |
0199114c | 388 | |
9e76a97e D |
389 | /* Check for violation of core thermal thresholds*/ |
390 | notify_thresholds(msr_val); | |
391 | ||
55d435a2 | 392 | if (therm_throt_process(msr_val & THERM_STATUS_PROCHOT, |
0199114c | 393 | THERMAL_THROTTLING_EVENT, |
55d435a2 | 394 | CORE_LEVEL) != 0) |
29e9bf18 | 395 | mce_log_therm_throt_event(msr_val); |
0199114c | 396 | |
6bb2ff84 | 397 | if (this_cpu_has(X86_FEATURE_PLN) && int_pln_enable) |
29e9bf18 | 398 | therm_throt_process(msr_val & THERM_STATUS_POWER_LIMIT, |
0199114c | 399 | POWER_LIMIT_EVENT, |
29e9bf18 | 400 | CORE_LEVEL); |
55d435a2 | 401 | |
fe504213 | 402 | if (this_cpu_has(X86_FEATURE_PTS)) { |
55d435a2 | 403 | rdmsrl(MSR_IA32_PACKAGE_THERM_STATUS, msr_val); |
25cdce17 SP |
404 | /* check violations of package thermal thresholds */ |
405 | notify_package_thresholds(msr_val); | |
29e9bf18 | 406 | therm_throt_process(msr_val & PACKAGE_THERM_STATUS_PROCHOT, |
0199114c | 407 | THERMAL_THROTTLING_EVENT, |
29e9bf18 | 408 | PACKAGE_LEVEL); |
6bb2ff84 | 409 | if (this_cpu_has(X86_FEATURE_PLN) && int_pln_enable) |
29e9bf18 | 410 | therm_throt_process(msr_val & |
0199114c FY |
411 | PACKAGE_THERM_STATUS_POWER_LIMIT, |
412 | POWER_LIMIT_EVENT, | |
29e9bf18 | 413 | PACKAGE_LEVEL); |
55d435a2 | 414 | } |
a65c88dd HS |
415 | } |
416 | ||
417 | static void unexpected_thermal_interrupt(void) | |
418 | { | |
1b74dde7 CY |
419 | pr_err("CPU%d: Unexpected LVT thermal interrupt!\n", |
420 | smp_processor_id()); | |
a65c88dd HS |
421 | } |
422 | ||
423 | static void (*smp_thermal_vector)(void) = unexpected_thermal_interrupt; | |
424 | ||
eddc0e92 | 425 | static inline void __smp_thermal_interrupt(void) |
a65c88dd | 426 | { |
a65c88dd HS |
427 | inc_irq_stat(irq_thermal_count); |
428 | smp_thermal_vector(); | |
eddc0e92 SA |
429 | } |
430 | ||
2605fc21 | 431 | asmlinkage __visible void smp_thermal_interrupt(struct pt_regs *regs) |
eddc0e92 SA |
432 | { |
433 | entering_irq(); | |
434 | __smp_thermal_interrupt(); | |
435 | exiting_ack_irq(); | |
a65c88dd HS |
436 | } |
437 | ||
2605fc21 | 438 | asmlinkage __visible void smp_trace_thermal_interrupt(struct pt_regs *regs) |
cf910e83 SA |
439 | { |
440 | entering_irq(); | |
441 | trace_thermal_apic_entry(THERMAL_APIC_VECTOR); | |
442 | __smp_thermal_interrupt(); | |
443 | trace_thermal_apic_exit(THERMAL_APIC_VECTOR); | |
444 | exiting_ack_irq(); | |
445 | } | |
446 | ||
70fe4407 HS |
447 | /* Thermal monitoring depends on APIC, ACPI and clock modulation */ |
448 | static int intel_thermal_supported(struct cpuinfo_x86 *c) | |
449 | { | |
450 | if (!cpu_has_apic) | |
451 | return 0; | |
452 | if (!cpu_has(c, X86_FEATURE_ACPI) || !cpu_has(c, X86_FEATURE_ACC)) | |
453 | return 0; | |
454 | return 1; | |
455 | } | |
456 | ||
ce6b5d76 | 457 | void __init mcheck_intel_therm_init(void) |
a2202aa2 YW |
458 | { |
459 | /* | |
460 | * This function is only called on boot CPU. Save the init thermal | |
461 | * LVT value on BSP and use that value to restore APs' thermal LVT | |
462 | * entry BIOS programmed later | |
463 | */ | |
70fe4407 | 464 | if (intel_thermal_supported(&boot_cpu_data)) |
a2202aa2 YW |
465 | lvtthmr_init = apic_read(APIC_LVTTHMR); |
466 | } | |
467 | ||
cffd377e | 468 | void intel_init_thermal(struct cpuinfo_x86 *c) |
895287c0 HS |
469 | { |
470 | unsigned int cpu = smp_processor_id(); | |
471 | int tm2 = 0; | |
472 | u32 l, h; | |
473 | ||
70fe4407 | 474 | if (!intel_thermal_supported(c)) |
895287c0 HS |
475 | return; |
476 | ||
477 | /* | |
478 | * First check if its enabled already, in which case there might | |
479 | * be some SMM goo which handles it, so we can't even put a handler | |
480 | * since it might be delivered via SMI already: | |
481 | */ | |
482 | rdmsr(MSR_IA32_MISC_ENABLE, l, h); | |
a2202aa2 | 483 | |
e503f9e4 | 484 | h = lvtthmr_init; |
a2202aa2 YW |
485 | /* |
486 | * The initial value of thermal LVT entries on all APs always reads | |
487 | * 0x10000 because APs are woken up by BSP issuing INIT-SIPI-SIPI | |
488 | * sequence to them and LVT registers are reset to 0s except for | |
489 | * the mask bits which are set to 1s when APs receive INIT IPI. | |
e503f9e4 YS |
490 | * If BIOS takes over the thermal interrupt and sets its interrupt |
491 | * delivery mode to SMI (not fixed), it restores the value that the | |
492 | * BIOS has programmed on AP based on BSP's info we saved since BIOS | |
493 | * is always setting the same value for all threads/cores. | |
a2202aa2 | 494 | */ |
e503f9e4 YS |
495 | if ((h & APIC_DM_FIXED_MASK) != APIC_DM_FIXED) |
496 | apic_write(APIC_LVTTHMR, lvtthmr_init); | |
a2202aa2 | 497 | |
a2202aa2 | 498 | |
895287c0 | 499 | if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) { |
d286c3af | 500 | if (system_state == SYSTEM_BOOTING) |
1b74dde7 | 501 | pr_debug("CPU%d: Thermal monitoring handled by SMI\n", cpu); |
895287c0 HS |
502 | return; |
503 | } | |
504 | ||
f3a0867b BZ |
505 | /* early Pentium M models use different method for enabling TM2 */ |
506 | if (cpu_has(c, X86_FEATURE_TM2)) { | |
507 | if (c->x86 == 6 && (c->x86_model == 9 || c->x86_model == 13)) { | |
508 | rdmsr(MSR_THERM2_CTL, l, h); | |
509 | if (l & MSR_THERM2_CTL_TM_SELECT) | |
510 | tm2 = 1; | |
511 | } else if (l & MSR_IA32_MISC_ENABLE_TM2) | |
512 | tm2 = 1; | |
513 | } | |
514 | ||
895287c0 HS |
515 | /* We'll mask the thermal vector in the lapic till we're ready: */ |
516 | h = THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED; | |
517 | apic_write(APIC_LVTTHMR, h); | |
518 | ||
519 | rdmsr(MSR_IA32_THERM_INTERRUPT, l, h); | |
6bb2ff84 | 520 | if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable) |
0199114c | 521 | wrmsr(MSR_IA32_THERM_INTERRUPT, |
6bb2ff84 FY |
522 | (l | (THERM_INT_LOW_ENABLE |
523 | | THERM_INT_HIGH_ENABLE)) & ~THERM_INT_PLN_ENABLE, h); | |
524 | else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable) | |
0199114c | 525 | wrmsr(MSR_IA32_THERM_INTERRUPT, |
6bb2ff84 | 526 | l | (THERM_INT_LOW_ENABLE |
0199114c FY |
527 | | THERM_INT_HIGH_ENABLE | THERM_INT_PLN_ENABLE), h); |
528 | else | |
529 | wrmsr(MSR_IA32_THERM_INTERRUPT, | |
530 | l | (THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE), h); | |
895287c0 | 531 | |
55d435a2 FY |
532 | if (cpu_has(c, X86_FEATURE_PTS)) { |
533 | rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); | |
6bb2ff84 | 534 | if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable) |
0199114c | 535 | wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, |
6bb2ff84 FY |
536 | (l | (PACKAGE_THERM_INT_LOW_ENABLE |
537 | | PACKAGE_THERM_INT_HIGH_ENABLE)) | |
538 | & ~PACKAGE_THERM_INT_PLN_ENABLE, h); | |
539 | else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable) | |
540 | wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, | |
541 | l | (PACKAGE_THERM_INT_LOW_ENABLE | |
0199114c FY |
542 | | PACKAGE_THERM_INT_HIGH_ENABLE |
543 | | PACKAGE_THERM_INT_PLN_ENABLE), h); | |
544 | else | |
545 | wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, | |
546 | l | (PACKAGE_THERM_INT_LOW_ENABLE | |
547 | | PACKAGE_THERM_INT_HIGH_ENABLE), h); | |
55d435a2 FY |
548 | } |
549 | ||
8363fc82 | 550 | smp_thermal_vector = intel_thermal_interrupt; |
895287c0 HS |
551 | |
552 | rdmsr(MSR_IA32_MISC_ENABLE, l, h); | |
553 | wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h); | |
554 | ||
555 | /* Unmask the thermal vector: */ | |
556 | l = apic_read(APIC_LVTTHMR); | |
557 | apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED); | |
558 | ||
1b74dde7 CY |
559 | pr_info_once("CPU0: Thermal monitoring enabled (%s)\n", |
560 | tm2 ? "TM2" : "TM1"); | |
895287c0 HS |
561 | |
562 | /* enable thermal throttle processing */ | |
563 | atomic_set(&therm_throt_en, 1); | |
564 | } |