[mirror_ubuntu-artful-kernel.git] / arch / x86 / kernel / cpu / mcheck / therm_throt.c

/*
 * Thermal throttle event support code (such as syslog messaging and rate
 * limiting) that was factored out from x86_64 (mce_intel.c) and i386 (p4.c).
 *
 * This allows consistent reporting of CPU thermal throttle events.
 *
 * Maintains a counter in /sys that keeps track of the number of thermal
 * events, such that the user knows how bad the thermal problem might be
 * (since the logging to syslog is rate limited).
 *
 * Author: Dmitriy Zavin (dmitriyz@google.com)
 *
 * Credits: Adapted from Zwane Mwaikambo's original code in mce_intel.c.
 *          Inspired by Ross Biro's and Al Borchers' counter code.
 */
#include <linux/interrupt.h>
#include <linux/notifier.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/percpu.h>
#include <linux/export.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/cpu.h>

#include <asm/processor.h>
#include <asm/apic.h>
#include <asm/mce.h>
#include <asm/msr.h>
#include <asm/trace/irq_vectors.h>

/* How long to wait between reporting thermal events */
#define CHECK_INTERVAL		(300 * HZ)

#define THERMAL_THROTTLING_EVENT	0
#define POWER_LIMIT_EVENT		1

/*
 * Current thermal event state:
 */
struct _thermal_state {
	bool			new_event;
	int			event;
	u64			next_check;
	unsigned long		count;
	unsigned long		last_count;
};

struct thermal_state {
	struct _thermal_state core_throttle;
	struct _thermal_state core_power_limit;
	struct _thermal_state package_throttle;
	struct _thermal_state package_power_limit;
	struct _thermal_state core_thresh0;
	struct _thermal_state core_thresh1;
	struct _thermal_state pkg_thresh0;
	struct _thermal_state pkg_thresh1;
};

/* Callback to handle core threshold interrupts */
int (*platform_thermal_notify)(__u64 msr_val);
EXPORT_SYMBOL(platform_thermal_notify);

/* Callback to handle core package threshold_interrupts */
int (*platform_thermal_package_notify)(__u64 msr_val);
EXPORT_SYMBOL_GPL(platform_thermal_package_notify);

/* Callback support of rate control, return true, if
 * callback has rate control */
bool (*platform_thermal_package_rate_control)(void);
EXPORT_SYMBOL_GPL(platform_thermal_package_rate_control);


static DEFINE_PER_CPU(struct thermal_state, thermal_state);

static atomic_t therm_throt_en	= ATOMIC_INIT(0);

static u32 lvtthmr_init __read_mostly;

#ifdef CONFIG_SYSFS
#define define_therm_throt_device_one_ro(_name)				\
	static DEVICE_ATTR(_name, 0444,					\
			   therm_throt_device_show_##_name,		\
				   NULL)				\

#define define_therm_throt_device_show_func(event, name)		\
									\
static ssize_t therm_throt_device_show_##event##_##name(		\
			struct device *dev,				\
			struct device_attribute *attr,			\
			char *buf)					\
{									\
	unsigned int cpu = dev->id;					\
	ssize_t ret;							\
									\
	preempt_disable();	/* CPU hotplug */			\
	if (cpu_online(cpu)) {						\
		ret = sprintf(buf, "%lu\n",				\
			      per_cpu(thermal_state, cpu).event.name);	\
	} else								\
		ret = 0;						\
	preempt_enable();						\
									\
	return ret;							\
}

define_therm_throt_device_show_func(core_throttle, count);
define_therm_throt_device_one_ro(core_throttle_count);

define_therm_throt_device_show_func(core_power_limit, count);
define_therm_throt_device_one_ro(core_power_limit_count);

define_therm_throt_device_show_func(package_throttle, count);
define_therm_throt_device_one_ro(package_throttle_count);

define_therm_throt_device_show_func(package_power_limit, count);
define_therm_throt_device_one_ro(package_power_limit_count);

static struct attribute *thermal_throttle_attrs[] = {
	&dev_attr_core_throttle_count.attr,
	NULL
};

static const struct attribute_group thermal_attr_group = {
	.attrs	= thermal_throttle_attrs,
	.name	= "thermal_throttle"
};
#endif /* CONFIG_SYSFS */

#define CORE_LEVEL	0
#define PACKAGE_LEVEL	1

/***
 * therm_throt_process - Process thermal throttling event from interrupt
 * @curr: Whether the condition is current or not (boolean), since the
 *        thermal interrupt normally gets called both when the thermal
 *        event begins and once the event has ended.
 *
 * This function is called by the thermal interrupt after the
 * IRQ has been acknowledged.
 *
 * It will take care of rate limiting and printing messages to the syslog.
 */
static void therm_throt_process(bool new_event, int event, int level)
{
	struct _thermal_state *state;
	unsigned int this_cpu = smp_processor_id();
	bool old_event;
	u64 now;
	struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu);

	now = get_jiffies_64();
	if (level == CORE_LEVEL) {
		if (event == THERMAL_THROTTLING_EVENT)
			state = &pstate->core_throttle;
		else if (event == POWER_LIMIT_EVENT)
			state = &pstate->core_power_limit;
		else
			return;
	} else if (level == PACKAGE_LEVEL) {
		if (event == THERMAL_THROTTLING_EVENT)
			state = &pstate->package_throttle;
		else if (event == POWER_LIMIT_EVENT)
			state = &pstate->package_power_limit;
		else
			return;
	} else
		return;

	old_event = state->new_event;
	state->new_event = new_event;

	if (new_event)
		state->count++;

	if (time_before64(now, state->next_check) &&
			state->count != state->last_count)
		return;

	state->next_check = now + CHECK_INTERVAL;
	state->last_count = state->count;

	/* if we just entered the thermal event */
	if (new_event) {
		if (event == THERMAL_THROTTLING_EVENT)
			pr_crit("CPU%d: %s temperature above threshold, cpu clock throttled (total events = %lu)\n",
				this_cpu,
				level == CORE_LEVEL ? "Core" : "Package",
				state->count);
		return;
	}
	if (old_event) {
		if (event == THERMAL_THROTTLING_EVENT)
			pr_info("CPU%d: %s temperature/speed normal\n", this_cpu,
				level == CORE_LEVEL ? "Core" : "Package");
		return;
	}
}

static int thresh_event_valid(int level, int event)
{
	struct _thermal_state *state;
	unsigned int this_cpu = smp_processor_id();
	struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu);
	u64 now = get_jiffies_64();

	if (level == PACKAGE_LEVEL)
		state = (event == 0) ? &pstate->pkg_thresh0 :
						&pstate->pkg_thresh1;
	else
		state = (event == 0) ? &pstate->core_thresh0 :
						&pstate->core_thresh1;

	if (time_before64(now, state->next_check))
		return 0;

	state->next_check = now + CHECK_INTERVAL;

	return 1;
}

static bool int_pln_enable;
static int __init int_pln_enable_setup(char *s)
{
	int_pln_enable = true;

	return 1;
}
__setup("int_pln_enable", int_pln_enable_setup);

#ifdef CONFIG_SYSFS
/* Add/Remove thermal_throttle interface for CPU device: */
static int thermal_throttle_add_dev(struct device *dev, unsigned int cpu)
{
	int err;
	struct cpuinfo_x86 *c = &cpu_data(cpu);

	err = sysfs_create_group(&dev->kobj, &thermal_attr_group);
	if (err)
		return err;

	if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
		err = sysfs_add_file_to_group(&dev->kobj,
					      &dev_attr_core_power_limit_count.attr,
					      thermal_attr_group.name);
	if (cpu_has(c, X86_FEATURE_PTS)) {
		err = sysfs_add_file_to_group(&dev->kobj,
					      &dev_attr_package_throttle_count.attr,
					      thermal_attr_group.name);
		if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
			err = sysfs_add_file_to_group(&dev->kobj,
					&dev_attr_package_power_limit_count.attr,
					thermal_attr_group.name);
	}

	return err;
}

static void thermal_throttle_remove_dev(struct device *dev)
{
	sysfs_remove_group(&dev->kobj, &thermal_attr_group);
}

/* Get notified when a cpu comes on/off. Be hotplug friendly. */
static int thermal_throttle_online(unsigned int cpu)
{
	struct device *dev = get_cpu_device(cpu);

	return thermal_throttle_add_dev(dev, cpu);
}

static int thermal_throttle_offline(unsigned int cpu)
{
	struct device *dev = get_cpu_device(cpu);

	thermal_throttle_remove_dev(dev);
	return 0;
}

static __init int thermal_throttle_init_device(void)
{
	int ret;

	if (!atomic_read(&therm_throt_en))
		return 0;

	ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/therm:online",
				thermal_throttle_online,
				thermal_throttle_offline);
	return ret < 0 ? ret : 0;
}
device_initcall(thermal_throttle_init_device);

#endif /* CONFIG_SYSFS */

static void notify_package_thresholds(__u64 msr_val)
{
	bool notify_thres_0 = false;
	bool notify_thres_1 = false;

	if (!platform_thermal_package_notify)
		return;

	/* lower threshold check */
	if (msr_val & THERM_LOG_THRESHOLD0)
		notify_thres_0 = true;
	/* higher threshold check */
	if (msr_val & THERM_LOG_THRESHOLD1)
		notify_thres_1 = true;

	if (!notify_thres_0 && !notify_thres_1)
		return;

	if (platform_thermal_package_rate_control &&
		platform_thermal_package_rate_control()) {
		/* Rate control is implemented in callback */
		platform_thermal_package_notify(msr_val);
		return;
	}

	/* lower threshold reached */
	if (notify_thres_0 && thresh_event_valid(PACKAGE_LEVEL, 0))
		platform_thermal_package_notify(msr_val);
	/* higher threshold reached */
	if (notify_thres_1 && thresh_event_valid(PACKAGE_LEVEL, 1))
		platform_thermal_package_notify(msr_val);
}

static void notify_thresholds(__u64 msr_val)
{
	/* check whether the interrupt handler is defined;
	 * otherwise simply return
	 */
	if (!platform_thermal_notify)
		return;

	/* lower threshold reached */
	if ((msr_val & THERM_LOG_THRESHOLD0) &&
			thresh_event_valid(CORE_LEVEL, 0))
		platform_thermal_notify(msr_val);
	/* higher threshold reached */
	if ((msr_val & THERM_LOG_THRESHOLD1) &&
			thresh_event_valid(CORE_LEVEL, 1))
		platform_thermal_notify(msr_val);
}

/* Thermal transition interrupt handler */
static void intel_thermal_interrupt(void)
{
	__u64 msr_val;

	if (static_cpu_has(X86_FEATURE_HWP))
		wrmsrl_safe(MSR_HWP_STATUS, 0);

	rdmsrl(MSR_IA32_THERM_STATUS, msr_val);

	/* Check for violation of core thermal thresholds*/
	notify_thresholds(msr_val);

	therm_throt_process(msr_val & THERM_STATUS_PROCHOT,
			    THERMAL_THROTTLING_EVENT,
			    CORE_LEVEL);

	if (this_cpu_has(X86_FEATURE_PLN) && int_pln_enable)
		therm_throt_process(msr_val & THERM_STATUS_POWER_LIMIT,
					POWER_LIMIT_EVENT,
					CORE_LEVEL);

	if (this_cpu_has(X86_FEATURE_PTS)) {
		rdmsrl(MSR_IA32_PACKAGE_THERM_STATUS, msr_val);
		/* check violations of package thermal thresholds */
		notify_package_thresholds(msr_val);
		therm_throt_process(msr_val & PACKAGE_THERM_STATUS_PROCHOT,
					THERMAL_THROTTLING_EVENT,
					PACKAGE_LEVEL);
		if (this_cpu_has(X86_FEATURE_PLN) && int_pln_enable)
			therm_throt_process(msr_val &
					PACKAGE_THERM_STATUS_POWER_LIMIT,
					POWER_LIMIT_EVENT,
					PACKAGE_LEVEL);
	}
}

static void unexpected_thermal_interrupt(void)
{
	pr_err("CPU%d: Unexpected LVT thermal interrupt!\n",
		smp_processor_id());
}

static void (*smp_thermal_vector)(void) = unexpected_thermal_interrupt;

static inline void __smp_thermal_interrupt(void)
{
	inc_irq_stat(irq_thermal_count);
	smp_thermal_vector();
}

asmlinkage __visible void __irq_entry
smp_thermal_interrupt(struct pt_regs *regs)
{
	entering_irq();
	__smp_thermal_interrupt();
	exiting_ack_irq();
}

asmlinkage __visible void __irq_entry
smp_trace_thermal_interrupt(struct pt_regs *regs)
{
	entering_irq();
	trace_thermal_apic_entry(THERMAL_APIC_VECTOR);
	__smp_thermal_interrupt();
	trace_thermal_apic_exit(THERMAL_APIC_VECTOR);
	exiting_ack_irq();
}

/* Thermal monitoring depends on APIC, ACPI and clock modulation */
static int intel_thermal_supported(struct cpuinfo_x86 *c)
{
	if (!boot_cpu_has(X86_FEATURE_APIC))
		return 0;
	if (!cpu_has(c, X86_FEATURE_ACPI) || !cpu_has(c, X86_FEATURE_ACC))
		return 0;
	return 1;
}

void __init mcheck_intel_therm_init(void)
{
	/*
	 * This function is only called on boot CPU. Save the init thermal
	 * LVT value on BSP and use that value to restore APs' thermal LVT
	 * entry BIOS programmed later
	 */
	if (intel_thermal_supported(&boot_cpu_data))
		lvtthmr_init = apic_read(APIC_LVTTHMR);
}

void intel_init_thermal(struct cpuinfo_x86 *c)
{
	unsigned int cpu = smp_processor_id();
	int tm2 = 0;
	u32 l, h;

	if (!intel_thermal_supported(c))
		return;

	/*
	 * First check if its enabled already, in which case there might
	 * be some SMM goo which handles it, so we can't even put a handler
	 * since it might be delivered via SMI already:
	 */
	rdmsr(MSR_IA32_MISC_ENABLE, l, h);

	h = lvtthmr_init;
	/*
	 * The initial value of thermal LVT entries on all APs always reads
	 * 0x10000 because APs are woken up by BSP issuing INIT-SIPI-SIPI
	 * sequence to them and LVT registers are reset to 0s except for
	 * the mask bits which are set to 1s when APs receive INIT IPI.
	 * If BIOS takes over the thermal interrupt and sets its interrupt
	 * delivery mode to SMI (not fixed), it restores the value that the
	 * BIOS has programmed on AP based on BSP's info we saved since BIOS
	 * is always setting the same value for all threads/cores.
	 */
	if ((h & APIC_DM_FIXED_MASK) != APIC_DM_FIXED)
		apic_write(APIC_LVTTHMR, lvtthmr_init);


	if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {
		if (system_state == SYSTEM_BOOTING)
			pr_debug("CPU%d: Thermal monitoring handled by SMI\n", cpu);
		return;
	}

	/* early Pentium M models use different method for enabling TM2 */
	if (cpu_has(c, X86_FEATURE_TM2)) {
		if (c->x86 == 6 && (c->x86_model == 9 || c->x86_model == 13)) {
			rdmsr(MSR_THERM2_CTL, l, h);
			if (l & MSR_THERM2_CTL_TM_SELECT)
				tm2 = 1;
		} else if (l & MSR_IA32_MISC_ENABLE_TM2)
			tm2 = 1;
	}

	/* We'll mask the thermal vector in the lapic till we're ready: */
	h = THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED;
	apic_write(APIC_LVTTHMR, h);

	rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
	if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable)
		wrmsr(MSR_IA32_THERM_INTERRUPT,
			(l | (THERM_INT_LOW_ENABLE
			| THERM_INT_HIGH_ENABLE)) & ~THERM_INT_PLN_ENABLE, h);
	else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
		wrmsr(MSR_IA32_THERM_INTERRUPT,
			l | (THERM_INT_LOW_ENABLE
			| THERM_INT_HIGH_ENABLE | THERM_INT_PLN_ENABLE), h);
	else
		wrmsr(MSR_IA32_THERM_INTERRUPT,
		      l | (THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE), h);

	if (cpu_has(c, X86_FEATURE_PTS)) {
		rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
		if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable)
			wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
				(l | (PACKAGE_THERM_INT_LOW_ENABLE
				| PACKAGE_THERM_INT_HIGH_ENABLE))
				& ~PACKAGE_THERM_INT_PLN_ENABLE, h);
		else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
			wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
				l | (PACKAGE_THERM_INT_LOW_ENABLE
				| PACKAGE_THERM_INT_HIGH_ENABLE
				| PACKAGE_THERM_INT_PLN_ENABLE), h);
		else
			wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
			      l | (PACKAGE_THERM_INT_LOW_ENABLE
				| PACKAGE_THERM_INT_HIGH_ENABLE), h);
	}

	smp_thermal_vector = intel_thermal_interrupt;

	rdmsr(MSR_IA32_MISC_ENABLE, l, h);
	wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);

	/* Unmask the thermal vector: */
	l = apic_read(APIC_LVTTHMR);
	apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);

	pr_info_once("CPU0: Thermal monitoring enabled (%s)\n",
		      tm2 ? "TM2" : "TM1");

	/* enable thermal throttle processing */
	atomic_set(&therm_throt_en, 1);
}
Commit	Line	Data
15d5f839	1	/*
3222b36f DZ	2	* Thermal throttle event support code (such as syslog messaging and rate
3222b36f DZ	3	* limiting) that was factored out from x86_64 (mce_intel.c) and i386 (p4.c).
cb6f3c15	4	*
3222b36f DZ	5	* This allows consistent reporting of CPU thermal throttle events.
	6	*
	7	* Maintains a counter in /sys that keeps track of the number of thermal
	8	* events, such that the user knows how bad the thermal problem might be
9b052ea4	9	* (since the logging to syslog is rate limited).
15d5f839 DZ	10	*
	11	* Author: Dmitriy Zavin (dmitriyz@google.com)
	12	*
	13	* Credits: Adapted from Zwane Mwaikambo's original code in mce_intel.c.
3222b36f	14	* Inspired by Ross Biro's and Al Borchers' counter code.
15d5f839	15	*/
a65c88dd	16	#include <linux/interrupt.h>
cb6f3c15 IM	17	#include <linux/notifier.h>
cb6f3c15 IM	18	#include <linux/jiffies.h>
895287c0	19	#include <linux/kernel.h>
15d5f839	20	#include <linux/percpu.h>
69c60c88	21	#include <linux/export.h>
895287c0 HS	22	#include <linux/types.h>
	23	#include <linux/init.h>
	24	#include <linux/smp.h>
15d5f839	25	#include <linux/cpu.h>
cb6f3c15	26
895287c0	27	#include <asm/processor.h>
895287c0	28	#include <asm/apic.h>
a65c88dd	29	#include <asm/mce.h>
895287c0	30	#include <asm/msr.h>
cf910e83	31	#include <asm/trace/irq_vectors.h>
15d5f839 DZ	32
15d5f839 DZ	33	/* How long to wait between reporting thermal events */
cb6f3c15	34	#define CHECK_INTERVAL (300 * HZ)
15d5f839	35
0199114c FY	36	#define THERMAL_THROTTLING_EVENT 0
	37	#define POWER_LIMIT_EVENT 1
	38
39676840	39	/*
0199114c	40	* Current thermal event state:
39676840	41	*/
55d435a2	42	struct _thermal_state {
0199114c FY	43	bool new_event;
0199114c FY	44	int event;
39676840	45	u64 next_check;
0199114c FY	46	unsigned long count;
0199114c FY	47	unsigned long last_count;
39676840	48	};
cb6f3c15	49
55d435a2	50	struct thermal_state {
0199114c FY	51	struct _thermal_state core_throttle;
	52	struct _thermal_state core_power_limit;
	53	struct _thermal_state package_throttle;
	54	struct _thermal_state package_power_limit;
9e76a97e D	55	struct _thermal_state core_thresh0;
9e76a97e D	56	struct _thermal_state core_thresh1;
25cdce17 SP	57	struct _thermal_state pkg_thresh0;
25cdce17 SP	58	struct _thermal_state pkg_thresh1;
55d435a2 FY	59	};
55d435a2 FY	60
9e76a97e D	61	/* Callback to handle core threshold interrupts */
9e76a97e D	62	int (*platform_thermal_notify)(__u64 msr_val);
f21bbec9	63	EXPORT_SYMBOL(platform_thermal_notify);
9e76a97e	64
25cdce17 SP	65	/* Callback to handle core package threshold_interrupts */
	66	int (*platform_thermal_package_notify)(__u64 msr_val);
	67	EXPORT_SYMBOL_GPL(platform_thermal_package_notify);
	68
	69	/* Callback support of rate control, return true, if
	70	* callback has rate control */
	71	bool (*platform_thermal_package_rate_control)(void);
	72	EXPORT_SYMBOL_GPL(platform_thermal_package_rate_control);
	73
	74
39676840 IM	75	static DEFINE_PER_CPU(struct thermal_state, thermal_state);
	76
	77	static atomic_t therm_throt_en = ATOMIC_INIT(0);
3222b36f	78
a2202aa2 YW	79	static u32 lvtthmr_init __read_mostly;
a2202aa2 YW	80
3222b36f	81	#ifdef CONFIG_SYSFS
8a25a2fd KS	82	#define define_therm_throt_device_one_ro(_name) \
	83	static DEVICE_ATTR(_name, 0444, \
	84	therm_throt_device_show_##_name, \
55d435a2	85	NULL) \
cb6f3c15	86
8a25a2fd	87	#define define_therm_throt_device_show_func(event, name) \
39676840	88	\
8a25a2fd KS	89	static ssize_t therm_throt_device_show_##event##_##name( \
	90	struct device *dev, \
	91	struct device_attribute *attr, \
39676840	92	char *buf) \
cb6f3c15 IM	93	{ \
	94	unsigned int cpu = dev->id; \
	95	ssize_t ret; \
	96	\
	97	preempt_disable(); /* CPU hotplug */ \
55d435a2	98	if (cpu_online(cpu)) { \
cb6f3c15	99	ret = sprintf(buf, "%lu\n", \
0199114c	100	per_cpu(thermal_state, cpu).event.name); \
55d435a2	101	} else \
cb6f3c15 IM	102	ret = 0; \
	103	preempt_enable(); \
	104	\
	105	return ret; \
3222b36f DZ	106	}
3222b36f DZ	107
8a25a2fd KS	108	define_therm_throt_device_show_func(core_throttle, count);
8a25a2fd KS	109	define_therm_throt_device_one_ro(core_throttle_count);
55d435a2	110
8a25a2fd KS	111	define_therm_throt_device_show_func(core_power_limit, count);
8a25a2fd KS	112	define_therm_throt_device_one_ro(core_power_limit_count);
0199114c	113
8a25a2fd KS	114	define_therm_throt_device_show_func(package_throttle, count);
8a25a2fd KS	115	define_therm_throt_device_one_ro(package_throttle_count);
3222b36f	116
8a25a2fd KS	117	define_therm_throt_device_show_func(package_power_limit, count);
8a25a2fd KS	118	define_therm_throt_device_one_ro(package_power_limit_count);
0199114c	119
3222b36f	120	static struct attribute *thermal_throttle_attrs[] = {
8a25a2fd	121	&dev_attr_core_throttle_count.attr,
3222b36f DZ	122	NULL
	123	};
	124
45bd07ad	125	static const struct attribute_group thermal_attr_group = {
cb6f3c15 IM	126	.attrs = thermal_throttle_attrs,
cb6f3c15 IM	127	.name = "thermal_throttle"
3222b36f DZ	128	};
3222b36f DZ	129	#endif /* CONFIG_SYSFS */
15d5f839	130
0199114c FY	131	#define CORE_LEVEL 0
	132	#define PACKAGE_LEVEL 1
	133
15d5f839	134	/***
3222b36f	135	* therm_throt_process - Process thermal throttling event from interrupt
15d5f839 DZ	136	* @curr: Whether the condition is current or not (boolean), since the
	137	* thermal interrupt normally gets called both when the thermal
	138	* event begins and once the event has ended.
	139	*
3222b36f	140	* This function is called by the thermal interrupt after the
15d5f839 DZ	141	* IRQ has been acknowledged.
	142	*
	143	* It will take care of rate limiting and printing messages to the syslog.
15d5f839	144	*/
9b052ea4	145	static void therm_throt_process(bool new_event, int event, int level)
15d5f839	146	{
55d435a2	147	struct _thermal_state *state;
0199114c FY	148	unsigned int this_cpu = smp_processor_id();
0199114c FY	149	bool old_event;
39676840	150	u64 now;
0199114c	151	struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu);
39676840	152
39676840	153	now = get_jiffies_64();
0199114c FY	154	if (level == CORE_LEVEL) {
	155	if (event == THERMAL_THROTTLING_EVENT)
	156	state = &pstate->core_throttle;
	157	else if (event == POWER_LIMIT_EVENT)
	158	state = &pstate->core_power_limit;
	159	else
9b052ea4	160	return;
0199114c FY	161	} else if (level == PACKAGE_LEVEL) {
	162	if (event == THERMAL_THROTTLING_EVENT)
	163	state = &pstate->package_throttle;
	164	else if (event == POWER_LIMIT_EVENT)
	165	state = &pstate->package_power_limit;
	166	else
9b052ea4	167	return;
0199114c	168	} else
9b052ea4	169	return;
39676840	170
0199114c FY	171	old_event = state->new_event;
0199114c FY	172	state->new_event = new_event;
15d5f839	173
0199114c FY	174	if (new_event)
0199114c FY	175	state->count++;
3222b36f	176
b417c9fd	177	if (time_before64(now, state->next_check) &&
0199114c	178	state->count != state->last_count)
9b052ea4	179	return;
15d5f839	180
39676840	181	state->next_check = now + CHECK_INTERVAL;
0199114c	182	state->last_count = state->count;
15d5f839 DZ	183
15d5f839 DZ	184	/* if we just entered the thermal event */
0199114c FY	185	if (new_event) {
0199114c FY	186	if (event == THERMAL_THROTTLING_EVENT)
1b74dde7	187	pr_crit("CPU%d: %s temperature above threshold, cpu clock throttled (total events = %lu)\n",
0199114c FY	188	this_cpu,
	189	level == CORE_LEVEL ? "Core" : "Package",
	190	state->count);
9b052ea4	191	return;
4e5c25d4	192	}
0199114c FY	193	if (old_event) {
0199114c FY	194	if (event == THERMAL_THROTTLING_EVENT)
1b74dde7	195	pr_info("CPU%d: %s temperature/speed normal\n", this_cpu,
0199114c	196	level == CORE_LEVEL ? "Core" : "Package");
9b052ea4	197	return;
15d5f839	198	}
15d5f839	199	}
3222b36f	200
25cdce17	201	static int thresh_event_valid(int level, int event)
9e76a97e D	202	{
	203	struct _thermal_state *state;
	204	unsigned int this_cpu = smp_processor_id();
	205	struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu);
	206	u64 now = get_jiffies_64();
	207
25cdce17 SP	208	if (level == PACKAGE_LEVEL)
	209	state = (event == 0) ? &pstate->pkg_thresh0 :
	210	&pstate->pkg_thresh1;
	211	else
	212	state = (event == 0) ? &pstate->core_thresh0 :
	213	&pstate->core_thresh1;
9e76a97e D	214
	215	if (time_before64(now, state->next_check))
	216	return 0;
	217
	218	state->next_check = now + CHECK_INTERVAL;
25cdce17	219
9e76a97e D	220	return 1;
	221	}
	222
6bb2ff84 FY	223	static bool int_pln_enable;
	224	static int __init int_pln_enable_setup(char *s)
	225	{
	226	int_pln_enable = true;
	227
	228	return 1;
	229	}
	230	__setup("int_pln_enable", int_pln_enable_setup);
	231
3222b36f	232	#ifdef CONFIG_SYSFS
cb6f3c15	233	/* Add/Remove thermal_throttle interface for CPU device: */
148f9bb8	234	static int thermal_throttle_add_dev(struct device *dev, unsigned int cpu)
3222b36f	235	{
55d435a2	236	int err;
51e3c1b5	237	struct cpuinfo_x86 *c = &cpu_data(cpu);
55d435a2	238
8a25a2fd	239	err = sysfs_create_group(&dev->kobj, &thermal_attr_group);
55d435a2 FY	240	if (err)
	241	return err;
	242
6bb2ff84	243	if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
8a25a2fd KS	244	err = sysfs_add_file_to_group(&dev->kobj,
8a25a2fd KS	245	&dev_attr_core_power_limit_count.attr,
0199114c	246	thermal_attr_group.name);
b62be8ea	247	if (cpu_has(c, X86_FEATURE_PTS)) {
8a25a2fd KS	248	err = sysfs_add_file_to_group(&dev->kobj,
8a25a2fd KS	249	&dev_attr_package_throttle_count.attr,
0199114c	250	thermal_attr_group.name);
6bb2ff84	251	if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
8a25a2fd KS	252	err = sysfs_add_file_to_group(&dev->kobj,
8a25a2fd KS	253	&dev_attr_package_power_limit_count.attr,
0199114c	254	thermal_attr_group.name);
b62be8ea	255	}
55d435a2 FY	256
55d435a2 FY	257	return err;
3222b36f DZ	258	}
3222b36f DZ	259
148f9bb8	260	static void thermal_throttle_remove_dev(struct device *dev)
3222b36f	261	{
8a25a2fd	262	sysfs_remove_group(&dev->kobj, &thermal_attr_group);
3222b36f DZ	263	}
3222b36f DZ	264
3222b36f	265	/* Get notified when a cpu comes on/off. Be hotplug friendly. */
33d97302	266	static int thermal_throttle_online(unsigned int cpu)
3222b36f	267	{
d6526e73 SAS	268	struct device *dev = get_cpu_device(cpu);
	269
	270	return thermal_throttle_add_dev(dev, cpu);
3222b36f DZ	271	}
3222b36f DZ	272
33d97302	273	static int thermal_throttle_offline(unsigned int cpu)
3222b36f	274	{
d6526e73 SAS	275	struct device *dev = get_cpu_device(cpu);
	276
	277	thermal_throttle_remove_dev(dev);
	278	return 0;
	279	}
3222b36f DZ	280
	281	static __init int thermal_throttle_init_device(void)
	282	{
33d97302	283	int ret;
3222b36f DZ	284
	285	if (!atomic_read(&therm_throt_en))
	286	return 0;
	287
33d97302 TG	288	ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/therm:online",
	289	thermal_throttle_online,
	290	thermal_throttle_offline);
	291	return ret < 0 ? ret : 0;
3222b36f	292	}
3222b36f	293	device_initcall(thermal_throttle_init_device);
a65c88dd	294
3222b36f	295	#endif /* CONFIG_SYSFS */
a65c88dd	296
25cdce17 SP	297	static void notify_package_thresholds(__u64 msr_val)
	298	{
	299	bool notify_thres_0 = false;
	300	bool notify_thres_1 = false;
	301
	302	if (!platform_thermal_package_notify)
	303	return;
	304
	305	/* lower threshold check */
	306	if (msr_val & THERM_LOG_THRESHOLD0)
	307	notify_thres_0 = true;
	308	/* higher threshold check */
	309	if (msr_val & THERM_LOG_THRESHOLD1)
	310	notify_thres_1 = true;
	311
	312	if (!notify_thres_0 && !notify_thres_1)
	313	return;
	314
	315	if (platform_thermal_package_rate_control &&
	316	platform_thermal_package_rate_control()) {
	317	/* Rate control is implemented in callback */
	318	platform_thermal_package_notify(msr_val);
	319	return;
	320	}
	321
	322	/* lower threshold reached */
	323	if (notify_thres_0 && thresh_event_valid(PACKAGE_LEVEL, 0))
	324	platform_thermal_package_notify(msr_val);
	325	/* higher threshold reached */
	326	if (notify_thres_1 && thresh_event_valid(PACKAGE_LEVEL, 1))
	327	platform_thermal_package_notify(msr_val);
	328	}
	329
9e76a97e D	330	static void notify_thresholds(__u64 msr_val)
	331	{
	332	/* check whether the interrupt handler is defined;
	333	* otherwise simply return
	334	*/
	335	if (!platform_thermal_notify)
	336	return;
	337
	338	/* lower threshold reached */
25cdce17 SP	339	if ((msr_val & THERM_LOG_THRESHOLD0) &&
25cdce17 SP	340	thresh_event_valid(CORE_LEVEL, 0))
9e76a97e D	341	platform_thermal_notify(msr_val);
9e76a97e D	342	/* higher threshold reached */
25cdce17 SP	343	if ((msr_val & THERM_LOG_THRESHOLD1) &&
25cdce17 SP	344	thresh_event_valid(CORE_LEVEL, 1))
9e76a97e D	345	platform_thermal_notify(msr_val);
	346	}
	347
a65c88dd	348	/* Thermal transition interrupt handler */
8363fc82	349	static void intel_thermal_interrupt(void)
a65c88dd HS	350	{
	351	__u64 msr_val;
	352
a2121167 SP	353	if (static_cpu_has(X86_FEATURE_HWP))
	354	wrmsrl_safe(MSR_HWP_STATUS, 0);
	355
a65c88dd	356	rdmsrl(MSR_IA32_THERM_STATUS, msr_val);
0199114c	357
9e76a97e D	358	/* Check for violation of core thermal thresholds*/
	359	notify_thresholds(msr_val);
	360
9b052ea4 BP	361	therm_throt_process(msr_val & THERM_STATUS_PROCHOT,
	362	THERMAL_THROTTLING_EVENT,
	363	CORE_LEVEL);
0199114c	364
6bb2ff84	365	if (this_cpu_has(X86_FEATURE_PLN) && int_pln_enable)
29e9bf18	366	therm_throt_process(msr_val & THERM_STATUS_POWER_LIMIT,
0199114c	367	POWER_LIMIT_EVENT,
29e9bf18	368	CORE_LEVEL);
55d435a2	369
fe504213	370	if (this_cpu_has(X86_FEATURE_PTS)) {
55d435a2	371	rdmsrl(MSR_IA32_PACKAGE_THERM_STATUS, msr_val);
25cdce17 SP	372	/* check violations of package thermal thresholds */
25cdce17 SP	373	notify_package_thresholds(msr_val);
29e9bf18	374	therm_throt_process(msr_val & PACKAGE_THERM_STATUS_PROCHOT,
0199114c	375	THERMAL_THROTTLING_EVENT,
29e9bf18	376	PACKAGE_LEVEL);
6bb2ff84	377	if (this_cpu_has(X86_FEATURE_PLN) && int_pln_enable)
29e9bf18	378	therm_throt_process(msr_val &
0199114c FY	379	PACKAGE_THERM_STATUS_POWER_LIMIT,
0199114c FY	380	POWER_LIMIT_EVENT,
29e9bf18	381	PACKAGE_LEVEL);
55d435a2	382	}
a65c88dd HS	383	}
	384
	385	static void unexpected_thermal_interrupt(void)
	386	{
1b74dde7 CY	387	pr_err("CPU%d: Unexpected LVT thermal interrupt!\n",
1b74dde7 CY	388	smp_processor_id());
a65c88dd HS	389	}
	390
	391	static void (*smp_thermal_vector)(void) = unexpected_thermal_interrupt;
	392
eddc0e92	393	static inline void __smp_thermal_interrupt(void)
a65c88dd	394	{
a65c88dd HS	395	inc_irq_stat(irq_thermal_count);
a65c88dd HS	396	smp_thermal_vector();
eddc0e92 SA	397	}
eddc0e92 SA	398
c4158ff5 DBO	399	asmlinkage __visible void __irq_entry
c4158ff5 DBO	400	smp_thermal_interrupt(struct pt_regs *regs)
eddc0e92 SA	401	{
	402	entering_irq();
	403	__smp_thermal_interrupt();
	404	exiting_ack_irq();
a65c88dd HS	405	}
a65c88dd HS	406
c4158ff5 DBO	407	asmlinkage __visible void __irq_entry
c4158ff5 DBO	408	smp_trace_thermal_interrupt(struct pt_regs *regs)
cf910e83 SA	409	{
	410	entering_irq();
	411	trace_thermal_apic_entry(THERMAL_APIC_VECTOR);
	412	__smp_thermal_interrupt();
	413	trace_thermal_apic_exit(THERMAL_APIC_VECTOR);
	414	exiting_ack_irq();
	415	}
	416
70fe4407 HS	417	/* Thermal monitoring depends on APIC, ACPI and clock modulation */
	418	static int intel_thermal_supported(struct cpuinfo_x86 *c)
	419	{
93984fbd	420	if (!boot_cpu_has(X86_FEATURE_APIC))
70fe4407 HS	421	return 0;
	422	if (!cpu_has(c, X86_FEATURE_ACPI) \|\| !cpu_has(c, X86_FEATURE_ACC))
	423	return 0;
	424	return 1;
	425	}
	426
ce6b5d76	427	void __init mcheck_intel_therm_init(void)
a2202aa2 YW	428	{
	429	/*
	430	* This function is only called on boot CPU. Save the init thermal
	431	* LVT value on BSP and use that value to restore APs' thermal LVT
	432	* entry BIOS programmed later
	433	*/
70fe4407	434	if (intel_thermal_supported(&boot_cpu_data))
a2202aa2 YW	435	lvtthmr_init = apic_read(APIC_LVTTHMR);
	436	}
	437
cffd377e	438	void intel_init_thermal(struct cpuinfo_x86 *c)
895287c0 HS	439	{
	440	unsigned int cpu = smp_processor_id();
	441	int tm2 = 0;
	442	u32 l, h;
	443
70fe4407	444	if (!intel_thermal_supported(c))
895287c0 HS	445	return;
	446
	447	/*
	448	* First check if its enabled already, in which case there might
	449	* be some SMM goo which handles it, so we can't even put a handler
	450	* since it might be delivered via SMI already:
	451	*/
	452	rdmsr(MSR_IA32_MISC_ENABLE, l, h);
a2202aa2	453
e503f9e4	454	h = lvtthmr_init;
a2202aa2 YW	455	/*
	456	* The initial value of thermal LVT entries on all APs always reads
	457	* 0x10000 because APs are woken up by BSP issuing INIT-SIPI-SIPI
	458	* sequence to them and LVT registers are reset to 0s except for
	459	* the mask bits which are set to 1s when APs receive INIT IPI.
e503f9e4 YS	460	* If BIOS takes over the thermal interrupt and sets its interrupt
	461	* delivery mode to SMI (not fixed), it restores the value that the
	462	* BIOS has programmed on AP based on BSP's info we saved since BIOS
	463	* is always setting the same value for all threads/cores.
a2202aa2	464	*/
e503f9e4 YS	465	if ((h & APIC_DM_FIXED_MASK) != APIC_DM_FIXED)
e503f9e4 YS	466	apic_write(APIC_LVTTHMR, lvtthmr_init);
a2202aa2	467
a2202aa2	468
895287c0	469	if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {
d286c3af	470	if (system_state == SYSTEM_BOOTING)
1b74dde7	471	pr_debug("CPU%d: Thermal monitoring handled by SMI\n", cpu);
895287c0 HS	472	return;
	473	}
	474
f3a0867b BZ	475	/* early Pentium M models use different method for enabling TM2 */
	476	if (cpu_has(c, X86_FEATURE_TM2)) {
	477	if (c->x86 == 6 && (c->x86_model == 9 \|\| c->x86_model == 13)) {
	478	rdmsr(MSR_THERM2_CTL, l, h);
	479	if (l & MSR_THERM2_CTL_TM_SELECT)
	480	tm2 = 1;
	481	} else if (l & MSR_IA32_MISC_ENABLE_TM2)
	482	tm2 = 1;
	483	}
	484
895287c0 HS	485	/* We'll mask the thermal vector in the lapic till we're ready: */
	486	h = THERMAL_APIC_VECTOR \| APIC_DM_FIXED \| APIC_LVT_MASKED;
	487	apic_write(APIC_LVTTHMR, h);
	488
	489	rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
6bb2ff84	490	if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable)
0199114c	491	wrmsr(MSR_IA32_THERM_INTERRUPT,
6bb2ff84 FY	492	(l \| (THERM_INT_LOW_ENABLE
	493	\| THERM_INT_HIGH_ENABLE)) & ~THERM_INT_PLN_ENABLE, h);
	494	else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
0199114c	495	wrmsr(MSR_IA32_THERM_INTERRUPT,
6bb2ff84	496	l \| (THERM_INT_LOW_ENABLE
0199114c FY	497	\| THERM_INT_HIGH_ENABLE \| THERM_INT_PLN_ENABLE), h);
	498	else
	499	wrmsr(MSR_IA32_THERM_INTERRUPT,
	500	l \| (THERM_INT_LOW_ENABLE \| THERM_INT_HIGH_ENABLE), h);
895287c0	501
55d435a2 FY	502	if (cpu_has(c, X86_FEATURE_PTS)) {
55d435a2 FY	503	rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
6bb2ff84	504	if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable)
0199114c	505	wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
6bb2ff84 FY	506	(l \| (PACKAGE_THERM_INT_LOW_ENABLE
	507	\| PACKAGE_THERM_INT_HIGH_ENABLE))
	508	& ~PACKAGE_THERM_INT_PLN_ENABLE, h);
	509	else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
	510	wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
	511	l \| (PACKAGE_THERM_INT_LOW_ENABLE
0199114c FY	512	\| PACKAGE_THERM_INT_HIGH_ENABLE
	513	\| PACKAGE_THERM_INT_PLN_ENABLE), h);
	514	else
	515	wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
	516	l \| (PACKAGE_THERM_INT_LOW_ENABLE
	517	\| PACKAGE_THERM_INT_HIGH_ENABLE), h);
55d435a2 FY	518	}
55d435a2 FY	519
8363fc82	520	smp_thermal_vector = intel_thermal_interrupt;
895287c0 HS	521
	522	rdmsr(MSR_IA32_MISC_ENABLE, l, h);
	523	wrmsr(MSR_IA32_MISC_ENABLE, l \| MSR_IA32_MISC_ENABLE_TM1, h);
	524
	525	/* Unmask the thermal vector: */
	526	l = apic_read(APIC_LVTTHMR);
	527	apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
	528
1b74dde7 CY	529	pr_info_once("CPU0: Thermal monitoring enabled (%s)\n",
1b74dde7 CY	530	tm2 ? "TM2" : "TM1");
895287c0 HS	531
	532	/* enable thermal throttle processing */
	533	atomic_set(&therm_throt_en, 1);
	534	}