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x86/microcode: Fix again accessing initrd after having been freed
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CommitLineData
3e135d88 1/*
6b44e72a 2 * CPU Microcode Update Driver for Linux
3e135d88 3 *
cea58224 4 * Copyright (C) 2000-2006 Tigran Aivazian <aivazian.tigran@gmail.com>
6b44e72a 5 * 2006 Shaohua Li <shaohua.li@intel.com>
14cfbe55 6 * 2013-2016 Borislav Petkov <bp@alien8.de>
3e135d88 7 *
fe055896
BP
8 * X86 CPU microcode early update for Linux:
9 *
10 * Copyright (C) 2012 Fenghua Yu <fenghua.yu@intel.com>
11 * H Peter Anvin" <hpa@zytor.com>
12 * (C) 2015 Borislav Petkov <bp@alien8.de>
13 *
6b44e72a 14 * This driver allows to upgrade microcode on x86 processors.
3e135d88 15 *
6b44e72a
BP
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License
18 * as published by the Free Software Foundation; either version
19 * 2 of the License, or (at your option) any later version.
3e135d88 20 */
f58e1f53 21
6b26e1bf 22#define pr_fmt(fmt) "microcode: " fmt
f58e1f53 23
4bae1967 24#include <linux/platform_device.h>
fe055896 25#include <linux/syscore_ops.h>
4bae1967 26#include <linux/miscdevice.h>
871b72dd 27#include <linux/capability.h>
fe055896 28#include <linux/firmware.h>
4bae1967 29#include <linux/kernel.h>
3e135d88
PO
30#include <linux/mutex.h>
31#include <linux/cpu.h>
4bae1967
IM
32#include <linux/fs.h>
33#include <linux/mm.h>
3e135d88 34
fe055896 35#include <asm/microcode_intel.h>
78ff123b 36#include <asm/cpu_device_id.h>
fe055896 37#include <asm/microcode_amd.h>
c93dc84c 38#include <asm/perf_event.h>
fe055896
BP
39#include <asm/microcode.h>
40#include <asm/processor.h>
41#include <asm/cmdline.h>
06b8534c 42#include <asm/setup.h>
3e135d88 43
14cfbe55 44#define DRIVER_VERSION "2.2"
3e135d88 45
4bae1967 46static struct microcode_ops *microcode_ops;
a15a7535 47static bool dis_ucode_ldr = true;
6b26e1bf 48
24c25032
BP
49bool initrd_gone;
50
058dc498
BP
51LIST_HEAD(microcode_cache);
52
871b72dd
DA
53/*
54 * Synchronization.
55 *
56 * All non cpu-hotplug-callback call sites use:
57 *
58 * - microcode_mutex to synchronize with each other;
59 * - get/put_online_cpus() to synchronize with
60 * the cpu-hotplug-callback call sites.
61 *
62 * We guarantee that only a single cpu is being
63 * updated at any particular moment of time.
64 */
d45de409 65static DEFINE_MUTEX(microcode_mutex);
3e135d88 66
4bae1967 67struct ucode_cpu_info ucode_cpu_info[NR_CPUS];
3e135d88 68
871b72dd
DA
69struct cpu_info_ctx {
70 struct cpu_signature *cpu_sig;
71 int err;
72};
73
f3ad136d
BP
74/*
75 * Those patch levels cannot be updated to newer ones and thus should be final.
76 */
77static u32 final_levels[] = {
78 0x01000098,
79 0x0100009f,
80 0x010000af,
81 0, /* T-101 terminator */
82};
83
84/*
85 * Check the current patch level on this CPU.
86 *
87 * Returns:
88 * - true: if update should stop
89 * - false: otherwise
90 */
91static bool amd_check_current_patch_level(void)
92{
93 u32 lvl, dummy, i;
94 u32 *levels;
95
96 native_rdmsr(MSR_AMD64_PATCH_LEVEL, lvl, dummy);
97
98 if (IS_ENABLED(CONFIG_X86_32))
99 levels = (u32 *)__pa_nodebug(&final_levels);
100 else
101 levels = final_levels;
102
103 for (i = 0; levels[i]; i++) {
104 if (lvl == levels[i])
105 return true;
106 }
107 return false;
108}
109
fe055896
BP
110static bool __init check_loader_disabled_bsp(void)
111{
e8c8165e
BP
112 static const char *__dis_opt_str = "dis_ucode_ldr";
113
fe055896
BP
114#ifdef CONFIG_X86_32
115 const char *cmdline = (const char *)__pa_nodebug(boot_command_line);
e8c8165e 116 const char *option = (const char *)__pa_nodebug(__dis_opt_str);
fe055896
BP
117 bool *res = (bool *)__pa_nodebug(&dis_ucode_ldr);
118
119#else /* CONFIG_X86_64 */
120 const char *cmdline = boot_command_line;
e8c8165e 121 const char *option = __dis_opt_str;
fe055896
BP
122 bool *res = &dis_ucode_ldr;
123#endif
124
a15a7535
BP
125 /*
126 * CPUID(1).ECX[31]: reserved for hypervisor use. This is still not
127 * completely accurate as xen pv guests don't see that CPUID bit set but
128 * that's good enough as they don't land on the BSP path anyway.
129 */
309aac77 130 if (native_cpuid_ecx(1) & BIT(31))
a15a7535
BP
131 return *res;
132
f3ad136d
BP
133 if (x86_cpuid_vendor() == X86_VENDOR_AMD) {
134 if (amd_check_current_patch_level())
135 return *res;
136 }
137
a15a7535
BP
138 if (cmdline_find_option_bool(cmdline, option) <= 0)
139 *res = false;
fe055896
BP
140
141 return *res;
142}
143
144extern struct builtin_fw __start_builtin_fw[];
145extern struct builtin_fw __end_builtin_fw[];
146
147bool get_builtin_firmware(struct cpio_data *cd, const char *name)
148{
149#ifdef CONFIG_FW_LOADER
150 struct builtin_fw *b_fw;
151
152 for (b_fw = __start_builtin_fw; b_fw != __end_builtin_fw; b_fw++) {
153 if (!strcmp(name, b_fw->name)) {
154 cd->size = b_fw->size;
155 cd->data = b_fw->data;
156 return true;
157 }
158 }
159#endif
160 return false;
161}
162
163void __init load_ucode_bsp(void)
164{
7a93a40b 165 unsigned int cpuid_1_eax;
1f161f67 166 bool intel = true;
fe055896 167
1f161f67 168 if (!have_cpuid_p())
fe055896
BP
169 return;
170
309aac77 171 cpuid_1_eax = native_cpuid_eax(1);
fe055896 172
7a93a40b 173 switch (x86_cpuid_vendor()) {
fe055896 174 case X86_VENDOR_INTEL:
1f161f67
BP
175 if (x86_family(cpuid_1_eax) < 6)
176 return;
fe055896 177 break;
1f161f67 178
fe055896 179 case X86_VENDOR_AMD:
1f161f67
BP
180 if (x86_family(cpuid_1_eax) < 0x10)
181 return;
182 intel = false;
fe055896 183 break;
1f161f67 184
fe055896 185 default:
1f161f67 186 return;
fe055896 187 }
1f161f67
BP
188
189 if (check_loader_disabled_bsp())
190 return;
191
192 if (intel)
193 load_ucode_intel_bsp();
194 else
195 load_ucode_amd_bsp(cpuid_1_eax);
fe055896
BP
196}
197
198static bool check_loader_disabled_ap(void)
199{
200#ifdef CONFIG_X86_32
201 return *((bool *)__pa_nodebug(&dis_ucode_ldr));
202#else
203 return dis_ucode_ldr;
204#endif
205}
206
207void load_ucode_ap(void)
208{
7a93a40b 209 unsigned int cpuid_1_eax;
fe055896
BP
210
211 if (check_loader_disabled_ap())
212 return;
213
309aac77 214 cpuid_1_eax = native_cpuid_eax(1);
fe055896 215
7a93a40b 216 switch (x86_cpuid_vendor()) {
fe055896 217 case X86_VENDOR_INTEL:
309aac77 218 if (x86_family(cpuid_1_eax) >= 6)
fe055896
BP
219 load_ucode_intel_ap();
220 break;
221 case X86_VENDOR_AMD:
309aac77
BP
222 if (x86_family(cpuid_1_eax) >= 0x10)
223 load_ucode_amd_ap(cpuid_1_eax);
fe055896
BP
224 break;
225 default:
226 break;
227 }
228}
229
4b703305 230static int __init save_microcode_in_initrd(void)
fe055896
BP
231{
232 struct cpuinfo_x86 *c = &boot_cpu_data;
24c25032 233 int ret = -EINVAL;
fe055896
BP
234
235 switch (c->x86_vendor) {
236 case X86_VENDOR_INTEL:
237 if (c->x86 >= 6)
24c25032 238 ret = save_microcode_in_initrd_intel();
fe055896
BP
239 break;
240 case X86_VENDOR_AMD:
241 if (c->x86 >= 0x10)
1d080f09 242 ret = save_microcode_in_initrd_amd(cpuid_eax(1));
fe055896
BP
243 break;
244 default:
245 break;
246 }
247
24c25032
BP
248 initrd_gone = true;
249
250 return ret;
fe055896
BP
251}
252
06b8534c
BP
253struct cpio_data find_microcode_in_initrd(const char *path, bool use_pa)
254{
255#ifdef CONFIG_BLK_DEV_INITRD
256 unsigned long start = 0;
257 size_t size;
258
259#ifdef CONFIG_X86_32
260 struct boot_params *params;
261
262 if (use_pa)
263 params = (struct boot_params *)__pa_nodebug(&boot_params);
264 else
265 params = &boot_params;
266
267 size = params->hdr.ramdisk_size;
268
269 /*
270 * Set start only if we have an initrd image. We cannot use initrd_start
271 * because it is not set that early yet.
272 */
273 if (size)
274 start = params->hdr.ramdisk_image;
275
276# else /* CONFIG_X86_64 */
277 size = (unsigned long)boot_params.ext_ramdisk_size << 32;
278 size |= boot_params.hdr.ramdisk_size;
279
280 if (size) {
281 start = (unsigned long)boot_params.ext_ramdisk_image << 32;
282 start |= boot_params.hdr.ramdisk_image;
283
284 start += PAGE_OFFSET;
285 }
286# endif
287
288 /*
8877ebdd
BP
289 * Fixup the start address: after reserve_initrd() runs, initrd_start
290 * has the virtual address of the beginning of the initrd. It also
291 * possibly relocates the ramdisk. In either case, initrd_start contains
292 * the updated address so use that instead.
24c25032
BP
293 *
294 * initrd_gone is for the hotplug case where we've thrown out initrd
295 * already.
06b8534c 296 */
24c25032
BP
297 if (!use_pa) {
298 if (initrd_gone)
299 return (struct cpio_data){ NULL, 0, "" };
300 if (initrd_start)
301 start = initrd_start;
a3d98c93
BP
302 } else {
303 /*
304 * The picture with physical addresses is a bit different: we
305 * need to get the *physical* address to which the ramdisk was
306 * relocated, i.e., relocated_ramdisk (not initrd_start) and
307 * since we're running from physical addresses, we need to access
308 * relocated_ramdisk through its *physical* address too.
309 */
310 u64 *rr = (u64 *)__pa_nodebug(&relocated_ramdisk);
311 if (*rr)
312 start = *rr;
24c25032 313 }
06b8534c
BP
314
315 return find_cpio_data(path, (void *)start, size, NULL);
316#else /* !CONFIG_BLK_DEV_INITRD */
317 return (struct cpio_data){ NULL, 0, "" };
318#endif
319}
320
fe055896
BP
321void reload_early_microcode(void)
322{
323 int vendor, family;
324
99f925ce
BP
325 vendor = x86_cpuid_vendor();
326 family = x86_cpuid_family();
fe055896
BP
327
328 switch (vendor) {
329 case X86_VENDOR_INTEL:
330 if (family >= 6)
331 reload_ucode_intel();
332 break;
333 case X86_VENDOR_AMD:
334 if (family >= 0x10)
335 reload_ucode_amd();
336 break;
337 default:
338 break;
339 }
340}
341
871b72dd
DA
342static void collect_cpu_info_local(void *arg)
343{
344 struct cpu_info_ctx *ctx = arg;
345
346 ctx->err = microcode_ops->collect_cpu_info(smp_processor_id(),
347 ctx->cpu_sig);
348}
349
350static int collect_cpu_info_on_target(int cpu, struct cpu_signature *cpu_sig)
351{
352 struct cpu_info_ctx ctx = { .cpu_sig = cpu_sig, .err = 0 };
353 int ret;
354
355 ret = smp_call_function_single(cpu, collect_cpu_info_local, &ctx, 1);
356 if (!ret)
357 ret = ctx.err;
358
359 return ret;
360}
361
362static int collect_cpu_info(int cpu)
363{
364 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
365 int ret;
366
367 memset(uci, 0, sizeof(*uci));
368
369 ret = collect_cpu_info_on_target(cpu, &uci->cpu_sig);
370 if (!ret)
371 uci->valid = 1;
372
373 return ret;
374}
375
376struct apply_microcode_ctx {
377 int err;
378};
379
380static void apply_microcode_local(void *arg)
381{
382 struct apply_microcode_ctx *ctx = arg;
383
384 ctx->err = microcode_ops->apply_microcode(smp_processor_id());
385}
386
387static int apply_microcode_on_target(int cpu)
388{
389 struct apply_microcode_ctx ctx = { .err = 0 };
390 int ret;
391
392 ret = smp_call_function_single(cpu, apply_microcode_local, &ctx, 1);
393 if (!ret)
394 ret = ctx.err;
395
396 return ret;
397}
398
3e135d88 399#ifdef CONFIG_MICROCODE_OLD_INTERFACE
a0a29b62 400static int do_microcode_update(const void __user *buf, size_t size)
3e135d88 401{
3e135d88 402 int error = 0;
3e135d88 403 int cpu;
6f66cbc6 404
a0a29b62
DA
405 for_each_online_cpu(cpu) {
406 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
871b72dd 407 enum ucode_state ustate;
a0a29b62
DA
408
409 if (!uci->valid)
410 continue;
6f66cbc6 411
871b72dd
DA
412 ustate = microcode_ops->request_microcode_user(cpu, buf, size);
413 if (ustate == UCODE_ERROR) {
414 error = -1;
415 break;
416 } else if (ustate == UCODE_OK)
417 apply_microcode_on_target(cpu);
3e135d88 418 }
871b72dd 419
3e135d88
PO
420 return error;
421}
422
3f10940e 423static int microcode_open(struct inode *inode, struct file *file)
3e135d88 424{
3f10940e 425 return capable(CAP_SYS_RAWIO) ? nonseekable_open(inode, file) : -EPERM;
3e135d88
PO
426}
427
d33dcb9e
PO
428static ssize_t microcode_write(struct file *file, const char __user *buf,
429 size_t len, loff_t *ppos)
3e135d88 430{
871b72dd 431 ssize_t ret = -EINVAL;
3e135d88 432
4481374c 433 if ((len >> PAGE_SHIFT) > totalram_pages) {
f58e1f53 434 pr_err("too much data (max %ld pages)\n", totalram_pages);
871b72dd 435 return ret;
3e135d88
PO
436 }
437
438 get_online_cpus();
439 mutex_lock(&microcode_mutex);
440
871b72dd 441 if (do_microcode_update(buf, len) == 0)
3e135d88
PO
442 ret = (ssize_t)len;
443
e3e45c01
SE
444 if (ret > 0)
445 perf_check_microcode();
446
3e135d88
PO
447 mutex_unlock(&microcode_mutex);
448 put_online_cpus();
449
450 return ret;
451}
452
453static const struct file_operations microcode_fops = {
871b72dd
DA
454 .owner = THIS_MODULE,
455 .write = microcode_write,
456 .open = microcode_open,
6038f373 457 .llseek = no_llseek,
3e135d88
PO
458};
459
460static struct miscdevice microcode_dev = {
871b72dd
DA
461 .minor = MICROCODE_MINOR,
462 .name = "microcode",
e454cea2 463 .nodename = "cpu/microcode",
871b72dd 464 .fops = &microcode_fops,
3e135d88
PO
465};
466
d33dcb9e 467static int __init microcode_dev_init(void)
3e135d88
PO
468{
469 int error;
470
471 error = misc_register(&microcode_dev);
472 if (error) {
f58e1f53 473 pr_err("can't misc_register on minor=%d\n", MICROCODE_MINOR);
3e135d88
PO
474 return error;
475 }
476
477 return 0;
478}
479
bd399063 480static void __exit microcode_dev_exit(void)
3e135d88
PO
481{
482 misc_deregister(&microcode_dev);
483}
3e135d88 484#else
4bae1967
IM
485#define microcode_dev_init() 0
486#define microcode_dev_exit() do { } while (0)
3e135d88
PO
487#endif
488
489/* fake device for request_firmware */
4bae1967 490static struct platform_device *microcode_pdev;
3e135d88 491
871b72dd 492static int reload_for_cpu(int cpu)
af5c820a 493{
871b72dd 494 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
4dbf32c3 495 enum ucode_state ustate;
af5c820a
RR
496 int err = 0;
497
4dbf32c3
BP
498 if (!uci->valid)
499 return err;
871b72dd 500
48e30685 501 ustate = microcode_ops->request_microcode_fw(cpu, &microcode_pdev->dev, true);
4dbf32c3
BP
502 if (ustate == UCODE_OK)
503 apply_microcode_on_target(cpu);
504 else
505 if (ustate == UCODE_ERROR)
506 err = -EINVAL;
af5c820a
RR
507 return err;
508}
509
8a25a2fd
KS
510static ssize_t reload_store(struct device *dev,
511 struct device_attribute *attr,
871b72dd 512 const char *buf, size_t size)
3e135d88 513{
871b72dd 514 unsigned long val;
c9fc3f77
BP
515 int cpu;
516 ssize_t ret = 0, tmp_ret;
517
e826abd5
SK
518 ret = kstrtoul(buf, 0, &val);
519 if (ret)
520 return ret;
871b72dd 521
c9fc3f77
BP
522 if (val != 1)
523 return size;
524
525 get_online_cpus();
c93dc84c 526 mutex_lock(&microcode_mutex);
c9fc3f77
BP
527 for_each_online_cpu(cpu) {
528 tmp_ret = reload_for_cpu(cpu);
529 if (tmp_ret != 0)
530 pr_warn("Error reloading microcode on CPU %d\n", cpu);
531
532 /* save retval of the first encountered reload error */
533 if (!ret)
534 ret = tmp_ret;
3e135d88 535 }
c93dc84c
PZ
536 if (!ret)
537 perf_check_microcode();
538 mutex_unlock(&microcode_mutex);
c9fc3f77 539 put_online_cpus();
871b72dd
DA
540
541 if (!ret)
542 ret = size;
543
544 return ret;
3e135d88
PO
545}
546
8a25a2fd
KS
547static ssize_t version_show(struct device *dev,
548 struct device_attribute *attr, char *buf)
3e135d88
PO
549{
550 struct ucode_cpu_info *uci = ucode_cpu_info + dev->id;
551
d45de409 552 return sprintf(buf, "0x%x\n", uci->cpu_sig.rev);
3e135d88
PO
553}
554
8a25a2fd
KS
555static ssize_t pf_show(struct device *dev,
556 struct device_attribute *attr, char *buf)
3e135d88
PO
557{
558 struct ucode_cpu_info *uci = ucode_cpu_info + dev->id;
559
d45de409 560 return sprintf(buf, "0x%x\n", uci->cpu_sig.pf);
3e135d88
PO
561}
562
8a25a2fd
KS
563static DEVICE_ATTR(reload, 0200, NULL, reload_store);
564static DEVICE_ATTR(version, 0400, version_show, NULL);
565static DEVICE_ATTR(processor_flags, 0400, pf_show, NULL);
3e135d88
PO
566
567static struct attribute *mc_default_attrs[] = {
8a25a2fd
KS
568 &dev_attr_version.attr,
569 &dev_attr_processor_flags.attr,
3e135d88
PO
570 NULL
571};
572
45bd07ad 573static const struct attribute_group mc_attr_group = {
871b72dd
DA
574 .attrs = mc_default_attrs,
575 .name = "microcode",
3e135d88
PO
576};
577
871b72dd 578static void microcode_fini_cpu(int cpu)
d45de409 579{
06b8534c
BP
580 if (microcode_ops->microcode_fini_cpu)
581 microcode_ops->microcode_fini_cpu(cpu);
280a9ca5
DA
582}
583
871b72dd 584static enum ucode_state microcode_resume_cpu(int cpu)
d45de409 585{
bb9d3e47
BP
586 if (apply_microcode_on_target(cpu))
587 return UCODE_ERROR;
871b72dd 588
6b14b818
BP
589 pr_debug("CPU%d updated upon resume\n", cpu);
590
871b72dd 591 return UCODE_OK;
d45de409
DA
592}
593
48e30685 594static enum ucode_state microcode_init_cpu(int cpu, bool refresh_fw)
d45de409 595{
871b72dd 596 enum ucode_state ustate;
9cd4d78e
FY
597 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
598
43858f57 599 if (uci->valid)
9cd4d78e 600 return UCODE_OK;
d45de409 601
871b72dd
DA
602 if (collect_cpu_info(cpu))
603 return UCODE_ERROR;
d45de409 604
871b72dd
DA
605 /* --dimm. Trigger a delayed update? */
606 if (system_state != SYSTEM_RUNNING)
607 return UCODE_NFOUND;
d45de409 608
48e30685
BP
609 ustate = microcode_ops->request_microcode_fw(cpu, &microcode_pdev->dev,
610 refresh_fw);
d45de409 611
871b72dd 612 if (ustate == UCODE_OK) {
f58e1f53 613 pr_debug("CPU%d updated upon init\n", cpu);
871b72dd 614 apply_microcode_on_target(cpu);
d45de409
DA
615 }
616
871b72dd 617 return ustate;
d45de409
DA
618}
619
871b72dd 620static enum ucode_state microcode_update_cpu(int cpu)
d45de409 621{
871b72dd 622 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
d45de409 623
7f709d0c
BP
624 /* Refresh CPU microcode revision after resume. */
625 collect_cpu_info(cpu);
626
2f99f5c8 627 if (uci->valid)
bb9d3e47 628 return microcode_resume_cpu(cpu);
d45de409 629
48e30685 630 return microcode_init_cpu(cpu, false);
d45de409
DA
631}
632
8a25a2fd 633static int mc_device_add(struct device *dev, struct subsys_interface *sif)
3e135d88 634{
8a25a2fd 635 int err, cpu = dev->id;
3e135d88
PO
636
637 if (!cpu_online(cpu))
638 return 0;
639
f58e1f53 640 pr_debug("CPU%d added\n", cpu);
3e135d88 641
8a25a2fd 642 err = sysfs_create_group(&dev->kobj, &mc_attr_group);
3e135d88
PO
643 if (err)
644 return err;
645
48e30685 646 if (microcode_init_cpu(cpu, true) == UCODE_ERROR)
6c53cbfc 647 return -EINVAL;
af5c820a
RR
648
649 return err;
3e135d88
PO
650}
651
71db87ba 652static void mc_device_remove(struct device *dev, struct subsys_interface *sif)
3e135d88 653{
8a25a2fd 654 int cpu = dev->id;
3e135d88
PO
655
656 if (!cpu_online(cpu))
71db87ba 657 return;
3e135d88 658
f58e1f53 659 pr_debug("CPU%d removed\n", cpu);
d45de409 660 microcode_fini_cpu(cpu);
8a25a2fd 661 sysfs_remove_group(&dev->kobj, &mc_attr_group);
3e135d88
PO
662}
663
8a25a2fd
KS
664static struct subsys_interface mc_cpu_interface = {
665 .name = "microcode",
666 .subsys = &cpu_subsys,
667 .add_dev = mc_device_add,
668 .remove_dev = mc_device_remove,
f3c6ea1b
RW
669};
670
671/**
672 * mc_bp_resume - Update boot CPU microcode during resume.
673 */
674static void mc_bp_resume(void)
3e135d88 675{
f3c6ea1b 676 int cpu = smp_processor_id();
871b72dd 677 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
3e135d88 678
871b72dd
DA
679 if (uci->valid && uci->mc)
680 microcode_ops->apply_microcode(cpu);
fb86b973 681 else if (!uci->mc)
fbae4ba8 682 reload_early_microcode();
3e135d88
PO
683}
684
f3c6ea1b
RW
685static struct syscore_ops mc_syscore_ops = {
686 .resume = mc_bp_resume,
3e135d88
PO
687};
688
29bd7fbc 689static int mc_cpu_online(unsigned int cpu)
3e135d88 690{
8a25a2fd 691 struct device *dev;
3e135d88 692
8a25a2fd 693 dev = get_cpu_device(cpu);
29bd7fbc
SAS
694 microcode_update_cpu(cpu);
695 pr_debug("CPU%d added\n", cpu);
09c3f0d8 696
29bd7fbc
SAS
697 if (sysfs_create_group(&dev->kobj, &mc_attr_group))
698 pr_err("Failed to create group for CPU%d\n", cpu);
699 return 0;
700}
09c3f0d8 701
29bd7fbc
SAS
702static int mc_cpu_down_prep(unsigned int cpu)
703{
704 struct device *dev;
70989449 705
29bd7fbc
SAS
706 dev = get_cpu_device(cpu);
707 /* Suspend is in progress, only remove the interface */
708 sysfs_remove_group(&dev->kobj, &mc_attr_group);
709 pr_debug("CPU%d removed\n", cpu);
06b8534c 710
29bd7fbc 711 return 0;
3e135d88
PO
712}
713
3d8986bc
BP
714static struct attribute *cpu_root_microcode_attrs[] = {
715 &dev_attr_reload.attr,
716 NULL
717};
718
45bd07ad 719static const struct attribute_group cpu_root_microcode_group = {
3d8986bc
BP
720 .name = "microcode",
721 .attrs = cpu_root_microcode_attrs,
722};
723
9a2bc335 724int __init microcode_init(void)
3e135d88 725{
9a2bc335 726 struct cpuinfo_x86 *c = &boot_cpu_data;
3e135d88
PO
727 int error;
728
84aba677 729 if (dis_ucode_ldr)
da63865a 730 return -EINVAL;
65cef131 731
18dbc916
DA
732 if (c->x86_vendor == X86_VENDOR_INTEL)
733 microcode_ops = init_intel_microcode();
82b07865 734 else if (c->x86_vendor == X86_VENDOR_AMD)
18dbc916 735 microcode_ops = init_amd_microcode();
283c1f25 736 else
f58e1f53 737 pr_err("no support for this CPU vendor\n");
283c1f25
AH
738
739 if (!microcode_ops)
18dbc916 740 return -ENODEV;
3e135d88 741
3e135d88
PO
742 microcode_pdev = platform_device_register_simple("microcode", -1,
743 NULL, 0);
bd399063 744 if (IS_ERR(microcode_pdev))
3e135d88 745 return PTR_ERR(microcode_pdev);
3e135d88
PO
746
747 get_online_cpus();
871b72dd
DA
748 mutex_lock(&microcode_mutex);
749
8a25a2fd 750 error = subsys_interface_register(&mc_cpu_interface);
c93dc84c
PZ
751 if (!error)
752 perf_check_microcode();
871b72dd 753 mutex_unlock(&microcode_mutex);
3e135d88 754 put_online_cpus();
871b72dd 755
bd399063
SB
756 if (error)
757 goto out_pdev;
3e135d88 758
3d8986bc
BP
759 error = sysfs_create_group(&cpu_subsys.dev_root->kobj,
760 &cpu_root_microcode_group);
761
762 if (error) {
763 pr_err("Error creating microcode group!\n");
764 goto out_driver;
765 }
766
871b72dd
DA
767 error = microcode_dev_init();
768 if (error)
3d8986bc 769 goto out_ucode_group;
871b72dd 770
f3c6ea1b 771 register_syscore_ops(&mc_syscore_ops);
29bd7fbc
SAS
772 cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/microcode:online",
773 mc_cpu_online, mc_cpu_down_prep);
8d86f390 774
14cfbe55 775 pr_info("Microcode Update Driver: v%s.", DRIVER_VERSION);
8d86f390 776
3e135d88 777 return 0;
bd399063 778
3d8986bc
BP
779 out_ucode_group:
780 sysfs_remove_group(&cpu_subsys.dev_root->kobj,
781 &cpu_root_microcode_group);
782
783 out_driver:
bd399063
SB
784 get_online_cpus();
785 mutex_lock(&microcode_mutex);
786
ff4b8a57 787 subsys_interface_unregister(&mc_cpu_interface);
bd399063
SB
788
789 mutex_unlock(&microcode_mutex);
790 put_online_cpus();
791
3d8986bc 792 out_pdev:
bd399063
SB
793 platform_device_unregister(microcode_pdev);
794 return error;
795
3e135d88 796}
4b703305 797fs_initcall(save_microcode_in_initrd);
2d5be37d 798late_initcall(microcode_init);