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Commit | Line | Data |
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3e135d88 | 1 | /* |
6b44e72a | 2 | * CPU Microcode Update Driver for Linux |
3e135d88 | 3 | * |
6b44e72a BP |
4 | * Copyright (C) 2000-2006 Tigran Aivazian <tigran@aivazian.fsnet.co.uk> |
5 | * 2006 Shaohua Li <shaohua.li@intel.com> | |
6 | * 2013-2015 Borislav Petkov <bp@alien8.de> | |
3e135d88 | 7 | * |
fe055896 BP |
8 | * X86 CPU microcode early update for Linux: |
9 | * | |
10 | * Copyright (C) 2012 Fenghua Yu <fenghua.yu@intel.com> | |
11 | * H Peter Anvin" <hpa@zytor.com> | |
12 | * (C) 2015 Borislav Petkov <bp@alien8.de> | |
13 | * | |
6b44e72a | 14 | * This driver allows to upgrade microcode on x86 processors. |
3e135d88 | 15 | * |
6b44e72a BP |
16 | * This program is free software; you can redistribute it and/or |
17 | * modify it under the terms of the GNU General Public License | |
18 | * as published by the Free Software Foundation; either version | |
19 | * 2 of the License, or (at your option) any later version. | |
3e135d88 | 20 | */ |
f58e1f53 | 21 | |
6b26e1bf | 22 | #define pr_fmt(fmt) "microcode: " fmt |
f58e1f53 | 23 | |
4bae1967 | 24 | #include <linux/platform_device.h> |
fe055896 | 25 | #include <linux/syscore_ops.h> |
4bae1967 | 26 | #include <linux/miscdevice.h> |
871b72dd | 27 | #include <linux/capability.h> |
fe055896 | 28 | #include <linux/firmware.h> |
4bae1967 | 29 | #include <linux/kernel.h> |
3e135d88 PO |
30 | #include <linux/mutex.h> |
31 | #include <linux/cpu.h> | |
4bae1967 IM |
32 | #include <linux/fs.h> |
33 | #include <linux/mm.h> | |
3e135d88 | 34 | |
fe055896 | 35 | #include <asm/microcode_intel.h> |
78ff123b | 36 | #include <asm/cpu_device_id.h> |
fe055896 | 37 | #include <asm/microcode_amd.h> |
c93dc84c | 38 | #include <asm/perf_event.h> |
fe055896 BP |
39 | #include <asm/microcode.h> |
40 | #include <asm/processor.h> | |
41 | #include <asm/cmdline.h> | |
3e135d88 | 42 | |
6b26e1bf | 43 | #define MICROCODE_VERSION "2.01" |
3e135d88 | 44 | |
4bae1967 | 45 | static struct microcode_ops *microcode_ops; |
3e135d88 | 46 | |
6b26e1bf BP |
47 | static bool dis_ucode_ldr; |
48 | ||
49 | static int __init disable_loader(char *str) | |
50 | { | |
51 | dis_ucode_ldr = true; | |
52 | return 1; | |
53 | } | |
54 | __setup("dis_ucode_ldr", disable_loader); | |
65cef131 | 55 | |
871b72dd DA |
56 | /* |
57 | * Synchronization. | |
58 | * | |
59 | * All non cpu-hotplug-callback call sites use: | |
60 | * | |
61 | * - microcode_mutex to synchronize with each other; | |
62 | * - get/put_online_cpus() to synchronize with | |
63 | * the cpu-hotplug-callback call sites. | |
64 | * | |
65 | * We guarantee that only a single cpu is being | |
66 | * updated at any particular moment of time. | |
67 | */ | |
d45de409 | 68 | static DEFINE_MUTEX(microcode_mutex); |
3e135d88 | 69 | |
4bae1967 | 70 | struct ucode_cpu_info ucode_cpu_info[NR_CPUS]; |
8d86f390 | 71 | EXPORT_SYMBOL_GPL(ucode_cpu_info); |
3e135d88 | 72 | |
871b72dd DA |
73 | /* |
74 | * Operations that are run on a target cpu: | |
75 | */ | |
76 | ||
77 | struct cpu_info_ctx { | |
78 | struct cpu_signature *cpu_sig; | |
79 | int err; | |
80 | }; | |
81 | ||
fe055896 BP |
82 | static bool __init check_loader_disabled_bsp(void) |
83 | { | |
84 | #ifdef CONFIG_X86_32 | |
85 | const char *cmdline = (const char *)__pa_nodebug(boot_command_line); | |
86 | const char *opt = "dis_ucode_ldr"; | |
87 | const char *option = (const char *)__pa_nodebug(opt); | |
88 | bool *res = (bool *)__pa_nodebug(&dis_ucode_ldr); | |
89 | ||
90 | #else /* CONFIG_X86_64 */ | |
91 | const char *cmdline = boot_command_line; | |
92 | const char *option = "dis_ucode_ldr"; | |
93 | bool *res = &dis_ucode_ldr; | |
94 | #endif | |
95 | ||
96 | if (cmdline_find_option_bool(cmdline, option)) | |
97 | *res = true; | |
98 | ||
99 | return *res; | |
100 | } | |
101 | ||
102 | extern struct builtin_fw __start_builtin_fw[]; | |
103 | extern struct builtin_fw __end_builtin_fw[]; | |
104 | ||
105 | bool get_builtin_firmware(struct cpio_data *cd, const char *name) | |
106 | { | |
107 | #ifdef CONFIG_FW_LOADER | |
108 | struct builtin_fw *b_fw; | |
109 | ||
110 | for (b_fw = __start_builtin_fw; b_fw != __end_builtin_fw; b_fw++) { | |
111 | if (!strcmp(name, b_fw->name)) { | |
112 | cd->size = b_fw->size; | |
113 | cd->data = b_fw->data; | |
114 | return true; | |
115 | } | |
116 | } | |
117 | #endif | |
118 | return false; | |
119 | } | |
120 | ||
121 | void __init load_ucode_bsp(void) | |
122 | { | |
123 | int vendor; | |
124 | unsigned int family; | |
125 | ||
126 | if (check_loader_disabled_bsp()) | |
127 | return; | |
128 | ||
129 | if (!have_cpuid_p()) | |
130 | return; | |
131 | ||
132 | vendor = x86_vendor(); | |
133 | family = x86_family(); | |
134 | ||
135 | switch (vendor) { | |
136 | case X86_VENDOR_INTEL: | |
137 | if (family >= 6) | |
138 | load_ucode_intel_bsp(); | |
139 | break; | |
140 | case X86_VENDOR_AMD: | |
141 | if (family >= 0x10) | |
142 | load_ucode_amd_bsp(family); | |
143 | break; | |
144 | default: | |
145 | break; | |
146 | } | |
147 | } | |
148 | ||
149 | static bool check_loader_disabled_ap(void) | |
150 | { | |
151 | #ifdef CONFIG_X86_32 | |
152 | return *((bool *)__pa_nodebug(&dis_ucode_ldr)); | |
153 | #else | |
154 | return dis_ucode_ldr; | |
155 | #endif | |
156 | } | |
157 | ||
158 | void load_ucode_ap(void) | |
159 | { | |
160 | int vendor, family; | |
161 | ||
162 | if (check_loader_disabled_ap()) | |
163 | return; | |
164 | ||
165 | if (!have_cpuid_p()) | |
166 | return; | |
167 | ||
168 | vendor = x86_vendor(); | |
169 | family = x86_family(); | |
170 | ||
171 | switch (vendor) { | |
172 | case X86_VENDOR_INTEL: | |
173 | if (family >= 6) | |
174 | load_ucode_intel_ap(); | |
175 | break; | |
176 | case X86_VENDOR_AMD: | |
177 | if (family >= 0x10) | |
178 | load_ucode_amd_ap(); | |
179 | break; | |
180 | default: | |
181 | break; | |
182 | } | |
183 | } | |
184 | ||
185 | int __init save_microcode_in_initrd(void) | |
186 | { | |
187 | struct cpuinfo_x86 *c = &boot_cpu_data; | |
188 | ||
189 | switch (c->x86_vendor) { | |
190 | case X86_VENDOR_INTEL: | |
191 | if (c->x86 >= 6) | |
192 | save_microcode_in_initrd_intel(); | |
193 | break; | |
194 | case X86_VENDOR_AMD: | |
195 | if (c->x86 >= 0x10) | |
196 | save_microcode_in_initrd_amd(); | |
197 | break; | |
198 | default: | |
199 | break; | |
200 | } | |
201 | ||
202 | return 0; | |
203 | } | |
204 | ||
205 | void reload_early_microcode(void) | |
206 | { | |
207 | int vendor, family; | |
208 | ||
209 | vendor = x86_vendor(); | |
210 | family = x86_family(); | |
211 | ||
212 | switch (vendor) { | |
213 | case X86_VENDOR_INTEL: | |
214 | if (family >= 6) | |
215 | reload_ucode_intel(); | |
216 | break; | |
217 | case X86_VENDOR_AMD: | |
218 | if (family >= 0x10) | |
219 | reload_ucode_amd(); | |
220 | break; | |
221 | default: | |
222 | break; | |
223 | } | |
224 | } | |
225 | ||
871b72dd DA |
226 | static void collect_cpu_info_local(void *arg) |
227 | { | |
228 | struct cpu_info_ctx *ctx = arg; | |
229 | ||
230 | ctx->err = microcode_ops->collect_cpu_info(smp_processor_id(), | |
231 | ctx->cpu_sig); | |
232 | } | |
233 | ||
234 | static int collect_cpu_info_on_target(int cpu, struct cpu_signature *cpu_sig) | |
235 | { | |
236 | struct cpu_info_ctx ctx = { .cpu_sig = cpu_sig, .err = 0 }; | |
237 | int ret; | |
238 | ||
239 | ret = smp_call_function_single(cpu, collect_cpu_info_local, &ctx, 1); | |
240 | if (!ret) | |
241 | ret = ctx.err; | |
242 | ||
243 | return ret; | |
244 | } | |
245 | ||
246 | static int collect_cpu_info(int cpu) | |
247 | { | |
248 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
249 | int ret; | |
250 | ||
251 | memset(uci, 0, sizeof(*uci)); | |
252 | ||
253 | ret = collect_cpu_info_on_target(cpu, &uci->cpu_sig); | |
254 | if (!ret) | |
255 | uci->valid = 1; | |
256 | ||
257 | return ret; | |
258 | } | |
259 | ||
260 | struct apply_microcode_ctx { | |
261 | int err; | |
262 | }; | |
263 | ||
264 | static void apply_microcode_local(void *arg) | |
265 | { | |
266 | struct apply_microcode_ctx *ctx = arg; | |
267 | ||
268 | ctx->err = microcode_ops->apply_microcode(smp_processor_id()); | |
269 | } | |
270 | ||
271 | static int apply_microcode_on_target(int cpu) | |
272 | { | |
273 | struct apply_microcode_ctx ctx = { .err = 0 }; | |
274 | int ret; | |
275 | ||
276 | ret = smp_call_function_single(cpu, apply_microcode_local, &ctx, 1); | |
277 | if (!ret) | |
278 | ret = ctx.err; | |
279 | ||
280 | return ret; | |
281 | } | |
282 | ||
3e135d88 | 283 | #ifdef CONFIG_MICROCODE_OLD_INTERFACE |
a0a29b62 | 284 | static int do_microcode_update(const void __user *buf, size_t size) |
3e135d88 | 285 | { |
3e135d88 | 286 | int error = 0; |
3e135d88 | 287 | int cpu; |
6f66cbc6 | 288 | |
a0a29b62 DA |
289 | for_each_online_cpu(cpu) { |
290 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
871b72dd | 291 | enum ucode_state ustate; |
a0a29b62 DA |
292 | |
293 | if (!uci->valid) | |
294 | continue; | |
6f66cbc6 | 295 | |
871b72dd DA |
296 | ustate = microcode_ops->request_microcode_user(cpu, buf, size); |
297 | if (ustate == UCODE_ERROR) { | |
298 | error = -1; | |
299 | break; | |
300 | } else if (ustate == UCODE_OK) | |
301 | apply_microcode_on_target(cpu); | |
3e135d88 | 302 | } |
871b72dd | 303 | |
3e135d88 PO |
304 | return error; |
305 | } | |
306 | ||
3f10940e | 307 | static int microcode_open(struct inode *inode, struct file *file) |
3e135d88 | 308 | { |
3f10940e | 309 | return capable(CAP_SYS_RAWIO) ? nonseekable_open(inode, file) : -EPERM; |
3e135d88 PO |
310 | } |
311 | ||
d33dcb9e PO |
312 | static ssize_t microcode_write(struct file *file, const char __user *buf, |
313 | size_t len, loff_t *ppos) | |
3e135d88 | 314 | { |
871b72dd | 315 | ssize_t ret = -EINVAL; |
3e135d88 | 316 | |
4481374c | 317 | if ((len >> PAGE_SHIFT) > totalram_pages) { |
f58e1f53 | 318 | pr_err("too much data (max %ld pages)\n", totalram_pages); |
871b72dd | 319 | return ret; |
3e135d88 PO |
320 | } |
321 | ||
322 | get_online_cpus(); | |
323 | mutex_lock(µcode_mutex); | |
324 | ||
871b72dd | 325 | if (do_microcode_update(buf, len) == 0) |
3e135d88 PO |
326 | ret = (ssize_t)len; |
327 | ||
e3e45c01 SE |
328 | if (ret > 0) |
329 | perf_check_microcode(); | |
330 | ||
3e135d88 PO |
331 | mutex_unlock(µcode_mutex); |
332 | put_online_cpus(); | |
333 | ||
334 | return ret; | |
335 | } | |
336 | ||
337 | static const struct file_operations microcode_fops = { | |
871b72dd DA |
338 | .owner = THIS_MODULE, |
339 | .write = microcode_write, | |
340 | .open = microcode_open, | |
6038f373 | 341 | .llseek = no_llseek, |
3e135d88 PO |
342 | }; |
343 | ||
344 | static struct miscdevice microcode_dev = { | |
871b72dd DA |
345 | .minor = MICROCODE_MINOR, |
346 | .name = "microcode", | |
e454cea2 | 347 | .nodename = "cpu/microcode", |
871b72dd | 348 | .fops = µcode_fops, |
3e135d88 PO |
349 | }; |
350 | ||
d33dcb9e | 351 | static int __init microcode_dev_init(void) |
3e135d88 PO |
352 | { |
353 | int error; | |
354 | ||
355 | error = misc_register(µcode_dev); | |
356 | if (error) { | |
f58e1f53 | 357 | pr_err("can't misc_register on minor=%d\n", MICROCODE_MINOR); |
3e135d88 PO |
358 | return error; |
359 | } | |
360 | ||
361 | return 0; | |
362 | } | |
363 | ||
bd399063 | 364 | static void __exit microcode_dev_exit(void) |
3e135d88 PO |
365 | { |
366 | misc_deregister(µcode_dev); | |
367 | } | |
3e135d88 | 368 | #else |
4bae1967 IM |
369 | #define microcode_dev_init() 0 |
370 | #define microcode_dev_exit() do { } while (0) | |
3e135d88 PO |
371 | #endif |
372 | ||
373 | /* fake device for request_firmware */ | |
4bae1967 | 374 | static struct platform_device *microcode_pdev; |
3e135d88 | 375 | |
871b72dd | 376 | static int reload_for_cpu(int cpu) |
af5c820a | 377 | { |
871b72dd | 378 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
4dbf32c3 | 379 | enum ucode_state ustate; |
af5c820a RR |
380 | int err = 0; |
381 | ||
4dbf32c3 BP |
382 | if (!uci->valid) |
383 | return err; | |
871b72dd | 384 | |
48e30685 | 385 | ustate = microcode_ops->request_microcode_fw(cpu, µcode_pdev->dev, true); |
4dbf32c3 BP |
386 | if (ustate == UCODE_OK) |
387 | apply_microcode_on_target(cpu); | |
388 | else | |
389 | if (ustate == UCODE_ERROR) | |
390 | err = -EINVAL; | |
af5c820a RR |
391 | return err; |
392 | } | |
393 | ||
8a25a2fd KS |
394 | static ssize_t reload_store(struct device *dev, |
395 | struct device_attribute *attr, | |
871b72dd | 396 | const char *buf, size_t size) |
3e135d88 | 397 | { |
871b72dd | 398 | unsigned long val; |
c9fc3f77 BP |
399 | int cpu; |
400 | ssize_t ret = 0, tmp_ret; | |
401 | ||
e826abd5 SK |
402 | ret = kstrtoul(buf, 0, &val); |
403 | if (ret) | |
404 | return ret; | |
871b72dd | 405 | |
c9fc3f77 BP |
406 | if (val != 1) |
407 | return size; | |
408 | ||
409 | get_online_cpus(); | |
c93dc84c | 410 | mutex_lock(µcode_mutex); |
c9fc3f77 BP |
411 | for_each_online_cpu(cpu) { |
412 | tmp_ret = reload_for_cpu(cpu); | |
413 | if (tmp_ret != 0) | |
414 | pr_warn("Error reloading microcode on CPU %d\n", cpu); | |
415 | ||
416 | /* save retval of the first encountered reload error */ | |
417 | if (!ret) | |
418 | ret = tmp_ret; | |
3e135d88 | 419 | } |
c93dc84c PZ |
420 | if (!ret) |
421 | perf_check_microcode(); | |
422 | mutex_unlock(µcode_mutex); | |
c9fc3f77 | 423 | put_online_cpus(); |
871b72dd DA |
424 | |
425 | if (!ret) | |
426 | ret = size; | |
427 | ||
428 | return ret; | |
3e135d88 PO |
429 | } |
430 | ||
8a25a2fd KS |
431 | static ssize_t version_show(struct device *dev, |
432 | struct device_attribute *attr, char *buf) | |
3e135d88 PO |
433 | { |
434 | struct ucode_cpu_info *uci = ucode_cpu_info + dev->id; | |
435 | ||
d45de409 | 436 | return sprintf(buf, "0x%x\n", uci->cpu_sig.rev); |
3e135d88 PO |
437 | } |
438 | ||
8a25a2fd KS |
439 | static ssize_t pf_show(struct device *dev, |
440 | struct device_attribute *attr, char *buf) | |
3e135d88 PO |
441 | { |
442 | struct ucode_cpu_info *uci = ucode_cpu_info + dev->id; | |
443 | ||
d45de409 | 444 | return sprintf(buf, "0x%x\n", uci->cpu_sig.pf); |
3e135d88 PO |
445 | } |
446 | ||
8a25a2fd KS |
447 | static DEVICE_ATTR(reload, 0200, NULL, reload_store); |
448 | static DEVICE_ATTR(version, 0400, version_show, NULL); | |
449 | static DEVICE_ATTR(processor_flags, 0400, pf_show, NULL); | |
3e135d88 PO |
450 | |
451 | static struct attribute *mc_default_attrs[] = { | |
8a25a2fd KS |
452 | &dev_attr_version.attr, |
453 | &dev_attr_processor_flags.attr, | |
3e135d88 PO |
454 | NULL |
455 | }; | |
456 | ||
457 | static struct attribute_group mc_attr_group = { | |
871b72dd DA |
458 | .attrs = mc_default_attrs, |
459 | .name = "microcode", | |
3e135d88 PO |
460 | }; |
461 | ||
871b72dd | 462 | static void microcode_fini_cpu(int cpu) |
d45de409 | 463 | { |
d45de409 | 464 | microcode_ops->microcode_fini_cpu(cpu); |
280a9ca5 DA |
465 | } |
466 | ||
871b72dd | 467 | static enum ucode_state microcode_resume_cpu(int cpu) |
d45de409 | 468 | { |
f58e1f53 | 469 | pr_debug("CPU%d updated upon resume\n", cpu); |
bb9d3e47 BP |
470 | |
471 | if (apply_microcode_on_target(cpu)) | |
472 | return UCODE_ERROR; | |
871b72dd DA |
473 | |
474 | return UCODE_OK; | |
d45de409 DA |
475 | } |
476 | ||
48e30685 | 477 | static enum ucode_state microcode_init_cpu(int cpu, bool refresh_fw) |
d45de409 | 478 | { |
871b72dd | 479 | enum ucode_state ustate; |
9cd4d78e FY |
480 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
481 | ||
482 | if (uci && uci->valid) | |
483 | return UCODE_OK; | |
d45de409 | 484 | |
871b72dd DA |
485 | if (collect_cpu_info(cpu)) |
486 | return UCODE_ERROR; | |
d45de409 | 487 | |
871b72dd DA |
488 | /* --dimm. Trigger a delayed update? */ |
489 | if (system_state != SYSTEM_RUNNING) | |
490 | return UCODE_NFOUND; | |
d45de409 | 491 | |
48e30685 BP |
492 | ustate = microcode_ops->request_microcode_fw(cpu, µcode_pdev->dev, |
493 | refresh_fw); | |
d45de409 | 494 | |
871b72dd | 495 | if (ustate == UCODE_OK) { |
f58e1f53 | 496 | pr_debug("CPU%d updated upon init\n", cpu); |
871b72dd | 497 | apply_microcode_on_target(cpu); |
d45de409 DA |
498 | } |
499 | ||
871b72dd | 500 | return ustate; |
d45de409 DA |
501 | } |
502 | ||
871b72dd | 503 | static enum ucode_state microcode_update_cpu(int cpu) |
d45de409 | 504 | { |
871b72dd | 505 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
d45de409 | 506 | |
2f99f5c8 | 507 | if (uci->valid) |
bb9d3e47 | 508 | return microcode_resume_cpu(cpu); |
d45de409 | 509 | |
48e30685 | 510 | return microcode_init_cpu(cpu, false); |
d45de409 DA |
511 | } |
512 | ||
8a25a2fd | 513 | static int mc_device_add(struct device *dev, struct subsys_interface *sif) |
3e135d88 | 514 | { |
8a25a2fd | 515 | int err, cpu = dev->id; |
3e135d88 PO |
516 | |
517 | if (!cpu_online(cpu)) | |
518 | return 0; | |
519 | ||
f58e1f53 | 520 | pr_debug("CPU%d added\n", cpu); |
3e135d88 | 521 | |
8a25a2fd | 522 | err = sysfs_create_group(&dev->kobj, &mc_attr_group); |
3e135d88 PO |
523 | if (err) |
524 | return err; | |
525 | ||
48e30685 | 526 | if (microcode_init_cpu(cpu, true) == UCODE_ERROR) |
6c53cbfc | 527 | return -EINVAL; |
af5c820a RR |
528 | |
529 | return err; | |
3e135d88 PO |
530 | } |
531 | ||
71db87ba | 532 | static void mc_device_remove(struct device *dev, struct subsys_interface *sif) |
3e135d88 | 533 | { |
8a25a2fd | 534 | int cpu = dev->id; |
3e135d88 PO |
535 | |
536 | if (!cpu_online(cpu)) | |
71db87ba | 537 | return; |
3e135d88 | 538 | |
f58e1f53 | 539 | pr_debug("CPU%d removed\n", cpu); |
d45de409 | 540 | microcode_fini_cpu(cpu); |
8a25a2fd | 541 | sysfs_remove_group(&dev->kobj, &mc_attr_group); |
3e135d88 PO |
542 | } |
543 | ||
8a25a2fd KS |
544 | static struct subsys_interface mc_cpu_interface = { |
545 | .name = "microcode", | |
546 | .subsys = &cpu_subsys, | |
547 | .add_dev = mc_device_add, | |
548 | .remove_dev = mc_device_remove, | |
f3c6ea1b RW |
549 | }; |
550 | ||
551 | /** | |
552 | * mc_bp_resume - Update boot CPU microcode during resume. | |
553 | */ | |
554 | static void mc_bp_resume(void) | |
3e135d88 | 555 | { |
f3c6ea1b | 556 | int cpu = smp_processor_id(); |
871b72dd | 557 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
3e135d88 | 558 | |
871b72dd DA |
559 | if (uci->valid && uci->mc) |
560 | microcode_ops->apply_microcode(cpu); | |
fb86b973 | 561 | else if (!uci->mc) |
fbae4ba8 | 562 | reload_early_microcode(); |
3e135d88 PO |
563 | } |
564 | ||
f3c6ea1b RW |
565 | static struct syscore_ops mc_syscore_ops = { |
566 | .resume = mc_bp_resume, | |
3e135d88 PO |
567 | }; |
568 | ||
148f9bb8 | 569 | static int |
3e135d88 PO |
570 | mc_cpu_callback(struct notifier_block *nb, unsigned long action, void *hcpu) |
571 | { | |
572 | unsigned int cpu = (unsigned long)hcpu; | |
8a25a2fd | 573 | struct device *dev; |
3e135d88 | 574 | |
8a25a2fd | 575 | dev = get_cpu_device(cpu); |
09c3f0d8 BP |
576 | |
577 | switch (action & ~CPU_TASKS_FROZEN) { | |
3e135d88 | 578 | case CPU_ONLINE: |
871b72dd | 579 | microcode_update_cpu(cpu); |
f58e1f53 | 580 | pr_debug("CPU%d added\n", cpu); |
09c3f0d8 BP |
581 | /* |
582 | * "break" is missing on purpose here because we want to fall | |
583 | * through in order to create the sysfs group. | |
584 | */ | |
585 | ||
586 | case CPU_DOWN_FAILED: | |
8a25a2fd | 587 | if (sysfs_create_group(&dev->kobj, &mc_attr_group)) |
f58e1f53 | 588 | pr_err("Failed to create group for CPU%d\n", cpu); |
3e135d88 | 589 | break; |
09c3f0d8 | 590 | |
3e135d88 | 591 | case CPU_DOWN_PREPARE: |
3e135d88 | 592 | /* Suspend is in progress, only remove the interface */ |
8a25a2fd | 593 | sysfs_remove_group(&dev->kobj, &mc_attr_group); |
f58e1f53 | 594 | pr_debug("CPU%d removed\n", cpu); |
d45de409 | 595 | break; |
70989449 SB |
596 | |
597 | /* | |
09c3f0d8 BP |
598 | * case CPU_DEAD: |
599 | * | |
70989449 SB |
600 | * When a CPU goes offline, don't free up or invalidate the copy of |
601 | * the microcode in kernel memory, so that we can reuse it when the | |
602 | * CPU comes back online without unnecessarily requesting the userspace | |
603 | * for it again. | |
604 | */ | |
3e135d88 | 605 | } |
09c3f0d8 BP |
606 | |
607 | /* The CPU refused to come up during a system resume */ | |
608 | if (action == CPU_UP_CANCELED_FROZEN) | |
609 | microcode_fini_cpu(cpu); | |
610 | ||
3e135d88 PO |
611 | return NOTIFY_OK; |
612 | } | |
613 | ||
4daa832d | 614 | static struct notifier_block mc_cpu_notifier = { |
4bae1967 | 615 | .notifier_call = mc_cpu_callback, |
3e135d88 PO |
616 | }; |
617 | ||
3d8986bc BP |
618 | static struct attribute *cpu_root_microcode_attrs[] = { |
619 | &dev_attr_reload.attr, | |
620 | NULL | |
621 | }; | |
622 | ||
623 | static struct attribute_group cpu_root_microcode_group = { | |
624 | .name = "microcode", | |
625 | .attrs = cpu_root_microcode_attrs, | |
626 | }; | |
627 | ||
9a2bc335 | 628 | int __init microcode_init(void) |
3e135d88 | 629 | { |
9a2bc335 | 630 | struct cpuinfo_x86 *c = &boot_cpu_data; |
3e135d88 PO |
631 | int error; |
632 | ||
a18a0f68 | 633 | if (paravirt_enabled() || dis_ucode_ldr) |
da63865a | 634 | return -EINVAL; |
65cef131 | 635 | |
18dbc916 DA |
636 | if (c->x86_vendor == X86_VENDOR_INTEL) |
637 | microcode_ops = init_intel_microcode(); | |
82b07865 | 638 | else if (c->x86_vendor == X86_VENDOR_AMD) |
18dbc916 | 639 | microcode_ops = init_amd_microcode(); |
283c1f25 | 640 | else |
f58e1f53 | 641 | pr_err("no support for this CPU vendor\n"); |
283c1f25 AH |
642 | |
643 | if (!microcode_ops) | |
18dbc916 | 644 | return -ENODEV; |
3e135d88 | 645 | |
3e135d88 PO |
646 | microcode_pdev = platform_device_register_simple("microcode", -1, |
647 | NULL, 0); | |
bd399063 | 648 | if (IS_ERR(microcode_pdev)) |
3e135d88 | 649 | return PTR_ERR(microcode_pdev); |
3e135d88 PO |
650 | |
651 | get_online_cpus(); | |
871b72dd DA |
652 | mutex_lock(µcode_mutex); |
653 | ||
8a25a2fd | 654 | error = subsys_interface_register(&mc_cpu_interface); |
c93dc84c PZ |
655 | if (!error) |
656 | perf_check_microcode(); | |
871b72dd | 657 | mutex_unlock(µcode_mutex); |
3e135d88 | 658 | put_online_cpus(); |
871b72dd | 659 | |
bd399063 SB |
660 | if (error) |
661 | goto out_pdev; | |
3e135d88 | 662 | |
3d8986bc BP |
663 | error = sysfs_create_group(&cpu_subsys.dev_root->kobj, |
664 | &cpu_root_microcode_group); | |
665 | ||
666 | if (error) { | |
667 | pr_err("Error creating microcode group!\n"); | |
668 | goto out_driver; | |
669 | } | |
670 | ||
871b72dd DA |
671 | error = microcode_dev_init(); |
672 | if (error) | |
3d8986bc | 673 | goto out_ucode_group; |
871b72dd | 674 | |
f3c6ea1b | 675 | register_syscore_ops(&mc_syscore_ops); |
3e135d88 | 676 | register_hotcpu_notifier(&mc_cpu_notifier); |
8d86f390 | 677 | |
871b72dd | 678 | pr_info("Microcode Update Driver: v" MICROCODE_VERSION |
f58e1f53 | 679 | " <tigran@aivazian.fsnet.co.uk>, Peter Oruba\n"); |
8d86f390 | 680 | |
3e135d88 | 681 | return 0; |
bd399063 | 682 | |
3d8986bc BP |
683 | out_ucode_group: |
684 | sysfs_remove_group(&cpu_subsys.dev_root->kobj, | |
685 | &cpu_root_microcode_group); | |
686 | ||
687 | out_driver: | |
bd399063 SB |
688 | get_online_cpus(); |
689 | mutex_lock(µcode_mutex); | |
690 | ||
ff4b8a57 | 691 | subsys_interface_unregister(&mc_cpu_interface); |
bd399063 SB |
692 | |
693 | mutex_unlock(µcode_mutex); | |
694 | put_online_cpus(); | |
695 | ||
3d8986bc | 696 | out_pdev: |
bd399063 SB |
697 | platform_device_unregister(microcode_pdev); |
698 | return error; | |
699 | ||
3e135d88 | 700 | } |
2d5be37d | 701 | late_initcall(microcode_init); |