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Commit | Line | Data |
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3e135d88 | 1 | /* |
6b44e72a | 2 | * CPU Microcode Update Driver for Linux |
3e135d88 | 3 | * |
6b44e72a BP |
4 | * Copyright (C) 2000-2006 Tigran Aivazian <tigran@aivazian.fsnet.co.uk> |
5 | * 2006 Shaohua Li <shaohua.li@intel.com> | |
14cfbe55 | 6 | * 2013-2016 Borislav Petkov <bp@alien8.de> |
3e135d88 | 7 | * |
fe055896 BP |
8 | * X86 CPU microcode early update for Linux: |
9 | * | |
10 | * Copyright (C) 2012 Fenghua Yu <fenghua.yu@intel.com> | |
11 | * H Peter Anvin" <hpa@zytor.com> | |
12 | * (C) 2015 Borislav Petkov <bp@alien8.de> | |
13 | * | |
6b44e72a | 14 | * This driver allows to upgrade microcode on x86 processors. |
3e135d88 | 15 | * |
6b44e72a BP |
16 | * This program is free software; you can redistribute it and/or |
17 | * modify it under the terms of the GNU General Public License | |
18 | * as published by the Free Software Foundation; either version | |
19 | * 2 of the License, or (at your option) any later version. | |
3e135d88 | 20 | */ |
f58e1f53 | 21 | |
6b26e1bf | 22 | #define pr_fmt(fmt) "microcode: " fmt |
f58e1f53 | 23 | |
4bae1967 | 24 | #include <linux/platform_device.h> |
fe055896 | 25 | #include <linux/syscore_ops.h> |
4bae1967 | 26 | #include <linux/miscdevice.h> |
871b72dd | 27 | #include <linux/capability.h> |
fe055896 | 28 | #include <linux/firmware.h> |
4bae1967 | 29 | #include <linux/kernel.h> |
3e135d88 PO |
30 | #include <linux/mutex.h> |
31 | #include <linux/cpu.h> | |
4bae1967 IM |
32 | #include <linux/fs.h> |
33 | #include <linux/mm.h> | |
3e135d88 | 34 | |
fe055896 | 35 | #include <asm/microcode_intel.h> |
78ff123b | 36 | #include <asm/cpu_device_id.h> |
fe055896 | 37 | #include <asm/microcode_amd.h> |
c93dc84c | 38 | #include <asm/perf_event.h> |
fe055896 BP |
39 | #include <asm/microcode.h> |
40 | #include <asm/processor.h> | |
41 | #include <asm/cmdline.h> | |
06b8534c | 42 | #include <asm/setup.h> |
3e135d88 | 43 | |
14cfbe55 | 44 | #define DRIVER_VERSION "2.2" |
3e135d88 | 45 | |
4bae1967 | 46 | static struct microcode_ops *microcode_ops; |
a15a7535 | 47 | static bool dis_ucode_ldr = true; |
6b26e1bf | 48 | |
058dc498 BP |
49 | LIST_HEAD(microcode_cache); |
50 | ||
871b72dd DA |
51 | /* |
52 | * Synchronization. | |
53 | * | |
54 | * All non cpu-hotplug-callback call sites use: | |
55 | * | |
56 | * - microcode_mutex to synchronize with each other; | |
57 | * - get/put_online_cpus() to synchronize with | |
58 | * the cpu-hotplug-callback call sites. | |
59 | * | |
60 | * We guarantee that only a single cpu is being | |
61 | * updated at any particular moment of time. | |
62 | */ | |
d45de409 | 63 | static DEFINE_MUTEX(microcode_mutex); |
3e135d88 | 64 | |
4bae1967 | 65 | struct ucode_cpu_info ucode_cpu_info[NR_CPUS]; |
3e135d88 | 66 | |
871b72dd DA |
67 | struct cpu_info_ctx { |
68 | struct cpu_signature *cpu_sig; | |
69 | int err; | |
70 | }; | |
71 | ||
fe055896 BP |
72 | static bool __init check_loader_disabled_bsp(void) |
73 | { | |
e8c8165e BP |
74 | static const char *__dis_opt_str = "dis_ucode_ldr"; |
75 | ||
fe055896 BP |
76 | #ifdef CONFIG_X86_32 |
77 | const char *cmdline = (const char *)__pa_nodebug(boot_command_line); | |
e8c8165e | 78 | const char *option = (const char *)__pa_nodebug(__dis_opt_str); |
fe055896 BP |
79 | bool *res = (bool *)__pa_nodebug(&dis_ucode_ldr); |
80 | ||
81 | #else /* CONFIG_X86_64 */ | |
82 | const char *cmdline = boot_command_line; | |
e8c8165e | 83 | const char *option = __dis_opt_str; |
fe055896 BP |
84 | bool *res = &dis_ucode_ldr; |
85 | #endif | |
86 | ||
a15a7535 BP |
87 | if (!have_cpuid_p()) |
88 | return *res; | |
89 | ||
a15a7535 BP |
90 | /* |
91 | * CPUID(1).ECX[31]: reserved for hypervisor use. This is still not | |
92 | * completely accurate as xen pv guests don't see that CPUID bit set but | |
93 | * that's good enough as they don't land on the BSP path anyway. | |
94 | */ | |
309aac77 | 95 | if (native_cpuid_ecx(1) & BIT(31)) |
a15a7535 BP |
96 | return *res; |
97 | ||
98 | if (cmdline_find_option_bool(cmdline, option) <= 0) | |
99 | *res = false; | |
fe055896 BP |
100 | |
101 | return *res; | |
102 | } | |
103 | ||
104 | extern struct builtin_fw __start_builtin_fw[]; | |
105 | extern struct builtin_fw __end_builtin_fw[]; | |
106 | ||
107 | bool get_builtin_firmware(struct cpio_data *cd, const char *name) | |
108 | { | |
109 | #ifdef CONFIG_FW_LOADER | |
110 | struct builtin_fw *b_fw; | |
111 | ||
112 | for (b_fw = __start_builtin_fw; b_fw != __end_builtin_fw; b_fw++) { | |
113 | if (!strcmp(name, b_fw->name)) { | |
114 | cd->size = b_fw->size; | |
115 | cd->data = b_fw->data; | |
116 | return true; | |
117 | } | |
118 | } | |
119 | #endif | |
120 | return false; | |
121 | } | |
122 | ||
123 | void __init load_ucode_bsp(void) | |
124 | { | |
7a93a40b | 125 | unsigned int cpuid_1_eax; |
fe055896 BP |
126 | |
127 | if (check_loader_disabled_bsp()) | |
128 | return; | |
129 | ||
309aac77 | 130 | cpuid_1_eax = native_cpuid_eax(1); |
fe055896 | 131 | |
7a93a40b | 132 | switch (x86_cpuid_vendor()) { |
fe055896 | 133 | case X86_VENDOR_INTEL: |
309aac77 | 134 | if (x86_family(cpuid_1_eax) >= 6) |
fe055896 BP |
135 | load_ucode_intel_bsp(); |
136 | break; | |
137 | case X86_VENDOR_AMD: | |
309aac77 BP |
138 | if (x86_family(cpuid_1_eax) >= 0x10) |
139 | load_ucode_amd_bsp(cpuid_1_eax); | |
fe055896 BP |
140 | break; |
141 | default: | |
142 | break; | |
143 | } | |
144 | } | |
145 | ||
146 | static bool check_loader_disabled_ap(void) | |
147 | { | |
148 | #ifdef CONFIG_X86_32 | |
149 | return *((bool *)__pa_nodebug(&dis_ucode_ldr)); | |
150 | #else | |
151 | return dis_ucode_ldr; | |
152 | #endif | |
153 | } | |
154 | ||
155 | void load_ucode_ap(void) | |
156 | { | |
7a93a40b | 157 | unsigned int cpuid_1_eax; |
fe055896 BP |
158 | |
159 | if (check_loader_disabled_ap()) | |
160 | return; | |
161 | ||
309aac77 | 162 | cpuid_1_eax = native_cpuid_eax(1); |
fe055896 | 163 | |
7a93a40b | 164 | switch (x86_cpuid_vendor()) { |
fe055896 | 165 | case X86_VENDOR_INTEL: |
309aac77 | 166 | if (x86_family(cpuid_1_eax) >= 6) |
fe055896 BP |
167 | load_ucode_intel_ap(); |
168 | break; | |
169 | case X86_VENDOR_AMD: | |
309aac77 BP |
170 | if (x86_family(cpuid_1_eax) >= 0x10) |
171 | load_ucode_amd_ap(cpuid_1_eax); | |
fe055896 BP |
172 | break; |
173 | default: | |
174 | break; | |
175 | } | |
176 | } | |
177 | ||
4b703305 | 178 | static int __init save_microcode_in_initrd(void) |
fe055896 BP |
179 | { |
180 | struct cpuinfo_x86 *c = &boot_cpu_data; | |
181 | ||
182 | switch (c->x86_vendor) { | |
183 | case X86_VENDOR_INTEL: | |
184 | if (c->x86 >= 6) | |
fa6788b8 | 185 | return save_microcode_in_initrd_intel(); |
fe055896 BP |
186 | break; |
187 | case X86_VENDOR_AMD: | |
188 | if (c->x86 >= 0x10) | |
309aac77 | 189 | return save_microcode_in_initrd_amd(cpuid_eax(1)); |
fe055896 BP |
190 | break; |
191 | default: | |
192 | break; | |
193 | } | |
194 | ||
fa6788b8 | 195 | return -EINVAL; |
fe055896 BP |
196 | } |
197 | ||
06b8534c BP |
198 | struct cpio_data find_microcode_in_initrd(const char *path, bool use_pa) |
199 | { | |
200 | #ifdef CONFIG_BLK_DEV_INITRD | |
201 | unsigned long start = 0; | |
202 | size_t size; | |
203 | ||
204 | #ifdef CONFIG_X86_32 | |
205 | struct boot_params *params; | |
206 | ||
207 | if (use_pa) | |
208 | params = (struct boot_params *)__pa_nodebug(&boot_params); | |
209 | else | |
210 | params = &boot_params; | |
211 | ||
212 | size = params->hdr.ramdisk_size; | |
213 | ||
214 | /* | |
215 | * Set start only if we have an initrd image. We cannot use initrd_start | |
216 | * because it is not set that early yet. | |
217 | */ | |
218 | if (size) | |
219 | start = params->hdr.ramdisk_image; | |
220 | ||
221 | # else /* CONFIG_X86_64 */ | |
222 | size = (unsigned long)boot_params.ext_ramdisk_size << 32; | |
223 | size |= boot_params.hdr.ramdisk_size; | |
224 | ||
225 | if (size) { | |
226 | start = (unsigned long)boot_params.ext_ramdisk_image << 32; | |
227 | start |= boot_params.hdr.ramdisk_image; | |
228 | ||
229 | start += PAGE_OFFSET; | |
230 | } | |
231 | # endif | |
232 | ||
233 | /* | |
8877ebdd BP |
234 | * Fixup the start address: after reserve_initrd() runs, initrd_start |
235 | * has the virtual address of the beginning of the initrd. It also | |
236 | * possibly relocates the ramdisk. In either case, initrd_start contains | |
237 | * the updated address so use that instead. | |
06b8534c | 238 | */ |
8877ebdd | 239 | if (!use_pa && initrd_start) |
06b8534c BP |
240 | start = initrd_start; |
241 | ||
242 | return find_cpio_data(path, (void *)start, size, NULL); | |
243 | #else /* !CONFIG_BLK_DEV_INITRD */ | |
244 | return (struct cpio_data){ NULL, 0, "" }; | |
245 | #endif | |
246 | } | |
247 | ||
fe055896 BP |
248 | void reload_early_microcode(void) |
249 | { | |
250 | int vendor, family; | |
251 | ||
99f925ce BP |
252 | vendor = x86_cpuid_vendor(); |
253 | family = x86_cpuid_family(); | |
fe055896 BP |
254 | |
255 | switch (vendor) { | |
256 | case X86_VENDOR_INTEL: | |
257 | if (family >= 6) | |
258 | reload_ucode_intel(); | |
259 | break; | |
260 | case X86_VENDOR_AMD: | |
261 | if (family >= 0x10) | |
262 | reload_ucode_amd(); | |
263 | break; | |
264 | default: | |
265 | break; | |
266 | } | |
267 | } | |
268 | ||
871b72dd DA |
269 | static void collect_cpu_info_local(void *arg) |
270 | { | |
271 | struct cpu_info_ctx *ctx = arg; | |
272 | ||
273 | ctx->err = microcode_ops->collect_cpu_info(smp_processor_id(), | |
274 | ctx->cpu_sig); | |
275 | } | |
276 | ||
277 | static int collect_cpu_info_on_target(int cpu, struct cpu_signature *cpu_sig) | |
278 | { | |
279 | struct cpu_info_ctx ctx = { .cpu_sig = cpu_sig, .err = 0 }; | |
280 | int ret; | |
281 | ||
282 | ret = smp_call_function_single(cpu, collect_cpu_info_local, &ctx, 1); | |
283 | if (!ret) | |
284 | ret = ctx.err; | |
285 | ||
286 | return ret; | |
287 | } | |
288 | ||
289 | static int collect_cpu_info(int cpu) | |
290 | { | |
291 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
292 | int ret; | |
293 | ||
294 | memset(uci, 0, sizeof(*uci)); | |
295 | ||
296 | ret = collect_cpu_info_on_target(cpu, &uci->cpu_sig); | |
297 | if (!ret) | |
298 | uci->valid = 1; | |
299 | ||
300 | return ret; | |
301 | } | |
302 | ||
303 | struct apply_microcode_ctx { | |
304 | int err; | |
305 | }; | |
306 | ||
307 | static void apply_microcode_local(void *arg) | |
308 | { | |
309 | struct apply_microcode_ctx *ctx = arg; | |
310 | ||
311 | ctx->err = microcode_ops->apply_microcode(smp_processor_id()); | |
312 | } | |
313 | ||
314 | static int apply_microcode_on_target(int cpu) | |
315 | { | |
316 | struct apply_microcode_ctx ctx = { .err = 0 }; | |
317 | int ret; | |
318 | ||
319 | ret = smp_call_function_single(cpu, apply_microcode_local, &ctx, 1); | |
320 | if (!ret) | |
321 | ret = ctx.err; | |
322 | ||
323 | return ret; | |
324 | } | |
325 | ||
3e135d88 | 326 | #ifdef CONFIG_MICROCODE_OLD_INTERFACE |
a0a29b62 | 327 | static int do_microcode_update(const void __user *buf, size_t size) |
3e135d88 | 328 | { |
3e135d88 | 329 | int error = 0; |
3e135d88 | 330 | int cpu; |
6f66cbc6 | 331 | |
a0a29b62 DA |
332 | for_each_online_cpu(cpu) { |
333 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
871b72dd | 334 | enum ucode_state ustate; |
a0a29b62 DA |
335 | |
336 | if (!uci->valid) | |
337 | continue; | |
6f66cbc6 | 338 | |
871b72dd DA |
339 | ustate = microcode_ops->request_microcode_user(cpu, buf, size); |
340 | if (ustate == UCODE_ERROR) { | |
341 | error = -1; | |
342 | break; | |
343 | } else if (ustate == UCODE_OK) | |
344 | apply_microcode_on_target(cpu); | |
3e135d88 | 345 | } |
871b72dd | 346 | |
3e135d88 PO |
347 | return error; |
348 | } | |
349 | ||
3f10940e | 350 | static int microcode_open(struct inode *inode, struct file *file) |
3e135d88 | 351 | { |
3f10940e | 352 | return capable(CAP_SYS_RAWIO) ? nonseekable_open(inode, file) : -EPERM; |
3e135d88 PO |
353 | } |
354 | ||
d33dcb9e PO |
355 | static ssize_t microcode_write(struct file *file, const char __user *buf, |
356 | size_t len, loff_t *ppos) | |
3e135d88 | 357 | { |
871b72dd | 358 | ssize_t ret = -EINVAL; |
3e135d88 | 359 | |
4481374c | 360 | if ((len >> PAGE_SHIFT) > totalram_pages) { |
f58e1f53 | 361 | pr_err("too much data (max %ld pages)\n", totalram_pages); |
871b72dd | 362 | return ret; |
3e135d88 PO |
363 | } |
364 | ||
365 | get_online_cpus(); | |
366 | mutex_lock(µcode_mutex); | |
367 | ||
871b72dd | 368 | if (do_microcode_update(buf, len) == 0) |
3e135d88 PO |
369 | ret = (ssize_t)len; |
370 | ||
e3e45c01 SE |
371 | if (ret > 0) |
372 | perf_check_microcode(); | |
373 | ||
3e135d88 PO |
374 | mutex_unlock(µcode_mutex); |
375 | put_online_cpus(); | |
376 | ||
377 | return ret; | |
378 | } | |
379 | ||
380 | static const struct file_operations microcode_fops = { | |
871b72dd DA |
381 | .owner = THIS_MODULE, |
382 | .write = microcode_write, | |
383 | .open = microcode_open, | |
6038f373 | 384 | .llseek = no_llseek, |
3e135d88 PO |
385 | }; |
386 | ||
387 | static struct miscdevice microcode_dev = { | |
871b72dd DA |
388 | .minor = MICROCODE_MINOR, |
389 | .name = "microcode", | |
e454cea2 | 390 | .nodename = "cpu/microcode", |
871b72dd | 391 | .fops = µcode_fops, |
3e135d88 PO |
392 | }; |
393 | ||
d33dcb9e | 394 | static int __init microcode_dev_init(void) |
3e135d88 PO |
395 | { |
396 | int error; | |
397 | ||
398 | error = misc_register(µcode_dev); | |
399 | if (error) { | |
f58e1f53 | 400 | pr_err("can't misc_register on minor=%d\n", MICROCODE_MINOR); |
3e135d88 PO |
401 | return error; |
402 | } | |
403 | ||
404 | return 0; | |
405 | } | |
406 | ||
bd399063 | 407 | static void __exit microcode_dev_exit(void) |
3e135d88 PO |
408 | { |
409 | misc_deregister(µcode_dev); | |
410 | } | |
3e135d88 | 411 | #else |
4bae1967 IM |
412 | #define microcode_dev_init() 0 |
413 | #define microcode_dev_exit() do { } while (0) | |
3e135d88 PO |
414 | #endif |
415 | ||
416 | /* fake device for request_firmware */ | |
4bae1967 | 417 | static struct platform_device *microcode_pdev; |
3e135d88 | 418 | |
871b72dd | 419 | static int reload_for_cpu(int cpu) |
af5c820a | 420 | { |
871b72dd | 421 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
4dbf32c3 | 422 | enum ucode_state ustate; |
af5c820a RR |
423 | int err = 0; |
424 | ||
4dbf32c3 BP |
425 | if (!uci->valid) |
426 | return err; | |
871b72dd | 427 | |
48e30685 | 428 | ustate = microcode_ops->request_microcode_fw(cpu, µcode_pdev->dev, true); |
4dbf32c3 BP |
429 | if (ustate == UCODE_OK) |
430 | apply_microcode_on_target(cpu); | |
431 | else | |
432 | if (ustate == UCODE_ERROR) | |
433 | err = -EINVAL; | |
af5c820a RR |
434 | return err; |
435 | } | |
436 | ||
8a25a2fd KS |
437 | static ssize_t reload_store(struct device *dev, |
438 | struct device_attribute *attr, | |
871b72dd | 439 | const char *buf, size_t size) |
3e135d88 | 440 | { |
871b72dd | 441 | unsigned long val; |
c9fc3f77 BP |
442 | int cpu; |
443 | ssize_t ret = 0, tmp_ret; | |
444 | ||
e826abd5 SK |
445 | ret = kstrtoul(buf, 0, &val); |
446 | if (ret) | |
447 | return ret; | |
871b72dd | 448 | |
c9fc3f77 BP |
449 | if (val != 1) |
450 | return size; | |
451 | ||
452 | get_online_cpus(); | |
c93dc84c | 453 | mutex_lock(µcode_mutex); |
c9fc3f77 BP |
454 | for_each_online_cpu(cpu) { |
455 | tmp_ret = reload_for_cpu(cpu); | |
456 | if (tmp_ret != 0) | |
457 | pr_warn("Error reloading microcode on CPU %d\n", cpu); | |
458 | ||
459 | /* save retval of the first encountered reload error */ | |
460 | if (!ret) | |
461 | ret = tmp_ret; | |
3e135d88 | 462 | } |
c93dc84c PZ |
463 | if (!ret) |
464 | perf_check_microcode(); | |
465 | mutex_unlock(µcode_mutex); | |
c9fc3f77 | 466 | put_online_cpus(); |
871b72dd DA |
467 | |
468 | if (!ret) | |
469 | ret = size; | |
470 | ||
471 | return ret; | |
3e135d88 PO |
472 | } |
473 | ||
8a25a2fd KS |
474 | static ssize_t version_show(struct device *dev, |
475 | struct device_attribute *attr, char *buf) | |
3e135d88 PO |
476 | { |
477 | struct ucode_cpu_info *uci = ucode_cpu_info + dev->id; | |
478 | ||
d45de409 | 479 | return sprintf(buf, "0x%x\n", uci->cpu_sig.rev); |
3e135d88 PO |
480 | } |
481 | ||
8a25a2fd KS |
482 | static ssize_t pf_show(struct device *dev, |
483 | struct device_attribute *attr, char *buf) | |
3e135d88 PO |
484 | { |
485 | struct ucode_cpu_info *uci = ucode_cpu_info + dev->id; | |
486 | ||
d45de409 | 487 | return sprintf(buf, "0x%x\n", uci->cpu_sig.pf); |
3e135d88 PO |
488 | } |
489 | ||
8a25a2fd KS |
490 | static DEVICE_ATTR(reload, 0200, NULL, reload_store); |
491 | static DEVICE_ATTR(version, 0400, version_show, NULL); | |
492 | static DEVICE_ATTR(processor_flags, 0400, pf_show, NULL); | |
3e135d88 PO |
493 | |
494 | static struct attribute *mc_default_attrs[] = { | |
8a25a2fd KS |
495 | &dev_attr_version.attr, |
496 | &dev_attr_processor_flags.attr, | |
3e135d88 PO |
497 | NULL |
498 | }; | |
499 | ||
500 | static struct attribute_group mc_attr_group = { | |
871b72dd DA |
501 | .attrs = mc_default_attrs, |
502 | .name = "microcode", | |
3e135d88 PO |
503 | }; |
504 | ||
871b72dd | 505 | static void microcode_fini_cpu(int cpu) |
d45de409 | 506 | { |
06b8534c BP |
507 | if (microcode_ops->microcode_fini_cpu) |
508 | microcode_ops->microcode_fini_cpu(cpu); | |
280a9ca5 DA |
509 | } |
510 | ||
871b72dd | 511 | static enum ucode_state microcode_resume_cpu(int cpu) |
d45de409 | 512 | { |
bb9d3e47 BP |
513 | if (apply_microcode_on_target(cpu)) |
514 | return UCODE_ERROR; | |
871b72dd | 515 | |
6b14b818 BP |
516 | pr_debug("CPU%d updated upon resume\n", cpu); |
517 | ||
871b72dd | 518 | return UCODE_OK; |
d45de409 DA |
519 | } |
520 | ||
48e30685 | 521 | static enum ucode_state microcode_init_cpu(int cpu, bool refresh_fw) |
d45de409 | 522 | { |
871b72dd | 523 | enum ucode_state ustate; |
9cd4d78e FY |
524 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
525 | ||
43858f57 | 526 | if (uci->valid) |
9cd4d78e | 527 | return UCODE_OK; |
d45de409 | 528 | |
871b72dd DA |
529 | if (collect_cpu_info(cpu)) |
530 | return UCODE_ERROR; | |
d45de409 | 531 | |
871b72dd DA |
532 | /* --dimm. Trigger a delayed update? */ |
533 | if (system_state != SYSTEM_RUNNING) | |
534 | return UCODE_NFOUND; | |
d45de409 | 535 | |
48e30685 BP |
536 | ustate = microcode_ops->request_microcode_fw(cpu, µcode_pdev->dev, |
537 | refresh_fw); | |
d45de409 | 538 | |
871b72dd | 539 | if (ustate == UCODE_OK) { |
f58e1f53 | 540 | pr_debug("CPU%d updated upon init\n", cpu); |
871b72dd | 541 | apply_microcode_on_target(cpu); |
d45de409 DA |
542 | } |
543 | ||
871b72dd | 544 | return ustate; |
d45de409 DA |
545 | } |
546 | ||
871b72dd | 547 | static enum ucode_state microcode_update_cpu(int cpu) |
d45de409 | 548 | { |
871b72dd | 549 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
d45de409 | 550 | |
7f709d0c BP |
551 | /* Refresh CPU microcode revision after resume. */ |
552 | collect_cpu_info(cpu); | |
553 | ||
2f99f5c8 | 554 | if (uci->valid) |
bb9d3e47 | 555 | return microcode_resume_cpu(cpu); |
d45de409 | 556 | |
48e30685 | 557 | return microcode_init_cpu(cpu, false); |
d45de409 DA |
558 | } |
559 | ||
8a25a2fd | 560 | static int mc_device_add(struct device *dev, struct subsys_interface *sif) |
3e135d88 | 561 | { |
8a25a2fd | 562 | int err, cpu = dev->id; |
3e135d88 PO |
563 | |
564 | if (!cpu_online(cpu)) | |
565 | return 0; | |
566 | ||
f58e1f53 | 567 | pr_debug("CPU%d added\n", cpu); |
3e135d88 | 568 | |
8a25a2fd | 569 | err = sysfs_create_group(&dev->kobj, &mc_attr_group); |
3e135d88 PO |
570 | if (err) |
571 | return err; | |
572 | ||
48e30685 | 573 | if (microcode_init_cpu(cpu, true) == UCODE_ERROR) |
6c53cbfc | 574 | return -EINVAL; |
af5c820a RR |
575 | |
576 | return err; | |
3e135d88 PO |
577 | } |
578 | ||
71db87ba | 579 | static void mc_device_remove(struct device *dev, struct subsys_interface *sif) |
3e135d88 | 580 | { |
8a25a2fd | 581 | int cpu = dev->id; |
3e135d88 PO |
582 | |
583 | if (!cpu_online(cpu)) | |
71db87ba | 584 | return; |
3e135d88 | 585 | |
f58e1f53 | 586 | pr_debug("CPU%d removed\n", cpu); |
d45de409 | 587 | microcode_fini_cpu(cpu); |
8a25a2fd | 588 | sysfs_remove_group(&dev->kobj, &mc_attr_group); |
3e135d88 PO |
589 | } |
590 | ||
8a25a2fd KS |
591 | static struct subsys_interface mc_cpu_interface = { |
592 | .name = "microcode", | |
593 | .subsys = &cpu_subsys, | |
594 | .add_dev = mc_device_add, | |
595 | .remove_dev = mc_device_remove, | |
f3c6ea1b RW |
596 | }; |
597 | ||
598 | /** | |
599 | * mc_bp_resume - Update boot CPU microcode during resume. | |
600 | */ | |
601 | static void mc_bp_resume(void) | |
3e135d88 | 602 | { |
f3c6ea1b | 603 | int cpu = smp_processor_id(); |
871b72dd | 604 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
3e135d88 | 605 | |
871b72dd DA |
606 | if (uci->valid && uci->mc) |
607 | microcode_ops->apply_microcode(cpu); | |
fb86b973 | 608 | else if (!uci->mc) |
fbae4ba8 | 609 | reload_early_microcode(); |
3e135d88 PO |
610 | } |
611 | ||
f3c6ea1b RW |
612 | static struct syscore_ops mc_syscore_ops = { |
613 | .resume = mc_bp_resume, | |
3e135d88 PO |
614 | }; |
615 | ||
29bd7fbc | 616 | static int mc_cpu_online(unsigned int cpu) |
3e135d88 | 617 | { |
8a25a2fd | 618 | struct device *dev; |
3e135d88 | 619 | |
8a25a2fd | 620 | dev = get_cpu_device(cpu); |
29bd7fbc SAS |
621 | microcode_update_cpu(cpu); |
622 | pr_debug("CPU%d added\n", cpu); | |
09c3f0d8 | 623 | |
29bd7fbc SAS |
624 | if (sysfs_create_group(&dev->kobj, &mc_attr_group)) |
625 | pr_err("Failed to create group for CPU%d\n", cpu); | |
626 | return 0; | |
627 | } | |
09c3f0d8 | 628 | |
29bd7fbc SAS |
629 | static int mc_cpu_down_prep(unsigned int cpu) |
630 | { | |
631 | struct device *dev; | |
70989449 | 632 | |
29bd7fbc SAS |
633 | dev = get_cpu_device(cpu); |
634 | /* Suspend is in progress, only remove the interface */ | |
635 | sysfs_remove_group(&dev->kobj, &mc_attr_group); | |
636 | pr_debug("CPU%d removed\n", cpu); | |
06b8534c | 637 | |
29bd7fbc | 638 | return 0; |
3e135d88 PO |
639 | } |
640 | ||
3d8986bc BP |
641 | static struct attribute *cpu_root_microcode_attrs[] = { |
642 | &dev_attr_reload.attr, | |
643 | NULL | |
644 | }; | |
645 | ||
646 | static struct attribute_group cpu_root_microcode_group = { | |
647 | .name = "microcode", | |
648 | .attrs = cpu_root_microcode_attrs, | |
649 | }; | |
650 | ||
9a2bc335 | 651 | int __init microcode_init(void) |
3e135d88 | 652 | { |
9a2bc335 | 653 | struct cpuinfo_x86 *c = &boot_cpu_data; |
3e135d88 PO |
654 | int error; |
655 | ||
84aba677 | 656 | if (dis_ucode_ldr) |
da63865a | 657 | return -EINVAL; |
65cef131 | 658 | |
18dbc916 DA |
659 | if (c->x86_vendor == X86_VENDOR_INTEL) |
660 | microcode_ops = init_intel_microcode(); | |
82b07865 | 661 | else if (c->x86_vendor == X86_VENDOR_AMD) |
18dbc916 | 662 | microcode_ops = init_amd_microcode(); |
283c1f25 | 663 | else |
f58e1f53 | 664 | pr_err("no support for this CPU vendor\n"); |
283c1f25 AH |
665 | |
666 | if (!microcode_ops) | |
18dbc916 | 667 | return -ENODEV; |
3e135d88 | 668 | |
3e135d88 PO |
669 | microcode_pdev = platform_device_register_simple("microcode", -1, |
670 | NULL, 0); | |
bd399063 | 671 | if (IS_ERR(microcode_pdev)) |
3e135d88 | 672 | return PTR_ERR(microcode_pdev); |
3e135d88 PO |
673 | |
674 | get_online_cpus(); | |
871b72dd DA |
675 | mutex_lock(µcode_mutex); |
676 | ||
8a25a2fd | 677 | error = subsys_interface_register(&mc_cpu_interface); |
c93dc84c PZ |
678 | if (!error) |
679 | perf_check_microcode(); | |
871b72dd | 680 | mutex_unlock(µcode_mutex); |
3e135d88 | 681 | put_online_cpus(); |
871b72dd | 682 | |
bd399063 SB |
683 | if (error) |
684 | goto out_pdev; | |
3e135d88 | 685 | |
3d8986bc BP |
686 | error = sysfs_create_group(&cpu_subsys.dev_root->kobj, |
687 | &cpu_root_microcode_group); | |
688 | ||
689 | if (error) { | |
690 | pr_err("Error creating microcode group!\n"); | |
691 | goto out_driver; | |
692 | } | |
693 | ||
871b72dd DA |
694 | error = microcode_dev_init(); |
695 | if (error) | |
3d8986bc | 696 | goto out_ucode_group; |
871b72dd | 697 | |
f3c6ea1b | 698 | register_syscore_ops(&mc_syscore_ops); |
29bd7fbc SAS |
699 | cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/microcode:online", |
700 | mc_cpu_online, mc_cpu_down_prep); | |
8d86f390 | 701 | |
14cfbe55 | 702 | pr_info("Microcode Update Driver: v%s.", DRIVER_VERSION); |
8d86f390 | 703 | |
3e135d88 | 704 | return 0; |
bd399063 | 705 | |
3d8986bc BP |
706 | out_ucode_group: |
707 | sysfs_remove_group(&cpu_subsys.dev_root->kobj, | |
708 | &cpu_root_microcode_group); | |
709 | ||
710 | out_driver: | |
bd399063 SB |
711 | get_online_cpus(); |
712 | mutex_lock(µcode_mutex); | |
713 | ||
ff4b8a57 | 714 | subsys_interface_unregister(&mc_cpu_interface); |
bd399063 SB |
715 | |
716 | mutex_unlock(µcode_mutex); | |
717 | put_online_cpus(); | |
718 | ||
3d8986bc | 719 | out_pdev: |
bd399063 SB |
720 | platform_device_unregister(microcode_pdev); |
721 | return error; | |
722 | ||
3e135d88 | 723 | } |
4b703305 | 724 | fs_initcall(save_microcode_in_initrd); |
2d5be37d | 725 | late_initcall(microcode_init); |