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[mirror_ubuntu-artful-kernel.git] / arch / x86 / kernel / cpu / microcode / core.c
CommitLineData
3e135d88 1/*
6b44e72a 2 * CPU Microcode Update Driver for Linux
3e135d88 3 *
cea58224 4 * Copyright (C) 2000-2006 Tigran Aivazian <aivazian.tigran@gmail.com>
6b44e72a 5 * 2006 Shaohua Li <shaohua.li@intel.com>
14cfbe55 6 * 2013-2016 Borislav Petkov <bp@alien8.de>
3e135d88 7 *
fe055896
BP
8 * X86 CPU microcode early update for Linux:
9 *
10 * Copyright (C) 2012 Fenghua Yu <fenghua.yu@intel.com>
11 * H Peter Anvin" <hpa@zytor.com>
12 * (C) 2015 Borislav Petkov <bp@alien8.de>
13 *
6b44e72a 14 * This driver allows to upgrade microcode on x86 processors.
3e135d88 15 *
6b44e72a
BP
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License
18 * as published by the Free Software Foundation; either version
19 * 2 of the License, or (at your option) any later version.
3e135d88 20 */
f58e1f53 21
6b26e1bf 22#define pr_fmt(fmt) "microcode: " fmt
f58e1f53 23
4bae1967 24#include <linux/platform_device.h>
fe055896 25#include <linux/syscore_ops.h>
4bae1967 26#include <linux/miscdevice.h>
871b72dd 27#include <linux/capability.h>
fe055896 28#include <linux/firmware.h>
4bae1967 29#include <linux/kernel.h>
3e135d88
PO
30#include <linux/mutex.h>
31#include <linux/cpu.h>
4bae1967
IM
32#include <linux/fs.h>
33#include <linux/mm.h>
3e135d88 34
fe055896 35#include <asm/microcode_intel.h>
78ff123b 36#include <asm/cpu_device_id.h>
fe055896 37#include <asm/microcode_amd.h>
c93dc84c 38#include <asm/perf_event.h>
fe055896
BP
39#include <asm/microcode.h>
40#include <asm/processor.h>
41#include <asm/cmdline.h>
06b8534c 42#include <asm/setup.h>
3e135d88 43
14cfbe55 44#define DRIVER_VERSION "2.2"
3e135d88 45
4bae1967 46static struct microcode_ops *microcode_ops;
a15a7535 47static bool dis_ucode_ldr = true;
6b26e1bf 48
24c25032
BP
49bool initrd_gone;
50
058dc498
BP
51LIST_HEAD(microcode_cache);
52
871b72dd
DA
53/*
54 * Synchronization.
55 *
56 * All non cpu-hotplug-callback call sites use:
57 *
58 * - microcode_mutex to synchronize with each other;
59 * - get/put_online_cpus() to synchronize with
60 * the cpu-hotplug-callback call sites.
61 *
62 * We guarantee that only a single cpu is being
63 * updated at any particular moment of time.
64 */
d45de409 65static DEFINE_MUTEX(microcode_mutex);
3e135d88 66
4bae1967 67struct ucode_cpu_info ucode_cpu_info[NR_CPUS];
3e135d88 68
871b72dd
DA
69struct cpu_info_ctx {
70 struct cpu_signature *cpu_sig;
71 int err;
72};
73
f3ad136d
BP
74/*
75 * Those patch levels cannot be updated to newer ones and thus should be final.
76 */
77static u32 final_levels[] = {
78 0x01000098,
79 0x0100009f,
80 0x010000af,
81 0, /* T-101 terminator */
82};
83
84/*
85 * Check the current patch level on this CPU.
86 *
87 * Returns:
88 * - true: if update should stop
89 * - false: otherwise
90 */
91static bool amd_check_current_patch_level(void)
92{
93 u32 lvl, dummy, i;
94 u32 *levels;
95
96 native_rdmsr(MSR_AMD64_PATCH_LEVEL, lvl, dummy);
97
98 if (IS_ENABLED(CONFIG_X86_32))
99 levels = (u32 *)__pa_nodebug(&final_levels);
100 else
101 levels = final_levels;
102
103 for (i = 0; levels[i]; i++) {
104 if (lvl == levels[i])
105 return true;
106 }
107 return false;
108}
109
fe055896
BP
110static bool __init check_loader_disabled_bsp(void)
111{
e8c8165e
BP
112 static const char *__dis_opt_str = "dis_ucode_ldr";
113
fe055896
BP
114#ifdef CONFIG_X86_32
115 const char *cmdline = (const char *)__pa_nodebug(boot_command_line);
e8c8165e 116 const char *option = (const char *)__pa_nodebug(__dis_opt_str);
fe055896
BP
117 bool *res = (bool *)__pa_nodebug(&dis_ucode_ldr);
118
119#else /* CONFIG_X86_64 */
120 const char *cmdline = boot_command_line;
e8c8165e 121 const char *option = __dis_opt_str;
fe055896
BP
122 bool *res = &dis_ucode_ldr;
123#endif
124
a15a7535
BP
125 if (!have_cpuid_p())
126 return *res;
127
a15a7535
BP
128 /*
129 * CPUID(1).ECX[31]: reserved for hypervisor use. This is still not
130 * completely accurate as xen pv guests don't see that CPUID bit set but
131 * that's good enough as they don't land on the BSP path anyway.
132 */
309aac77 133 if (native_cpuid_ecx(1) & BIT(31))
a15a7535
BP
134 return *res;
135
f3ad136d
BP
136 if (x86_cpuid_vendor() == X86_VENDOR_AMD) {
137 if (amd_check_current_patch_level())
138 return *res;
139 }
140
a15a7535
BP
141 if (cmdline_find_option_bool(cmdline, option) <= 0)
142 *res = false;
fe055896
BP
143
144 return *res;
145}
146
147extern struct builtin_fw __start_builtin_fw[];
148extern struct builtin_fw __end_builtin_fw[];
149
150bool get_builtin_firmware(struct cpio_data *cd, const char *name)
151{
152#ifdef CONFIG_FW_LOADER
153 struct builtin_fw *b_fw;
154
155 for (b_fw = __start_builtin_fw; b_fw != __end_builtin_fw; b_fw++) {
156 if (!strcmp(name, b_fw->name)) {
157 cd->size = b_fw->size;
158 cd->data = b_fw->data;
159 return true;
160 }
161 }
162#endif
163 return false;
164}
165
166void __init load_ucode_bsp(void)
167{
7a93a40b 168 unsigned int cpuid_1_eax;
fe055896
BP
169
170 if (check_loader_disabled_bsp())
171 return;
172
309aac77 173 cpuid_1_eax = native_cpuid_eax(1);
fe055896 174
7a93a40b 175 switch (x86_cpuid_vendor()) {
fe055896 176 case X86_VENDOR_INTEL:
309aac77 177 if (x86_family(cpuid_1_eax) >= 6)
fe055896
BP
178 load_ucode_intel_bsp();
179 break;
180 case X86_VENDOR_AMD:
309aac77
BP
181 if (x86_family(cpuid_1_eax) >= 0x10)
182 load_ucode_amd_bsp(cpuid_1_eax);
fe055896
BP
183 break;
184 default:
185 break;
186 }
187}
188
189static bool check_loader_disabled_ap(void)
190{
191#ifdef CONFIG_X86_32
192 return *((bool *)__pa_nodebug(&dis_ucode_ldr));
193#else
194 return dis_ucode_ldr;
195#endif
196}
197
198void load_ucode_ap(void)
199{
7a93a40b 200 unsigned int cpuid_1_eax;
fe055896
BP
201
202 if (check_loader_disabled_ap())
203 return;
204
309aac77 205 cpuid_1_eax = native_cpuid_eax(1);
fe055896 206
7a93a40b 207 switch (x86_cpuid_vendor()) {
fe055896 208 case X86_VENDOR_INTEL:
309aac77 209 if (x86_family(cpuid_1_eax) >= 6)
fe055896
BP
210 load_ucode_intel_ap();
211 break;
212 case X86_VENDOR_AMD:
309aac77
BP
213 if (x86_family(cpuid_1_eax) >= 0x10)
214 load_ucode_amd_ap(cpuid_1_eax);
fe055896
BP
215 break;
216 default:
217 break;
218 }
219}
220
4b703305 221static int __init save_microcode_in_initrd(void)
fe055896
BP
222{
223 struct cpuinfo_x86 *c = &boot_cpu_data;
24c25032 224 int ret = -EINVAL;
fe055896
BP
225
226 switch (c->x86_vendor) {
227 case X86_VENDOR_INTEL:
228 if (c->x86 >= 6)
24c25032 229 ret = save_microcode_in_initrd_intel();
fe055896
BP
230 break;
231 case X86_VENDOR_AMD:
232 if (c->x86 >= 0x10)
309aac77 233 return save_microcode_in_initrd_amd(cpuid_eax(1));
fe055896
BP
234 break;
235 default:
236 break;
237 }
238
24c25032
BP
239 initrd_gone = true;
240
241 return ret;
fe055896
BP
242}
243
06b8534c
BP
244struct cpio_data find_microcode_in_initrd(const char *path, bool use_pa)
245{
246#ifdef CONFIG_BLK_DEV_INITRD
247 unsigned long start = 0;
248 size_t size;
249
250#ifdef CONFIG_X86_32
251 struct boot_params *params;
252
253 if (use_pa)
254 params = (struct boot_params *)__pa_nodebug(&boot_params);
255 else
256 params = &boot_params;
257
258 size = params->hdr.ramdisk_size;
259
260 /*
261 * Set start only if we have an initrd image. We cannot use initrd_start
262 * because it is not set that early yet.
263 */
264 if (size)
265 start = params->hdr.ramdisk_image;
266
267# else /* CONFIG_X86_64 */
268 size = (unsigned long)boot_params.ext_ramdisk_size << 32;
269 size |= boot_params.hdr.ramdisk_size;
270
271 if (size) {
272 start = (unsigned long)boot_params.ext_ramdisk_image << 32;
273 start |= boot_params.hdr.ramdisk_image;
274
275 start += PAGE_OFFSET;
276 }
277# endif
278
279 /*
8877ebdd
BP
280 * Fixup the start address: after reserve_initrd() runs, initrd_start
281 * has the virtual address of the beginning of the initrd. It also
282 * possibly relocates the ramdisk. In either case, initrd_start contains
283 * the updated address so use that instead.
24c25032
BP
284 *
285 * initrd_gone is for the hotplug case where we've thrown out initrd
286 * already.
06b8534c 287 */
24c25032
BP
288 if (!use_pa) {
289 if (initrd_gone)
290 return (struct cpio_data){ NULL, 0, "" };
291 if (initrd_start)
292 start = initrd_start;
a3d98c93
BP
293 } else {
294 /*
295 * The picture with physical addresses is a bit different: we
296 * need to get the *physical* address to which the ramdisk was
297 * relocated, i.e., relocated_ramdisk (not initrd_start) and
298 * since we're running from physical addresses, we need to access
299 * relocated_ramdisk through its *physical* address too.
300 */
301 u64 *rr = (u64 *)__pa_nodebug(&relocated_ramdisk);
302 if (*rr)
303 start = *rr;
24c25032 304 }
06b8534c
BP
305
306 return find_cpio_data(path, (void *)start, size, NULL);
307#else /* !CONFIG_BLK_DEV_INITRD */
308 return (struct cpio_data){ NULL, 0, "" };
309#endif
310}
311
fe055896
BP
312void reload_early_microcode(void)
313{
314 int vendor, family;
315
99f925ce
BP
316 vendor = x86_cpuid_vendor();
317 family = x86_cpuid_family();
fe055896
BP
318
319 switch (vendor) {
320 case X86_VENDOR_INTEL:
321 if (family >= 6)
322 reload_ucode_intel();
323 break;
324 case X86_VENDOR_AMD:
325 if (family >= 0x10)
326 reload_ucode_amd();
327 break;
328 default:
329 break;
330 }
331}
332
871b72dd
DA
333static void collect_cpu_info_local(void *arg)
334{
335 struct cpu_info_ctx *ctx = arg;
336
337 ctx->err = microcode_ops->collect_cpu_info(smp_processor_id(),
338 ctx->cpu_sig);
339}
340
341static int collect_cpu_info_on_target(int cpu, struct cpu_signature *cpu_sig)
342{
343 struct cpu_info_ctx ctx = { .cpu_sig = cpu_sig, .err = 0 };
344 int ret;
345
346 ret = smp_call_function_single(cpu, collect_cpu_info_local, &ctx, 1);
347 if (!ret)
348 ret = ctx.err;
349
350 return ret;
351}
352
353static int collect_cpu_info(int cpu)
354{
355 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
356 int ret;
357
358 memset(uci, 0, sizeof(*uci));
359
360 ret = collect_cpu_info_on_target(cpu, &uci->cpu_sig);
361 if (!ret)
362 uci->valid = 1;
363
364 return ret;
365}
366
367struct apply_microcode_ctx {
368 int err;
369};
370
371static void apply_microcode_local(void *arg)
372{
373 struct apply_microcode_ctx *ctx = arg;
374
375 ctx->err = microcode_ops->apply_microcode(smp_processor_id());
376}
377
378static int apply_microcode_on_target(int cpu)
379{
380 struct apply_microcode_ctx ctx = { .err = 0 };
381 int ret;
382
383 ret = smp_call_function_single(cpu, apply_microcode_local, &ctx, 1);
384 if (!ret)
385 ret = ctx.err;
386
387 return ret;
388}
389
3e135d88 390#ifdef CONFIG_MICROCODE_OLD_INTERFACE
a0a29b62 391static int do_microcode_update(const void __user *buf, size_t size)
3e135d88 392{
3e135d88 393 int error = 0;
3e135d88 394 int cpu;
6f66cbc6 395
a0a29b62
DA
396 for_each_online_cpu(cpu) {
397 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
871b72dd 398 enum ucode_state ustate;
a0a29b62
DA
399
400 if (!uci->valid)
401 continue;
6f66cbc6 402
871b72dd
DA
403 ustate = microcode_ops->request_microcode_user(cpu, buf, size);
404 if (ustate == UCODE_ERROR) {
405 error = -1;
406 break;
407 } else if (ustate == UCODE_OK)
408 apply_microcode_on_target(cpu);
3e135d88 409 }
871b72dd 410
3e135d88
PO
411 return error;
412}
413
3f10940e 414static int microcode_open(struct inode *inode, struct file *file)
3e135d88 415{
3f10940e 416 return capable(CAP_SYS_RAWIO) ? nonseekable_open(inode, file) : -EPERM;
3e135d88
PO
417}
418
d33dcb9e
PO
419static ssize_t microcode_write(struct file *file, const char __user *buf,
420 size_t len, loff_t *ppos)
3e135d88 421{
871b72dd 422 ssize_t ret = -EINVAL;
3e135d88 423
4481374c 424 if ((len >> PAGE_SHIFT) > totalram_pages) {
f58e1f53 425 pr_err("too much data (max %ld pages)\n", totalram_pages);
871b72dd 426 return ret;
3e135d88
PO
427 }
428
429 get_online_cpus();
430 mutex_lock(&microcode_mutex);
431
871b72dd 432 if (do_microcode_update(buf, len) == 0)
3e135d88
PO
433 ret = (ssize_t)len;
434
e3e45c01
SE
435 if (ret > 0)
436 perf_check_microcode();
437
3e135d88
PO
438 mutex_unlock(&microcode_mutex);
439 put_online_cpus();
440
441 return ret;
442}
443
444static const struct file_operations microcode_fops = {
871b72dd
DA
445 .owner = THIS_MODULE,
446 .write = microcode_write,
447 .open = microcode_open,
6038f373 448 .llseek = no_llseek,
3e135d88
PO
449};
450
451static struct miscdevice microcode_dev = {
871b72dd
DA
452 .minor = MICROCODE_MINOR,
453 .name = "microcode",
e454cea2 454 .nodename = "cpu/microcode",
871b72dd 455 .fops = &microcode_fops,
3e135d88
PO
456};
457
d33dcb9e 458static int __init microcode_dev_init(void)
3e135d88
PO
459{
460 int error;
461
462 error = misc_register(&microcode_dev);
463 if (error) {
f58e1f53 464 pr_err("can't misc_register on minor=%d\n", MICROCODE_MINOR);
3e135d88
PO
465 return error;
466 }
467
468 return 0;
469}
470
bd399063 471static void __exit microcode_dev_exit(void)
3e135d88
PO
472{
473 misc_deregister(&microcode_dev);
474}
3e135d88 475#else
4bae1967
IM
476#define microcode_dev_init() 0
477#define microcode_dev_exit() do { } while (0)
3e135d88
PO
478#endif
479
480/* fake device for request_firmware */
4bae1967 481static struct platform_device *microcode_pdev;
3e135d88 482
871b72dd 483static int reload_for_cpu(int cpu)
af5c820a 484{
871b72dd 485 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
4dbf32c3 486 enum ucode_state ustate;
af5c820a
RR
487 int err = 0;
488
4dbf32c3
BP
489 if (!uci->valid)
490 return err;
871b72dd 491
48e30685 492 ustate = microcode_ops->request_microcode_fw(cpu, &microcode_pdev->dev, true);
4dbf32c3
BP
493 if (ustate == UCODE_OK)
494 apply_microcode_on_target(cpu);
495 else
496 if (ustate == UCODE_ERROR)
497 err = -EINVAL;
af5c820a
RR
498 return err;
499}
500
8a25a2fd
KS
501static ssize_t reload_store(struct device *dev,
502 struct device_attribute *attr,
871b72dd 503 const char *buf, size_t size)
3e135d88 504{
871b72dd 505 unsigned long val;
c9fc3f77
BP
506 int cpu;
507 ssize_t ret = 0, tmp_ret;
508
e826abd5
SK
509 ret = kstrtoul(buf, 0, &val);
510 if (ret)
511 return ret;
871b72dd 512
c9fc3f77
BP
513 if (val != 1)
514 return size;
515
516 get_online_cpus();
c93dc84c 517 mutex_lock(&microcode_mutex);
c9fc3f77
BP
518 for_each_online_cpu(cpu) {
519 tmp_ret = reload_for_cpu(cpu);
520 if (tmp_ret != 0)
521 pr_warn("Error reloading microcode on CPU %d\n", cpu);
522
523 /* save retval of the first encountered reload error */
524 if (!ret)
525 ret = tmp_ret;
3e135d88 526 }
c93dc84c
PZ
527 if (!ret)
528 perf_check_microcode();
529 mutex_unlock(&microcode_mutex);
c9fc3f77 530 put_online_cpus();
871b72dd
DA
531
532 if (!ret)
533 ret = size;
534
535 return ret;
3e135d88
PO
536}
537
8a25a2fd
KS
538static ssize_t version_show(struct device *dev,
539 struct device_attribute *attr, char *buf)
3e135d88
PO
540{
541 struct ucode_cpu_info *uci = ucode_cpu_info + dev->id;
542
d45de409 543 return sprintf(buf, "0x%x\n", uci->cpu_sig.rev);
3e135d88
PO
544}
545
8a25a2fd
KS
546static ssize_t pf_show(struct device *dev,
547 struct device_attribute *attr, char *buf)
3e135d88
PO
548{
549 struct ucode_cpu_info *uci = ucode_cpu_info + dev->id;
550
d45de409 551 return sprintf(buf, "0x%x\n", uci->cpu_sig.pf);
3e135d88
PO
552}
553
8a25a2fd
KS
554static DEVICE_ATTR(reload, 0200, NULL, reload_store);
555static DEVICE_ATTR(version, 0400, version_show, NULL);
556static DEVICE_ATTR(processor_flags, 0400, pf_show, NULL);
3e135d88
PO
557
558static struct attribute *mc_default_attrs[] = {
8a25a2fd
KS
559 &dev_attr_version.attr,
560 &dev_attr_processor_flags.attr,
3e135d88
PO
561 NULL
562};
563
45bd07ad 564static const struct attribute_group mc_attr_group = {
871b72dd
DA
565 .attrs = mc_default_attrs,
566 .name = "microcode",
3e135d88
PO
567};
568
871b72dd 569static void microcode_fini_cpu(int cpu)
d45de409 570{
06b8534c
BP
571 if (microcode_ops->microcode_fini_cpu)
572 microcode_ops->microcode_fini_cpu(cpu);
280a9ca5
DA
573}
574
871b72dd 575static enum ucode_state microcode_resume_cpu(int cpu)
d45de409 576{
bb9d3e47
BP
577 if (apply_microcode_on_target(cpu))
578 return UCODE_ERROR;
871b72dd 579
6b14b818
BP
580 pr_debug("CPU%d updated upon resume\n", cpu);
581
871b72dd 582 return UCODE_OK;
d45de409
DA
583}
584
48e30685 585static enum ucode_state microcode_init_cpu(int cpu, bool refresh_fw)
d45de409 586{
871b72dd 587 enum ucode_state ustate;
9cd4d78e
FY
588 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
589
43858f57 590 if (uci->valid)
9cd4d78e 591 return UCODE_OK;
d45de409 592
871b72dd
DA
593 if (collect_cpu_info(cpu))
594 return UCODE_ERROR;
d45de409 595
871b72dd
DA
596 /* --dimm. Trigger a delayed update? */
597 if (system_state != SYSTEM_RUNNING)
598 return UCODE_NFOUND;
d45de409 599
48e30685
BP
600 ustate = microcode_ops->request_microcode_fw(cpu, &microcode_pdev->dev,
601 refresh_fw);
d45de409 602
871b72dd 603 if (ustate == UCODE_OK) {
f58e1f53 604 pr_debug("CPU%d updated upon init\n", cpu);
871b72dd 605 apply_microcode_on_target(cpu);
d45de409
DA
606 }
607
871b72dd 608 return ustate;
d45de409
DA
609}
610
871b72dd 611static enum ucode_state microcode_update_cpu(int cpu)
d45de409 612{
871b72dd 613 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
d45de409 614
7f709d0c
BP
615 /* Refresh CPU microcode revision after resume. */
616 collect_cpu_info(cpu);
617
2f99f5c8 618 if (uci->valid)
bb9d3e47 619 return microcode_resume_cpu(cpu);
d45de409 620
48e30685 621 return microcode_init_cpu(cpu, false);
d45de409
DA
622}
623
8a25a2fd 624static int mc_device_add(struct device *dev, struct subsys_interface *sif)
3e135d88 625{
8a25a2fd 626 int err, cpu = dev->id;
3e135d88
PO
627
628 if (!cpu_online(cpu))
629 return 0;
630
f58e1f53 631 pr_debug("CPU%d added\n", cpu);
3e135d88 632
8a25a2fd 633 err = sysfs_create_group(&dev->kobj, &mc_attr_group);
3e135d88
PO
634 if (err)
635 return err;
636
48e30685 637 if (microcode_init_cpu(cpu, true) == UCODE_ERROR)
6c53cbfc 638 return -EINVAL;
af5c820a
RR
639
640 return err;
3e135d88
PO
641}
642
71db87ba 643static void mc_device_remove(struct device *dev, struct subsys_interface *sif)
3e135d88 644{
8a25a2fd 645 int cpu = dev->id;
3e135d88
PO
646
647 if (!cpu_online(cpu))
71db87ba 648 return;
3e135d88 649
f58e1f53 650 pr_debug("CPU%d removed\n", cpu);
d45de409 651 microcode_fini_cpu(cpu);
8a25a2fd 652 sysfs_remove_group(&dev->kobj, &mc_attr_group);
3e135d88
PO
653}
654
8a25a2fd
KS
655static struct subsys_interface mc_cpu_interface = {
656 .name = "microcode",
657 .subsys = &cpu_subsys,
658 .add_dev = mc_device_add,
659 .remove_dev = mc_device_remove,
f3c6ea1b
RW
660};
661
662/**
663 * mc_bp_resume - Update boot CPU microcode during resume.
664 */
665static void mc_bp_resume(void)
3e135d88 666{
f3c6ea1b 667 int cpu = smp_processor_id();
871b72dd 668 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
3e135d88 669
871b72dd
DA
670 if (uci->valid && uci->mc)
671 microcode_ops->apply_microcode(cpu);
fb86b973 672 else if (!uci->mc)
fbae4ba8 673 reload_early_microcode();
3e135d88
PO
674}
675
f3c6ea1b
RW
676static struct syscore_ops mc_syscore_ops = {
677 .resume = mc_bp_resume,
3e135d88
PO
678};
679
29bd7fbc 680static int mc_cpu_online(unsigned int cpu)
3e135d88 681{
8a25a2fd 682 struct device *dev;
3e135d88 683
8a25a2fd 684 dev = get_cpu_device(cpu);
29bd7fbc
SAS
685 microcode_update_cpu(cpu);
686 pr_debug("CPU%d added\n", cpu);
09c3f0d8 687
29bd7fbc
SAS
688 if (sysfs_create_group(&dev->kobj, &mc_attr_group))
689 pr_err("Failed to create group for CPU%d\n", cpu);
690 return 0;
691}
09c3f0d8 692
29bd7fbc
SAS
693static int mc_cpu_down_prep(unsigned int cpu)
694{
695 struct device *dev;
70989449 696
29bd7fbc
SAS
697 dev = get_cpu_device(cpu);
698 /* Suspend is in progress, only remove the interface */
699 sysfs_remove_group(&dev->kobj, &mc_attr_group);
700 pr_debug("CPU%d removed\n", cpu);
06b8534c 701
29bd7fbc 702 return 0;
3e135d88
PO
703}
704
3d8986bc
BP
705static struct attribute *cpu_root_microcode_attrs[] = {
706 &dev_attr_reload.attr,
707 NULL
708};
709
45bd07ad 710static const struct attribute_group cpu_root_microcode_group = {
3d8986bc
BP
711 .name = "microcode",
712 .attrs = cpu_root_microcode_attrs,
713};
714
9a2bc335 715int __init microcode_init(void)
3e135d88 716{
9a2bc335 717 struct cpuinfo_x86 *c = &boot_cpu_data;
3e135d88
PO
718 int error;
719
84aba677 720 if (dis_ucode_ldr)
da63865a 721 return -EINVAL;
65cef131 722
18dbc916
DA
723 if (c->x86_vendor == X86_VENDOR_INTEL)
724 microcode_ops = init_intel_microcode();
82b07865 725 else if (c->x86_vendor == X86_VENDOR_AMD)
18dbc916 726 microcode_ops = init_amd_microcode();
283c1f25 727 else
f58e1f53 728 pr_err("no support for this CPU vendor\n");
283c1f25
AH
729
730 if (!microcode_ops)
18dbc916 731 return -ENODEV;
3e135d88 732
3e135d88
PO
733 microcode_pdev = platform_device_register_simple("microcode", -1,
734 NULL, 0);
bd399063 735 if (IS_ERR(microcode_pdev))
3e135d88 736 return PTR_ERR(microcode_pdev);
3e135d88
PO
737
738 get_online_cpus();
871b72dd
DA
739 mutex_lock(&microcode_mutex);
740
8a25a2fd 741 error = subsys_interface_register(&mc_cpu_interface);
c93dc84c
PZ
742 if (!error)
743 perf_check_microcode();
871b72dd 744 mutex_unlock(&microcode_mutex);
3e135d88 745 put_online_cpus();
871b72dd 746
bd399063
SB
747 if (error)
748 goto out_pdev;
3e135d88 749
3d8986bc
BP
750 error = sysfs_create_group(&cpu_subsys.dev_root->kobj,
751 &cpu_root_microcode_group);
752
753 if (error) {
754 pr_err("Error creating microcode group!\n");
755 goto out_driver;
756 }
757
871b72dd
DA
758 error = microcode_dev_init();
759 if (error)
3d8986bc 760 goto out_ucode_group;
871b72dd 761
f3c6ea1b 762 register_syscore_ops(&mc_syscore_ops);
29bd7fbc
SAS
763 cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/microcode:online",
764 mc_cpu_online, mc_cpu_down_prep);
8d86f390 765
14cfbe55 766 pr_info("Microcode Update Driver: v%s.", DRIVER_VERSION);
8d86f390 767
3e135d88 768 return 0;
bd399063 769
3d8986bc
BP
770 out_ucode_group:
771 sysfs_remove_group(&cpu_subsys.dev_root->kobj,
772 &cpu_root_microcode_group);
773
774 out_driver:
bd399063
SB
775 get_online_cpus();
776 mutex_lock(&microcode_mutex);
777
ff4b8a57 778 subsys_interface_unregister(&mc_cpu_interface);
bd399063
SB
779
780 mutex_unlock(&microcode_mutex);
781 put_online_cpus();
782
3d8986bc 783 out_pdev:
bd399063
SB
784 platform_device_unregister(microcode_pdev);
785 return error;
786
3e135d88 787}
4b703305 788fs_initcall(save_microcode_in_initrd);
2d5be37d 789late_initcall(microcode_init);