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Commit | Line | Data |
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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
3e135d88 | 2 | /* |
6b44e72a | 3 | * CPU Microcode Update Driver for Linux |
3e135d88 | 4 | * |
cea58224 | 5 | * Copyright (C) 2000-2006 Tigran Aivazian <aivazian.tigran@gmail.com> |
6b44e72a | 6 | * 2006 Shaohua Li <shaohua.li@intel.com> |
14cfbe55 | 7 | * 2013-2016 Borislav Petkov <bp@alien8.de> |
3e135d88 | 8 | * |
fe055896 BP |
9 | * X86 CPU microcode early update for Linux: |
10 | * | |
11 | * Copyright (C) 2012 Fenghua Yu <fenghua.yu@intel.com> | |
12 | * H Peter Anvin" <hpa@zytor.com> | |
13 | * (C) 2015 Borislav Petkov <bp@alien8.de> | |
14 | * | |
6b44e72a | 15 | * This driver allows to upgrade microcode on x86 processors. |
3e135d88 | 16 | */ |
f58e1f53 | 17 | |
6b26e1bf | 18 | #define pr_fmt(fmt) "microcode: " fmt |
f58e1f53 | 19 | |
4bae1967 | 20 | #include <linux/platform_device.h> |
a5321aec | 21 | #include <linux/stop_machine.h> |
fe055896 | 22 | #include <linux/syscore_ops.h> |
4bae1967 | 23 | #include <linux/miscdevice.h> |
871b72dd | 24 | #include <linux/capability.h> |
fe055896 | 25 | #include <linux/firmware.h> |
4bae1967 | 26 | #include <linux/kernel.h> |
a5321aec | 27 | #include <linux/delay.h> |
3e135d88 PO |
28 | #include <linux/mutex.h> |
29 | #include <linux/cpu.h> | |
a5321aec | 30 | #include <linux/nmi.h> |
4bae1967 IM |
31 | #include <linux/fs.h> |
32 | #include <linux/mm.h> | |
3e135d88 | 33 | |
fe055896 | 34 | #include <asm/microcode_intel.h> |
78ff123b | 35 | #include <asm/cpu_device_id.h> |
fe055896 | 36 | #include <asm/microcode_amd.h> |
c93dc84c | 37 | #include <asm/perf_event.h> |
fe055896 BP |
38 | #include <asm/microcode.h> |
39 | #include <asm/processor.h> | |
40 | #include <asm/cmdline.h> | |
06b8534c | 41 | #include <asm/setup.h> |
3e135d88 | 42 | |
14cfbe55 | 43 | #define DRIVER_VERSION "2.2" |
3e135d88 | 44 | |
4bae1967 | 45 | static struct microcode_ops *microcode_ops; |
a15a7535 | 46 | static bool dis_ucode_ldr = true; |
6b26e1bf | 47 | |
24c25032 BP |
48 | bool initrd_gone; |
49 | ||
058dc498 BP |
50 | LIST_HEAD(microcode_cache); |
51 | ||
871b72dd DA |
52 | /* |
53 | * Synchronization. | |
54 | * | |
55 | * All non cpu-hotplug-callback call sites use: | |
56 | * | |
57 | * - microcode_mutex to synchronize with each other; | |
2089f34f | 58 | * - cpus_read_lock/unlock() to synchronize with |
871b72dd DA |
59 | * the cpu-hotplug-callback call sites. |
60 | * | |
61 | * We guarantee that only a single cpu is being | |
62 | * updated at any particular moment of time. | |
63 | */ | |
d45de409 | 64 | static DEFINE_MUTEX(microcode_mutex); |
3e135d88 | 65 | |
4bae1967 | 66 | struct ucode_cpu_info ucode_cpu_info[NR_CPUS]; |
3e135d88 | 67 | |
871b72dd DA |
68 | struct cpu_info_ctx { |
69 | struct cpu_signature *cpu_sig; | |
70 | int err; | |
71 | }; | |
72 | ||
f3ad136d BP |
73 | /* |
74 | * Those patch levels cannot be updated to newer ones and thus should be final. | |
75 | */ | |
76 | static u32 final_levels[] = { | |
77 | 0x01000098, | |
78 | 0x0100009f, | |
79 | 0x010000af, | |
80 | 0, /* T-101 terminator */ | |
81 | }; | |
82 | ||
83 | /* | |
84 | * Check the current patch level on this CPU. | |
85 | * | |
86 | * Returns: | |
87 | * - true: if update should stop | |
88 | * - false: otherwise | |
89 | */ | |
90 | static bool amd_check_current_patch_level(void) | |
91 | { | |
92 | u32 lvl, dummy, i; | |
93 | u32 *levels; | |
94 | ||
95 | native_rdmsr(MSR_AMD64_PATCH_LEVEL, lvl, dummy); | |
96 | ||
97 | if (IS_ENABLED(CONFIG_X86_32)) | |
98 | levels = (u32 *)__pa_nodebug(&final_levels); | |
99 | else | |
100 | levels = final_levels; | |
101 | ||
102 | for (i = 0; levels[i]; i++) { | |
103 | if (lvl == levels[i]) | |
104 | return true; | |
105 | } | |
106 | return false; | |
107 | } | |
108 | ||
fe055896 BP |
109 | static bool __init check_loader_disabled_bsp(void) |
110 | { | |
e8c8165e BP |
111 | static const char *__dis_opt_str = "dis_ucode_ldr"; |
112 | ||
fe055896 BP |
113 | #ifdef CONFIG_X86_32 |
114 | const char *cmdline = (const char *)__pa_nodebug(boot_command_line); | |
e8c8165e | 115 | const char *option = (const char *)__pa_nodebug(__dis_opt_str); |
fe055896 BP |
116 | bool *res = (bool *)__pa_nodebug(&dis_ucode_ldr); |
117 | ||
118 | #else /* CONFIG_X86_64 */ | |
119 | const char *cmdline = boot_command_line; | |
e8c8165e | 120 | const char *option = __dis_opt_str; |
fe055896 BP |
121 | bool *res = &dis_ucode_ldr; |
122 | #endif | |
123 | ||
a15a7535 BP |
124 | /* |
125 | * CPUID(1).ECX[31]: reserved for hypervisor use. This is still not | |
126 | * completely accurate as xen pv guests don't see that CPUID bit set but | |
127 | * that's good enough as they don't land on the BSP path anyway. | |
128 | */ | |
309aac77 | 129 | if (native_cpuid_ecx(1) & BIT(31)) |
a15a7535 BP |
130 | return *res; |
131 | ||
f3ad136d BP |
132 | if (x86_cpuid_vendor() == X86_VENDOR_AMD) { |
133 | if (amd_check_current_patch_level()) | |
134 | return *res; | |
135 | } | |
136 | ||
a15a7535 BP |
137 | if (cmdline_find_option_bool(cmdline, option) <= 0) |
138 | *res = false; | |
fe055896 BP |
139 | |
140 | return *res; | |
141 | } | |
142 | ||
143 | extern struct builtin_fw __start_builtin_fw[]; | |
144 | extern struct builtin_fw __end_builtin_fw[]; | |
145 | ||
146 | bool get_builtin_firmware(struct cpio_data *cd, const char *name) | |
147 | { | |
fe055896 BP |
148 | struct builtin_fw *b_fw; |
149 | ||
150 | for (b_fw = __start_builtin_fw; b_fw != __end_builtin_fw; b_fw++) { | |
151 | if (!strcmp(name, b_fw->name)) { | |
152 | cd->size = b_fw->size; | |
153 | cd->data = b_fw->data; | |
154 | return true; | |
155 | } | |
156 | } | |
fe055896 BP |
157 | return false; |
158 | } | |
159 | ||
160 | void __init load_ucode_bsp(void) | |
161 | { | |
7a93a40b | 162 | unsigned int cpuid_1_eax; |
1f161f67 | 163 | bool intel = true; |
fe055896 | 164 | |
1f161f67 | 165 | if (!have_cpuid_p()) |
fe055896 BP |
166 | return; |
167 | ||
309aac77 | 168 | cpuid_1_eax = native_cpuid_eax(1); |
fe055896 | 169 | |
7a93a40b | 170 | switch (x86_cpuid_vendor()) { |
fe055896 | 171 | case X86_VENDOR_INTEL: |
1f161f67 BP |
172 | if (x86_family(cpuid_1_eax) < 6) |
173 | return; | |
fe055896 | 174 | break; |
1f161f67 | 175 | |
fe055896 | 176 | case X86_VENDOR_AMD: |
1f161f67 BP |
177 | if (x86_family(cpuid_1_eax) < 0x10) |
178 | return; | |
179 | intel = false; | |
fe055896 | 180 | break; |
1f161f67 | 181 | |
fe055896 | 182 | default: |
1f161f67 | 183 | return; |
fe055896 | 184 | } |
1f161f67 BP |
185 | |
186 | if (check_loader_disabled_bsp()) | |
187 | return; | |
188 | ||
189 | if (intel) | |
190 | load_ucode_intel_bsp(); | |
191 | else | |
192 | load_ucode_amd_bsp(cpuid_1_eax); | |
fe055896 BP |
193 | } |
194 | ||
195 | static bool check_loader_disabled_ap(void) | |
196 | { | |
197 | #ifdef CONFIG_X86_32 | |
198 | return *((bool *)__pa_nodebug(&dis_ucode_ldr)); | |
199 | #else | |
200 | return dis_ucode_ldr; | |
201 | #endif | |
202 | } | |
203 | ||
204 | void load_ucode_ap(void) | |
205 | { | |
7a93a40b | 206 | unsigned int cpuid_1_eax; |
fe055896 BP |
207 | |
208 | if (check_loader_disabled_ap()) | |
209 | return; | |
210 | ||
309aac77 | 211 | cpuid_1_eax = native_cpuid_eax(1); |
fe055896 | 212 | |
7a93a40b | 213 | switch (x86_cpuid_vendor()) { |
fe055896 | 214 | case X86_VENDOR_INTEL: |
309aac77 | 215 | if (x86_family(cpuid_1_eax) >= 6) |
fe055896 BP |
216 | load_ucode_intel_ap(); |
217 | break; | |
218 | case X86_VENDOR_AMD: | |
309aac77 BP |
219 | if (x86_family(cpuid_1_eax) >= 0x10) |
220 | load_ucode_amd_ap(cpuid_1_eax); | |
fe055896 BP |
221 | break; |
222 | default: | |
223 | break; | |
224 | } | |
225 | } | |
226 | ||
4b703305 | 227 | static int __init save_microcode_in_initrd(void) |
fe055896 BP |
228 | { |
229 | struct cpuinfo_x86 *c = &boot_cpu_data; | |
24c25032 | 230 | int ret = -EINVAL; |
fe055896 BP |
231 | |
232 | switch (c->x86_vendor) { | |
233 | case X86_VENDOR_INTEL: | |
234 | if (c->x86 >= 6) | |
24c25032 | 235 | ret = save_microcode_in_initrd_intel(); |
fe055896 BP |
236 | break; |
237 | case X86_VENDOR_AMD: | |
238 | if (c->x86 >= 0x10) | |
1d080f09 | 239 | ret = save_microcode_in_initrd_amd(cpuid_eax(1)); |
fe055896 BP |
240 | break; |
241 | default: | |
242 | break; | |
243 | } | |
244 | ||
24c25032 BP |
245 | initrd_gone = true; |
246 | ||
247 | return ret; | |
fe055896 BP |
248 | } |
249 | ||
06b8534c BP |
250 | struct cpio_data find_microcode_in_initrd(const char *path, bool use_pa) |
251 | { | |
252 | #ifdef CONFIG_BLK_DEV_INITRD | |
253 | unsigned long start = 0; | |
254 | size_t size; | |
255 | ||
256 | #ifdef CONFIG_X86_32 | |
257 | struct boot_params *params; | |
258 | ||
259 | if (use_pa) | |
260 | params = (struct boot_params *)__pa_nodebug(&boot_params); | |
261 | else | |
262 | params = &boot_params; | |
263 | ||
264 | size = params->hdr.ramdisk_size; | |
265 | ||
266 | /* | |
267 | * Set start only if we have an initrd image. We cannot use initrd_start | |
268 | * because it is not set that early yet. | |
269 | */ | |
270 | if (size) | |
271 | start = params->hdr.ramdisk_image; | |
272 | ||
273 | # else /* CONFIG_X86_64 */ | |
274 | size = (unsigned long)boot_params.ext_ramdisk_size << 32; | |
275 | size |= boot_params.hdr.ramdisk_size; | |
276 | ||
277 | if (size) { | |
278 | start = (unsigned long)boot_params.ext_ramdisk_image << 32; | |
279 | start |= boot_params.hdr.ramdisk_image; | |
280 | ||
281 | start += PAGE_OFFSET; | |
282 | } | |
283 | # endif | |
284 | ||
285 | /* | |
8877ebdd BP |
286 | * Fixup the start address: after reserve_initrd() runs, initrd_start |
287 | * has the virtual address of the beginning of the initrd. It also | |
288 | * possibly relocates the ramdisk. In either case, initrd_start contains | |
289 | * the updated address so use that instead. | |
24c25032 BP |
290 | * |
291 | * initrd_gone is for the hotplug case where we've thrown out initrd | |
292 | * already. | |
06b8534c | 293 | */ |
24c25032 BP |
294 | if (!use_pa) { |
295 | if (initrd_gone) | |
296 | return (struct cpio_data){ NULL, 0, "" }; | |
297 | if (initrd_start) | |
298 | start = initrd_start; | |
a3d98c93 BP |
299 | } else { |
300 | /* | |
301 | * The picture with physical addresses is a bit different: we | |
302 | * need to get the *physical* address to which the ramdisk was | |
303 | * relocated, i.e., relocated_ramdisk (not initrd_start) and | |
304 | * since we're running from physical addresses, we need to access | |
305 | * relocated_ramdisk through its *physical* address too. | |
306 | */ | |
307 | u64 *rr = (u64 *)__pa_nodebug(&relocated_ramdisk); | |
308 | if (*rr) | |
309 | start = *rr; | |
24c25032 | 310 | } |
06b8534c BP |
311 | |
312 | return find_cpio_data(path, (void *)start, size, NULL); | |
313 | #else /* !CONFIG_BLK_DEV_INITRD */ | |
314 | return (struct cpio_data){ NULL, 0, "" }; | |
315 | #endif | |
316 | } | |
317 | ||
fe055896 BP |
318 | void reload_early_microcode(void) |
319 | { | |
320 | int vendor, family; | |
321 | ||
99f925ce BP |
322 | vendor = x86_cpuid_vendor(); |
323 | family = x86_cpuid_family(); | |
fe055896 BP |
324 | |
325 | switch (vendor) { | |
326 | case X86_VENDOR_INTEL: | |
327 | if (family >= 6) | |
328 | reload_ucode_intel(); | |
329 | break; | |
330 | case X86_VENDOR_AMD: | |
331 | if (family >= 0x10) | |
332 | reload_ucode_amd(); | |
333 | break; | |
334 | default: | |
335 | break; | |
336 | } | |
337 | } | |
338 | ||
871b72dd DA |
339 | static void collect_cpu_info_local(void *arg) |
340 | { | |
341 | struct cpu_info_ctx *ctx = arg; | |
342 | ||
343 | ctx->err = microcode_ops->collect_cpu_info(smp_processor_id(), | |
344 | ctx->cpu_sig); | |
345 | } | |
346 | ||
347 | static int collect_cpu_info_on_target(int cpu, struct cpu_signature *cpu_sig) | |
348 | { | |
349 | struct cpu_info_ctx ctx = { .cpu_sig = cpu_sig, .err = 0 }; | |
350 | int ret; | |
351 | ||
352 | ret = smp_call_function_single(cpu, collect_cpu_info_local, &ctx, 1); | |
353 | if (!ret) | |
354 | ret = ctx.err; | |
355 | ||
356 | return ret; | |
357 | } | |
358 | ||
359 | static int collect_cpu_info(int cpu) | |
360 | { | |
361 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
362 | int ret; | |
363 | ||
364 | memset(uci, 0, sizeof(*uci)); | |
365 | ||
366 | ret = collect_cpu_info_on_target(cpu, &uci->cpu_sig); | |
367 | if (!ret) | |
368 | uci->valid = 1; | |
369 | ||
370 | return ret; | |
371 | } | |
372 | ||
871b72dd DA |
373 | static void apply_microcode_local(void *arg) |
374 | { | |
854857f5 | 375 | enum ucode_state *err = arg; |
871b72dd | 376 | |
854857f5 | 377 | *err = microcode_ops->apply_microcode(smp_processor_id()); |
871b72dd DA |
378 | } |
379 | ||
380 | static int apply_microcode_on_target(int cpu) | |
381 | { | |
854857f5 | 382 | enum ucode_state err; |
871b72dd DA |
383 | int ret; |
384 | ||
854857f5 BP |
385 | ret = smp_call_function_single(cpu, apply_microcode_local, &err, 1); |
386 | if (!ret) { | |
387 | if (err == UCODE_ERROR) | |
388 | ret = 1; | |
389 | } | |
871b72dd DA |
390 | return ret; |
391 | } | |
392 | ||
3e135d88 | 393 | #ifdef CONFIG_MICROCODE_OLD_INTERFACE |
a0a29b62 | 394 | static int do_microcode_update(const void __user *buf, size_t size) |
3e135d88 | 395 | { |
3e135d88 | 396 | int error = 0; |
3e135d88 | 397 | int cpu; |
6f66cbc6 | 398 | |
a0a29b62 DA |
399 | for_each_online_cpu(cpu) { |
400 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
871b72dd | 401 | enum ucode_state ustate; |
a0a29b62 DA |
402 | |
403 | if (!uci->valid) | |
404 | continue; | |
6f66cbc6 | 405 | |
871b72dd DA |
406 | ustate = microcode_ops->request_microcode_user(cpu, buf, size); |
407 | if (ustate == UCODE_ERROR) { | |
408 | error = -1; | |
409 | break; | |
24613a04 | 410 | } else if (ustate == UCODE_NEW) { |
871b72dd | 411 | apply_microcode_on_target(cpu); |
24613a04 | 412 | } |
3e135d88 | 413 | } |
871b72dd | 414 | |
3e135d88 PO |
415 | return error; |
416 | } | |
417 | ||
3f10940e | 418 | static int microcode_open(struct inode *inode, struct file *file) |
3e135d88 | 419 | { |
c5bf68fe | 420 | return capable(CAP_SYS_RAWIO) ? stream_open(inode, file) : -EPERM; |
3e135d88 PO |
421 | } |
422 | ||
d33dcb9e PO |
423 | static ssize_t microcode_write(struct file *file, const char __user *buf, |
424 | size_t len, loff_t *ppos) | |
3e135d88 | 425 | { |
871b72dd | 426 | ssize_t ret = -EINVAL; |
ca79b0c2 | 427 | unsigned long nr_pages = totalram_pages(); |
3e135d88 | 428 | |
3d6357de AK |
429 | if ((len >> PAGE_SHIFT) > nr_pages) { |
430 | pr_err("too much data (max %ld pages)\n", nr_pages); | |
871b72dd | 431 | return ret; |
3e135d88 PO |
432 | } |
433 | ||
2089f34f | 434 | cpus_read_lock(); |
3e135d88 PO |
435 | mutex_lock(µcode_mutex); |
436 | ||
871b72dd | 437 | if (do_microcode_update(buf, len) == 0) |
3e135d88 PO |
438 | ret = (ssize_t)len; |
439 | ||
e3e45c01 SE |
440 | if (ret > 0) |
441 | perf_check_microcode(); | |
442 | ||
3e135d88 | 443 | mutex_unlock(µcode_mutex); |
2089f34f | 444 | cpus_read_unlock(); |
3e135d88 PO |
445 | |
446 | return ret; | |
447 | } | |
448 | ||
449 | static const struct file_operations microcode_fops = { | |
871b72dd DA |
450 | .owner = THIS_MODULE, |
451 | .write = microcode_write, | |
452 | .open = microcode_open, | |
6038f373 | 453 | .llseek = no_llseek, |
3e135d88 PO |
454 | }; |
455 | ||
456 | static struct miscdevice microcode_dev = { | |
871b72dd DA |
457 | .minor = MICROCODE_MINOR, |
458 | .name = "microcode", | |
e454cea2 | 459 | .nodename = "cpu/microcode", |
871b72dd | 460 | .fops = µcode_fops, |
3e135d88 PO |
461 | }; |
462 | ||
d33dcb9e | 463 | static int __init microcode_dev_init(void) |
3e135d88 PO |
464 | { |
465 | int error; | |
466 | ||
467 | error = misc_register(µcode_dev); | |
468 | if (error) { | |
f58e1f53 | 469 | pr_err("can't misc_register on minor=%d\n", MICROCODE_MINOR); |
3e135d88 PO |
470 | return error; |
471 | } | |
472 | ||
473 | return 0; | |
474 | } | |
475 | ||
bd399063 | 476 | static void __exit microcode_dev_exit(void) |
3e135d88 PO |
477 | { |
478 | misc_deregister(µcode_dev); | |
479 | } | |
3e135d88 | 480 | #else |
4bae1967 IM |
481 | #define microcode_dev_init() 0 |
482 | #define microcode_dev_exit() do { } while (0) | |
3e135d88 PO |
483 | #endif |
484 | ||
485 | /* fake device for request_firmware */ | |
4bae1967 | 486 | static struct platform_device *microcode_pdev; |
3e135d88 | 487 | |
a5321aec AR |
488 | /* |
489 | * Late loading dance. Why the heavy-handed stomp_machine effort? | |
490 | * | |
491 | * - HT siblings must be idle and not execute other code while the other sibling | |
492 | * is loading microcode in order to avoid any negative interactions caused by | |
493 | * the loading. | |
494 | * | |
495 | * - In addition, microcode update on the cores must be serialized until this | |
496 | * requirement can be relaxed in the future. Right now, this is conservative | |
497 | * and good. | |
498 | */ | |
499 | #define SPINUNIT 100 /* 100 nsec */ | |
500 | ||
30ec26da AR |
501 | static int check_online_cpus(void) |
502 | { | |
07d981ad | 503 | unsigned int cpu; |
30ec26da | 504 | |
07d981ad JP |
505 | /* |
506 | * Make sure all CPUs are online. It's fine for SMT to be disabled if | |
507 | * all the primary threads are still online. | |
508 | */ | |
509 | for_each_present_cpu(cpu) { | |
510 | if (topology_is_primary_thread(cpu) && !cpu_online(cpu)) { | |
511 | pr_err("Not all CPUs online, aborting microcode update.\n"); | |
512 | return -EINVAL; | |
513 | } | |
514 | } | |
30ec26da | 515 | |
07d981ad | 516 | return 0; |
30ec26da AR |
517 | } |
518 | ||
bb8c13d6 BP |
519 | static atomic_t late_cpus_in; |
520 | static atomic_t late_cpus_out; | |
521 | ||
522 | static int __wait_for_cpus(atomic_t *t, long long timeout) | |
523 | { | |
524 | int all_cpus = num_online_cpus(); | |
525 | ||
526 | atomic_inc(t); | |
527 | ||
528 | while (atomic_read(t) < all_cpus) { | |
529 | if (timeout < SPINUNIT) { | |
530 | pr_err("Timeout while waiting for CPUs rendezvous, remaining: %d\n", | |
531 | all_cpus - atomic_read(t)); | |
532 | return 1; | |
533 | } | |
534 | ||
535 | ndelay(SPINUNIT); | |
536 | timeout -= SPINUNIT; | |
537 | ||
538 | touch_nmi_watchdog(); | |
539 | } | |
540 | return 0; | |
541 | } | |
a5321aec AR |
542 | |
543 | /* | |
544 | * Returns: | |
545 | * < 0 - on error | |
9adbf3c6 | 546 | * 0 - success (no update done or microcode was updated) |
a5321aec AR |
547 | */ |
548 | static int __reload_late(void *info) | |
af5c820a | 549 | { |
a5321aec AR |
550 | int cpu = smp_processor_id(); |
551 | enum ucode_state err; | |
552 | int ret = 0; | |
553 | ||
a5321aec AR |
554 | /* |
555 | * Wait for all CPUs to arrive. A load will not be attempted unless all | |
556 | * CPUs show up. | |
557 | * */ | |
bb8c13d6 BP |
558 | if (__wait_for_cpus(&late_cpus_in, NSEC_PER_SEC)) |
559 | return -1; | |
a5321aec | 560 | |
93946a33 AR |
561 | /* |
562 | * On an SMT system, it suffices to load the microcode on one sibling of | |
563 | * the core because the microcode engine is shared between the threads. | |
564 | * Synchronization still needs to take place so that no concurrent | |
565 | * loading attempts happen on multiple threads of an SMT core. See | |
566 | * below. | |
567 | */ | |
568 | if (cpumask_first(topology_sibling_cpumask(cpu)) == cpu) | |
569 | apply_microcode_local(&err); | |
570 | else | |
571 | goto wait_for_siblings; | |
a5321aec | 572 | |
9adbf3c6 MC |
573 | if (err >= UCODE_NFOUND) { |
574 | if (err == UCODE_ERROR) | |
575 | pr_warn("Error reloading microcode on CPU %d\n", cpu); | |
576 | ||
09e182d1 | 577 | ret = -1; |
a5321aec | 578 | } |
af5c820a | 579 | |
93946a33 AR |
580 | wait_for_siblings: |
581 | if (__wait_for_cpus(&late_cpus_out, NSEC_PER_SEC)) | |
582 | panic("Timeout during microcode update!\n"); | |
583 | ||
bb8c13d6 | 584 | /* |
93946a33 AR |
585 | * At least one thread has completed update on each core. |
586 | * For others, simply call the update to make sure the | |
587 | * per-cpu cpuinfo can be updated with right microcode | |
588 | * revision. | |
bb8c13d6 | 589 | */ |
93946a33 AR |
590 | if (cpumask_first(topology_sibling_cpumask(cpu)) != cpu) |
591 | apply_microcode_local(&err); | |
a5321aec AR |
592 | |
593 | return ret; | |
594 | } | |
595 | ||
596 | /* | |
597 | * Reload microcode late on all CPUs. Wait for a sec until they | |
598 | * all gather together. | |
599 | */ | |
600 | static int microcode_reload_late(void) | |
601 | { | |
602 | int ret; | |
603 | ||
bb8c13d6 BP |
604 | atomic_set(&late_cpus_in, 0); |
605 | atomic_set(&late_cpus_out, 0); | |
a5321aec AR |
606 | |
607 | ret = stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask); | |
9adbf3c6 | 608 | if (ret == 0) |
a5321aec AR |
609 | microcode_check(); |
610 | ||
9bd68125 BP |
611 | pr_info("Reload completed, microcode revision: 0x%x\n", boot_cpu_data.microcode); |
612 | ||
a5321aec | 613 | return ret; |
af5c820a RR |
614 | } |
615 | ||
8a25a2fd KS |
616 | static ssize_t reload_store(struct device *dev, |
617 | struct device_attribute *attr, | |
871b72dd | 618 | const char *buf, size_t size) |
3e135d88 | 619 | { |
3f1f576a | 620 | enum ucode_state tmp_ret = UCODE_OK; |
a5321aec | 621 | int bsp = boot_cpu_data.cpu_index; |
871b72dd | 622 | unsigned long val; |
3f1f576a | 623 | ssize_t ret = 0; |
c9fc3f77 | 624 | |
e826abd5 SK |
625 | ret = kstrtoul(buf, 0, &val); |
626 | if (ret) | |
627 | return ret; | |
871b72dd | 628 | |
c9fc3f77 BP |
629 | if (val != 1) |
630 | return size; | |
631 | ||
2089f34f | 632 | cpus_read_lock(); |
30ec26da AR |
633 | |
634 | ret = check_online_cpus(); | |
635 | if (ret) | |
636 | goto put; | |
637 | ||
7189b3c1 OP |
638 | tmp_ret = microcode_ops->request_microcode_fw(bsp, µcode_pdev->dev, true); |
639 | if (tmp_ret != UCODE_NEW) | |
640 | goto put; | |
641 | ||
c93dc84c | 642 | mutex_lock(µcode_mutex); |
a5321aec | 643 | ret = microcode_reload_late(); |
c93dc84c | 644 | mutex_unlock(µcode_mutex); |
30ec26da AR |
645 | |
646 | put: | |
2089f34f | 647 | cpus_read_unlock(); |
871b72dd | 648 | |
9adbf3c6 | 649 | if (ret == 0) |
871b72dd DA |
650 | ret = size; |
651 | ||
652 | return ret; | |
3e135d88 PO |
653 | } |
654 | ||
8a25a2fd KS |
655 | static ssize_t version_show(struct device *dev, |
656 | struct device_attribute *attr, char *buf) | |
3e135d88 PO |
657 | { |
658 | struct ucode_cpu_info *uci = ucode_cpu_info + dev->id; | |
659 | ||
d45de409 | 660 | return sprintf(buf, "0x%x\n", uci->cpu_sig.rev); |
3e135d88 PO |
661 | } |
662 | ||
8a25a2fd KS |
663 | static ssize_t pf_show(struct device *dev, |
664 | struct device_attribute *attr, char *buf) | |
3e135d88 PO |
665 | { |
666 | struct ucode_cpu_info *uci = ucode_cpu_info + dev->id; | |
667 | ||
d45de409 | 668 | return sprintf(buf, "0x%x\n", uci->cpu_sig.pf); |
3e135d88 PO |
669 | } |
670 | ||
6cbaefb4 | 671 | static DEVICE_ATTR_WO(reload); |
f4661d29 JT |
672 | static DEVICE_ATTR(version, 0444, version_show, NULL); |
673 | static DEVICE_ATTR(processor_flags, 0444, pf_show, NULL); | |
3e135d88 PO |
674 | |
675 | static struct attribute *mc_default_attrs[] = { | |
8a25a2fd KS |
676 | &dev_attr_version.attr, |
677 | &dev_attr_processor_flags.attr, | |
3e135d88 PO |
678 | NULL |
679 | }; | |
680 | ||
45bd07ad | 681 | static const struct attribute_group mc_attr_group = { |
871b72dd DA |
682 | .attrs = mc_default_attrs, |
683 | .name = "microcode", | |
3e135d88 PO |
684 | }; |
685 | ||
871b72dd | 686 | static void microcode_fini_cpu(int cpu) |
d45de409 | 687 | { |
06b8534c BP |
688 | if (microcode_ops->microcode_fini_cpu) |
689 | microcode_ops->microcode_fini_cpu(cpu); | |
280a9ca5 DA |
690 | } |
691 | ||
871b72dd | 692 | static enum ucode_state microcode_resume_cpu(int cpu) |
d45de409 | 693 | { |
bb9d3e47 BP |
694 | if (apply_microcode_on_target(cpu)) |
695 | return UCODE_ERROR; | |
871b72dd | 696 | |
6b14b818 BP |
697 | pr_debug("CPU%d updated upon resume\n", cpu); |
698 | ||
871b72dd | 699 | return UCODE_OK; |
d45de409 DA |
700 | } |
701 | ||
48e30685 | 702 | static enum ucode_state microcode_init_cpu(int cpu, bool refresh_fw) |
d45de409 | 703 | { |
871b72dd | 704 | enum ucode_state ustate; |
9cd4d78e FY |
705 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
706 | ||
43858f57 | 707 | if (uci->valid) |
9cd4d78e | 708 | return UCODE_OK; |
d45de409 | 709 | |
871b72dd DA |
710 | if (collect_cpu_info(cpu)) |
711 | return UCODE_ERROR; | |
d45de409 | 712 | |
871b72dd DA |
713 | /* --dimm. Trigger a delayed update? */ |
714 | if (system_state != SYSTEM_RUNNING) | |
715 | return UCODE_NFOUND; | |
d45de409 | 716 | |
2613f36e BP |
717 | ustate = microcode_ops->request_microcode_fw(cpu, µcode_pdev->dev, refresh_fw); |
718 | if (ustate == UCODE_NEW) { | |
f58e1f53 | 719 | pr_debug("CPU%d updated upon init\n", cpu); |
871b72dd | 720 | apply_microcode_on_target(cpu); |
d45de409 DA |
721 | } |
722 | ||
871b72dd | 723 | return ustate; |
d45de409 DA |
724 | } |
725 | ||
871b72dd | 726 | static enum ucode_state microcode_update_cpu(int cpu) |
d45de409 | 727 | { |
871b72dd | 728 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
d45de409 | 729 | |
7f709d0c BP |
730 | /* Refresh CPU microcode revision after resume. */ |
731 | collect_cpu_info(cpu); | |
732 | ||
2f99f5c8 | 733 | if (uci->valid) |
bb9d3e47 | 734 | return microcode_resume_cpu(cpu); |
d45de409 | 735 | |
48e30685 | 736 | return microcode_init_cpu(cpu, false); |
d45de409 DA |
737 | } |
738 | ||
8a25a2fd | 739 | static int mc_device_add(struct device *dev, struct subsys_interface *sif) |
3e135d88 | 740 | { |
8a25a2fd | 741 | int err, cpu = dev->id; |
3e135d88 PO |
742 | |
743 | if (!cpu_online(cpu)) | |
744 | return 0; | |
745 | ||
f58e1f53 | 746 | pr_debug("CPU%d added\n", cpu); |
3e135d88 | 747 | |
8a25a2fd | 748 | err = sysfs_create_group(&dev->kobj, &mc_attr_group); |
3e135d88 PO |
749 | if (err) |
750 | return err; | |
751 | ||
48e30685 | 752 | if (microcode_init_cpu(cpu, true) == UCODE_ERROR) |
6c53cbfc | 753 | return -EINVAL; |
af5c820a RR |
754 | |
755 | return err; | |
3e135d88 PO |
756 | } |
757 | ||
71db87ba | 758 | static void mc_device_remove(struct device *dev, struct subsys_interface *sif) |
3e135d88 | 759 | { |
8a25a2fd | 760 | int cpu = dev->id; |
3e135d88 PO |
761 | |
762 | if (!cpu_online(cpu)) | |
71db87ba | 763 | return; |
3e135d88 | 764 | |
f58e1f53 | 765 | pr_debug("CPU%d removed\n", cpu); |
d45de409 | 766 | microcode_fini_cpu(cpu); |
8a25a2fd | 767 | sysfs_remove_group(&dev->kobj, &mc_attr_group); |
3e135d88 PO |
768 | } |
769 | ||
8a25a2fd KS |
770 | static struct subsys_interface mc_cpu_interface = { |
771 | .name = "microcode", | |
772 | .subsys = &cpu_subsys, | |
773 | .add_dev = mc_device_add, | |
774 | .remove_dev = mc_device_remove, | |
f3c6ea1b RW |
775 | }; |
776 | ||
777 | /** | |
fb347589 | 778 | * microcode_bsp_resume - Update boot CPU microcode during resume. |
f3c6ea1b | 779 | */ |
fb347589 | 780 | void microcode_bsp_resume(void) |
3e135d88 | 781 | { |
f3c6ea1b | 782 | int cpu = smp_processor_id(); |
871b72dd | 783 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
3e135d88 | 784 | |
871b72dd DA |
785 | if (uci->valid && uci->mc) |
786 | microcode_ops->apply_microcode(cpu); | |
fb86b973 | 787 | else if (!uci->mc) |
fbae4ba8 | 788 | reload_early_microcode(); |
3e135d88 PO |
789 | } |
790 | ||
f3c6ea1b | 791 | static struct syscore_ops mc_syscore_ops = { |
fb347589 | 792 | .resume = microcode_bsp_resume, |
3e135d88 PO |
793 | }; |
794 | ||
5423f5ce | 795 | static int mc_cpu_starting(unsigned int cpu) |
3e135d88 | 796 | { |
29bd7fbc SAS |
797 | microcode_update_cpu(cpu); |
798 | pr_debug("CPU%d added\n", cpu); | |
5423f5ce TG |
799 | return 0; |
800 | } | |
801 | ||
802 | static int mc_cpu_online(unsigned int cpu) | |
803 | { | |
804 | struct device *dev = get_cpu_device(cpu); | |
09c3f0d8 | 805 | |
29bd7fbc SAS |
806 | if (sysfs_create_group(&dev->kobj, &mc_attr_group)) |
807 | pr_err("Failed to create group for CPU%d\n", cpu); | |
808 | return 0; | |
809 | } | |
09c3f0d8 | 810 | |
29bd7fbc SAS |
811 | static int mc_cpu_down_prep(unsigned int cpu) |
812 | { | |
813 | struct device *dev; | |
70989449 | 814 | |
29bd7fbc SAS |
815 | dev = get_cpu_device(cpu); |
816 | /* Suspend is in progress, only remove the interface */ | |
817 | sysfs_remove_group(&dev->kobj, &mc_attr_group); | |
818 | pr_debug("CPU%d removed\n", cpu); | |
06b8534c | 819 | |
29bd7fbc | 820 | return 0; |
3e135d88 PO |
821 | } |
822 | ||
3d8986bc BP |
823 | static struct attribute *cpu_root_microcode_attrs[] = { |
824 | &dev_attr_reload.attr, | |
825 | NULL | |
826 | }; | |
827 | ||
45bd07ad | 828 | static const struct attribute_group cpu_root_microcode_group = { |
3d8986bc BP |
829 | .name = "microcode", |
830 | .attrs = cpu_root_microcode_attrs, | |
831 | }; | |
832 | ||
c769dcd4 | 833 | static int __init microcode_init(void) |
3e135d88 | 834 | { |
9a2bc335 | 835 | struct cpuinfo_x86 *c = &boot_cpu_data; |
3e135d88 PO |
836 | int error; |
837 | ||
84aba677 | 838 | if (dis_ucode_ldr) |
da63865a | 839 | return -EINVAL; |
65cef131 | 840 | |
18dbc916 DA |
841 | if (c->x86_vendor == X86_VENDOR_INTEL) |
842 | microcode_ops = init_intel_microcode(); | |
82b07865 | 843 | else if (c->x86_vendor == X86_VENDOR_AMD) |
18dbc916 | 844 | microcode_ops = init_amd_microcode(); |
283c1f25 | 845 | else |
f58e1f53 | 846 | pr_err("no support for this CPU vendor\n"); |
283c1f25 AH |
847 | |
848 | if (!microcode_ops) | |
18dbc916 | 849 | return -ENODEV; |
3e135d88 | 850 | |
3e135d88 PO |
851 | microcode_pdev = platform_device_register_simple("microcode", -1, |
852 | NULL, 0); | |
bd399063 | 853 | if (IS_ERR(microcode_pdev)) |
3e135d88 | 854 | return PTR_ERR(microcode_pdev); |
3e135d88 | 855 | |
2089f34f | 856 | cpus_read_lock(); |
871b72dd DA |
857 | mutex_lock(µcode_mutex); |
858 | ||
8a25a2fd | 859 | error = subsys_interface_register(&mc_cpu_interface); |
c93dc84c PZ |
860 | if (!error) |
861 | perf_check_microcode(); | |
871b72dd | 862 | mutex_unlock(µcode_mutex); |
2089f34f | 863 | cpus_read_unlock(); |
871b72dd | 864 | |
bd399063 SB |
865 | if (error) |
866 | goto out_pdev; | |
3e135d88 | 867 | |
3d8986bc BP |
868 | error = sysfs_create_group(&cpu_subsys.dev_root->kobj, |
869 | &cpu_root_microcode_group); | |
870 | ||
871 | if (error) { | |
872 | pr_err("Error creating microcode group!\n"); | |
873 | goto out_driver; | |
874 | } | |
875 | ||
871b72dd DA |
876 | error = microcode_dev_init(); |
877 | if (error) | |
3d8986bc | 878 | goto out_ucode_group; |
871b72dd | 879 | |
f3c6ea1b | 880 | register_syscore_ops(&mc_syscore_ops); |
5423f5ce TG |
881 | cpuhp_setup_state_nocalls(CPUHP_AP_MICROCODE_LOADER, "x86/microcode:starting", |
882 | mc_cpu_starting, NULL); | |
883 | cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/microcode:online", | |
29bd7fbc | 884 | mc_cpu_online, mc_cpu_down_prep); |
8d86f390 | 885 | |
14cfbe55 | 886 | pr_info("Microcode Update Driver: v%s.", DRIVER_VERSION); |
8d86f390 | 887 | |
3e135d88 | 888 | return 0; |
bd399063 | 889 | |
3d8986bc BP |
890 | out_ucode_group: |
891 | sysfs_remove_group(&cpu_subsys.dev_root->kobj, | |
892 | &cpu_root_microcode_group); | |
893 | ||
894 | out_driver: | |
2089f34f | 895 | cpus_read_lock(); |
bd399063 SB |
896 | mutex_lock(µcode_mutex); |
897 | ||
ff4b8a57 | 898 | subsys_interface_unregister(&mc_cpu_interface); |
bd399063 SB |
899 | |
900 | mutex_unlock(µcode_mutex); | |
2089f34f | 901 | cpus_read_unlock(); |
bd399063 | 902 | |
3d8986bc | 903 | out_pdev: |
bd399063 SB |
904 | platform_device_unregister(microcode_pdev); |
905 | return error; | |
906 | ||
3e135d88 | 907 | } |
4b703305 | 908 | fs_initcall(save_microcode_in_initrd); |
2d5be37d | 909 | late_initcall(microcode_init); |