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x86/microcode/intel: Remove unused arg of get_matching_model_microcode()
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1da177e4 1/*
6b44e72a 2 * Intel CPU Microcode Update Driver for Linux
1da177e4 3 *
6b44e72a
BP
4 * Copyright (C) 2000-2006 Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
5 * 2006 Shaohua Li <shaohua.li@intel.com>
1da177e4 6 *
fe055896
BP
7 * Intel CPU microcode early update for Linux
8 *
9 * Copyright (C) 2012 Fenghua Yu <fenghua.yu@intel.com>
10 * H Peter Anvin" <hpa@zytor.com>
11 *
6b44e72a
BP
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
1da177e4 16 */
f58e1f53 17
fe055896
BP
18/*
19 * This needs to be before all headers so that pr_debug in printk.h doesn't turn
20 * printk calls into no_printk().
21 *
22 *#define DEBUG
23 */
6b26e1bf 24#define pr_fmt(fmt) "microcode: " fmt
f58e1f53 25
fe055896 26#include <linux/earlycpio.h>
4bae1967 27#include <linux/firmware.h>
4bae1967 28#include <linux/uaccess.h>
fe055896
BP
29#include <linux/vmalloc.h>
30#include <linux/initrd.h>
4bae1967 31#include <linux/kernel.h>
fe055896
BP
32#include <linux/slab.h>
33#include <linux/cpu.h>
34#include <linux/mm.h>
1da177e4 35
9cd4d78e 36#include <asm/microcode_intel.h>
4bae1967 37#include <asm/processor.h>
fe055896
BP
38#include <asm/tlbflush.h>
39#include <asm/setup.h>
4bae1967 40#include <asm/msr.h>
1da177e4 41
f8bb45e2
BP
42/*
43 * Temporary microcode blobs pointers storage. We note here the pointers to
44 * microcode blobs we've got from whatever storage (detached initrd, builtin).
45 * Later on, we put those into final storage mc_saved_data.mc_saved.
46 */
47static unsigned long mc_tmp_ptrs[MAX_UCODE_COUNT];
48
fe055896 49static struct mc_saved_data {
4fe9349f 50 unsigned int num_saved;
fe055896
BP
51 struct microcode_intel **mc_saved;
52} mc_saved_data;
53
54static enum ucode_state
55load_microcode_early(struct microcode_intel **saved,
56 unsigned int num_saved, struct ucode_cpu_info *uci)
57{
58 struct microcode_intel *ucode_ptr, *new_mc = NULL;
59 struct microcode_header_intel *mc_hdr;
60 int new_rev, ret, i;
61
62 new_rev = uci->cpu_sig.rev;
63
64 for (i = 0; i < num_saved; i++) {
65 ucode_ptr = saved[i];
66 mc_hdr = (struct microcode_header_intel *)ucode_ptr;
67
68 ret = has_newer_microcode(ucode_ptr,
69 uci->cpu_sig.sig,
70 uci->cpu_sig.pf,
71 new_rev);
72 if (!ret)
73 continue;
74
75 new_rev = mc_hdr->rev;
76 new_mc = ucode_ptr;
77 }
78
79 if (!new_mc)
80 return UCODE_NFOUND;
81
82 uci->mc = (struct microcode_intel *)new_mc;
83 return UCODE_OK;
84}
85
86static inline void
f8bb45e2
BP
87copy_ptrs(struct microcode_intel **mc_saved, unsigned long *mc_ptrs,
88 unsigned long off, int num_saved)
fe055896
BP
89{
90 int i;
91
92 for (i = 0; i < num_saved; i++)
f8bb45e2 93 mc_saved[i] = (struct microcode_intel *)(mc_ptrs[i] + off);
fe055896
BP
94}
95
96#ifdef CONFIG_X86_32
97static void
bd6fe58d 98microcode_phys(struct microcode_intel **mc_saved_tmp, struct mc_saved_data *mcs)
fe055896
BP
99{
100 int i;
101 struct microcode_intel ***mc_saved;
102
bd6fe58d
BP
103 mc_saved = (struct microcode_intel ***)__pa_nodebug(&mcs->mc_saved);
104
4fe9349f 105 for (i = 0; i < mcs->num_saved; i++) {
fe055896
BP
106 struct microcode_intel *p;
107
bd6fe58d 108 p = *(struct microcode_intel **)__pa_nodebug(mcs->mc_saved + i);
fe055896
BP
109 mc_saved_tmp[i] = (struct microcode_intel *)__pa_nodebug(p);
110 }
111}
112#endif
113
114static enum ucode_state
f8bb45e2
BP
115load_microcode(struct mc_saved_data *mcs, unsigned long *mc_ptrs,
116 unsigned long offset, struct ucode_cpu_info *uci)
fe055896
BP
117{
118 struct microcode_intel *mc_saved_tmp[MAX_UCODE_COUNT];
4fe9349f 119 unsigned int count = mcs->num_saved;
fe055896 120
bd6fe58d 121 if (!mcs->mc_saved) {
f8bb45e2 122 copy_ptrs(mc_saved_tmp, mc_ptrs, offset, count);
fe055896
BP
123
124 return load_microcode_early(mc_saved_tmp, count, uci);
125 } else {
126#ifdef CONFIG_X86_32
bd6fe58d 127 microcode_phys(mc_saved_tmp, mcs);
fe055896
BP
128 return load_microcode_early(mc_saved_tmp, count, uci);
129#else
bd6fe58d 130 return load_microcode_early(mcs->mc_saved, count, uci);
fe055896
BP
131#endif
132 }
133}
134
135/*
136 * Given CPU signature and a microcode patch, this function finds if the
137 * microcode patch has matching family and model with the CPU.
138 */
139static enum ucode_state
140matching_model_microcode(struct microcode_header_intel *mc_header,
141 unsigned long sig)
142{
143 unsigned int fam, model;
144 unsigned int fam_ucode, model_ucode;
145 struct extended_sigtable *ext_header;
146 unsigned long total_size = get_totalsize(mc_header);
147 unsigned long data_size = get_datasize(mc_header);
148 int ext_sigcount, i;
149 struct extended_signature *ext_sig;
150
99f925ce 151 fam = x86_family(sig);
fe055896
BP
152 model = x86_model(sig);
153
99f925ce 154 fam_ucode = x86_family(mc_header->sig);
fe055896
BP
155 model_ucode = x86_model(mc_header->sig);
156
157 if (fam == fam_ucode && model == model_ucode)
158 return UCODE_OK;
159
160 /* Look for ext. headers: */
161 if (total_size <= data_size + MC_HEADER_SIZE)
162 return UCODE_NFOUND;
163
164 ext_header = (void *) mc_header + data_size + MC_HEADER_SIZE;
165 ext_sig = (void *)ext_header + EXT_HEADER_SIZE;
166 ext_sigcount = ext_header->count;
167
168 for (i = 0; i < ext_sigcount; i++) {
99f925ce 169 fam_ucode = x86_family(ext_sig->sig);
fe055896
BP
170 model_ucode = x86_model(ext_sig->sig);
171
172 if (fam == fam_ucode && model == model_ucode)
173 return UCODE_OK;
174
175 ext_sig++;
176 }
177 return UCODE_NFOUND;
178}
179
180static int
bd6fe58d 181save_microcode(struct mc_saved_data *mcs,
fe055896 182 struct microcode_intel **mc_saved_src,
4fe9349f 183 unsigned int num_saved)
fe055896
BP
184{
185 int i, j;
186 struct microcode_intel **saved_ptr;
187 int ret;
188
4fe9349f 189 if (!num_saved)
fe055896
BP
190 return -EINVAL;
191
192 /*
193 * Copy new microcode data.
194 */
4fe9349f 195 saved_ptr = kcalloc(num_saved, sizeof(struct microcode_intel *), GFP_KERNEL);
fe055896
BP
196 if (!saved_ptr)
197 return -ENOMEM;
198
4fe9349f 199 for (i = 0; i < num_saved; i++) {
fe055896
BP
200 struct microcode_header_intel *mc_hdr;
201 struct microcode_intel *mc;
202 unsigned long size;
203
204 if (!mc_saved_src[i]) {
205 ret = -EINVAL;
206 goto err;
207 }
208
209 mc = mc_saved_src[i];
210 mc_hdr = &mc->hdr;
211 size = get_totalsize(mc_hdr);
212
213 saved_ptr[i] = kmalloc(size, GFP_KERNEL);
214 if (!saved_ptr[i]) {
215 ret = -ENOMEM;
216 goto err;
217 }
218
219 memcpy(saved_ptr[i], mc, size);
220 }
221
222 /*
223 * Point to newly saved microcode.
224 */
4fe9349f
BP
225 mcs->mc_saved = saved_ptr;
226 mcs->num_saved = num_saved;
fe055896
BP
227
228 return 0;
229
230err:
231 for (j = 0; j <= i; j++)
232 kfree(saved_ptr[j]);
233 kfree(saved_ptr);
234
235 return ret;
236}
237
238/*
239 * A microcode patch in ucode_ptr is saved into mc_saved
240 * - if it has matching signature and newer revision compared to an existing
241 * patch mc_saved.
242 * - or if it is a newly discovered microcode patch.
243 *
244 * The microcode patch should have matching model with CPU.
245 *
246 * Returns: The updated number @num_saved of saved microcode patches.
247 */
248static unsigned int _save_mc(struct microcode_intel **mc_saved,
249 u8 *ucode_ptr, unsigned int num_saved)
250{
251 struct microcode_header_intel *mc_hdr, *mc_saved_hdr;
252 unsigned int sig, pf;
253 int found = 0, i;
254
255 mc_hdr = (struct microcode_header_intel *)ucode_ptr;
256
257 for (i = 0; i < num_saved; i++) {
258 mc_saved_hdr = (struct microcode_header_intel *)mc_saved[i];
259 sig = mc_saved_hdr->sig;
260 pf = mc_saved_hdr->pf;
261
262 if (!find_matching_signature(ucode_ptr, sig, pf))
263 continue;
264
265 found = 1;
266
267 if (mc_hdr->rev <= mc_saved_hdr->rev)
268 continue;
269
270 /*
271 * Found an older ucode saved earlier. Replace it with
272 * this newer one.
273 */
274 mc_saved[i] = (struct microcode_intel *)ucode_ptr;
275 break;
276 }
277
278 /* Newly detected microcode, save it to memory. */
279 if (i >= num_saved && !found)
280 mc_saved[num_saved++] = (struct microcode_intel *)ucode_ptr;
281
282 return num_saved;
283}
284
285/*
286 * Get microcode matching with BSP's model. Only CPUs with the same model as
287 * BSP can stay in the platform.
288 */
289static enum ucode_state __init
2f303c52 290get_matching_model_microcode(unsigned long start,
fe055896 291 void *data, size_t size,
bd6fe58d 292 struct mc_saved_data *mcs,
f8bb45e2 293 unsigned long *mc_ptrs,
fe055896
BP
294 struct ucode_cpu_info *uci)
295{
296 u8 *ucode_ptr = data;
297 unsigned int leftover = size;
298 enum ucode_state state = UCODE_OK;
299 unsigned int mc_size;
300 struct microcode_header_intel *mc_header;
301 struct microcode_intel *mc_saved_tmp[MAX_UCODE_COUNT];
4fe9349f 302 unsigned int num_saved = mcs->num_saved;
fe055896
BP
303 int i;
304
4fe9349f 305 while (leftover && num_saved < ARRAY_SIZE(mc_saved_tmp)) {
fe055896
BP
306
307 if (leftover < sizeof(mc_header))
308 break;
309
310 mc_header = (struct microcode_header_intel *)ucode_ptr;
311
312 mc_size = get_totalsize(mc_header);
313 if (!mc_size || mc_size > leftover ||
314 microcode_sanity_check(ucode_ptr, 0) < 0)
315 break;
316
317 leftover -= mc_size;
318
319 /*
320 * Since APs with same family and model as the BSP may boot in
321 * the platform, we need to find and save microcode patches
322 * with the same family and model as the BSP.
323 */
324 if (matching_model_microcode(mc_header, uci->cpu_sig.sig) !=
325 UCODE_OK) {
326 ucode_ptr += mc_size;
327 continue;
328 }
329
4fe9349f 330 num_saved = _save_mc(mc_saved_tmp, ucode_ptr, num_saved);
fe055896
BP
331
332 ucode_ptr += mc_size;
333 }
334
335 if (leftover) {
336 state = UCODE_ERROR;
337 goto out;
338 }
339
4fe9349f 340 if (!num_saved) {
fe055896
BP
341 state = UCODE_NFOUND;
342 goto out;
343 }
344
4fe9349f 345 for (i = 0; i < num_saved; i++)
f8bb45e2 346 mc_ptrs[i] = (unsigned long)mc_saved_tmp[i] - start;
fe055896 347
4fe9349f 348 mcs->num_saved = num_saved;
fe055896
BP
349out:
350 return state;
351}
352
353static int collect_cpu_info_early(struct ucode_cpu_info *uci)
354{
355 unsigned int val[2];
356 unsigned int family, model;
357 struct cpu_signature csig;
358 unsigned int eax, ebx, ecx, edx;
359
360 csig.sig = 0;
361 csig.pf = 0;
362 csig.rev = 0;
363
364 memset(uci, 0, sizeof(*uci));
365
366 eax = 0x00000001;
367 ecx = 0;
368 native_cpuid(&eax, &ebx, &ecx, &edx);
369 csig.sig = eax;
370
99f925ce 371 family = x86_family(csig.sig);
fe055896
BP
372 model = x86_model(csig.sig);
373
374 if ((model >= 5) || (family > 6)) {
375 /* get processor flags from MSR 0x17 */
376 native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
377 csig.pf = 1 << ((val[1] >> 18) & 7);
378 }
c416e611 379 native_wrmsrl(MSR_IA32_UCODE_REV, 0);
fe055896
BP
380
381 /* As documented in the SDM: Do a CPUID 1 here */
382 sync_core();
383
384 /* get the current revision from MSR 0x8B */
385 native_rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
386
387 csig.rev = val[1];
388
389 uci->cpu_sig = csig;
390 uci->valid = 1;
391
392 return 0;
393}
394
fe055896
BP
395static void show_saved_mc(void)
396{
c595ac2b 397#ifdef DEBUG
fe055896
BP
398 int i, j;
399 unsigned int sig, pf, rev, total_size, data_size, date;
400 struct ucode_cpu_info uci;
401
4fe9349f 402 if (!mc_saved_data.num_saved) {
fe055896
BP
403 pr_debug("no microcode data saved.\n");
404 return;
405 }
4fe9349f 406 pr_debug("Total microcode saved: %d\n", mc_saved_data.num_saved);
fe055896
BP
407
408 collect_cpu_info_early(&uci);
409
410 sig = uci.cpu_sig.sig;
411 pf = uci.cpu_sig.pf;
412 rev = uci.cpu_sig.rev;
413 pr_debug("CPU: sig=0x%x, pf=0x%x, rev=0x%x\n", sig, pf, rev);
414
4fe9349f 415 for (i = 0; i < mc_saved_data.num_saved; i++) {
fe055896
BP
416 struct microcode_header_intel *mc_saved_header;
417 struct extended_sigtable *ext_header;
418 int ext_sigcount;
419 struct extended_signature *ext_sig;
420
421 mc_saved_header = (struct microcode_header_intel *)
422 mc_saved_data.mc_saved[i];
423 sig = mc_saved_header->sig;
424 pf = mc_saved_header->pf;
425 rev = mc_saved_header->rev;
426 total_size = get_totalsize(mc_saved_header);
427 data_size = get_datasize(mc_saved_header);
428 date = mc_saved_header->date;
429
430 pr_debug("mc_saved[%d]: sig=0x%x, pf=0x%x, rev=0x%x, toal size=0x%x, date = %04x-%02x-%02x\n",
431 i, sig, pf, rev, total_size,
432 date & 0xffff,
433 date >> 24,
434 (date >> 16) & 0xff);
435
436 /* Look for ext. headers: */
437 if (total_size <= data_size + MC_HEADER_SIZE)
438 continue;
439
440 ext_header = (void *) mc_saved_header + data_size + MC_HEADER_SIZE;
441 ext_sigcount = ext_header->count;
442 ext_sig = (void *)ext_header + EXT_HEADER_SIZE;
443
444 for (j = 0; j < ext_sigcount; j++) {
445 sig = ext_sig->sig;
446 pf = ext_sig->pf;
447
448 pr_debug("\tExtended[%d]: sig=0x%x, pf=0x%x\n",
449 j, sig, pf);
450
451 ext_sig++;
452 }
453
454 }
fe055896 455#endif
c595ac2b 456}
fe055896
BP
457
458#ifdef CONFIG_HOTPLUG_CPU
459static DEFINE_MUTEX(x86_cpu_microcode_mutex);
460/*
461 * Save this mc into mc_saved_data. So it will be loaded early when a CPU is
462 * hot added or resumes.
463 *
464 * Please make sure this mc should be a valid microcode patch before calling
465 * this function.
466 */
467int save_mc_for_early(u8 *mc)
468{
469 struct microcode_intel *mc_saved_tmp[MAX_UCODE_COUNT];
470 unsigned int mc_saved_count_init;
4fe9349f 471 unsigned int num_saved;
fe055896
BP
472 struct microcode_intel **mc_saved;
473 int ret = 0;
474 int i;
475
476 /*
477 * Hold hotplug lock so mc_saved_data is not accessed by a CPU in
478 * hotplug.
479 */
480 mutex_lock(&x86_cpu_microcode_mutex);
481
4fe9349f
BP
482 mc_saved_count_init = mc_saved_data.num_saved;
483 num_saved = mc_saved_data.num_saved;
fe055896
BP
484 mc_saved = mc_saved_data.mc_saved;
485
4fe9349f 486 if (mc_saved && num_saved)
fe055896 487 memcpy(mc_saved_tmp, mc_saved,
4fe9349f 488 num_saved * sizeof(struct microcode_intel *));
fe055896
BP
489 /*
490 * Save the microcode patch mc in mc_save_tmp structure if it's a newer
491 * version.
492 */
4fe9349f 493 num_saved = _save_mc(mc_saved_tmp, mc, num_saved);
fe055896
BP
494
495 /*
496 * Save the mc_save_tmp in global mc_saved_data.
497 */
4fe9349f 498 ret = save_microcode(&mc_saved_data, mc_saved_tmp, num_saved);
fe055896
BP
499 if (ret) {
500 pr_err("Cannot save microcode patch.\n");
501 goto out;
502 }
503
504 show_saved_mc();
505
506 /*
507 * Free old saved microcode data.
508 */
509 if (mc_saved) {
510 for (i = 0; i < mc_saved_count_init; i++)
511 kfree(mc_saved[i]);
512 kfree(mc_saved);
513 }
514
515out:
516 mutex_unlock(&x86_cpu_microcode_mutex);
517
518 return ret;
519}
520EXPORT_SYMBOL_GPL(save_mc_for_early);
521#endif
522
523static bool __init load_builtin_intel_microcode(struct cpio_data *cp)
524{
525#ifdef CONFIG_X86_64
526 unsigned int eax = 0x00000001, ebx, ecx = 0, edx;
fe055896
BP
527 char name[30];
528
529 native_cpuid(&eax, &ebx, &ecx, &edx);
530
99f925ce
BP
531 sprintf(name, "intel-ucode/%02x-%02x-%02x",
532 x86_family(eax), x86_model(eax), x86_stepping(eax));
fe055896
BP
533
534 return get_builtin_firmware(cp, name);
535#else
536 return false;
537#endif
538}
539
540static __initdata char ucode_name[] = "kernel/x86/microcode/GenuineIntel.bin";
541static __init enum ucode_state
f8bb45e2 542scan_microcode(struct mc_saved_data *mcs, unsigned long *mc_ptrs,
fe055896
BP
543 unsigned long start, unsigned long size,
544 struct ucode_cpu_info *uci)
545{
546 struct cpio_data cd;
547 long offset = 0;
548#ifdef CONFIG_X86_32
549 char *p = (char *)__pa_nodebug(ucode_name);
550#else
551 char *p = ucode_name;
552#endif
553
554 cd.data = NULL;
555 cd.size = 0;
556
264285ac
BP
557 /* try built-in microcode if no initrd */
558 if (!size) {
fe055896
BP
559 if (!load_builtin_intel_microcode(&cd))
560 return UCODE_ERROR;
264285ac
BP
561 } else {
562 cd = find_cpio_data(p, (void *)start, size, &offset);
563 if (!cd.data)
564 return UCODE_ERROR;
fe055896
BP
565 }
566
2f303c52 567 return get_matching_model_microcode(start, cd.data, cd.size,
f8bb45e2 568 mcs, mc_ptrs, uci);
fe055896
BP
569}
570
571/*
572 * Print ucode update info.
573 */
574static void
575print_ucode_info(struct ucode_cpu_info *uci, unsigned int date)
576{
b7f500ae
BP
577 pr_info_once("microcode updated early to revision 0x%x, date = %04x-%02x-%02x\n",
578 uci->cpu_sig.rev,
579 date & 0xffff,
580 date >> 24,
581 (date >> 16) & 0xff);
fe055896
BP
582}
583
584#ifdef CONFIG_X86_32
585
586static int delay_ucode_info;
587static int current_mc_date;
588
589/*
590 * Print early updated ucode info after printk works. This is delayed info dump.
591 */
592void show_ucode_info_early(void)
593{
594 struct ucode_cpu_info uci;
595
596 if (delay_ucode_info) {
597 collect_cpu_info_early(&uci);
598 print_ucode_info(&uci, current_mc_date);
599 delay_ucode_info = 0;
600 }
601}
602
603/*
604 * At this point, we can not call printk() yet. Keep microcode patch number in
605 * mc_saved_data.mc_saved and delay printing microcode info in
606 * show_ucode_info_early() until printk() works.
607 */
608static void print_ucode(struct ucode_cpu_info *uci)
609{
de778275 610 struct microcode_intel *mc;
fe055896
BP
611 int *delay_ucode_info_p;
612 int *current_mc_date_p;
613
de778275
BP
614 mc = uci->mc;
615 if (!mc)
fe055896
BP
616 return;
617
618 delay_ucode_info_p = (int *)__pa_nodebug(&delay_ucode_info);
619 current_mc_date_p = (int *)__pa_nodebug(&current_mc_date);
620
621 *delay_ucode_info_p = 1;
de778275 622 *current_mc_date_p = mc->hdr.date;
fe055896
BP
623}
624#else
625
626/*
627 * Flush global tlb. We only do this in x86_64 where paging has been enabled
628 * already and PGE should be enabled as well.
629 */
630static inline void flush_tlb_early(void)
631{
632 __native_flush_tlb_global_irq_disabled();
633}
634
635static inline void print_ucode(struct ucode_cpu_info *uci)
636{
de778275 637 struct microcode_intel *mc;
fe055896 638
de778275
BP
639 mc = uci->mc;
640 if (!mc)
fe055896
BP
641 return;
642
de778275 643 print_ucode_info(uci, mc->hdr.date);
fe055896
BP
644}
645#endif
646
647static int apply_microcode_early(struct ucode_cpu_info *uci, bool early)
648{
de778275 649 struct microcode_intel *mc;
fe055896
BP
650 unsigned int val[2];
651
de778275
BP
652 mc = uci->mc;
653 if (!mc)
fe055896
BP
654 return 0;
655
656 /* write microcode via MSR 0x79 */
c416e611
BP
657 native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
658 native_wrmsrl(MSR_IA32_UCODE_REV, 0);
fe055896
BP
659
660 /* As documented in the SDM: Do a CPUID 1 here */
661 sync_core();
662
663 /* get the current revision from MSR 0x8B */
664 native_rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
de778275 665 if (val[1] != mc->hdr.rev)
fe055896
BP
666 return -1;
667
668#ifdef CONFIG_X86_64
669 /* Flush global tlb. This is precaution. */
670 flush_tlb_early();
671#endif
672 uci->cpu_sig.rev = val[1];
673
674 if (early)
675 print_ucode(uci);
676 else
de778275 677 print_ucode_info(uci, mc->hdr.date);
fe055896
BP
678
679 return 0;
680}
681
682/*
683 * This function converts microcode patch offsets previously stored in
f8bb45e2 684 * mc_tmp_ptrs to pointers and stores the pointers in mc_saved_data.
fe055896
BP
685 */
686int __init save_microcode_in_initrd_intel(void)
687{
4fe9349f 688 unsigned int count = mc_saved_data.num_saved;
fe055896
BP
689 struct microcode_intel *mc_saved[MAX_UCODE_COUNT];
690 int ret = 0;
691
4fe9349f 692 if (!count)
fe055896
BP
693 return ret;
694
f8bb45e2 695 copy_ptrs(mc_saved, mc_tmp_ptrs, get_initrd_start(), count);
4fe9349f 696
fe055896
BP
697 ret = save_microcode(&mc_saved_data, mc_saved, count);
698 if (ret)
699 pr_err("Cannot save microcode patches from initrd.\n");
700
701 show_saved_mc();
702
703 return ret;
704}
705
706static void __init
f8bb45e2 707_load_ucode_intel_bsp(struct mc_saved_data *mcs, unsigned long *mc_ptrs,
fe055896
BP
708 unsigned long start, unsigned long size)
709{
710 struct ucode_cpu_info uci;
711 enum ucode_state ret;
712
713 collect_cpu_info_early(&uci);
714
f8bb45e2 715 ret = scan_microcode(mcs, mc_ptrs, start, size, &uci);
fe055896
BP
716 if (ret != UCODE_OK)
717 return;
718
f8bb45e2 719 ret = load_microcode(mcs, mc_ptrs, start, &uci);
fe055896
BP
720 if (ret != UCODE_OK)
721 return;
722
723 apply_microcode_early(&uci, true);
724}
725
726void __init load_ucode_intel_bsp(void)
727{
728 u64 start, size;
729#ifdef CONFIG_X86_32
730 struct boot_params *p;
731
732 p = (struct boot_params *)__pa_nodebug(&boot_params);
fe055896
BP
733 size = p->hdr.ramdisk_size;
734
264285ac
BP
735 /*
736 * Set start only if we have an initrd image. We cannot use initrd_start
737 * because it is not set that early yet.
738 */
739 start = (size ? p->hdr.ramdisk_image : 0);
740
741 _load_ucode_intel_bsp((struct mc_saved_data *)__pa_nodebug(&mc_saved_data),
f8bb45e2 742 (unsigned long *)__pa_nodebug(&mc_tmp_ptrs),
264285ac 743 start, size);
fe055896 744#else
fe055896 745 size = boot_params.hdr.ramdisk_size;
264285ac 746 start = (size ? boot_params.hdr.ramdisk_image + PAGE_OFFSET : 0);
fe055896 747
f8bb45e2 748 _load_ucode_intel_bsp(&mc_saved_data, mc_tmp_ptrs, start, size);
fe055896
BP
749#endif
750}
751
752void load_ucode_intel_ap(void)
753{
f8bb45e2 754 unsigned long *mcs_tmp_p;
bd6fe58d
BP
755 struct mc_saved_data *mcs_p;
756 struct ucode_cpu_info uci;
fe055896
BP
757 enum ucode_state ret;
758#ifdef CONFIG_X86_32
fe055896 759
f8bb45e2 760 mcs_tmp_p = (unsigned long *)__pa_nodebug(mc_tmp_ptrs);
bd6fe58d 761 mcs_p = (struct mc_saved_data *)__pa_nodebug(&mc_saved_data);
fe055896 762#else
f8bb45e2 763 mcs_tmp_p = mc_tmp_ptrs;
bd6fe58d 764 mcs_p = &mc_saved_data;
fe055896
BP
765#endif
766
767 /*
768 * If there is no valid ucode previously saved in memory, no need to
769 * update ucode on this AP.
770 */
4fe9349f 771 if (!mcs_p->num_saved)
fe055896
BP
772 return;
773
774 collect_cpu_info_early(&uci);
f8bb45e2 775 ret = load_microcode(mcs_p, mcs_tmp_p, get_initrd_start_addr(), &uci);
fe055896
BP
776 if (ret != UCODE_OK)
777 return;
778
779 apply_microcode_early(&uci, true);
780}
781
782void reload_ucode_intel(void)
783{
784 struct ucode_cpu_info uci;
785 enum ucode_state ret;
786
4fe9349f 787 if (!mc_saved_data.num_saved)
fe055896
BP
788 return;
789
790 collect_cpu_info_early(&uci);
791
792 ret = load_microcode_early(mc_saved_data.mc_saved,
4fe9349f 793 mc_saved_data.num_saved, &uci);
fe055896
BP
794 if (ret != UCODE_OK)
795 return;
796
797 apply_microcode_early(&uci, false);
798}
799
d45de409 800static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
1da177e4 801{
92cb7612 802 struct cpuinfo_x86 *c = &cpu_data(cpu_num);
1da177e4
LT
803 unsigned int val[2];
804
d45de409 805 memset(csig, 0, sizeof(*csig));
1da177e4 806
d45de409 807 csig->sig = cpuid_eax(0x00000001);
9a3110bf
SL
808
809 if ((c->x86_model >= 5) || (c->x86 > 6)) {
810 /* get processor flags from MSR 0x17 */
811 rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
d45de409 812 csig->pf = 1 << ((val[1] >> 18) & 7);
1da177e4
LT
813 }
814
506ed6b5 815 csig->rev = c->microcode;
f58e1f53
JP
816 pr_info("CPU%d sig=0x%x, pf=0x%x, revision=0x%x\n",
817 cpu_num, csig->sig, csig->pf, csig->rev);
d45de409
DA
818
819 return 0;
1da177e4
LT
820}
821
9a3110bf
SL
822/*
823 * return 0 - no update found
824 * return 1 - found update
9a3110bf 825 */
de778275 826static int get_matching_mc(struct microcode_intel *mc, int cpu)
9a3110bf 827{
9cd4d78e
FY
828 struct cpu_signature cpu_sig;
829 unsigned int csig, cpf, crev;
9a3110bf 830
9cd4d78e 831 collect_cpu_info(cpu, &cpu_sig);
a0a29b62 832
9cd4d78e
FY
833 csig = cpu_sig.sig;
834 cpf = cpu_sig.pf;
835 crev = cpu_sig.rev;
9a3110bf 836
de778275 837 return has_newer_microcode(mc, csig, cpf, crev);
1da177e4
LT
838}
839
532ed374 840static int apply_microcode_intel(int cpu)
1da177e4 841{
de778275 842 struct microcode_intel *mc;
4bae1967 843 struct ucode_cpu_info *uci;
26cbaa4d 844 struct cpuinfo_x86 *c;
1da177e4 845 unsigned int val[2];
4bae1967 846
9a3110bf 847 /* We should bind the task to the CPU */
26cbaa4d 848 if (WARN_ON(raw_smp_processor_id() != cpu))
58b5f2cc 849 return -1;
9a3110bf 850
58b5f2cc
BP
851 uci = ucode_cpu_info + cpu;
852 mc = uci->mc;
de778275 853 if (!mc)
871b72dd 854 return 0;
1da177e4 855
9cd4d78e
FY
856 /*
857 * Microcode on this CPU could be updated earlier. Only apply the
de778275 858 * microcode patch in mc when it is newer than the one on this
9cd4d78e
FY
859 * CPU.
860 */
de778275 861 if (!get_matching_mc(mc, cpu))
9cd4d78e
FY
862 return 0;
863
1da177e4 864 /* write microcode via MSR 0x79 */
c416e611
BP
865 wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
866 wrmsrl(MSR_IA32_UCODE_REV, 0);
1da177e4 867
506ed6b5 868 /* As documented in the SDM: Do a CPUID 1 here */
487472bc 869 sync_core();
245067d1 870
1da177e4
LT
871 /* get the current revision from MSR 0x8B */
872 rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
873
de778275 874 if (val[1] != mc->hdr.rev) {
f58e1f53 875 pr_err("CPU%d update to revision 0x%x failed\n",
26cbaa4d 876 cpu, mc->hdr.rev);
871b72dd 877 return -1;
9a3110bf 878 }
26cbaa4d 879
3235dc3f 880 pr_info("CPU%d updated to revision 0x%x, date = %04x-%02x-%02x\n",
26cbaa4d 881 cpu, val[1],
de778275
BP
882 mc->hdr.date & 0xffff,
883 mc->hdr.date >> 24,
884 (mc->hdr.date >> 16) & 0xff);
4bae1967 885
26cbaa4d
BP
886 c = &cpu_data(cpu);
887
d45de409 888 uci->cpu_sig.rev = val[1];
506ed6b5 889 c->microcode = val[1];
871b72dd
DA
890
891 return 0;
1da177e4
LT
892}
893
871b72dd
DA
894static enum ucode_state generic_load_microcode(int cpu, void *data, size_t size,
895 int (*get_ucode_data)(void *, const void *, size_t))
9a3110bf 896{
a0a29b62 897 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
938179b4 898 u8 *ucode_ptr = data, *new_mc = NULL, *mc = NULL;
a0a29b62
DA
899 int new_rev = uci->cpu_sig.rev;
900 unsigned int leftover = size;
871b72dd 901 enum ucode_state state = UCODE_OK;
938179b4 902 unsigned int curr_mc_size = 0;
9cd4d78e 903 unsigned int csig, cpf;
9a3110bf 904
a0a29b62
DA
905 while (leftover) {
906 struct microcode_header_intel mc_header;
907 unsigned int mc_size;
9a3110bf 908
35a9ff4e
QC
909 if (leftover < sizeof(mc_header)) {
910 pr_err("error! Truncated header in microcode data file\n");
911 break;
912 }
913
a0a29b62
DA
914 if (get_ucode_data(&mc_header, ucode_ptr, sizeof(mc_header)))
915 break;
a30a6a2c 916
a0a29b62
DA
917 mc_size = get_totalsize(&mc_header);
918 if (!mc_size || mc_size > leftover) {
f58e1f53 919 pr_err("error! Bad data in microcode data file\n");
a0a29b62
DA
920 break;
921 }
a30a6a2c 922
938179b4
DS
923 /* For performance reasons, reuse mc area when possible */
924 if (!mc || mc_size > curr_mc_size) {
5cdd2de0 925 vfree(mc);
938179b4
DS
926 mc = vmalloc(mc_size);
927 if (!mc)
928 break;
929 curr_mc_size = mc_size;
930 }
a0a29b62
DA
931
932 if (get_ucode_data(mc, ucode_ptr, mc_size) ||
9cd4d78e 933 microcode_sanity_check(mc, 1) < 0) {
a0a29b62
DA
934 break;
935 }
936
9cd4d78e
FY
937 csig = uci->cpu_sig.sig;
938 cpf = uci->cpu_sig.pf;
8de3eafc 939 if (has_newer_microcode(mc, csig, cpf, new_rev)) {
5cdd2de0 940 vfree(new_mc);
a0a29b62
DA
941 new_rev = mc_header.rev;
942 new_mc = mc;
938179b4
DS
943 mc = NULL; /* trigger new vmalloc */
944 }
a0a29b62
DA
945
946 ucode_ptr += mc_size;
947 leftover -= mc_size;
a30a6a2c
SL
948 }
949
5cdd2de0 950 vfree(mc);
938179b4 951
871b72dd 952 if (leftover) {
5cdd2de0 953 vfree(new_mc);
871b72dd 954 state = UCODE_ERROR;
4bae1967 955 goto out;
871b72dd 956 }
4bae1967 957
871b72dd
DA
958 if (!new_mc) {
959 state = UCODE_NFOUND;
4bae1967 960 goto out;
a30a6a2c 961 }
a0a29b62 962
5cdd2de0 963 vfree(uci->mc);
4bae1967
IM
964 uci->mc = (struct microcode_intel *)new_mc;
965
9cd4d78e
FY
966 /*
967 * If early loading microcode is supported, save this mc into
968 * permanent memory. So it will be loaded early when a CPU is hot added
969 * or resumes.
970 */
971 save_mc_for_early(new_mc);
972
f58e1f53
JP
973 pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n",
974 cpu, new_rev, uci->cpu_sig.rev);
871b72dd
DA
975out:
976 return state;
a30a6a2c
SL
977}
978
a0a29b62
DA
979static int get_ucode_fw(void *to, const void *from, size_t n)
980{
981 memcpy(to, from, n);
982 return 0;
983}
a30a6a2c 984
48e30685
BP
985static enum ucode_state request_microcode_fw(int cpu, struct device *device,
986 bool refresh_fw)
a30a6a2c
SL
987{
988 char name[30];
92cb7612 989 struct cpuinfo_x86 *c = &cpu_data(cpu);
a30a6a2c 990 const struct firmware *firmware;
871b72dd 991 enum ucode_state ret;
a30a6a2c 992
3e135d88 993 sprintf(name, "intel-ucode/%02x-%02x-%02x",
a30a6a2c 994 c->x86, c->x86_model, c->x86_mask);
871b72dd 995
75da02b2 996 if (request_firmware_direct(&firmware, name, device)) {
f58e1f53 997 pr_debug("data file %s load failed\n", name);
871b72dd 998 return UCODE_NFOUND;
a30a6a2c 999 }
a0a29b62 1000
dd3feda7
JSR
1001 ret = generic_load_microcode(cpu, (void *)firmware->data,
1002 firmware->size, &get_ucode_fw);
a0a29b62 1003
a30a6a2c
SL
1004 release_firmware(firmware);
1005
a0a29b62
DA
1006 return ret;
1007}
1008
1009static int get_ucode_user(void *to, const void *from, size_t n)
1010{
1011 return copy_from_user(to, from, n);
1012}
1013
871b72dd
DA
1014static enum ucode_state
1015request_microcode_user(int cpu, const void __user *buf, size_t size)
a0a29b62 1016{
dd3feda7 1017 return generic_load_microcode(cpu, (void *)buf, size, &get_ucode_user);
a30a6a2c
SL
1018}
1019
8d86f390 1020static void microcode_fini_cpu(int cpu)
a30a6a2c
SL
1021{
1022 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
1023
18dbc916
DA
1024 vfree(uci->mc);
1025 uci->mc = NULL;
a30a6a2c 1026}
8d86f390 1027
4db646b1 1028static struct microcode_ops microcode_intel_ops = {
a0a29b62
DA
1029 .request_microcode_user = request_microcode_user,
1030 .request_microcode_fw = request_microcode_fw,
8d86f390 1031 .collect_cpu_info = collect_cpu_info,
532ed374 1032 .apply_microcode = apply_microcode_intel,
8d86f390
PO
1033 .microcode_fini_cpu = microcode_fini_cpu,
1034};
1035
18dbc916 1036struct microcode_ops * __init init_intel_microcode(void)
8d86f390 1037{
9a2bc335 1038 struct cpuinfo_x86 *c = &boot_cpu_data;
7164b3f5
SB
1039
1040 if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 ||
1041 cpu_has(c, X86_FEATURE_IA64)) {
1042 pr_err("Intel CPU family 0x%x not supported\n", c->x86);
1043 return NULL;
1044 }
1045
18dbc916 1046 return &microcode_intel_ops;
8d86f390
PO
1047}
1048