[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kernel / cpu / mtrr / cyrix.c

// SPDX-License-Identifier: GPL-2.0
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mm.h>

#include <asm/processor-cyrix.h>
#include <asm/processor-flags.h>
#include <asm/mtrr.h>
#include <asm/msr.h>

#include "mtrr.h"

static void
cyrix_get_arr(unsigned int reg, unsigned long *base,
	      unsigned long *size, mtrr_type * type)
{
	unsigned char arr, ccr3, rcr, shift;
	unsigned long flags;

	arr = CX86_ARR_BASE + (reg << 1) + reg;	/* avoid multiplication by 3 */

	local_irq_save(flags);

	ccr3 = getCx86(CX86_CCR3);
	setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);	/* enable MAPEN */
	((unsigned char *)base)[3] = getCx86(arr);
	((unsigned char *)base)[2] = getCx86(arr + 1);
	((unsigned char *)base)[1] = getCx86(arr + 2);
	rcr = getCx86(CX86_RCR_BASE + reg);
	setCx86(CX86_CCR3, ccr3);			/* disable MAPEN */

	local_irq_restore(flags);

	shift = ((unsigned char *) base)[1] & 0x0f;
	*base >>= PAGE_SHIFT;

	/*
	 * Power of two, at least 4K on ARR0-ARR6, 256K on ARR7
	 * Note: shift==0xf means 4G, this is unsupported.
	 */
	if (shift)
		*size = (reg < 7 ? 0x1UL : 0x40UL) << (shift - 1);
	else
		*size = 0;

	/* Bit 0 is Cache Enable on ARR7, Cache Disable on ARR0-ARR6 */
	if (reg < 7) {
		switch (rcr) {
		case 1:
			*type = MTRR_TYPE_UNCACHABLE;
			break;
		case 8:
			*type = MTRR_TYPE_WRBACK;
			break;
		case 9:
			*type = MTRR_TYPE_WRCOMB;
			break;
		case 24:
		default:
			*type = MTRR_TYPE_WRTHROUGH;
			break;
		}
	} else {
		switch (rcr) {
		case 0:
			*type = MTRR_TYPE_UNCACHABLE;
			break;
		case 8:
			*type = MTRR_TYPE_WRCOMB;
			break;
		case 9:
			*type = MTRR_TYPE_WRBACK;
			break;
		case 25:
		default:
			*type = MTRR_TYPE_WRTHROUGH;
			break;
		}
	}
}

/*
 * cyrix_get_free_region - get a free ARR.
 *
 * @base: the starting (base) address of the region.
 * @size: the size (in bytes) of the region.
 *
 * Returns: the index of the region on success, else -1 on error.
*/
static int
cyrix_get_free_region(unsigned long base, unsigned long size, int replace_reg)
{
	unsigned long lbase, lsize;
	mtrr_type ltype;
	int i;

	switch (replace_reg) {
	case 7:
		if (size < 0x40)
			break;
	case 6:
	case 5:
	case 4:
		return replace_reg;
	case 3:
	case 2:
	case 1:
	case 0:
		return replace_reg;
	}
	/* If we are to set up a region >32M then look at ARR7 immediately */
	if (size > 0x2000) {
		cyrix_get_arr(7, &lbase, &lsize, &ltype);
		if (lsize == 0)
			return 7;
		/* Else try ARR0-ARR6 first  */
	} else {
		for (i = 0; i < 7; i++) {
			cyrix_get_arr(i, &lbase, &lsize, &ltype);
			if (lsize == 0)
				return i;
		}
		/*
		 * ARR0-ARR6 isn't free
		 * try ARR7 but its size must be at least 256K
		 */
		cyrix_get_arr(i, &lbase, &lsize, &ltype);
		if ((lsize == 0) && (size >= 0x40))
			return i;
	}
	return -ENOSPC;
}

static u32 cr4, ccr3;

static void prepare_set(void)
{
	u32 cr0;

	/*  Save value of CR4 and clear Page Global Enable (bit 7)  */
	if (boot_cpu_has(X86_FEATURE_PGE)) {
		cr4 = __read_cr4();
		__write_cr4(cr4 & ~X86_CR4_PGE);
	}

	/*
	 * Disable and flush caches.
	 * Note that wbinvd flushes the TLBs as a side-effect
	 */
	cr0 = read_cr0() | X86_CR0_CD;
	wbinvd();
	write_cr0(cr0);
	wbinvd();

	/* Cyrix ARRs - everything else was excluded at the top */
	ccr3 = getCx86(CX86_CCR3);

	/* Cyrix ARRs - everything else was excluded at the top */
	setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);
}

static void post_set(void)
{
	/* Flush caches and TLBs */
	wbinvd();

	/* Cyrix ARRs - everything else was excluded at the top */
	setCx86(CX86_CCR3, ccr3);

	/* Enable caches */
	write_cr0(read_cr0() & ~X86_CR0_CD);

	/* Restore value of CR4 */
	if (boot_cpu_has(X86_FEATURE_PGE))
		__write_cr4(cr4);
}

static void cyrix_set_arr(unsigned int reg, unsigned long base,
			  unsigned long size, mtrr_type type)
{
	unsigned char arr, arr_type, arr_size;

	arr = CX86_ARR_BASE + (reg << 1) + reg;	/* avoid multiplication by 3 */

	/* count down from 32M (ARR0-ARR6) or from 2G (ARR7) */
	if (reg >= 7)
		size >>= 6;

	size &= 0x7fff;		/* make sure arr_size <= 14 */
	for (arr_size = 0; size; arr_size++, size >>= 1)
		;

	if (reg < 7) {
		switch (type) {
		case MTRR_TYPE_UNCACHABLE:
			arr_type = 1;
			break;
		case MTRR_TYPE_WRCOMB:
			arr_type = 9;
			break;
		case MTRR_TYPE_WRTHROUGH:
			arr_type = 24;
			break;
		default:
			arr_type = 8;
			break;
		}
	} else {
		switch (type) {
		case MTRR_TYPE_UNCACHABLE:
			arr_type = 0;
			break;
		case MTRR_TYPE_WRCOMB:
			arr_type = 8;
			break;
		case MTRR_TYPE_WRTHROUGH:
			arr_type = 25;
			break;
		default:
			arr_type = 9;
			break;
		}
	}

	prepare_set();

	base <<= PAGE_SHIFT;
	setCx86(arr + 0,  ((unsigned char *)&base)[3]);
	setCx86(arr + 1,  ((unsigned char *)&base)[2]);
	setCx86(arr + 2, (((unsigned char *)&base)[1]) | arr_size);
	setCx86(CX86_RCR_BASE + reg, arr_type);

	post_set();
}

typedef struct {
	unsigned long	base;
	unsigned long	size;
	mtrr_type	type;
} arr_state_t;

static arr_state_t arr_state[8] = {
	{0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL},
	{0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}
};

static unsigned char ccr_state[7] = { 0, 0, 0, 0, 0, 0, 0 };

static void cyrix_set_all(void)
{
	int i;

	prepare_set();

	/* the CCRs are not contiguous */
	for (i = 0; i < 4; i++)
		setCx86(CX86_CCR0 + i, ccr_state[i]);
	for (; i < 7; i++)
		setCx86(CX86_CCR4 + i, ccr_state[i]);

	for (i = 0; i < 8; i++) {
		cyrix_set_arr(i, arr_state[i].base,
			      arr_state[i].size, arr_state[i].type);
	}

	post_set();
}

static const struct mtrr_ops cyrix_mtrr_ops = {
	.vendor            = X86_VENDOR_CYRIX,
	.set_all	   = cyrix_set_all,
	.set               = cyrix_set_arr,
	.get               = cyrix_get_arr,
	.get_free_region   = cyrix_get_free_region,
	.validate_add_page = generic_validate_add_page,
	.have_wrcomb       = positive_have_wrcomb,
};

int __init cyrix_init_mtrr(void)
{
	set_mtrr_ops(&cyrix_mtrr_ops);
	return 0;
}
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
1da177e4	2	#include <linux/init.h>
23110377	3	#include <linux/io.h>
1da177e4	4	#include <linux/mm.h>
23110377	5
f25f64ed	6	#include <asm/processor-cyrix.h>
7ebad705	7	#include <asm/processor-flags.h>
23110377 JSR	8	#include <asm/mtrr.h>
	9	#include <asm/msr.h>
	10
1da177e4 LT	11	#include "mtrr.h"
1da177e4 LT	12
1da177e4 LT	13	static void
1da177e4 LT	14	cyrix_get_arr(unsigned int reg, unsigned long *base,
365bff80	15	unsigned long size, mtrr_type type)
1da177e4	16	{
1da177e4	17	unsigned char arr, ccr3, rcr, shift;
23110377	18	unsigned long flags;
1da177e4 LT	19
	20	arr = CX86_ARR_BASE + (reg << 1) + reg; /* avoid multiplication by 3 */
	21
1da177e4 LT	22	local_irq_save(flags);
	23
	24	ccr3 = getCx86(CX86_CCR3);
	25	setCx86(CX86_CCR3, (ccr3 & 0x0f) \| 0x10); /* enable MAPEN */
23110377 JSR	26	((unsigned char *)base)[3] = getCx86(arr);
	27	((unsigned char *)base)[2] = getCx86(arr + 1);
	28	((unsigned char *)base)[1] = getCx86(arr + 2);
1da177e4	29	rcr = getCx86(CX86_RCR_BASE + reg);
23110377	30	setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
1da177e4	31
1da177e4	32	local_irq_restore(flags);
23110377	33
1da177e4 LT	34	shift = ((unsigned char *) base)[1] & 0x0f;
	35	*base >>= PAGE_SHIFT;
	36
23110377 JSR	37	/*
23110377 JSR	38	* Power of two, at least 4K on ARR0-ARR6, 256K on ARR7
1da177e4 LT	39	* Note: shift==0xf means 4G, this is unsupported.
	40	*/
	41	if (shift)
	42	*size = (reg < 7 ? 0x1UL : 0x40UL) << (shift - 1);
	43	else
	44	*size = 0;
	45
	46	/* Bit 0 is Cache Enable on ARR7, Cache Disable on ARR0-ARR6 */
	47	if (reg < 7) {
	48	switch (rcr) {
	49	case 1:
	50	*type = MTRR_TYPE_UNCACHABLE;
	51	break;
	52	case 8:
	53	*type = MTRR_TYPE_WRBACK;
	54	break;
	55	case 9:
	56	*type = MTRR_TYPE_WRCOMB;
	57	break;
	58	case 24:
	59	default:
	60	*type = MTRR_TYPE_WRTHROUGH;
	61	break;
	62	}
	63	} else {
	64	switch (rcr) {
	65	case 0:
	66	*type = MTRR_TYPE_UNCACHABLE;
	67	break;
	68	case 8:
	69	*type = MTRR_TYPE_WRCOMB;
	70	break;
	71	case 9:
	72	*type = MTRR_TYPE_WRBACK;
	73	break;
	74	case 25:
	75	default:
	76	*type = MTRR_TYPE_WRTHROUGH;
	77	break;
	78	}
	79	}
	80	}
	81
23110377 JSR	82	/*
	83	* cyrix_get_free_region - get a free ARR.
	84	*
	85	* @base: the starting (base) address of the region.
	86	* @size: the size (in bytes) of the region.
	87	*
	88	* Returns: the index of the region on success, else -1 on error.
	89	*/
1da177e4	90	static int
365bff80	91	cyrix_get_free_region(unsigned long base, unsigned long size, int replace_reg)
1da177e4	92	{
365bff80	93	unsigned long lbase, lsize;
23110377 JSR	94	mtrr_type ltype;
23110377 JSR	95	int i;
1da177e4	96
365bff80 JB	97	switch (replace_reg) {
	98	case 7:
	99	if (size < 0x40)
	100	break;
	101	case 6:
	102	case 5:
	103	case 4:
	104	return replace_reg;
	105	case 3:
365bff80 JB	106	case 2:
	107	case 1:
	108	case 0:
	109	return replace_reg;
	110	}
1da177e4 LT	111	/* If we are to set up a region >32M then look at ARR7 immediately */
	112	if (size > 0x2000) {
	113	cyrix_get_arr(7, &lbase, &lsize, &ltype);
	114	if (lsize == 0)
	115	return 7;
23110377	116	/* Else try ARR0-ARR6 first */
1da177e4 LT	117	} else {
	118	for (i = 0; i < 7; i++) {
	119	cyrix_get_arr(i, &lbase, &lsize, &ltype);
1da177e4 LT	120	if (lsize == 0)
	121	return i;
	122	}
23110377 JSR	123	/*
	124	* ARR0-ARR6 isn't free
	125	* try ARR7 but its size must be at least 256K
	126	*/
1da177e4 LT	127	cyrix_get_arr(i, &lbase, &lsize, &ltype);
	128	if ((lsize == 0) && (size >= 0x40))
	129	return i;
	130	}
	131	return -ENOSPC;
	132	}
	133
23110377	134	static u32 cr4, ccr3;
1da177e4 LT	135
	136	static void prepare_set(void)
	137	{
	138	u32 cr0;
	139
	140	/* Save value of CR4 and clear Page Global Enable (bit 7) */
c109bf95	141	if (boot_cpu_has(X86_FEATURE_PGE)) {
1e02ce4c AL	142	cr4 = __read_cr4();
1e02ce4c AL	143	__write_cr4(cr4 & ~X86_CR4_PGE);
1da177e4 LT	144	}
1da177e4 LT	145
23110377 JSR	146	/*
	147	* Disable and flush caches.
	148	* Note that wbinvd flushes the TLBs as a side-effect
	149	*/
7ebad705	150	cr0 = read_cr0() \| X86_CR0_CD;
1da177e4 LT	151	wbinvd();
	152	write_cr0(cr0);
	153	wbinvd();
	154
27b46d76	155	/* Cyrix ARRs - everything else was excluded at the top */
1da177e4 LT	156	ccr3 = getCx86(CX86_CCR3);
1da177e4 LT	157
27b46d76	158	/* Cyrix ARRs - everything else was excluded at the top */
1da177e4	159	setCx86(CX86_CCR3, (ccr3 & 0x0f) \| 0x10);
1da177e4 LT	160	}
	161
	162	static void post_set(void)
	163	{
23110377	164	/* Flush caches and TLBs */
1da177e4 LT	165	wbinvd();
	166
	167	/* Cyrix ARRs - everything else was excluded at the top */
	168	setCx86(CX86_CCR3, ccr3);
23110377 JSR	169
23110377 JSR	170	/* Enable caches */
a3d7b7dd	171	write_cr0(read_cr0() & ~X86_CR0_CD);
1da177e4	172
23110377	173	/* Restore value of CR4 */
c109bf95	174	if (boot_cpu_has(X86_FEATURE_PGE))
1e02ce4c	175	__write_cr4(cr4);
1da177e4 LT	176	}
	177
	178	static void cyrix_set_arr(unsigned int reg, unsigned long base,
	179	unsigned long size, mtrr_type type)
	180	{
	181	unsigned char arr, arr_type, arr_size;
	182
	183	arr = CX86_ARR_BASE + (reg << 1) + reg; /* avoid multiplication by 3 */
	184
	185	/* count down from 32M (ARR0-ARR6) or from 2G (ARR7) */
	186	if (reg >= 7)
	187	size >>= 6;
	188
	189	size &= 0x7fff; /* make sure arr_size <= 14 */
23110377 JSR	190	for (arr_size = 0; size; arr_size++, size >>= 1)
23110377 JSR	191	;
1da177e4 LT	192
	193	if (reg < 7) {
	194	switch (type) {
	195	case MTRR_TYPE_UNCACHABLE:
	196	arr_type = 1;
	197	break;
	198	case MTRR_TYPE_WRCOMB:
	199	arr_type = 9;
	200	break;
	201	case MTRR_TYPE_WRTHROUGH:
	202	arr_type = 24;
	203	break;
	204	default:
	205	arr_type = 8;
	206	break;
	207	}
	208	} else {
	209	switch (type) {
	210	case MTRR_TYPE_UNCACHABLE:
	211	arr_type = 0;
	212	break;
	213	case MTRR_TYPE_WRCOMB:
	214	arr_type = 8;
	215	break;
	216	case MTRR_TYPE_WRTHROUGH:
	217	arr_type = 25;
	218	break;
	219	default:
	220	arr_type = 9;
	221	break;
	222	}
	223	}
	224
	225	prepare_set();
	226
	227	base <<= PAGE_SHIFT;
23110377 JSR	228	setCx86(arr + 0, ((unsigned char *)&base)[3]);
	229	setCx86(arr + 1, ((unsigned char *)&base)[2]);
	230	setCx86(arr + 2, (((unsigned char *)&base)[1]) \| arr_size);
1da177e4 LT	231	setCx86(CX86_RCR_BASE + reg, arr_type);
	232
	233	post_set();
	234	}
	235
	236	typedef struct {
23110377 JSR	237	unsigned long base;
	238	unsigned long size;
	239	mtrr_type type;
1da177e4 LT	240	} arr_state_t;
1da177e4 LT	241
80581c43	242	static arr_state_t arr_state[8] = {
1da177e4 LT	243	{0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL},
	244	{0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}, {0UL, 0UL, 0UL}
	245	};
	246
80581c43	247	static unsigned char ccr_state[7] = { 0, 0, 0, 0, 0, 0, 0 };
1da177e4 LT	248
	249	static void cyrix_set_all(void)
	250	{
	251	int i;
	252
	253	prepare_set();
	254
	255	/* the CCRs are not contiguous */
	256	for (i = 0; i < 4; i++)
	257	setCx86(CX86_CCR0 + i, ccr_state[i]);
	258	for (; i < 7; i++)
	259	setCx86(CX86_CCR4 + i, ccr_state[i]);
23110377 JSR	260
	261	for (i = 0; i < 8; i++) {
	262	cyrix_set_arr(i, arr_state[i].base,
1da177e4	263	arr_state[i].size, arr_state[i].type);
23110377	264	}
1da177e4 LT	265
	266	post_set();
	267	}
	268
3b9cfc0a	269	static const struct mtrr_ops cyrix_mtrr_ops = {
1da177e4	270	.vendor = X86_VENDOR_CYRIX,
1da177e4 LT	271	.set_all = cyrix_set_all,
	272	.set = cyrix_set_arr,
	273	.get = cyrix_get_arr,
	274	.get_free_region = cyrix_get_free_region,
	275	.validate_add_page = generic_validate_add_page,
	276	.have_wrcomb = positive_have_wrcomb,
	277	};
	278
	279	int __init cyrix_init_mtrr(void)
	280	{
	281	set_mtrr_ops(&cyrix_mtrr_ops);
	282	return 0;
	283	}