]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* Generic MTRR (Memory Type Range Register) driver. |
2 | ||
3 | Copyright (C) 1997-2000 Richard Gooch | |
4 | Copyright (c) 2002 Patrick Mochel | |
5 | ||
6 | This library is free software; you can redistribute it and/or | |
7 | modify it under the terms of the GNU Library General Public | |
8 | License as published by the Free Software Foundation; either | |
9 | version 2 of the License, or (at your option) any later version. | |
10 | ||
11 | This library is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | Library General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU Library General Public | |
17 | License along with this library; if not, write to the Free | |
18 | Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | ||
20 | Richard Gooch may be reached by email at rgooch@atnf.csiro.au | |
21 | The postal address is: | |
22 | Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia. | |
23 | ||
24 | Source: "Pentium Pro Family Developer's Manual, Volume 3: | |
25 | Operating System Writer's Guide" (Intel document number 242692), | |
26 | section 11.11.7 | |
27 | ||
dbd51be0 JSR |
28 | This was cleaned and made readable by Patrick Mochel <mochel@osdl.org> |
29 | on 6-7 March 2002. | |
30 | Source: Intel Architecture Software Developers Manual, Volume 3: | |
1da177e4 LT |
31 | System Programming Guide; Section 9.11. (1997 edition - PPro). |
32 | */ | |
33 | ||
dbd51be0 JSR |
34 | #define DEBUG |
35 | ||
36 | #include <linux/types.h> /* FIXME: kvm_para.h needs this */ | |
37 | ||
68f202e4 | 38 | #include <linux/stop_machine.h> |
dbd51be0 JSR |
39 | #include <linux/kvm_para.h> |
40 | #include <linux/uaccess.h> | |
1da177e4 | 41 | #include <linux/module.h> |
dbd51be0 | 42 | #include <linux/mutex.h> |
1da177e4 | 43 | #include <linux/init.h> |
dbd51be0 JSR |
44 | #include <linux/sort.h> |
45 | #include <linux/cpu.h> | |
1da177e4 LT |
46 | #include <linux/pci.h> |
47 | #include <linux/smp.h> | |
1da177e4 | 48 | |
dbd51be0 | 49 | #include <asm/processor.h> |
99fc8d42 | 50 | #include <asm/e820.h> |
1da177e4 | 51 | #include <asm/mtrr.h> |
1da177e4 | 52 | #include <asm/msr.h> |
dbd51be0 | 53 | |
1da177e4 LT |
54 | #include "mtrr.h" |
55 | ||
dbd51be0 | 56 | u32 num_var_ranges; |
1da177e4 | 57 | |
b558bc0a | 58 | unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES]; |
14cc3e2b | 59 | static DEFINE_MUTEX(mtrr_mutex); |
1da177e4 | 60 | |
6c5806ca | 61 | u64 size_or_mask, size_and_mask; |
5400743d | 62 | static bool mtrr_aps_delayed_init; |
1da177e4 | 63 | |
3b9cfc0a | 64 | static const struct mtrr_ops *mtrr_ops[X86_VENDOR_NUM]; |
1da177e4 | 65 | |
3b9cfc0a | 66 | const struct mtrr_ops *mtrr_if; |
1da177e4 LT |
67 | |
68 | static void set_mtrr(unsigned int reg, unsigned long base, | |
69 | unsigned long size, mtrr_type type); | |
70 | ||
3b9cfc0a | 71 | void set_mtrr_ops(const struct mtrr_ops *ops) |
1da177e4 LT |
72 | { |
73 | if (ops->vendor && ops->vendor < X86_VENDOR_NUM) | |
74 | mtrr_ops[ops->vendor] = ops; | |
75 | } | |
76 | ||
77 | /* Returns non-zero if we have the write-combining memory type */ | |
78 | static int have_wrcomb(void) | |
79 | { | |
80 | struct pci_dev *dev; | |
a6954ba2 | 81 | u8 rev; |
dbd51be0 JSR |
82 | |
83 | dev = pci_get_class(PCI_CLASS_BRIDGE_HOST << 8, NULL); | |
84 | if (dev != NULL) { | |
85 | /* | |
86 | * ServerWorks LE chipsets < rev 6 have problems with | |
87 | * write-combining. Don't allow it and leave room for other | |
88 | * chipsets to be tagged | |
89 | */ | |
1da177e4 LT |
90 | if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS && |
91 | dev->device == PCI_DEVICE_ID_SERVERWORKS_LE) { | |
a6954ba2 LR |
92 | pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev); |
93 | if (rev <= 5) { | |
dbd51be0 | 94 | pr_info("mtrr: Serverworks LE rev < 6 detected. Write-combining disabled.\n"); |
a6954ba2 LR |
95 | pci_dev_put(dev); |
96 | return 0; | |
97 | } | |
1da177e4 | 98 | } |
dbd51be0 JSR |
99 | /* |
100 | * Intel 450NX errata # 23. Non ascending cacheline evictions to | |
101 | * write combining memory may resulting in data corruption | |
102 | */ | |
1da177e4 LT |
103 | if (dev->vendor == PCI_VENDOR_ID_INTEL && |
104 | dev->device == PCI_DEVICE_ID_INTEL_82451NX) { | |
dbd51be0 | 105 | pr_info("mtrr: Intel 450NX MMC detected. Write-combining disabled.\n"); |
1da177e4 LT |
106 | pci_dev_put(dev); |
107 | return 0; | |
108 | } | |
109 | pci_dev_put(dev); | |
dbd51be0 JSR |
110 | } |
111 | return mtrr_if->have_wrcomb ? mtrr_if->have_wrcomb() : 0; | |
1da177e4 LT |
112 | } |
113 | ||
114 | /* This function returns the number of variable MTRRs */ | |
115 | static void __init set_num_var_ranges(void) | |
116 | { | |
117 | unsigned long config = 0, dummy; | |
118 | ||
dbd51be0 | 119 | if (use_intel()) |
d9bcc01d | 120 | rdmsr(MSR_MTRRcap, config, dummy); |
dbd51be0 | 121 | else if (is_cpu(AMD)) |
1da177e4 LT |
122 | config = 2; |
123 | else if (is_cpu(CYRIX) || is_cpu(CENTAUR)) | |
124 | config = 8; | |
dbd51be0 | 125 | |
1da177e4 LT |
126 | num_var_ranges = config & 0xff; |
127 | } | |
128 | ||
129 | static void __init init_table(void) | |
130 | { | |
131 | int i, max; | |
132 | ||
133 | max = num_var_ranges; | |
1da177e4 | 134 | for (i = 0; i < max; i++) |
99fc8d42 | 135 | mtrr_usage_table[i] = 1; |
1da177e4 LT |
136 | } |
137 | ||
138 | struct set_mtrr_data { | |
139 | atomic_t count; | |
140 | atomic_t gate; | |
141 | unsigned long smp_base; | |
142 | unsigned long smp_size; | |
143 | unsigned int smp_reg; | |
144 | mtrr_type smp_type; | |
145 | }; | |
146 | ||
68f202e4 SS |
147 | static DEFINE_PER_CPU(struct cpu_stop_work, mtrr_work); |
148 | ||
dbd51be0 | 149 | /** |
68f202e4 | 150 | * mtrr_work_handler - Synchronisation handler. Executed by "other" CPUs. |
6c550ee4 | 151 | * @info: pointer to mtrr configuration data |
dbd51be0 JSR |
152 | * |
153 | * Returns nothing. | |
154 | */ | |
68f202e4 | 155 | static int mtrr_work_handler(void *info) |
1da177e4 | 156 | { |
4e2947f1 | 157 | #ifdef CONFIG_SMP |
1da177e4 LT |
158 | struct set_mtrr_data *data = info; |
159 | unsigned long flags; | |
160 | ||
68f202e4 SS |
161 | atomic_dec(&data->count); |
162 | while (!atomic_read(&data->gate)) | |
163 | cpu_relax(); | |
164 | ||
1da177e4 LT |
165 | local_irq_save(flags); |
166 | ||
167 | atomic_dec(&data->count); | |
68f202e4 | 168 | while (atomic_read(&data->gate)) |
1da177e4 LT |
169 | cpu_relax(); |
170 | ||
171 | /* The master has cleared me to execute */ | |
dbd51be0 JSR |
172 | if (data->smp_reg != ~0U) { |
173 | mtrr_if->set(data->smp_reg, data->smp_base, | |
1da177e4 | 174 | data->smp_size, data->smp_type); |
d0af9eed SS |
175 | } else if (mtrr_aps_delayed_init) { |
176 | /* | |
177 | * Initialize the MTRRs inaddition to the synchronisation. | |
178 | */ | |
1da177e4 | 179 | mtrr_if->set_all(); |
dbd51be0 | 180 | } |
1da177e4 LT |
181 | |
182 | atomic_dec(&data->count); | |
68f202e4 | 183 | while (!atomic_read(&data->gate)) |
1da177e4 LT |
184 | cpu_relax(); |
185 | ||
186 | atomic_dec(&data->count); | |
187 | local_irq_restore(flags); | |
1da177e4 | 188 | #endif |
68f202e4 | 189 | return 0; |
4e2947f1 | 190 | } |
1da177e4 | 191 | |
dbd51be0 JSR |
192 | static inline int types_compatible(mtrr_type type1, mtrr_type type2) |
193 | { | |
365bff80 JB |
194 | return type1 == MTRR_TYPE_UNCACHABLE || |
195 | type2 == MTRR_TYPE_UNCACHABLE || | |
196 | (type1 == MTRR_TYPE_WRTHROUGH && type2 == MTRR_TYPE_WRBACK) || | |
197 | (type1 == MTRR_TYPE_WRBACK && type2 == MTRR_TYPE_WRTHROUGH); | |
198 | } | |
199 | ||
1da177e4 LT |
200 | /** |
201 | * set_mtrr - update mtrrs on all processors | |
202 | * @reg: mtrr in question | |
203 | * @base: mtrr base | |
204 | * @size: mtrr size | |
205 | * @type: mtrr type | |
206 | * | |
207 | * This is kinda tricky, but fortunately, Intel spelled it out for us cleanly: | |
dbd51be0 | 208 | * |
68f202e4 | 209 | * 1. Queue work to do the following on all processors: |
1da177e4 | 210 | * 2. Disable Interrupts |
dbd51be0 | 211 | * 3. Wait for all procs to do so |
1da177e4 LT |
212 | * 4. Enter no-fill cache mode |
213 | * 5. Flush caches | |
214 | * 6. Clear PGE bit | |
215 | * 7. Flush all TLBs | |
216 | * 8. Disable all range registers | |
217 | * 9. Update the MTRRs | |
218 | * 10. Enable all range registers | |
219 | * 11. Flush all TLBs and caches again | |
220 | * 12. Enter normal cache mode and reenable caching | |
dbd51be0 | 221 | * 13. Set PGE |
1da177e4 LT |
222 | * 14. Wait for buddies to catch up |
223 | * 15. Enable interrupts. | |
dbd51be0 | 224 | * |
1da177e4 | 225 | * What does that mean for us? Well, first we set data.count to the number |
68f202e4 SS |
226 | * of CPUs. As each CPU announces that it started the rendezvous handler by |
227 | * decrementing the count, We reset data.count and set the data.gate flag | |
228 | * allowing all the cpu's to proceed with the work. As each cpu disables | |
229 | * interrupts, it'll decrement data.count once. We wait until it hits 0 and | |
230 | * proceed. We clear the data.gate flag and reset data.count. Meanwhile, they | |
231 | * are waiting for that flag to be cleared. Once it's cleared, each | |
dbd51be0 JSR |
232 | * CPU goes through the transition of updating MTRRs. |
233 | * The CPU vendors may each do it differently, | |
234 | * so we call mtrr_if->set() callback and let them take care of it. | |
235 | * When they're done, they again decrement data->count and wait for data.gate | |
68f202e4 | 236 | * to be set. |
dbd51be0 | 237 | * When we finish, we wait for data.count to hit 0 and toggle the data.gate flag |
1da177e4 LT |
238 | * Everyone then enables interrupts and we all continue on. |
239 | * | |
240 | * Note that the mechanism is the same for UP systems, too; all the SMP stuff | |
241 | * becomes nops. | |
242 | */ | |
dbd51be0 JSR |
243 | static void |
244 | set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type) | |
1da177e4 LT |
245 | { |
246 | struct set_mtrr_data data; | |
247 | unsigned long flags; | |
68f202e4 SS |
248 | int cpu; |
249 | ||
250 | preempt_disable(); | |
1da177e4 LT |
251 | |
252 | data.smp_reg = reg; | |
253 | data.smp_base = base; | |
254 | data.smp_size = size; | |
255 | data.smp_type = type; | |
256 | atomic_set(&data.count, num_booting_cpus() - 1); | |
dbd51be0 JSR |
257 | |
258 | /* Make sure data.count is visible before unleashing other CPUs */ | |
d25c1ba2 | 259 | smp_wmb(); |
dbd51be0 | 260 | atomic_set(&data.gate, 0); |
1da177e4 | 261 | |
dbd51be0 | 262 | /* Start the ball rolling on other CPUs */ |
68f202e4 SS |
263 | for_each_online_cpu(cpu) { |
264 | struct cpu_stop_work *work = &per_cpu(mtrr_work, cpu); | |
265 | ||
266 | if (cpu == smp_processor_id()) | |
267 | continue; | |
268 | ||
269 | stop_one_cpu_nowait(cpu, mtrr_work_handler, &data, work); | |
270 | } | |
1da177e4 | 271 | |
1da177e4 | 272 | |
dbd51be0 | 273 | while (atomic_read(&data.count)) |
1da177e4 LT |
274 | cpu_relax(); |
275 | ||
dbd51be0 | 276 | /* Ok, reset count and toggle gate */ |
1da177e4 | 277 | atomic_set(&data.count, num_booting_cpus() - 1); |
d25c1ba2 | 278 | smp_wmb(); |
dbd51be0 | 279 | atomic_set(&data.gate, 1); |
1da177e4 | 280 | |
68f202e4 SS |
281 | local_irq_save(flags); |
282 | ||
283 | while (atomic_read(&data.count)) | |
284 | cpu_relax(); | |
285 | ||
286 | /* Ok, reset count and toggle gate */ | |
287 | atomic_set(&data.count, num_booting_cpus() - 1); | |
288 | smp_wmb(); | |
289 | atomic_set(&data.gate, 0); | |
290 | ||
dbd51be0 | 291 | /* Do our MTRR business */ |
1da177e4 | 292 | |
dbd51be0 JSR |
293 | /* |
294 | * HACK! | |
1da177e4 LT |
295 | * We use this same function to initialize the mtrrs on boot. |
296 | * The state of the boot cpu's mtrrs has been saved, and we want | |
dbd51be0 | 297 | * to replicate across all the APs. |
1da177e4 LT |
298 | * If we're doing that @reg is set to something special... |
299 | */ | |
dbd51be0 JSR |
300 | if (reg != ~0U) |
301 | mtrr_if->set(reg, base, size, type); | |
d0af9eed SS |
302 | else if (!mtrr_aps_delayed_init) |
303 | mtrr_if->set_all(); | |
1da177e4 | 304 | |
dbd51be0 JSR |
305 | /* Wait for the others */ |
306 | while (atomic_read(&data.count)) | |
1da177e4 LT |
307 | cpu_relax(); |
308 | ||
309 | atomic_set(&data.count, num_booting_cpus() - 1); | |
d25c1ba2 | 310 | smp_wmb(); |
68f202e4 | 311 | atomic_set(&data.gate, 1); |
1da177e4 LT |
312 | |
313 | /* | |
314 | * Wait here for everyone to have seen the gate change | |
315 | * So we're the last ones to touch 'data' | |
316 | */ | |
dbd51be0 | 317 | while (atomic_read(&data.count)) |
1da177e4 LT |
318 | cpu_relax(); |
319 | ||
320 | local_irq_restore(flags); | |
68f202e4 | 321 | preempt_enable(); |
1da177e4 LT |
322 | } |
323 | ||
324 | /** | |
dbd51be0 JSR |
325 | * mtrr_add_page - Add a memory type region |
326 | * @base: Physical base address of region in pages (in units of 4 kB!) | |
327 | * @size: Physical size of region in pages (4 kB) | |
328 | * @type: Type of MTRR desired | |
329 | * @increment: If this is true do usage counting on the region | |
1da177e4 | 330 | * |
dbd51be0 JSR |
331 | * Memory type region registers control the caching on newer Intel and |
332 | * non Intel processors. This function allows drivers to request an | |
333 | * MTRR is added. The details and hardware specifics of each processor's | |
334 | * implementation are hidden from the caller, but nevertheless the | |
335 | * caller should expect to need to provide a power of two size on an | |
336 | * equivalent power of two boundary. | |
1da177e4 | 337 | * |
dbd51be0 JSR |
338 | * If the region cannot be added either because all regions are in use |
339 | * or the CPU cannot support it a negative value is returned. On success | |
340 | * the register number for this entry is returned, but should be treated | |
341 | * as a cookie only. | |
1da177e4 | 342 | * |
dbd51be0 JSR |
343 | * On a multiprocessor machine the changes are made to all processors. |
344 | * This is required on x86 by the Intel processors. | |
1da177e4 | 345 | * |
dbd51be0 | 346 | * The available types are |
1da177e4 | 347 | * |
dbd51be0 | 348 | * %MTRR_TYPE_UNCACHABLE - No caching |
1da177e4 | 349 | * |
dbd51be0 | 350 | * %MTRR_TYPE_WRBACK - Write data back in bursts whenever |
1da177e4 | 351 | * |
dbd51be0 | 352 | * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts |
1da177e4 | 353 | * |
dbd51be0 | 354 | * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes |
1da177e4 | 355 | * |
dbd51be0 JSR |
356 | * BUGS: Needs a quiet flag for the cases where drivers do not mind |
357 | * failures and do not wish system log messages to be sent. | |
1da177e4 | 358 | */ |
dbd51be0 | 359 | int mtrr_add_page(unsigned long base, unsigned long size, |
2d2ee8de | 360 | unsigned int type, bool increment) |
1da177e4 | 361 | { |
dbd51be0 | 362 | unsigned long lbase, lsize; |
365bff80 | 363 | int i, replace, error; |
1da177e4 | 364 | mtrr_type ltype; |
1da177e4 LT |
365 | |
366 | if (!mtrr_if) | |
367 | return -ENXIO; | |
dbd51be0 JSR |
368 | |
369 | error = mtrr_if->validate_add_page(base, size, type); | |
370 | if (error) | |
1da177e4 LT |
371 | return error; |
372 | ||
373 | if (type >= MTRR_NUM_TYPES) { | |
dbd51be0 | 374 | pr_warning("mtrr: type: %u invalid\n", type); |
1da177e4 LT |
375 | return -EINVAL; |
376 | } | |
377 | ||
dbd51be0 | 378 | /* If the type is WC, check that this processor supports it */ |
1da177e4 | 379 | if ((type == MTRR_TYPE_WRCOMB) && !have_wrcomb()) { |
dbd51be0 | 380 | pr_warning("mtrr: your processor doesn't support write-combining\n"); |
1da177e4 LT |
381 | return -ENOSYS; |
382 | } | |
383 | ||
365bff80 | 384 | if (!size) { |
dbd51be0 | 385 | pr_warning("mtrr: zero sized request\n"); |
365bff80 JB |
386 | return -EINVAL; |
387 | } | |
388 | ||
1da177e4 | 389 | if (base & size_or_mask || size & size_or_mask) { |
dbd51be0 | 390 | pr_warning("mtrr: base or size exceeds the MTRR width\n"); |
1da177e4 LT |
391 | return -EINVAL; |
392 | } | |
393 | ||
394 | error = -EINVAL; | |
365bff80 | 395 | replace = -1; |
1da177e4 | 396 | |
3b520b23 | 397 | /* No CPU hotplug when we change MTRR entries */ |
86ef5c9a | 398 | get_online_cpus(); |
dbd51be0 JSR |
399 | |
400 | /* Search for existing MTRR */ | |
14cc3e2b | 401 | mutex_lock(&mtrr_mutex); |
1da177e4 LT |
402 | for (i = 0; i < num_var_ranges; ++i) { |
403 | mtrr_if->get(i, &lbase, &lsize, <ype); | |
dbd51be0 JSR |
404 | if (!lsize || base > lbase + lsize - 1 || |
405 | base + size - 1 < lbase) | |
1da177e4 | 406 | continue; |
dbd51be0 JSR |
407 | /* |
408 | * At this point we know there is some kind of | |
409 | * overlap/enclosure | |
410 | */ | |
365bff80 | 411 | if (base < lbase || base + size - 1 > lbase + lsize - 1) { |
dbd51be0 JSR |
412 | if (base <= lbase && |
413 | base + size - 1 >= lbase + lsize - 1) { | |
365bff80 JB |
414 | /* New region encloses an existing region */ |
415 | if (type == ltype) { | |
416 | replace = replace == -1 ? i : -2; | |
417 | continue; | |
dbd51be0 | 418 | } else if (types_compatible(type, ltype)) |
365bff80 JB |
419 | continue; |
420 | } | |
dbd51be0 JSR |
421 | pr_warning("mtrr: 0x%lx000,0x%lx000 overlaps existing" |
422 | " 0x%lx000,0x%lx000\n", base, size, lbase, | |
423 | lsize); | |
1da177e4 LT |
424 | goto out; |
425 | } | |
dbd51be0 | 426 | /* New region is enclosed by an existing region */ |
1da177e4 | 427 | if (ltype != type) { |
365bff80 | 428 | if (types_compatible(type, ltype)) |
1da177e4 | 429 | continue; |
dbd51be0 JSR |
430 | pr_warning("mtrr: type mismatch for %lx000,%lx000 old: %s new: %s\n", |
431 | base, size, mtrr_attrib_to_str(ltype), | |
432 | mtrr_attrib_to_str(type)); | |
1da177e4 LT |
433 | goto out; |
434 | } | |
435 | if (increment) | |
99fc8d42 | 436 | ++mtrr_usage_table[i]; |
1da177e4 LT |
437 | error = i; |
438 | goto out; | |
439 | } | |
dbd51be0 | 440 | /* Search for an empty MTRR */ |
365bff80 | 441 | i = mtrr_if->get_free_region(base, size, replace); |
1da177e4 LT |
442 | if (i >= 0) { |
443 | set_mtrr(i, base, size, type); | |
99fc8d42 JB |
444 | if (likely(replace < 0)) { |
445 | mtrr_usage_table[i] = 1; | |
446 | } else { | |
447 | mtrr_usage_table[i] = mtrr_usage_table[replace]; | |
2d2ee8de | 448 | if (increment) |
99fc8d42 | 449 | mtrr_usage_table[i]++; |
365bff80 JB |
450 | if (unlikely(replace != i)) { |
451 | set_mtrr(replace, 0, 0, 0); | |
99fc8d42 | 452 | mtrr_usage_table[replace] = 0; |
365bff80 JB |
453 | } |
454 | } | |
dbd51be0 JSR |
455 | } else { |
456 | pr_info("mtrr: no more MTRRs available\n"); | |
457 | } | |
1da177e4 LT |
458 | error = i; |
459 | out: | |
14cc3e2b | 460 | mutex_unlock(&mtrr_mutex); |
86ef5c9a | 461 | put_online_cpus(); |
1da177e4 LT |
462 | return error; |
463 | } | |
464 | ||
c92c6ffd AM |
465 | static int mtrr_check(unsigned long base, unsigned long size) |
466 | { | |
467 | if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) { | |
dbd51be0 JSR |
468 | pr_warning("mtrr: size and base must be multiples of 4 kiB\n"); |
469 | pr_debug("mtrr: size: 0x%lx base: 0x%lx\n", size, base); | |
c92c6ffd AM |
470 | dump_stack(); |
471 | return -1; | |
472 | } | |
473 | return 0; | |
474 | } | |
475 | ||
1da177e4 | 476 | /** |
dbd51be0 JSR |
477 | * mtrr_add - Add a memory type region |
478 | * @base: Physical base address of region | |
479 | * @size: Physical size of region | |
480 | * @type: Type of MTRR desired | |
481 | * @increment: If this is true do usage counting on the region | |
1da177e4 | 482 | * |
dbd51be0 JSR |
483 | * Memory type region registers control the caching on newer Intel and |
484 | * non Intel processors. This function allows drivers to request an | |
485 | * MTRR is added. The details and hardware specifics of each processor's | |
486 | * implementation are hidden from the caller, but nevertheless the | |
487 | * caller should expect to need to provide a power of two size on an | |
488 | * equivalent power of two boundary. | |
1da177e4 | 489 | * |
dbd51be0 JSR |
490 | * If the region cannot be added either because all regions are in use |
491 | * or the CPU cannot support it a negative value is returned. On success | |
492 | * the register number for this entry is returned, but should be treated | |
493 | * as a cookie only. | |
1da177e4 | 494 | * |
dbd51be0 JSR |
495 | * On a multiprocessor machine the changes are made to all processors. |
496 | * This is required on x86 by the Intel processors. | |
1da177e4 | 497 | * |
dbd51be0 | 498 | * The available types are |
1da177e4 | 499 | * |
dbd51be0 | 500 | * %MTRR_TYPE_UNCACHABLE - No caching |
1da177e4 | 501 | * |
dbd51be0 | 502 | * %MTRR_TYPE_WRBACK - Write data back in bursts whenever |
1da177e4 | 503 | * |
dbd51be0 | 504 | * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts |
1da177e4 | 505 | * |
dbd51be0 | 506 | * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes |
1da177e4 | 507 | * |
dbd51be0 JSR |
508 | * BUGS: Needs a quiet flag for the cases where drivers do not mind |
509 | * failures and do not wish system log messages to be sent. | |
1da177e4 | 510 | */ |
dbd51be0 JSR |
511 | int mtrr_add(unsigned long base, unsigned long size, unsigned int type, |
512 | bool increment) | |
1da177e4 | 513 | { |
c92c6ffd | 514 | if (mtrr_check(base, size)) |
1da177e4 | 515 | return -EINVAL; |
1da177e4 LT |
516 | return mtrr_add_page(base >> PAGE_SHIFT, size >> PAGE_SHIFT, type, |
517 | increment); | |
518 | } | |
dbd51be0 | 519 | EXPORT_SYMBOL(mtrr_add); |
1da177e4 LT |
520 | |
521 | /** | |
dbd51be0 JSR |
522 | * mtrr_del_page - delete a memory type region |
523 | * @reg: Register returned by mtrr_add | |
524 | * @base: Physical base address | |
525 | * @size: Size of region | |
1da177e4 | 526 | * |
dbd51be0 JSR |
527 | * If register is supplied then base and size are ignored. This is |
528 | * how drivers should call it. | |
1da177e4 | 529 | * |
dbd51be0 JSR |
530 | * Releases an MTRR region. If the usage count drops to zero the |
531 | * register is freed and the region returns to default state. | |
532 | * On success the register is returned, on failure a negative error | |
533 | * code. | |
1da177e4 | 534 | */ |
1da177e4 LT |
535 | int mtrr_del_page(int reg, unsigned long base, unsigned long size) |
536 | { | |
537 | int i, max; | |
538 | mtrr_type ltype; | |
365bff80 | 539 | unsigned long lbase, lsize; |
1da177e4 LT |
540 | int error = -EINVAL; |
541 | ||
542 | if (!mtrr_if) | |
543 | return -ENXIO; | |
544 | ||
545 | max = num_var_ranges; | |
3b520b23 | 546 | /* No CPU hotplug when we change MTRR entries */ |
86ef5c9a | 547 | get_online_cpus(); |
14cc3e2b | 548 | mutex_lock(&mtrr_mutex); |
1da177e4 LT |
549 | if (reg < 0) { |
550 | /* Search for existing MTRR */ | |
551 | for (i = 0; i < max; ++i) { | |
552 | mtrr_if->get(i, &lbase, &lsize, <ype); | |
553 | if (lbase == base && lsize == size) { | |
554 | reg = i; | |
555 | break; | |
556 | } | |
557 | } | |
558 | if (reg < 0) { | |
dbd51be0 JSR |
559 | pr_debug("mtrr: no MTRR for %lx000,%lx000 found\n", |
560 | base, size); | |
1da177e4 LT |
561 | goto out; |
562 | } | |
563 | } | |
564 | if (reg >= max) { | |
dbd51be0 | 565 | pr_warning("mtrr: register: %d too big\n", reg); |
1da177e4 LT |
566 | goto out; |
567 | } | |
1da177e4 LT |
568 | mtrr_if->get(reg, &lbase, &lsize, <ype); |
569 | if (lsize < 1) { | |
dbd51be0 | 570 | pr_warning("mtrr: MTRR %d not used\n", reg); |
1da177e4 LT |
571 | goto out; |
572 | } | |
99fc8d42 | 573 | if (mtrr_usage_table[reg] < 1) { |
dbd51be0 | 574 | pr_warning("mtrr: reg: %d has count=0\n", reg); |
1da177e4 LT |
575 | goto out; |
576 | } | |
99fc8d42 | 577 | if (--mtrr_usage_table[reg] < 1) |
1da177e4 LT |
578 | set_mtrr(reg, 0, 0, 0); |
579 | error = reg; | |
580 | out: | |
14cc3e2b | 581 | mutex_unlock(&mtrr_mutex); |
86ef5c9a | 582 | put_online_cpus(); |
1da177e4 LT |
583 | return error; |
584 | } | |
dbd51be0 | 585 | |
1da177e4 | 586 | /** |
dbd51be0 JSR |
587 | * mtrr_del - delete a memory type region |
588 | * @reg: Register returned by mtrr_add | |
589 | * @base: Physical base address | |
590 | * @size: Size of region | |
1da177e4 | 591 | * |
dbd51be0 JSR |
592 | * If register is supplied then base and size are ignored. This is |
593 | * how drivers should call it. | |
1da177e4 | 594 | * |
dbd51be0 JSR |
595 | * Releases an MTRR region. If the usage count drops to zero the |
596 | * register is freed and the region returns to default state. | |
597 | * On success the register is returned, on failure a negative error | |
598 | * code. | |
1da177e4 | 599 | */ |
dbd51be0 | 600 | int mtrr_del(int reg, unsigned long base, unsigned long size) |
1da177e4 | 601 | { |
c92c6ffd | 602 | if (mtrr_check(base, size)) |
1da177e4 | 603 | return -EINVAL; |
1da177e4 LT |
604 | return mtrr_del_page(reg, base >> PAGE_SHIFT, size >> PAGE_SHIFT); |
605 | } | |
1da177e4 LT |
606 | EXPORT_SYMBOL(mtrr_del); |
607 | ||
dbd51be0 JSR |
608 | /* |
609 | * HACK ALERT! | |
1da177e4 LT |
610 | * These should be called implicitly, but we can't yet until all the initcall |
611 | * stuff is done... | |
612 | */ | |
1da177e4 LT |
613 | static void __init init_ifs(void) |
614 | { | |
475850c8 | 615 | #ifndef CONFIG_X86_64 |
1da177e4 LT |
616 | amd_init_mtrr(); |
617 | cyrix_init_mtrr(); | |
618 | centaur_init_mtrr(); | |
475850c8 | 619 | #endif |
1da177e4 LT |
620 | } |
621 | ||
3b520b23 SL |
622 | /* The suspend/resume methods are only for CPU without MTRR. CPU using generic |
623 | * MTRR driver doesn't require this | |
624 | */ | |
1da177e4 LT |
625 | struct mtrr_value { |
626 | mtrr_type ltype; | |
627 | unsigned long lbase; | |
365bff80 | 628 | unsigned long lsize; |
1da177e4 LT |
629 | }; |
630 | ||
f0348c43 | 631 | static struct mtrr_value mtrr_value[MTRR_MAX_VAR_RANGES]; |
1da177e4 | 632 | |
dbd51be0 | 633 | static int mtrr_save(struct sys_device *sysdev, pm_message_t state) |
1da177e4 LT |
634 | { |
635 | int i; | |
1da177e4 LT |
636 | |
637 | for (i = 0; i < num_var_ranges; i++) { | |
dbd51be0 JSR |
638 | mtrr_if->get(i, &mtrr_value[i].lbase, |
639 | &mtrr_value[i].lsize, | |
640 | &mtrr_value[i].ltype); | |
1da177e4 LT |
641 | } |
642 | return 0; | |
643 | } | |
644 | ||
dbd51be0 | 645 | static int mtrr_restore(struct sys_device *sysdev) |
1da177e4 LT |
646 | { |
647 | int i; | |
648 | ||
649 | for (i = 0; i < num_var_ranges; i++) { | |
dbd51be0 JSR |
650 | if (mtrr_value[i].lsize) { |
651 | set_mtrr(i, mtrr_value[i].lbase, | |
652 | mtrr_value[i].lsize, | |
653 | mtrr_value[i].ltype); | |
654 | } | |
1da177e4 | 655 | } |
1da177e4 LT |
656 | return 0; |
657 | } | |
658 | ||
659 | ||
660 | ||
661 | static struct sysdev_driver mtrr_sysdev_driver = { | |
662 | .suspend = mtrr_save, | |
663 | .resume = mtrr_restore, | |
664 | }; | |
665 | ||
0d890355 | 666 | int __initdata changed_by_mtrr_cleanup; |
1da177e4 LT |
667 | |
668 | /** | |
3b520b23 | 669 | * mtrr_bp_init - initialize mtrrs on the boot CPU |
1da177e4 | 670 | * |
dbd51be0 | 671 | * This needs to be called early; before any of the other CPUs are |
1da177e4 | 672 | * initialized (i.e. before smp_init()). |
dbd51be0 | 673 | * |
1da177e4 | 674 | */ |
9ef231a4 | 675 | void __init mtrr_bp_init(void) |
1da177e4 | 676 | { |
95ffa243 | 677 | u32 phys_addr; |
dbd51be0 | 678 | |
1da177e4 LT |
679 | init_ifs(); |
680 | ||
95ffa243 YL |
681 | phys_addr = 32; |
682 | ||
1da177e4 LT |
683 | if (cpu_has_mtrr) { |
684 | mtrr_if = &generic_mtrr_ops; | |
dbd51be0 | 685 | size_or_mask = 0xff000000; /* 36 bits */ |
1da177e4 | 686 | size_and_mask = 0x00f00000; |
95ffa243 | 687 | phys_addr = 36; |
1f2c958a | 688 | |
dbd51be0 JSR |
689 | /* |
690 | * This is an AMD specific MSR, but we assume(hope?) that | |
691 | * Intel will implement it to when they extend the address | |
692 | * bus of the Xeon. | |
693 | */ | |
1f2c958a | 694 | if (cpuid_eax(0x80000000) >= 0x80000008) { |
1f2c958a | 695 | phys_addr = cpuid_eax(0x80000008) & 0xff; |
af9c142d SL |
696 | /* CPUID workaround for Intel 0F33/0F34 CPU */ |
697 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
698 | boot_cpu_data.x86 == 0xF && | |
699 | boot_cpu_data.x86_model == 0x3 && | |
700 | (boot_cpu_data.x86_mask == 0x3 || | |
701 | boot_cpu_data.x86_mask == 0x4)) | |
702 | phys_addr = 36; | |
703 | ||
6c5806ca AH |
704 | size_or_mask = ~((1ULL << (phys_addr - PAGE_SHIFT)) - 1); |
705 | size_and_mask = ~size_or_mask & 0xfffff00000ULL; | |
1f2c958a AK |
706 | } else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR && |
707 | boot_cpu_data.x86 == 6) { | |
dbd51be0 JSR |
708 | /* |
709 | * VIA C* family have Intel style MTRRs, | |
710 | * but don't support PAE | |
711 | */ | |
712 | size_or_mask = 0xfff00000; /* 32 bits */ | |
1f2c958a | 713 | size_and_mask = 0; |
95ffa243 | 714 | phys_addr = 32; |
1da177e4 LT |
715 | } |
716 | } else { | |
717 | switch (boot_cpu_data.x86_vendor) { | |
718 | case X86_VENDOR_AMD: | |
719 | if (cpu_has_k6_mtrr) { | |
720 | /* Pre-Athlon (K6) AMD CPU MTRRs */ | |
721 | mtrr_if = mtrr_ops[X86_VENDOR_AMD]; | |
722 | size_or_mask = 0xfff00000; /* 32 bits */ | |
723 | size_and_mask = 0; | |
724 | } | |
725 | break; | |
726 | case X86_VENDOR_CENTAUR: | |
727 | if (cpu_has_centaur_mcr) { | |
728 | mtrr_if = mtrr_ops[X86_VENDOR_CENTAUR]; | |
729 | size_or_mask = 0xfff00000; /* 32 bits */ | |
730 | size_and_mask = 0; | |
731 | } | |
732 | break; | |
733 | case X86_VENDOR_CYRIX: | |
734 | if (cpu_has_cyrix_arr) { | |
735 | mtrr_if = mtrr_ops[X86_VENDOR_CYRIX]; | |
736 | size_or_mask = 0xfff00000; /* 32 bits */ | |
737 | size_and_mask = 0; | |
738 | } | |
739 | break; | |
740 | default: | |
741 | break; | |
742 | } | |
743 | } | |
1da177e4 LT |
744 | |
745 | if (mtrr_if) { | |
746 | set_num_var_ranges(); | |
747 | init_table(); | |
95ffa243 | 748 | if (use_intel()) { |
3b520b23 | 749 | get_mtrr_state(); |
95ffa243 | 750 | |
12031a62 YL |
751 | if (mtrr_cleanup(phys_addr)) { |
752 | changed_by_mtrr_cleanup = 1; | |
95ffa243 | 753 | mtrr_if->set_all(); |
12031a62 | 754 | } |
95ffa243 | 755 | } |
1da177e4 | 756 | } |
1da177e4 LT |
757 | } |
758 | ||
3b520b23 SL |
759 | void mtrr_ap_init(void) |
760 | { | |
d0af9eed | 761 | if (!use_intel() || mtrr_aps_delayed_init) |
3b520b23 SL |
762 | return; |
763 | /* | |
dbd51be0 JSR |
764 | * Ideally we should hold mtrr_mutex here to avoid mtrr entries |
765 | * changed, but this routine will be called in cpu boot time, | |
766 | * holding the lock breaks it. | |
767 | * | |
768 | * This routine is called in two cases: | |
769 | * | |
770 | * 1. very earily time of software resume, when there absolutely | |
771 | * isn't mtrr entry changes; | |
772 | * | |
773 | * 2. cpu hotadd time. We let mtrr_add/del_page hold cpuhotplug | |
774 | * lock to prevent mtrr entry changes | |
3b520b23 | 775 | */ |
d0af9eed | 776 | set_mtrr(~0U, 0, 0, 0); |
3b520b23 SL |
777 | } |
778 | ||
2b1f6278 BK |
779 | /** |
780 | * Save current fixed-range MTRR state of the BSP | |
781 | */ | |
782 | void mtrr_save_state(void) | |
783 | { | |
8691e5a8 | 784 | smp_call_function_single(0, mtrr_save_fixed_ranges, NULL, 1); |
2b1f6278 BK |
785 | } |
786 | ||
d0af9eed SS |
787 | void set_mtrr_aps_delayed_init(void) |
788 | { | |
789 | if (!use_intel()) | |
790 | return; | |
791 | ||
5400743d | 792 | mtrr_aps_delayed_init = true; |
d0af9eed SS |
793 | } |
794 | ||
795 | /* | |
f7448548 | 796 | * Delayed MTRR initialization for all AP's |
d0af9eed SS |
797 | */ |
798 | void mtrr_aps_init(void) | |
799 | { | |
800 | if (!use_intel()) | |
801 | return; | |
802 | ||
f7448548 SS |
803 | /* |
804 | * Check if someone has requested the delay of AP MTRR initialization, | |
805 | * by doing set_mtrr_aps_delayed_init(), prior to this point. If not, | |
806 | * then we are done. | |
807 | */ | |
808 | if (!mtrr_aps_delayed_init) | |
809 | return; | |
810 | ||
d0af9eed | 811 | set_mtrr(~0U, 0, 0, 0); |
5400743d | 812 | mtrr_aps_delayed_init = false; |
d0af9eed SS |
813 | } |
814 | ||
815 | void mtrr_bp_restore(void) | |
816 | { | |
817 | if (!use_intel()) | |
818 | return; | |
819 | ||
820 | mtrr_if->set_all(); | |
821 | } | |
822 | ||
3b520b23 SL |
823 | static int __init mtrr_init_finialize(void) |
824 | { | |
825 | if (!mtrr_if) | |
826 | return 0; | |
dbd51be0 | 827 | |
95ffa243 | 828 | if (use_intel()) { |
12031a62 | 829 | if (!changed_by_mtrr_cleanup) |
95ffa243 | 830 | mtrr_state_warn(); |
dbd51be0 | 831 | return 0; |
3b520b23 | 832 | } |
dbd51be0 JSR |
833 | |
834 | /* | |
835 | * The CPU has no MTRR and seems to not support SMP. They have | |
836 | * specific drivers, we use a tricky method to support | |
837 | * suspend/resume for them. | |
838 | * | |
839 | * TBD: is there any system with such CPU which supports | |
840 | * suspend/resume? If no, we should remove the code. | |
841 | */ | |
842 | sysdev_driver_register(&cpu_sysdev_class, &mtrr_sysdev_driver); | |
843 | ||
3b520b23 SL |
844 | return 0; |
845 | } | |
846 | subsys_initcall(mtrr_init_finialize); |