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Commit | Line | Data |
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1da177e4 LT |
1 | /* Generic MTRR (Memory Type Range Register) driver. |
2 | ||
3 | Copyright (C) 1997-2000 Richard Gooch | |
4 | Copyright (c) 2002 Patrick Mochel | |
5 | ||
6 | This library is free software; you can redistribute it and/or | |
7 | modify it under the terms of the GNU Library General Public | |
8 | License as published by the Free Software Foundation; either | |
9 | version 2 of the License, or (at your option) any later version. | |
10 | ||
11 | This library is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | Library General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU Library General Public | |
17 | License along with this library; if not, write to the Free | |
18 | Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | ||
20 | Richard Gooch may be reached by email at rgooch@atnf.csiro.au | |
21 | The postal address is: | |
22 | Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia. | |
23 | ||
24 | Source: "Pentium Pro Family Developer's Manual, Volume 3: | |
25 | Operating System Writer's Guide" (Intel document number 242692), | |
26 | section 11.11.7 | |
27 | ||
28 | This was cleaned and made readable by Patrick Mochel <mochel@osdl.org> | |
29 | on 6-7 March 2002. | |
30 | Source: Intel Architecture Software Developers Manual, Volume 3: | |
31 | System Programming Guide; Section 9.11. (1997 edition - PPro). | |
32 | */ | |
33 | ||
34 | #include <linux/module.h> | |
35 | #include <linux/init.h> | |
36 | #include <linux/pci.h> | |
37 | #include <linux/smp.h> | |
38 | #include <linux/cpu.h> | |
14cc3e2b | 39 | #include <linux/mutex.h> |
1da177e4 | 40 | |
99fc8d42 | 41 | #include <asm/e820.h> |
1da177e4 | 42 | #include <asm/mtrr.h> |
1da177e4 LT |
43 | #include <asm/uaccess.h> |
44 | #include <asm/processor.h> | |
45 | #include <asm/msr.h> | |
4147c874 | 46 | #include <asm/kvm_para.h> |
1da177e4 LT |
47 | #include "mtrr.h" |
48 | ||
1da177e4 LT |
49 | u32 num_var_ranges = 0; |
50 | ||
99fc8d42 | 51 | unsigned int mtrr_usage_table[MAX_VAR_RANGES]; |
14cc3e2b | 52 | static DEFINE_MUTEX(mtrr_mutex); |
1da177e4 | 53 | |
6c5806ca | 54 | u64 size_or_mask, size_and_mask; |
1da177e4 LT |
55 | |
56 | static struct mtrr_ops * mtrr_ops[X86_VENDOR_NUM] = {}; | |
57 | ||
58 | struct mtrr_ops * mtrr_if = NULL; | |
59 | ||
60 | static void set_mtrr(unsigned int reg, unsigned long base, | |
61 | unsigned long size, mtrr_type type); | |
62 | ||
1da177e4 LT |
63 | void set_mtrr_ops(struct mtrr_ops * ops) |
64 | { | |
65 | if (ops->vendor && ops->vendor < X86_VENDOR_NUM) | |
66 | mtrr_ops[ops->vendor] = ops; | |
67 | } | |
68 | ||
69 | /* Returns non-zero if we have the write-combining memory type */ | |
70 | static int have_wrcomb(void) | |
71 | { | |
72 | struct pci_dev *dev; | |
a6954ba2 | 73 | u8 rev; |
1da177e4 LT |
74 | |
75 | if ((dev = pci_get_class(PCI_CLASS_BRIDGE_HOST << 8, NULL)) != NULL) { | |
a6954ba2 | 76 | /* ServerWorks LE chipsets < rev 6 have problems with write-combining |
1da177e4 LT |
77 | Don't allow it and leave room for other chipsets to be tagged */ |
78 | if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS && | |
79 | dev->device == PCI_DEVICE_ID_SERVERWORKS_LE) { | |
a6954ba2 LR |
80 | pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev); |
81 | if (rev <= 5) { | |
82 | printk(KERN_INFO "mtrr: Serverworks LE rev < 6 detected. Write-combining disabled.\n"); | |
83 | pci_dev_put(dev); | |
84 | return 0; | |
85 | } | |
1da177e4 | 86 | } |
a6954ba2 | 87 | /* Intel 450NX errata # 23. Non ascending cacheline evictions to |
1da177e4 LT |
88 | write combining memory may resulting in data corruption */ |
89 | if (dev->vendor == PCI_VENDOR_ID_INTEL && | |
90 | dev->device == PCI_DEVICE_ID_INTEL_82451NX) { | |
91 | printk(KERN_INFO "mtrr: Intel 450NX MMC detected. Write-combining disabled.\n"); | |
92 | pci_dev_put(dev); | |
93 | return 0; | |
94 | } | |
95 | pci_dev_put(dev); | |
96 | } | |
97 | return (mtrr_if->have_wrcomb ? mtrr_if->have_wrcomb() : 0); | |
98 | } | |
99 | ||
100 | /* This function returns the number of variable MTRRs */ | |
101 | static void __init set_num_var_ranges(void) | |
102 | { | |
103 | unsigned long config = 0, dummy; | |
104 | ||
105 | if (use_intel()) { | |
106 | rdmsr(MTRRcap_MSR, config, dummy); | |
107 | } else if (is_cpu(AMD)) | |
108 | config = 2; | |
109 | else if (is_cpu(CYRIX) || is_cpu(CENTAUR)) | |
110 | config = 8; | |
111 | num_var_ranges = config & 0xff; | |
112 | } | |
113 | ||
114 | static void __init init_table(void) | |
115 | { | |
116 | int i, max; | |
117 | ||
118 | max = num_var_ranges; | |
1da177e4 | 119 | for (i = 0; i < max; i++) |
99fc8d42 | 120 | mtrr_usage_table[i] = 1; |
1da177e4 LT |
121 | } |
122 | ||
123 | struct set_mtrr_data { | |
124 | atomic_t count; | |
125 | atomic_t gate; | |
126 | unsigned long smp_base; | |
127 | unsigned long smp_size; | |
128 | unsigned int smp_reg; | |
129 | mtrr_type smp_type; | |
130 | }; | |
131 | ||
1da177e4 LT |
132 | static void ipi_handler(void *info) |
133 | /* [SUMMARY] Synchronisation handler. Executed by "other" CPUs. | |
134 | [RETURNS] Nothing. | |
135 | */ | |
136 | { | |
4e2947f1 | 137 | #ifdef CONFIG_SMP |
1da177e4 LT |
138 | struct set_mtrr_data *data = info; |
139 | unsigned long flags; | |
140 | ||
141 | local_irq_save(flags); | |
142 | ||
143 | atomic_dec(&data->count); | |
144 | while(!atomic_read(&data->gate)) | |
145 | cpu_relax(); | |
146 | ||
147 | /* The master has cleared me to execute */ | |
148 | if (data->smp_reg != ~0U) | |
149 | mtrr_if->set(data->smp_reg, data->smp_base, | |
150 | data->smp_size, data->smp_type); | |
151 | else | |
152 | mtrr_if->set_all(); | |
153 | ||
154 | atomic_dec(&data->count); | |
155 | while(atomic_read(&data->gate)) | |
156 | cpu_relax(); | |
157 | ||
158 | atomic_dec(&data->count); | |
159 | local_irq_restore(flags); | |
1da177e4 | 160 | #endif |
4e2947f1 | 161 | } |
1da177e4 | 162 | |
365bff80 JB |
163 | static inline int types_compatible(mtrr_type type1, mtrr_type type2) { |
164 | return type1 == MTRR_TYPE_UNCACHABLE || | |
165 | type2 == MTRR_TYPE_UNCACHABLE || | |
166 | (type1 == MTRR_TYPE_WRTHROUGH && type2 == MTRR_TYPE_WRBACK) || | |
167 | (type1 == MTRR_TYPE_WRBACK && type2 == MTRR_TYPE_WRTHROUGH); | |
168 | } | |
169 | ||
1da177e4 LT |
170 | /** |
171 | * set_mtrr - update mtrrs on all processors | |
172 | * @reg: mtrr in question | |
173 | * @base: mtrr base | |
174 | * @size: mtrr size | |
175 | * @type: mtrr type | |
176 | * | |
177 | * This is kinda tricky, but fortunately, Intel spelled it out for us cleanly: | |
178 | * | |
179 | * 1. Send IPI to do the following: | |
180 | * 2. Disable Interrupts | |
181 | * 3. Wait for all procs to do so | |
182 | * 4. Enter no-fill cache mode | |
183 | * 5. Flush caches | |
184 | * 6. Clear PGE bit | |
185 | * 7. Flush all TLBs | |
186 | * 8. Disable all range registers | |
187 | * 9. Update the MTRRs | |
188 | * 10. Enable all range registers | |
189 | * 11. Flush all TLBs and caches again | |
190 | * 12. Enter normal cache mode and reenable caching | |
191 | * 13. Set PGE | |
192 | * 14. Wait for buddies to catch up | |
193 | * 15. Enable interrupts. | |
194 | * | |
195 | * What does that mean for us? Well, first we set data.count to the number | |
196 | * of CPUs. As each CPU disables interrupts, it'll decrement it once. We wait | |
197 | * until it hits 0 and proceed. We set the data.gate flag and reset data.count. | |
198 | * Meanwhile, they are waiting for that flag to be set. Once it's set, each | |
199 | * CPU goes through the transition of updating MTRRs. The CPU vendors may each do it | |
200 | * differently, so we call mtrr_if->set() callback and let them take care of it. | |
201 | * When they're done, they again decrement data->count and wait for data.gate to | |
202 | * be reset. | |
203 | * When we finish, we wait for data.count to hit 0 and toggle the data.gate flag. | |
204 | * Everyone then enables interrupts and we all continue on. | |
205 | * | |
206 | * Note that the mechanism is the same for UP systems, too; all the SMP stuff | |
207 | * becomes nops. | |
208 | */ | |
209 | static void set_mtrr(unsigned int reg, unsigned long base, | |
210 | unsigned long size, mtrr_type type) | |
211 | { | |
212 | struct set_mtrr_data data; | |
213 | unsigned long flags; | |
214 | ||
215 | data.smp_reg = reg; | |
216 | data.smp_base = base; | |
217 | data.smp_size = size; | |
218 | data.smp_type = type; | |
219 | atomic_set(&data.count, num_booting_cpus() - 1); | |
d25c1ba2 LP |
220 | /* make sure data.count is visible before unleashing other CPUs */ |
221 | smp_wmb(); | |
1da177e4 LT |
222 | atomic_set(&data.gate,0); |
223 | ||
224 | /* Start the ball rolling on other CPUs */ | |
225 | if (smp_call_function(ipi_handler, &data, 1, 0) != 0) | |
226 | panic("mtrr: timed out waiting for other CPUs\n"); | |
227 | ||
228 | local_irq_save(flags); | |
229 | ||
230 | while(atomic_read(&data.count)) | |
231 | cpu_relax(); | |
232 | ||
233 | /* ok, reset count and toggle gate */ | |
234 | atomic_set(&data.count, num_booting_cpus() - 1); | |
d25c1ba2 | 235 | smp_wmb(); |
1da177e4 LT |
236 | atomic_set(&data.gate,1); |
237 | ||
238 | /* do our MTRR business */ | |
239 | ||
240 | /* HACK! | |
241 | * We use this same function to initialize the mtrrs on boot. | |
242 | * The state of the boot cpu's mtrrs has been saved, and we want | |
243 | * to replicate across all the APs. | |
244 | * If we're doing that @reg is set to something special... | |
245 | */ | |
246 | if (reg != ~0U) | |
247 | mtrr_if->set(reg,base,size,type); | |
248 | ||
249 | /* wait for the others */ | |
250 | while(atomic_read(&data.count)) | |
251 | cpu_relax(); | |
252 | ||
253 | atomic_set(&data.count, num_booting_cpus() - 1); | |
d25c1ba2 | 254 | smp_wmb(); |
1da177e4 LT |
255 | atomic_set(&data.gate,0); |
256 | ||
257 | /* | |
258 | * Wait here for everyone to have seen the gate change | |
259 | * So we're the last ones to touch 'data' | |
260 | */ | |
261 | while(atomic_read(&data.count)) | |
262 | cpu_relax(); | |
263 | ||
264 | local_irq_restore(flags); | |
265 | } | |
266 | ||
267 | /** | |
268 | * mtrr_add_page - Add a memory type region | |
9b483417 AM |
269 | * @base: Physical base address of region in pages (in units of 4 kB!) |
270 | * @size: Physical size of region in pages (4 kB) | |
1da177e4 LT |
271 | * @type: Type of MTRR desired |
272 | * @increment: If this is true do usage counting on the region | |
273 | * | |
274 | * Memory type region registers control the caching on newer Intel and | |
275 | * non Intel processors. This function allows drivers to request an | |
276 | * MTRR is added. The details and hardware specifics of each processor's | |
277 | * implementation are hidden from the caller, but nevertheless the | |
278 | * caller should expect to need to provide a power of two size on an | |
279 | * equivalent power of two boundary. | |
280 | * | |
281 | * If the region cannot be added either because all regions are in use | |
282 | * or the CPU cannot support it a negative value is returned. On success | |
283 | * the register number for this entry is returned, but should be treated | |
284 | * as a cookie only. | |
285 | * | |
286 | * On a multiprocessor machine the changes are made to all processors. | |
287 | * This is required on x86 by the Intel processors. | |
288 | * | |
289 | * The available types are | |
290 | * | |
291 | * %MTRR_TYPE_UNCACHABLE - No caching | |
292 | * | |
293 | * %MTRR_TYPE_WRBACK - Write data back in bursts whenever | |
294 | * | |
295 | * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts | |
296 | * | |
297 | * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes | |
298 | * | |
299 | * BUGS: Needs a quiet flag for the cases where drivers do not mind | |
300 | * failures and do not wish system log messages to be sent. | |
301 | */ | |
302 | ||
303 | int mtrr_add_page(unsigned long base, unsigned long size, | |
2d2ee8de | 304 | unsigned int type, bool increment) |
1da177e4 | 305 | { |
365bff80 | 306 | int i, replace, error; |
1da177e4 | 307 | mtrr_type ltype; |
365bff80 | 308 | unsigned long lbase, lsize; |
1da177e4 LT |
309 | |
310 | if (!mtrr_if) | |
311 | return -ENXIO; | |
312 | ||
313 | if ((error = mtrr_if->validate_add_page(base,size,type))) | |
314 | return error; | |
315 | ||
316 | if (type >= MTRR_NUM_TYPES) { | |
317 | printk(KERN_WARNING "mtrr: type: %u invalid\n", type); | |
318 | return -EINVAL; | |
319 | } | |
320 | ||
321 | /* If the type is WC, check that this processor supports it */ | |
322 | if ((type == MTRR_TYPE_WRCOMB) && !have_wrcomb()) { | |
323 | printk(KERN_WARNING | |
324 | "mtrr: your processor doesn't support write-combining\n"); | |
325 | return -ENOSYS; | |
326 | } | |
327 | ||
365bff80 JB |
328 | if (!size) { |
329 | printk(KERN_WARNING "mtrr: zero sized request\n"); | |
330 | return -EINVAL; | |
331 | } | |
332 | ||
1da177e4 LT |
333 | if (base & size_or_mask || size & size_or_mask) { |
334 | printk(KERN_WARNING "mtrr: base or size exceeds the MTRR width\n"); | |
335 | return -EINVAL; | |
336 | } | |
337 | ||
338 | error = -EINVAL; | |
365bff80 | 339 | replace = -1; |
1da177e4 | 340 | |
3b520b23 | 341 | /* No CPU hotplug when we change MTRR entries */ |
86ef5c9a | 342 | get_online_cpus(); |
1da177e4 | 343 | /* Search for existing MTRR */ |
14cc3e2b | 344 | mutex_lock(&mtrr_mutex); |
1da177e4 LT |
345 | for (i = 0; i < num_var_ranges; ++i) { |
346 | mtrr_if->get(i, &lbase, &lsize, <ype); | |
365bff80 | 347 | if (!lsize || base > lbase + lsize - 1 || base + size - 1 < lbase) |
1da177e4 LT |
348 | continue; |
349 | /* At this point we know there is some kind of overlap/enclosure */ | |
365bff80 JB |
350 | if (base < lbase || base + size - 1 > lbase + lsize - 1) { |
351 | if (base <= lbase && base + size - 1 >= lbase + lsize - 1) { | |
352 | /* New region encloses an existing region */ | |
353 | if (type == ltype) { | |
354 | replace = replace == -1 ? i : -2; | |
355 | continue; | |
356 | } | |
357 | else if (types_compatible(type, ltype)) | |
358 | continue; | |
359 | } | |
1da177e4 LT |
360 | printk(KERN_WARNING |
361 | "mtrr: 0x%lx000,0x%lx000 overlaps existing" | |
365bff80 | 362 | " 0x%lx000,0x%lx000\n", base, size, lbase, |
1da177e4 LT |
363 | lsize); |
364 | goto out; | |
365 | } | |
366 | /* New region is enclosed by an existing region */ | |
367 | if (ltype != type) { | |
365bff80 | 368 | if (types_compatible(type, ltype)) |
1da177e4 LT |
369 | continue; |
370 | printk (KERN_WARNING "mtrr: type mismatch for %lx000,%lx000 old: %s new: %s\n", | |
371 | base, size, mtrr_attrib_to_str(ltype), | |
372 | mtrr_attrib_to_str(type)); | |
373 | goto out; | |
374 | } | |
375 | if (increment) | |
99fc8d42 | 376 | ++mtrr_usage_table[i]; |
1da177e4 LT |
377 | error = i; |
378 | goto out; | |
379 | } | |
380 | /* Search for an empty MTRR */ | |
365bff80 | 381 | i = mtrr_if->get_free_region(base, size, replace); |
1da177e4 LT |
382 | if (i >= 0) { |
383 | set_mtrr(i, base, size, type); | |
99fc8d42 JB |
384 | if (likely(replace < 0)) { |
385 | mtrr_usage_table[i] = 1; | |
386 | } else { | |
387 | mtrr_usage_table[i] = mtrr_usage_table[replace]; | |
2d2ee8de | 388 | if (increment) |
99fc8d42 | 389 | mtrr_usage_table[i]++; |
365bff80 JB |
390 | if (unlikely(replace != i)) { |
391 | set_mtrr(replace, 0, 0, 0); | |
99fc8d42 | 392 | mtrr_usage_table[replace] = 0; |
365bff80 JB |
393 | } |
394 | } | |
1da177e4 LT |
395 | } else |
396 | printk(KERN_INFO "mtrr: no more MTRRs available\n"); | |
397 | error = i; | |
398 | out: | |
14cc3e2b | 399 | mutex_unlock(&mtrr_mutex); |
86ef5c9a | 400 | put_online_cpus(); |
1da177e4 LT |
401 | return error; |
402 | } | |
403 | ||
c92c6ffd AM |
404 | static int mtrr_check(unsigned long base, unsigned long size) |
405 | { | |
406 | if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) { | |
407 | printk(KERN_WARNING | |
408 | "mtrr: size and base must be multiples of 4 kiB\n"); | |
409 | printk(KERN_DEBUG | |
410 | "mtrr: size: 0x%lx base: 0x%lx\n", size, base); | |
411 | dump_stack(); | |
412 | return -1; | |
413 | } | |
414 | return 0; | |
415 | } | |
416 | ||
1da177e4 LT |
417 | /** |
418 | * mtrr_add - Add a memory type region | |
419 | * @base: Physical base address of region | |
420 | * @size: Physical size of region | |
421 | * @type: Type of MTRR desired | |
422 | * @increment: If this is true do usage counting on the region | |
423 | * | |
424 | * Memory type region registers control the caching on newer Intel and | |
425 | * non Intel processors. This function allows drivers to request an | |
426 | * MTRR is added. The details and hardware specifics of each processor's | |
427 | * implementation are hidden from the caller, but nevertheless the | |
428 | * caller should expect to need to provide a power of two size on an | |
429 | * equivalent power of two boundary. | |
430 | * | |
431 | * If the region cannot be added either because all regions are in use | |
432 | * or the CPU cannot support it a negative value is returned. On success | |
433 | * the register number for this entry is returned, but should be treated | |
434 | * as a cookie only. | |
435 | * | |
436 | * On a multiprocessor machine the changes are made to all processors. | |
437 | * This is required on x86 by the Intel processors. | |
438 | * | |
439 | * The available types are | |
440 | * | |
441 | * %MTRR_TYPE_UNCACHABLE - No caching | |
442 | * | |
443 | * %MTRR_TYPE_WRBACK - Write data back in bursts whenever | |
444 | * | |
445 | * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts | |
446 | * | |
447 | * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes | |
448 | * | |
449 | * BUGS: Needs a quiet flag for the cases where drivers do not mind | |
450 | * failures and do not wish system log messages to be sent. | |
451 | */ | |
452 | ||
453 | int | |
454 | mtrr_add(unsigned long base, unsigned long size, unsigned int type, | |
2d2ee8de | 455 | bool increment) |
1da177e4 | 456 | { |
c92c6ffd | 457 | if (mtrr_check(base, size)) |
1da177e4 | 458 | return -EINVAL; |
1da177e4 LT |
459 | return mtrr_add_page(base >> PAGE_SHIFT, size >> PAGE_SHIFT, type, |
460 | increment); | |
461 | } | |
462 | ||
463 | /** | |
464 | * mtrr_del_page - delete a memory type region | |
465 | * @reg: Register returned by mtrr_add | |
466 | * @base: Physical base address | |
467 | * @size: Size of region | |
468 | * | |
469 | * If register is supplied then base and size are ignored. This is | |
470 | * how drivers should call it. | |
471 | * | |
472 | * Releases an MTRR region. If the usage count drops to zero the | |
473 | * register is freed and the region returns to default state. | |
474 | * On success the register is returned, on failure a negative error | |
475 | * code. | |
476 | */ | |
477 | ||
478 | int mtrr_del_page(int reg, unsigned long base, unsigned long size) | |
479 | { | |
480 | int i, max; | |
481 | mtrr_type ltype; | |
365bff80 | 482 | unsigned long lbase, lsize; |
1da177e4 LT |
483 | int error = -EINVAL; |
484 | ||
485 | if (!mtrr_if) | |
486 | return -ENXIO; | |
487 | ||
488 | max = num_var_ranges; | |
3b520b23 | 489 | /* No CPU hotplug when we change MTRR entries */ |
86ef5c9a | 490 | get_online_cpus(); |
14cc3e2b | 491 | mutex_lock(&mtrr_mutex); |
1da177e4 LT |
492 | if (reg < 0) { |
493 | /* Search for existing MTRR */ | |
494 | for (i = 0; i < max; ++i) { | |
495 | mtrr_if->get(i, &lbase, &lsize, <ype); | |
496 | if (lbase == base && lsize == size) { | |
497 | reg = i; | |
498 | break; | |
499 | } | |
500 | } | |
501 | if (reg < 0) { | |
502 | printk(KERN_DEBUG "mtrr: no MTRR for %lx000,%lx000 found\n", base, | |
503 | size); | |
504 | goto out; | |
505 | } | |
506 | } | |
507 | if (reg >= max) { | |
508 | printk(KERN_WARNING "mtrr: register: %d too big\n", reg); | |
509 | goto out; | |
510 | } | |
1da177e4 LT |
511 | mtrr_if->get(reg, &lbase, &lsize, <ype); |
512 | if (lsize < 1) { | |
513 | printk(KERN_WARNING "mtrr: MTRR %d not used\n", reg); | |
514 | goto out; | |
515 | } | |
99fc8d42 | 516 | if (mtrr_usage_table[reg] < 1) { |
1da177e4 LT |
517 | printk(KERN_WARNING "mtrr: reg: %d has count=0\n", reg); |
518 | goto out; | |
519 | } | |
99fc8d42 | 520 | if (--mtrr_usage_table[reg] < 1) |
1da177e4 LT |
521 | set_mtrr(reg, 0, 0, 0); |
522 | error = reg; | |
523 | out: | |
14cc3e2b | 524 | mutex_unlock(&mtrr_mutex); |
86ef5c9a | 525 | put_online_cpus(); |
1da177e4 LT |
526 | return error; |
527 | } | |
528 | /** | |
529 | * mtrr_del - delete a memory type region | |
530 | * @reg: Register returned by mtrr_add | |
531 | * @base: Physical base address | |
532 | * @size: Size of region | |
533 | * | |
534 | * If register is supplied then base and size are ignored. This is | |
535 | * how drivers should call it. | |
536 | * | |
537 | * Releases an MTRR region. If the usage count drops to zero the | |
538 | * register is freed and the region returns to default state. | |
539 | * On success the register is returned, on failure a negative error | |
540 | * code. | |
541 | */ | |
542 | ||
543 | int | |
544 | mtrr_del(int reg, unsigned long base, unsigned long size) | |
545 | { | |
c92c6ffd | 546 | if (mtrr_check(base, size)) |
1da177e4 | 547 | return -EINVAL; |
1da177e4 LT |
548 | return mtrr_del_page(reg, base >> PAGE_SHIFT, size >> PAGE_SHIFT); |
549 | } | |
550 | ||
551 | EXPORT_SYMBOL(mtrr_add); | |
552 | EXPORT_SYMBOL(mtrr_del); | |
553 | ||
554 | /* HACK ALERT! | |
555 | * These should be called implicitly, but we can't yet until all the initcall | |
556 | * stuff is done... | |
557 | */ | |
1da177e4 LT |
558 | static void __init init_ifs(void) |
559 | { | |
475850c8 | 560 | #ifndef CONFIG_X86_64 |
1da177e4 LT |
561 | amd_init_mtrr(); |
562 | cyrix_init_mtrr(); | |
563 | centaur_init_mtrr(); | |
475850c8 | 564 | #endif |
1da177e4 LT |
565 | } |
566 | ||
3b520b23 SL |
567 | /* The suspend/resume methods are only for CPU without MTRR. CPU using generic |
568 | * MTRR driver doesn't require this | |
569 | */ | |
1da177e4 LT |
570 | struct mtrr_value { |
571 | mtrr_type ltype; | |
572 | unsigned long lbase; | |
365bff80 | 573 | unsigned long lsize; |
1da177e4 LT |
574 | }; |
575 | ||
99fc8d42 | 576 | static struct mtrr_value mtrr_state[MAX_VAR_RANGES]; |
1da177e4 | 577 | |
829ca9a3 | 578 | static int mtrr_save(struct sys_device * sysdev, pm_message_t state) |
1da177e4 LT |
579 | { |
580 | int i; | |
1da177e4 LT |
581 | |
582 | for (i = 0; i < num_var_ranges; i++) { | |
583 | mtrr_if->get(i, | |
584 | &mtrr_state[i].lbase, | |
585 | &mtrr_state[i].lsize, | |
586 | &mtrr_state[i].ltype); | |
587 | } | |
588 | return 0; | |
589 | } | |
590 | ||
591 | static int mtrr_restore(struct sys_device * sysdev) | |
592 | { | |
593 | int i; | |
594 | ||
595 | for (i = 0; i < num_var_ranges; i++) { | |
596 | if (mtrr_state[i].lsize) | |
597 | set_mtrr(i, | |
598 | mtrr_state[i].lbase, | |
599 | mtrr_state[i].lsize, | |
600 | mtrr_state[i].ltype); | |
601 | } | |
1da177e4 LT |
602 | return 0; |
603 | } | |
604 | ||
605 | ||
606 | ||
607 | static struct sysdev_driver mtrr_sysdev_driver = { | |
608 | .suspend = mtrr_save, | |
609 | .resume = mtrr_restore, | |
610 | }; | |
611 | ||
99fc8d42 JB |
612 | static int disable_mtrr_trim; |
613 | ||
614 | static int __init disable_mtrr_trim_setup(char *str) | |
615 | { | |
616 | disable_mtrr_trim = 1; | |
617 | return 0; | |
618 | } | |
619 | early_param("disable_mtrr_trim", disable_mtrr_trim_setup); | |
620 | ||
621 | /* | |
622 | * Newer AMD K8s and later CPUs have a special magic MSR way to force WB | |
623 | * for memory >4GB. Check for that here. | |
624 | * Note this won't check if the MTRRs < 4GB where the magic bit doesn't | |
625 | * apply to are wrong, but so far we don't know of any such case in the wild. | |
626 | */ | |
627 | #define Tom2Enabled (1U << 21) | |
628 | #define Tom2ForceMemTypeWB (1U << 22) | |
629 | ||
093af8d7 | 630 | static __init int amd_special_default_mtrr(void) |
99fc8d42 JB |
631 | { |
632 | u32 l, h; | |
633 | ||
99fc8d42 JB |
634 | if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) |
635 | return 0; | |
636 | if (boot_cpu_data.x86 < 0xf || boot_cpu_data.x86 > 0x11) | |
637 | return 0; | |
638 | /* In case some hypervisor doesn't pass SYSCFG through */ | |
639 | if (rdmsr_safe(MSR_K8_SYSCFG, &l, &h) < 0) | |
640 | return 0; | |
641 | /* | |
642 | * Memory between 4GB and top of mem is forced WB by this magic bit. | |
643 | * Reserved before K8RevF, but should be zero there. | |
644 | */ | |
645 | if ((l & (Tom2Enabled | Tom2ForceMemTypeWB)) == | |
646 | (Tom2Enabled | Tom2ForceMemTypeWB)) | |
647 | return 1; | |
648 | return 0; | |
649 | } | |
650 | ||
651 | /** | |
652 | * mtrr_trim_uncached_memory - trim RAM not covered by MTRRs | |
f5106d91 | 653 | * @end_pfn: ending page frame number |
99fc8d42 JB |
654 | * |
655 | * Some buggy BIOSes don't setup the MTRRs properly for systems with certain | |
656 | * memory configurations. This routine checks that the highest MTRR matches | |
657 | * the end of memory, to make sure the MTRRs having a write back type cover | |
658 | * all of the memory the kernel is intending to use. If not, it'll trim any | |
659 | * memory off the end by adjusting end_pfn, removing it from the kernel's | |
660 | * allocation pools, warning the user with an obnoxious message. | |
661 | */ | |
662 | int __init mtrr_trim_uncached_memory(unsigned long end_pfn) | |
663 | { | |
20651af9 | 664 | unsigned long i, base, size, highest_pfn = 0, def, dummy; |
99fc8d42 JB |
665 | mtrr_type type; |
666 | u64 trim_start, trim_size; | |
667 | ||
668 | /* | |
669 | * Make sure we only trim uncachable memory on machines that | |
670 | * support the Intel MTRR architecture: | |
671 | */ | |
093af8d7 YL |
672 | if (!is_cpu(INTEL) || disable_mtrr_trim) |
673 | return 0; | |
99fc8d42 JB |
674 | rdmsr(MTRRdefType_MSR, def, dummy); |
675 | def &= 0xff; | |
093af8d7 YL |
676 | if (def != MTRR_TYPE_UNCACHABLE) |
677 | return 0; | |
678 | ||
679 | if (amd_special_default_mtrr()) | |
99fc8d42 JB |
680 | return 0; |
681 | ||
682 | /* Find highest cached pfn */ | |
683 | for (i = 0; i < num_var_ranges; i++) { | |
684 | mtrr_if->get(i, &base, &size, &type); | |
685 | if (type != MTRR_TYPE_WRBACK) | |
686 | continue; | |
20651af9 YL |
687 | if (highest_pfn < base + size) |
688 | highest_pfn = base + size; | |
99fc8d42 JB |
689 | } |
690 | ||
093af8d7 | 691 | /* kvm/qemu doesn't have mtrr set right, don't trim them all */ |
20651af9 | 692 | if (!highest_pfn) { |
4147c874 JR |
693 | if (!kvm_para_available()) { |
694 | printk(KERN_WARNING | |
695 | "WARNING: strange, CPU MTRRs all blank?\n"); | |
696 | WARN_ON(1); | |
697 | } | |
99fc8d42 | 698 | return 0; |
093af8d7 | 699 | } |
99fc8d42 | 700 | |
20651af9 | 701 | if (highest_pfn < end_pfn) { |
cd7d72bb | 702 | printk(KERN_WARNING "WARNING: BIOS bug: CPU MTRRs don't cover" |
20651af9 YL |
703 | " all of memory, losing %luMB of RAM.\n", |
704 | (end_pfn - highest_pfn) >> (20 - PAGE_SHIFT)); | |
cd7d72bb IM |
705 | |
706 | WARN_ON(1); | |
99fc8d42 JB |
707 | |
708 | printk(KERN_INFO "update e820 for mtrr\n"); | |
20651af9 YL |
709 | trim_start = highest_pfn; |
710 | trim_start <<= PAGE_SHIFT; | |
99fc8d42 JB |
711 | trim_size = end_pfn; |
712 | trim_size <<= PAGE_SHIFT; | |
713 | trim_size -= trim_start; | |
714 | add_memory_region(trim_start, trim_size, E820_RESERVED); | |
715 | update_e820(); | |
716 | return 1; | |
717 | } | |
718 | ||
719 | return 0; | |
720 | } | |
1da177e4 LT |
721 | |
722 | /** | |
3b520b23 | 723 | * mtrr_bp_init - initialize mtrrs on the boot CPU |
1da177e4 LT |
724 | * |
725 | * This needs to be called early; before any of the other CPUs are | |
726 | * initialized (i.e. before smp_init()). | |
727 | * | |
728 | */ | |
9ef231a4 | 729 | void __init mtrr_bp_init(void) |
1da177e4 LT |
730 | { |
731 | init_ifs(); | |
732 | ||
733 | if (cpu_has_mtrr) { | |
734 | mtrr_if = &generic_mtrr_ops; | |
735 | size_or_mask = 0xff000000; /* 36 bits */ | |
736 | size_and_mask = 0x00f00000; | |
1f2c958a AK |
737 | |
738 | /* This is an AMD specific MSR, but we assume(hope?) that | |
739 | Intel will implement it to when they extend the address | |
740 | bus of the Xeon. */ | |
741 | if (cpuid_eax(0x80000000) >= 0x80000008) { | |
742 | u32 phys_addr; | |
743 | phys_addr = cpuid_eax(0x80000008) & 0xff; | |
af9c142d SL |
744 | /* CPUID workaround for Intel 0F33/0F34 CPU */ |
745 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
746 | boot_cpu_data.x86 == 0xF && | |
747 | boot_cpu_data.x86_model == 0x3 && | |
748 | (boot_cpu_data.x86_mask == 0x3 || | |
749 | boot_cpu_data.x86_mask == 0x4)) | |
750 | phys_addr = 36; | |
751 | ||
6c5806ca AH |
752 | size_or_mask = ~((1ULL << (phys_addr - PAGE_SHIFT)) - 1); |
753 | size_and_mask = ~size_or_mask & 0xfffff00000ULL; | |
1f2c958a AK |
754 | } else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR && |
755 | boot_cpu_data.x86 == 6) { | |
756 | /* VIA C* family have Intel style MTRRs, but | |
757 | don't support PAE */ | |
758 | size_or_mask = 0xfff00000; /* 32 bits */ | |
759 | size_and_mask = 0; | |
1da177e4 LT |
760 | } |
761 | } else { | |
762 | switch (boot_cpu_data.x86_vendor) { | |
763 | case X86_VENDOR_AMD: | |
764 | if (cpu_has_k6_mtrr) { | |
765 | /* Pre-Athlon (K6) AMD CPU MTRRs */ | |
766 | mtrr_if = mtrr_ops[X86_VENDOR_AMD]; | |
767 | size_or_mask = 0xfff00000; /* 32 bits */ | |
768 | size_and_mask = 0; | |
769 | } | |
770 | break; | |
771 | case X86_VENDOR_CENTAUR: | |
772 | if (cpu_has_centaur_mcr) { | |
773 | mtrr_if = mtrr_ops[X86_VENDOR_CENTAUR]; | |
774 | size_or_mask = 0xfff00000; /* 32 bits */ | |
775 | size_and_mask = 0; | |
776 | } | |
777 | break; | |
778 | case X86_VENDOR_CYRIX: | |
779 | if (cpu_has_cyrix_arr) { | |
780 | mtrr_if = mtrr_ops[X86_VENDOR_CYRIX]; | |
781 | size_or_mask = 0xfff00000; /* 32 bits */ | |
782 | size_and_mask = 0; | |
783 | } | |
784 | break; | |
785 | default: | |
786 | break; | |
787 | } | |
788 | } | |
1da177e4 LT |
789 | |
790 | if (mtrr_if) { | |
791 | set_num_var_ranges(); | |
792 | init_table(); | |
3b520b23 SL |
793 | if (use_intel()) |
794 | get_mtrr_state(); | |
1da177e4 | 795 | } |
1da177e4 LT |
796 | } |
797 | ||
3b520b23 SL |
798 | void mtrr_ap_init(void) |
799 | { | |
800 | unsigned long flags; | |
801 | ||
802 | if (!mtrr_if || !use_intel()) | |
803 | return; | |
804 | /* | |
14cc3e2b | 805 | * Ideally we should hold mtrr_mutex here to avoid mtrr entries changed, |
3b520b23 SL |
806 | * but this routine will be called in cpu boot time, holding the lock |
807 | * breaks it. This routine is called in two cases: 1.very earily time | |
808 | * of software resume, when there absolutely isn't mtrr entry changes; | |
809 | * 2.cpu hotadd time. We let mtrr_add/del_page hold cpuhotplug lock to | |
810 | * prevent mtrr entry changes | |
811 | */ | |
812 | local_irq_save(flags); | |
813 | ||
814 | mtrr_if->set_all(); | |
815 | ||
816 | local_irq_restore(flags); | |
817 | } | |
818 | ||
2b1f6278 BK |
819 | /** |
820 | * Save current fixed-range MTRR state of the BSP | |
821 | */ | |
822 | void mtrr_save_state(void) | |
823 | { | |
c8f2518e | 824 | smp_call_function_single(0, mtrr_save_fixed_ranges, NULL, 1, 1); |
2b1f6278 BK |
825 | } |
826 | ||
3b520b23 SL |
827 | static int __init mtrr_init_finialize(void) |
828 | { | |
829 | if (!mtrr_if) | |
830 | return 0; | |
831 | if (use_intel()) | |
832 | mtrr_state_warn(); | |
833 | else { | |
27b46d76 | 834 | /* The CPUs haven't MTRR and seem to not support SMP. They have |
3b520b23 SL |
835 | * specific drivers, we use a tricky method to support |
836 | * suspend/resume for them. | |
837 | * TBD: is there any system with such CPU which supports | |
838 | * suspend/resume? if no, we should remove the code. | |
839 | */ | |
840 | sysdev_driver_register(&cpu_sysdev_class, | |
841 | &mtrr_sysdev_driver); | |
842 | } | |
843 | return 0; | |
844 | } | |
845 | subsys_initcall(mtrr_init_finialize); |