]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* Generic MTRR (Memory Type Range Register) driver. |
2 | ||
3 | Copyright (C) 1997-2000 Richard Gooch | |
4 | Copyright (c) 2002 Patrick Mochel | |
5 | ||
6 | This library is free software; you can redistribute it and/or | |
7 | modify it under the terms of the GNU Library General Public | |
8 | License as published by the Free Software Foundation; either | |
9 | version 2 of the License, or (at your option) any later version. | |
10 | ||
11 | This library is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | Library General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU Library General Public | |
17 | License along with this library; if not, write to the Free | |
18 | Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | ||
20 | Richard Gooch may be reached by email at rgooch@atnf.csiro.au | |
21 | The postal address is: | |
22 | Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia. | |
23 | ||
24 | Source: "Pentium Pro Family Developer's Manual, Volume 3: | |
25 | Operating System Writer's Guide" (Intel document number 242692), | |
26 | section 11.11.7 | |
27 | ||
28 | This was cleaned and made readable by Patrick Mochel <mochel@osdl.org> | |
29 | on 6-7 March 2002. | |
30 | Source: Intel Architecture Software Developers Manual, Volume 3: | |
31 | System Programming Guide; Section 9.11. (1997 edition - PPro). | |
32 | */ | |
33 | ||
34 | #include <linux/module.h> | |
35 | #include <linux/init.h> | |
36 | #include <linux/pci.h> | |
37 | #include <linux/smp.h> | |
38 | #include <linux/cpu.h> | |
14cc3e2b | 39 | #include <linux/mutex.h> |
1da177e4 LT |
40 | |
41 | #include <asm/mtrr.h> | |
42 | ||
43 | #include <asm/uaccess.h> | |
44 | #include <asm/processor.h> | |
45 | #include <asm/msr.h> | |
46 | #include "mtrr.h" | |
47 | ||
1da177e4 LT |
48 | u32 num_var_ranges = 0; |
49 | ||
50 | unsigned int *usage_table; | |
14cc3e2b | 51 | static DEFINE_MUTEX(mtrr_mutex); |
1da177e4 | 52 | |
6c5806ca | 53 | u64 size_or_mask, size_and_mask; |
1da177e4 LT |
54 | |
55 | static struct mtrr_ops * mtrr_ops[X86_VENDOR_NUM] = {}; | |
56 | ||
57 | struct mtrr_ops * mtrr_if = NULL; | |
58 | ||
59 | static void set_mtrr(unsigned int reg, unsigned long base, | |
60 | unsigned long size, mtrr_type type); | |
61 | ||
475850c8 | 62 | #ifndef CONFIG_X86_64 |
1da177e4 | 63 | extern int arr3_protected; |
475850c8 JB |
64 | #else |
65 | #define arr3_protected 0 | |
66 | #endif | |
1da177e4 LT |
67 | |
68 | void set_mtrr_ops(struct mtrr_ops * ops) | |
69 | { | |
70 | if (ops->vendor && ops->vendor < X86_VENDOR_NUM) | |
71 | mtrr_ops[ops->vendor] = ops; | |
72 | } | |
73 | ||
74 | /* Returns non-zero if we have the write-combining memory type */ | |
75 | static int have_wrcomb(void) | |
76 | { | |
77 | struct pci_dev *dev; | |
a6954ba2 | 78 | u8 rev; |
1da177e4 LT |
79 | |
80 | if ((dev = pci_get_class(PCI_CLASS_BRIDGE_HOST << 8, NULL)) != NULL) { | |
a6954ba2 | 81 | /* ServerWorks LE chipsets < rev 6 have problems with write-combining |
1da177e4 LT |
82 | Don't allow it and leave room for other chipsets to be tagged */ |
83 | if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS && | |
84 | dev->device == PCI_DEVICE_ID_SERVERWORKS_LE) { | |
a6954ba2 LR |
85 | pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev); |
86 | if (rev <= 5) { | |
87 | printk(KERN_INFO "mtrr: Serverworks LE rev < 6 detected. Write-combining disabled.\n"); | |
88 | pci_dev_put(dev); | |
89 | return 0; | |
90 | } | |
1da177e4 | 91 | } |
a6954ba2 | 92 | /* Intel 450NX errata # 23. Non ascending cacheline evictions to |
1da177e4 LT |
93 | write combining memory may resulting in data corruption */ |
94 | if (dev->vendor == PCI_VENDOR_ID_INTEL && | |
95 | dev->device == PCI_DEVICE_ID_INTEL_82451NX) { | |
96 | printk(KERN_INFO "mtrr: Intel 450NX MMC detected. Write-combining disabled.\n"); | |
97 | pci_dev_put(dev); | |
98 | return 0; | |
99 | } | |
100 | pci_dev_put(dev); | |
101 | } | |
102 | return (mtrr_if->have_wrcomb ? mtrr_if->have_wrcomb() : 0); | |
103 | } | |
104 | ||
105 | /* This function returns the number of variable MTRRs */ | |
106 | static void __init set_num_var_ranges(void) | |
107 | { | |
108 | unsigned long config = 0, dummy; | |
109 | ||
110 | if (use_intel()) { | |
111 | rdmsr(MTRRcap_MSR, config, dummy); | |
112 | } else if (is_cpu(AMD)) | |
113 | config = 2; | |
114 | else if (is_cpu(CYRIX) || is_cpu(CENTAUR)) | |
115 | config = 8; | |
116 | num_var_ranges = config & 0xff; | |
117 | } | |
118 | ||
119 | static void __init init_table(void) | |
120 | { | |
121 | int i, max; | |
122 | ||
123 | max = num_var_ranges; | |
124 | if ((usage_table = kmalloc(max * sizeof *usage_table, GFP_KERNEL)) | |
125 | == NULL) { | |
126 | printk(KERN_ERR "mtrr: could not allocate\n"); | |
127 | return; | |
128 | } | |
129 | for (i = 0; i < max; i++) | |
130 | usage_table[i] = 1; | |
131 | } | |
132 | ||
133 | struct set_mtrr_data { | |
134 | atomic_t count; | |
135 | atomic_t gate; | |
136 | unsigned long smp_base; | |
137 | unsigned long smp_size; | |
138 | unsigned int smp_reg; | |
139 | mtrr_type smp_type; | |
140 | }; | |
141 | ||
1da177e4 LT |
142 | static void ipi_handler(void *info) |
143 | /* [SUMMARY] Synchronisation handler. Executed by "other" CPUs. | |
144 | [RETURNS] Nothing. | |
145 | */ | |
146 | { | |
4e2947f1 | 147 | #ifdef CONFIG_SMP |
1da177e4 LT |
148 | struct set_mtrr_data *data = info; |
149 | unsigned long flags; | |
150 | ||
151 | local_irq_save(flags); | |
152 | ||
153 | atomic_dec(&data->count); | |
154 | while(!atomic_read(&data->gate)) | |
155 | cpu_relax(); | |
156 | ||
157 | /* The master has cleared me to execute */ | |
158 | if (data->smp_reg != ~0U) | |
159 | mtrr_if->set(data->smp_reg, data->smp_base, | |
160 | data->smp_size, data->smp_type); | |
161 | else | |
162 | mtrr_if->set_all(); | |
163 | ||
164 | atomic_dec(&data->count); | |
165 | while(atomic_read(&data->gate)) | |
166 | cpu_relax(); | |
167 | ||
168 | atomic_dec(&data->count); | |
169 | local_irq_restore(flags); | |
1da177e4 | 170 | #endif |
4e2947f1 | 171 | } |
1da177e4 | 172 | |
365bff80 JB |
173 | static inline int types_compatible(mtrr_type type1, mtrr_type type2) { |
174 | return type1 == MTRR_TYPE_UNCACHABLE || | |
175 | type2 == MTRR_TYPE_UNCACHABLE || | |
176 | (type1 == MTRR_TYPE_WRTHROUGH && type2 == MTRR_TYPE_WRBACK) || | |
177 | (type1 == MTRR_TYPE_WRBACK && type2 == MTRR_TYPE_WRTHROUGH); | |
178 | } | |
179 | ||
1da177e4 LT |
180 | /** |
181 | * set_mtrr - update mtrrs on all processors | |
182 | * @reg: mtrr in question | |
183 | * @base: mtrr base | |
184 | * @size: mtrr size | |
185 | * @type: mtrr type | |
186 | * | |
187 | * This is kinda tricky, but fortunately, Intel spelled it out for us cleanly: | |
188 | * | |
189 | * 1. Send IPI to do the following: | |
190 | * 2. Disable Interrupts | |
191 | * 3. Wait for all procs to do so | |
192 | * 4. Enter no-fill cache mode | |
193 | * 5. Flush caches | |
194 | * 6. Clear PGE bit | |
195 | * 7. Flush all TLBs | |
196 | * 8. Disable all range registers | |
197 | * 9. Update the MTRRs | |
198 | * 10. Enable all range registers | |
199 | * 11. Flush all TLBs and caches again | |
200 | * 12. Enter normal cache mode and reenable caching | |
201 | * 13. Set PGE | |
202 | * 14. Wait for buddies to catch up | |
203 | * 15. Enable interrupts. | |
204 | * | |
205 | * What does that mean for us? Well, first we set data.count to the number | |
206 | * of CPUs. As each CPU disables interrupts, it'll decrement it once. We wait | |
207 | * until it hits 0 and proceed. We set the data.gate flag and reset data.count. | |
208 | * Meanwhile, they are waiting for that flag to be set. Once it's set, each | |
209 | * CPU goes through the transition of updating MTRRs. The CPU vendors may each do it | |
210 | * differently, so we call mtrr_if->set() callback and let them take care of it. | |
211 | * When they're done, they again decrement data->count and wait for data.gate to | |
212 | * be reset. | |
213 | * When we finish, we wait for data.count to hit 0 and toggle the data.gate flag. | |
214 | * Everyone then enables interrupts and we all continue on. | |
215 | * | |
216 | * Note that the mechanism is the same for UP systems, too; all the SMP stuff | |
217 | * becomes nops. | |
218 | */ | |
219 | static void set_mtrr(unsigned int reg, unsigned long base, | |
220 | unsigned long size, mtrr_type type) | |
221 | { | |
222 | struct set_mtrr_data data; | |
223 | unsigned long flags; | |
224 | ||
225 | data.smp_reg = reg; | |
226 | data.smp_base = base; | |
227 | data.smp_size = size; | |
228 | data.smp_type = type; | |
229 | atomic_set(&data.count, num_booting_cpus() - 1); | |
d25c1ba2 LP |
230 | /* make sure data.count is visible before unleashing other CPUs */ |
231 | smp_wmb(); | |
1da177e4 LT |
232 | atomic_set(&data.gate,0); |
233 | ||
234 | /* Start the ball rolling on other CPUs */ | |
235 | if (smp_call_function(ipi_handler, &data, 1, 0) != 0) | |
236 | panic("mtrr: timed out waiting for other CPUs\n"); | |
237 | ||
238 | local_irq_save(flags); | |
239 | ||
240 | while(atomic_read(&data.count)) | |
241 | cpu_relax(); | |
242 | ||
243 | /* ok, reset count and toggle gate */ | |
244 | atomic_set(&data.count, num_booting_cpus() - 1); | |
d25c1ba2 | 245 | smp_wmb(); |
1da177e4 LT |
246 | atomic_set(&data.gate,1); |
247 | ||
248 | /* do our MTRR business */ | |
249 | ||
250 | /* HACK! | |
251 | * We use this same function to initialize the mtrrs on boot. | |
252 | * The state of the boot cpu's mtrrs has been saved, and we want | |
253 | * to replicate across all the APs. | |
254 | * If we're doing that @reg is set to something special... | |
255 | */ | |
256 | if (reg != ~0U) | |
257 | mtrr_if->set(reg,base,size,type); | |
258 | ||
259 | /* wait for the others */ | |
260 | while(atomic_read(&data.count)) | |
261 | cpu_relax(); | |
262 | ||
263 | atomic_set(&data.count, num_booting_cpus() - 1); | |
d25c1ba2 | 264 | smp_wmb(); |
1da177e4 LT |
265 | atomic_set(&data.gate,0); |
266 | ||
267 | /* | |
268 | * Wait here for everyone to have seen the gate change | |
269 | * So we're the last ones to touch 'data' | |
270 | */ | |
271 | while(atomic_read(&data.count)) | |
272 | cpu_relax(); | |
273 | ||
274 | local_irq_restore(flags); | |
275 | } | |
276 | ||
277 | /** | |
278 | * mtrr_add_page - Add a memory type region | |
9b483417 AM |
279 | * @base: Physical base address of region in pages (in units of 4 kB!) |
280 | * @size: Physical size of region in pages (4 kB) | |
1da177e4 LT |
281 | * @type: Type of MTRR desired |
282 | * @increment: If this is true do usage counting on the region | |
283 | * | |
284 | * Memory type region registers control the caching on newer Intel and | |
285 | * non Intel processors. This function allows drivers to request an | |
286 | * MTRR is added. The details and hardware specifics of each processor's | |
287 | * implementation are hidden from the caller, but nevertheless the | |
288 | * caller should expect to need to provide a power of two size on an | |
289 | * equivalent power of two boundary. | |
290 | * | |
291 | * If the region cannot be added either because all regions are in use | |
292 | * or the CPU cannot support it a negative value is returned. On success | |
293 | * the register number for this entry is returned, but should be treated | |
294 | * as a cookie only. | |
295 | * | |
296 | * On a multiprocessor machine the changes are made to all processors. | |
297 | * This is required on x86 by the Intel processors. | |
298 | * | |
299 | * The available types are | |
300 | * | |
301 | * %MTRR_TYPE_UNCACHABLE - No caching | |
302 | * | |
303 | * %MTRR_TYPE_WRBACK - Write data back in bursts whenever | |
304 | * | |
305 | * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts | |
306 | * | |
307 | * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes | |
308 | * | |
309 | * BUGS: Needs a quiet flag for the cases where drivers do not mind | |
310 | * failures and do not wish system log messages to be sent. | |
311 | */ | |
312 | ||
313 | int mtrr_add_page(unsigned long base, unsigned long size, | |
314 | unsigned int type, char increment) | |
315 | { | |
365bff80 | 316 | int i, replace, error; |
1da177e4 | 317 | mtrr_type ltype; |
365bff80 | 318 | unsigned long lbase, lsize; |
1da177e4 LT |
319 | |
320 | if (!mtrr_if) | |
321 | return -ENXIO; | |
322 | ||
323 | if ((error = mtrr_if->validate_add_page(base,size,type))) | |
324 | return error; | |
325 | ||
326 | if (type >= MTRR_NUM_TYPES) { | |
327 | printk(KERN_WARNING "mtrr: type: %u invalid\n", type); | |
328 | return -EINVAL; | |
329 | } | |
330 | ||
331 | /* If the type is WC, check that this processor supports it */ | |
332 | if ((type == MTRR_TYPE_WRCOMB) && !have_wrcomb()) { | |
333 | printk(KERN_WARNING | |
334 | "mtrr: your processor doesn't support write-combining\n"); | |
335 | return -ENOSYS; | |
336 | } | |
337 | ||
365bff80 JB |
338 | if (!size) { |
339 | printk(KERN_WARNING "mtrr: zero sized request\n"); | |
340 | return -EINVAL; | |
341 | } | |
342 | ||
1da177e4 LT |
343 | if (base & size_or_mask || size & size_or_mask) { |
344 | printk(KERN_WARNING "mtrr: base or size exceeds the MTRR width\n"); | |
345 | return -EINVAL; | |
346 | } | |
347 | ||
348 | error = -EINVAL; | |
365bff80 | 349 | replace = -1; |
1da177e4 | 350 | |
3b520b23 SL |
351 | /* No CPU hotplug when we change MTRR entries */ |
352 | lock_cpu_hotplug(); | |
1da177e4 | 353 | /* Search for existing MTRR */ |
14cc3e2b | 354 | mutex_lock(&mtrr_mutex); |
1da177e4 LT |
355 | for (i = 0; i < num_var_ranges; ++i) { |
356 | mtrr_if->get(i, &lbase, &lsize, <ype); | |
365bff80 | 357 | if (!lsize || base > lbase + lsize - 1 || base + size - 1 < lbase) |
1da177e4 LT |
358 | continue; |
359 | /* At this point we know there is some kind of overlap/enclosure */ | |
365bff80 JB |
360 | if (base < lbase || base + size - 1 > lbase + lsize - 1) { |
361 | if (base <= lbase && base + size - 1 >= lbase + lsize - 1) { | |
362 | /* New region encloses an existing region */ | |
363 | if (type == ltype) { | |
364 | replace = replace == -1 ? i : -2; | |
365 | continue; | |
366 | } | |
367 | else if (types_compatible(type, ltype)) | |
368 | continue; | |
369 | } | |
1da177e4 LT |
370 | printk(KERN_WARNING |
371 | "mtrr: 0x%lx000,0x%lx000 overlaps existing" | |
365bff80 | 372 | " 0x%lx000,0x%lx000\n", base, size, lbase, |
1da177e4 LT |
373 | lsize); |
374 | goto out; | |
375 | } | |
376 | /* New region is enclosed by an existing region */ | |
377 | if (ltype != type) { | |
365bff80 | 378 | if (types_compatible(type, ltype)) |
1da177e4 LT |
379 | continue; |
380 | printk (KERN_WARNING "mtrr: type mismatch for %lx000,%lx000 old: %s new: %s\n", | |
381 | base, size, mtrr_attrib_to_str(ltype), | |
382 | mtrr_attrib_to_str(type)); | |
383 | goto out; | |
384 | } | |
385 | if (increment) | |
386 | ++usage_table[i]; | |
387 | error = i; | |
388 | goto out; | |
389 | } | |
390 | /* Search for an empty MTRR */ | |
365bff80 | 391 | i = mtrr_if->get_free_region(base, size, replace); |
1da177e4 LT |
392 | if (i >= 0) { |
393 | set_mtrr(i, base, size, type); | |
365bff80 JB |
394 | if (likely(replace < 0)) |
395 | usage_table[i] = 1; | |
396 | else { | |
397 | usage_table[i] = usage_table[replace] + !!increment; | |
398 | if (unlikely(replace != i)) { | |
399 | set_mtrr(replace, 0, 0, 0); | |
400 | usage_table[replace] = 0; | |
401 | } | |
402 | } | |
1da177e4 LT |
403 | } else |
404 | printk(KERN_INFO "mtrr: no more MTRRs available\n"); | |
405 | error = i; | |
406 | out: | |
14cc3e2b | 407 | mutex_unlock(&mtrr_mutex); |
3b520b23 | 408 | unlock_cpu_hotplug(); |
1da177e4 LT |
409 | return error; |
410 | } | |
411 | ||
c92c6ffd AM |
412 | static int mtrr_check(unsigned long base, unsigned long size) |
413 | { | |
414 | if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) { | |
415 | printk(KERN_WARNING | |
416 | "mtrr: size and base must be multiples of 4 kiB\n"); | |
417 | printk(KERN_DEBUG | |
418 | "mtrr: size: 0x%lx base: 0x%lx\n", size, base); | |
419 | dump_stack(); | |
420 | return -1; | |
421 | } | |
422 | return 0; | |
423 | } | |
424 | ||
1da177e4 LT |
425 | /** |
426 | * mtrr_add - Add a memory type region | |
427 | * @base: Physical base address of region | |
428 | * @size: Physical size of region | |
429 | * @type: Type of MTRR desired | |
430 | * @increment: If this is true do usage counting on the region | |
431 | * | |
432 | * Memory type region registers control the caching on newer Intel and | |
433 | * non Intel processors. This function allows drivers to request an | |
434 | * MTRR is added. The details and hardware specifics of each processor's | |
435 | * implementation are hidden from the caller, but nevertheless the | |
436 | * caller should expect to need to provide a power of two size on an | |
437 | * equivalent power of two boundary. | |
438 | * | |
439 | * If the region cannot be added either because all regions are in use | |
440 | * or the CPU cannot support it a negative value is returned. On success | |
441 | * the register number for this entry is returned, but should be treated | |
442 | * as a cookie only. | |
443 | * | |
444 | * On a multiprocessor machine the changes are made to all processors. | |
445 | * This is required on x86 by the Intel processors. | |
446 | * | |
447 | * The available types are | |
448 | * | |
449 | * %MTRR_TYPE_UNCACHABLE - No caching | |
450 | * | |
451 | * %MTRR_TYPE_WRBACK - Write data back in bursts whenever | |
452 | * | |
453 | * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts | |
454 | * | |
455 | * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes | |
456 | * | |
457 | * BUGS: Needs a quiet flag for the cases where drivers do not mind | |
458 | * failures and do not wish system log messages to be sent. | |
459 | */ | |
460 | ||
461 | int | |
462 | mtrr_add(unsigned long base, unsigned long size, unsigned int type, | |
463 | char increment) | |
464 | { | |
c92c6ffd | 465 | if (mtrr_check(base, size)) |
1da177e4 | 466 | return -EINVAL; |
1da177e4 LT |
467 | return mtrr_add_page(base >> PAGE_SHIFT, size >> PAGE_SHIFT, type, |
468 | increment); | |
469 | } | |
470 | ||
471 | /** | |
472 | * mtrr_del_page - delete a memory type region | |
473 | * @reg: Register returned by mtrr_add | |
474 | * @base: Physical base address | |
475 | * @size: Size of region | |
476 | * | |
477 | * If register is supplied then base and size are ignored. This is | |
478 | * how drivers should call it. | |
479 | * | |
480 | * Releases an MTRR region. If the usage count drops to zero the | |
481 | * register is freed and the region returns to default state. | |
482 | * On success the register is returned, on failure a negative error | |
483 | * code. | |
484 | */ | |
485 | ||
486 | int mtrr_del_page(int reg, unsigned long base, unsigned long size) | |
487 | { | |
488 | int i, max; | |
489 | mtrr_type ltype; | |
365bff80 | 490 | unsigned long lbase, lsize; |
1da177e4 LT |
491 | int error = -EINVAL; |
492 | ||
493 | if (!mtrr_if) | |
494 | return -ENXIO; | |
495 | ||
496 | max = num_var_ranges; | |
3b520b23 SL |
497 | /* No CPU hotplug when we change MTRR entries */ |
498 | lock_cpu_hotplug(); | |
14cc3e2b | 499 | mutex_lock(&mtrr_mutex); |
1da177e4 LT |
500 | if (reg < 0) { |
501 | /* Search for existing MTRR */ | |
502 | for (i = 0; i < max; ++i) { | |
503 | mtrr_if->get(i, &lbase, &lsize, <ype); | |
504 | if (lbase == base && lsize == size) { | |
505 | reg = i; | |
506 | break; | |
507 | } | |
508 | } | |
509 | if (reg < 0) { | |
510 | printk(KERN_DEBUG "mtrr: no MTRR for %lx000,%lx000 found\n", base, | |
511 | size); | |
512 | goto out; | |
513 | } | |
514 | } | |
515 | if (reg >= max) { | |
516 | printk(KERN_WARNING "mtrr: register: %d too big\n", reg); | |
517 | goto out; | |
518 | } | |
519 | if (is_cpu(CYRIX) && !use_intel()) { | |
520 | if ((reg == 3) && arr3_protected) { | |
521 | printk(KERN_WARNING "mtrr: ARR3 cannot be changed\n"); | |
522 | goto out; | |
523 | } | |
524 | } | |
525 | mtrr_if->get(reg, &lbase, &lsize, <ype); | |
526 | if (lsize < 1) { | |
527 | printk(KERN_WARNING "mtrr: MTRR %d not used\n", reg); | |
528 | goto out; | |
529 | } | |
530 | if (usage_table[reg] < 1) { | |
531 | printk(KERN_WARNING "mtrr: reg: %d has count=0\n", reg); | |
532 | goto out; | |
533 | } | |
534 | if (--usage_table[reg] < 1) | |
535 | set_mtrr(reg, 0, 0, 0); | |
536 | error = reg; | |
537 | out: | |
14cc3e2b | 538 | mutex_unlock(&mtrr_mutex); |
3b520b23 | 539 | unlock_cpu_hotplug(); |
1da177e4 LT |
540 | return error; |
541 | } | |
542 | /** | |
543 | * mtrr_del - delete a memory type region | |
544 | * @reg: Register returned by mtrr_add | |
545 | * @base: Physical base address | |
546 | * @size: Size of region | |
547 | * | |
548 | * If register is supplied then base and size are ignored. This is | |
549 | * how drivers should call it. | |
550 | * | |
551 | * Releases an MTRR region. If the usage count drops to zero the | |
552 | * register is freed and the region returns to default state. | |
553 | * On success the register is returned, on failure a negative error | |
554 | * code. | |
555 | */ | |
556 | ||
557 | int | |
558 | mtrr_del(int reg, unsigned long base, unsigned long size) | |
559 | { | |
c92c6ffd | 560 | if (mtrr_check(base, size)) |
1da177e4 | 561 | return -EINVAL; |
1da177e4 LT |
562 | return mtrr_del_page(reg, base >> PAGE_SHIFT, size >> PAGE_SHIFT); |
563 | } | |
564 | ||
565 | EXPORT_SYMBOL(mtrr_add); | |
566 | EXPORT_SYMBOL(mtrr_del); | |
567 | ||
568 | /* HACK ALERT! | |
569 | * These should be called implicitly, but we can't yet until all the initcall | |
570 | * stuff is done... | |
571 | */ | |
572 | extern void amd_init_mtrr(void); | |
573 | extern void cyrix_init_mtrr(void); | |
574 | extern void centaur_init_mtrr(void); | |
575 | ||
576 | static void __init init_ifs(void) | |
577 | { | |
475850c8 | 578 | #ifndef CONFIG_X86_64 |
1da177e4 LT |
579 | amd_init_mtrr(); |
580 | cyrix_init_mtrr(); | |
581 | centaur_init_mtrr(); | |
475850c8 | 582 | #endif |
1da177e4 LT |
583 | } |
584 | ||
3b520b23 SL |
585 | /* The suspend/resume methods are only for CPU without MTRR. CPU using generic |
586 | * MTRR driver doesn't require this | |
587 | */ | |
1da177e4 LT |
588 | struct mtrr_value { |
589 | mtrr_type ltype; | |
590 | unsigned long lbase; | |
365bff80 | 591 | unsigned long lsize; |
1da177e4 LT |
592 | }; |
593 | ||
594 | static struct mtrr_value * mtrr_state; | |
595 | ||
829ca9a3 | 596 | static int mtrr_save(struct sys_device * sysdev, pm_message_t state) |
1da177e4 LT |
597 | { |
598 | int i; | |
599 | int size = num_var_ranges * sizeof(struct mtrr_value); | |
600 | ||
9cfa5b5d BY |
601 | mtrr_state = kzalloc(size,GFP_ATOMIC); |
602 | if (!mtrr_state) | |
1da177e4 LT |
603 | return -ENOMEM; |
604 | ||
605 | for (i = 0; i < num_var_ranges; i++) { | |
606 | mtrr_if->get(i, | |
607 | &mtrr_state[i].lbase, | |
608 | &mtrr_state[i].lsize, | |
609 | &mtrr_state[i].ltype); | |
610 | } | |
611 | return 0; | |
612 | } | |
613 | ||
614 | static int mtrr_restore(struct sys_device * sysdev) | |
615 | { | |
616 | int i; | |
617 | ||
618 | for (i = 0; i < num_var_ranges; i++) { | |
619 | if (mtrr_state[i].lsize) | |
620 | set_mtrr(i, | |
621 | mtrr_state[i].lbase, | |
622 | mtrr_state[i].lsize, | |
623 | mtrr_state[i].ltype); | |
624 | } | |
625 | kfree(mtrr_state); | |
626 | return 0; | |
627 | } | |
628 | ||
629 | ||
630 | ||
631 | static struct sysdev_driver mtrr_sysdev_driver = { | |
632 | .suspend = mtrr_save, | |
633 | .resume = mtrr_restore, | |
634 | }; | |
635 | ||
636 | ||
637 | /** | |
3b520b23 | 638 | * mtrr_bp_init - initialize mtrrs on the boot CPU |
1da177e4 LT |
639 | * |
640 | * This needs to be called early; before any of the other CPUs are | |
641 | * initialized (i.e. before smp_init()). | |
642 | * | |
643 | */ | |
9ef231a4 | 644 | void __init mtrr_bp_init(void) |
1da177e4 LT |
645 | { |
646 | init_ifs(); | |
647 | ||
648 | if (cpu_has_mtrr) { | |
649 | mtrr_if = &generic_mtrr_ops; | |
650 | size_or_mask = 0xff000000; /* 36 bits */ | |
651 | size_and_mask = 0x00f00000; | |
1f2c958a AK |
652 | |
653 | /* This is an AMD specific MSR, but we assume(hope?) that | |
654 | Intel will implement it to when they extend the address | |
655 | bus of the Xeon. */ | |
656 | if (cpuid_eax(0x80000000) >= 0x80000008) { | |
657 | u32 phys_addr; | |
658 | phys_addr = cpuid_eax(0x80000008) & 0xff; | |
af9c142d SL |
659 | /* CPUID workaround for Intel 0F33/0F34 CPU */ |
660 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
661 | boot_cpu_data.x86 == 0xF && | |
662 | boot_cpu_data.x86_model == 0x3 && | |
663 | (boot_cpu_data.x86_mask == 0x3 || | |
664 | boot_cpu_data.x86_mask == 0x4)) | |
665 | phys_addr = 36; | |
666 | ||
6c5806ca AH |
667 | size_or_mask = ~((1ULL << (phys_addr - PAGE_SHIFT)) - 1); |
668 | size_and_mask = ~size_or_mask & 0xfffff00000ULL; | |
1f2c958a AK |
669 | } else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR && |
670 | boot_cpu_data.x86 == 6) { | |
671 | /* VIA C* family have Intel style MTRRs, but | |
672 | don't support PAE */ | |
673 | size_or_mask = 0xfff00000; /* 32 bits */ | |
674 | size_and_mask = 0; | |
1da177e4 LT |
675 | } |
676 | } else { | |
677 | switch (boot_cpu_data.x86_vendor) { | |
678 | case X86_VENDOR_AMD: | |
679 | if (cpu_has_k6_mtrr) { | |
680 | /* Pre-Athlon (K6) AMD CPU MTRRs */ | |
681 | mtrr_if = mtrr_ops[X86_VENDOR_AMD]; | |
682 | size_or_mask = 0xfff00000; /* 32 bits */ | |
683 | size_and_mask = 0; | |
684 | } | |
685 | break; | |
686 | case X86_VENDOR_CENTAUR: | |
687 | if (cpu_has_centaur_mcr) { | |
688 | mtrr_if = mtrr_ops[X86_VENDOR_CENTAUR]; | |
689 | size_or_mask = 0xfff00000; /* 32 bits */ | |
690 | size_and_mask = 0; | |
691 | } | |
692 | break; | |
693 | case X86_VENDOR_CYRIX: | |
694 | if (cpu_has_cyrix_arr) { | |
695 | mtrr_if = mtrr_ops[X86_VENDOR_CYRIX]; | |
696 | size_or_mask = 0xfff00000; /* 32 bits */ | |
697 | size_and_mask = 0; | |
698 | } | |
699 | break; | |
700 | default: | |
701 | break; | |
702 | } | |
703 | } | |
1da177e4 LT |
704 | |
705 | if (mtrr_if) { | |
706 | set_num_var_ranges(); | |
707 | init_table(); | |
3b520b23 SL |
708 | if (use_intel()) |
709 | get_mtrr_state(); | |
1da177e4 | 710 | } |
1da177e4 LT |
711 | } |
712 | ||
3b520b23 SL |
713 | void mtrr_ap_init(void) |
714 | { | |
715 | unsigned long flags; | |
716 | ||
717 | if (!mtrr_if || !use_intel()) | |
718 | return; | |
719 | /* | |
14cc3e2b | 720 | * Ideally we should hold mtrr_mutex here to avoid mtrr entries changed, |
3b520b23 SL |
721 | * but this routine will be called in cpu boot time, holding the lock |
722 | * breaks it. This routine is called in two cases: 1.very earily time | |
723 | * of software resume, when there absolutely isn't mtrr entry changes; | |
724 | * 2.cpu hotadd time. We let mtrr_add/del_page hold cpuhotplug lock to | |
725 | * prevent mtrr entry changes | |
726 | */ | |
727 | local_irq_save(flags); | |
728 | ||
729 | mtrr_if->set_all(); | |
730 | ||
731 | local_irq_restore(flags); | |
732 | } | |
733 | ||
2b1f6278 BK |
734 | /** |
735 | * Save current fixed-range MTRR state of the BSP | |
736 | */ | |
737 | void mtrr_save_state(void) | |
738 | { | |
c8f2518e | 739 | smp_call_function_single(0, mtrr_save_fixed_ranges, NULL, 1, 1); |
2b1f6278 BK |
740 | } |
741 | ||
3b520b23 SL |
742 | static int __init mtrr_init_finialize(void) |
743 | { | |
744 | if (!mtrr_if) | |
745 | return 0; | |
746 | if (use_intel()) | |
747 | mtrr_state_warn(); | |
748 | else { | |
27b46d76 | 749 | /* The CPUs haven't MTRR and seem to not support SMP. They have |
3b520b23 SL |
750 | * specific drivers, we use a tricky method to support |
751 | * suspend/resume for them. | |
752 | * TBD: is there any system with such CPU which supports | |
753 | * suspend/resume? if no, we should remove the code. | |
754 | */ | |
755 | sysdev_driver_register(&cpu_sysdev_class, | |
756 | &mtrr_sysdev_driver); | |
757 | } | |
758 | return 0; | |
759 | } | |
760 | subsys_initcall(mtrr_init_finialize); |