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Commit | Line | Data |
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1da177e4 LT |
1 | /* Generic MTRR (Memory Type Range Register) driver. |
2 | ||
3 | Copyright (C) 1997-2000 Richard Gooch | |
4 | Copyright (c) 2002 Patrick Mochel | |
5 | ||
6 | This library is free software; you can redistribute it and/or | |
7 | modify it under the terms of the GNU Library General Public | |
8 | License as published by the Free Software Foundation; either | |
9 | version 2 of the License, or (at your option) any later version. | |
10 | ||
11 | This library is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | Library General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU Library General Public | |
17 | License along with this library; if not, write to the Free | |
18 | Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | ||
20 | Richard Gooch may be reached by email at rgooch@atnf.csiro.au | |
21 | The postal address is: | |
22 | Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia. | |
23 | ||
24 | Source: "Pentium Pro Family Developer's Manual, Volume 3: | |
25 | Operating System Writer's Guide" (Intel document number 242692), | |
26 | section 11.11.7 | |
27 | ||
28 | This was cleaned and made readable by Patrick Mochel <mochel@osdl.org> | |
29 | on 6-7 March 2002. | |
30 | Source: Intel Architecture Software Developers Manual, Volume 3: | |
31 | System Programming Guide; Section 9.11. (1997 edition - PPro). | |
32 | */ | |
33 | ||
34 | #include <linux/module.h> | |
35 | #include <linux/init.h> | |
36 | #include <linux/pci.h> | |
37 | #include <linux/smp.h> | |
38 | #include <linux/cpu.h> | |
14cc3e2b | 39 | #include <linux/mutex.h> |
95ffa243 | 40 | #include <linux/sort.h> |
1da177e4 | 41 | |
99fc8d42 | 42 | #include <asm/e820.h> |
1da177e4 | 43 | #include <asm/mtrr.h> |
1da177e4 LT |
44 | #include <asm/uaccess.h> |
45 | #include <asm/processor.h> | |
46 | #include <asm/msr.h> | |
4147c874 | 47 | #include <asm/kvm_para.h> |
1da177e4 LT |
48 | #include "mtrr.h" |
49 | ||
1da177e4 LT |
50 | u32 num_var_ranges = 0; |
51 | ||
99fc8d42 | 52 | unsigned int mtrr_usage_table[MAX_VAR_RANGES]; |
14cc3e2b | 53 | static DEFINE_MUTEX(mtrr_mutex); |
1da177e4 | 54 | |
6c5806ca | 55 | u64 size_or_mask, size_and_mask; |
1da177e4 LT |
56 | |
57 | static struct mtrr_ops * mtrr_ops[X86_VENDOR_NUM] = {}; | |
58 | ||
59 | struct mtrr_ops * mtrr_if = NULL; | |
60 | ||
61 | static void set_mtrr(unsigned int reg, unsigned long base, | |
62 | unsigned long size, mtrr_type type); | |
63 | ||
1da177e4 LT |
64 | void set_mtrr_ops(struct mtrr_ops * ops) |
65 | { | |
66 | if (ops->vendor && ops->vendor < X86_VENDOR_NUM) | |
67 | mtrr_ops[ops->vendor] = ops; | |
68 | } | |
69 | ||
70 | /* Returns non-zero if we have the write-combining memory type */ | |
71 | static int have_wrcomb(void) | |
72 | { | |
73 | struct pci_dev *dev; | |
a6954ba2 | 74 | u8 rev; |
1da177e4 LT |
75 | |
76 | if ((dev = pci_get_class(PCI_CLASS_BRIDGE_HOST << 8, NULL)) != NULL) { | |
a6954ba2 | 77 | /* ServerWorks LE chipsets < rev 6 have problems with write-combining |
1da177e4 LT |
78 | Don't allow it and leave room for other chipsets to be tagged */ |
79 | if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS && | |
80 | dev->device == PCI_DEVICE_ID_SERVERWORKS_LE) { | |
a6954ba2 LR |
81 | pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev); |
82 | if (rev <= 5) { | |
83 | printk(KERN_INFO "mtrr: Serverworks LE rev < 6 detected. Write-combining disabled.\n"); | |
84 | pci_dev_put(dev); | |
85 | return 0; | |
86 | } | |
1da177e4 | 87 | } |
a6954ba2 | 88 | /* Intel 450NX errata # 23. Non ascending cacheline evictions to |
1da177e4 LT |
89 | write combining memory may resulting in data corruption */ |
90 | if (dev->vendor == PCI_VENDOR_ID_INTEL && | |
91 | dev->device == PCI_DEVICE_ID_INTEL_82451NX) { | |
92 | printk(KERN_INFO "mtrr: Intel 450NX MMC detected. Write-combining disabled.\n"); | |
93 | pci_dev_put(dev); | |
94 | return 0; | |
95 | } | |
96 | pci_dev_put(dev); | |
97 | } | |
98 | return (mtrr_if->have_wrcomb ? mtrr_if->have_wrcomb() : 0); | |
99 | } | |
100 | ||
101 | /* This function returns the number of variable MTRRs */ | |
102 | static void __init set_num_var_ranges(void) | |
103 | { | |
104 | unsigned long config = 0, dummy; | |
105 | ||
106 | if (use_intel()) { | |
107 | rdmsr(MTRRcap_MSR, config, dummy); | |
108 | } else if (is_cpu(AMD)) | |
109 | config = 2; | |
110 | else if (is_cpu(CYRIX) || is_cpu(CENTAUR)) | |
111 | config = 8; | |
112 | num_var_ranges = config & 0xff; | |
113 | } | |
114 | ||
115 | static void __init init_table(void) | |
116 | { | |
117 | int i, max; | |
118 | ||
119 | max = num_var_ranges; | |
1da177e4 | 120 | for (i = 0; i < max; i++) |
99fc8d42 | 121 | mtrr_usage_table[i] = 1; |
1da177e4 LT |
122 | } |
123 | ||
124 | struct set_mtrr_data { | |
125 | atomic_t count; | |
126 | atomic_t gate; | |
127 | unsigned long smp_base; | |
128 | unsigned long smp_size; | |
129 | unsigned int smp_reg; | |
130 | mtrr_type smp_type; | |
131 | }; | |
132 | ||
1da177e4 LT |
133 | static void ipi_handler(void *info) |
134 | /* [SUMMARY] Synchronisation handler. Executed by "other" CPUs. | |
135 | [RETURNS] Nothing. | |
136 | */ | |
137 | { | |
4e2947f1 | 138 | #ifdef CONFIG_SMP |
1da177e4 LT |
139 | struct set_mtrr_data *data = info; |
140 | unsigned long flags; | |
141 | ||
142 | local_irq_save(flags); | |
143 | ||
144 | atomic_dec(&data->count); | |
145 | while(!atomic_read(&data->gate)) | |
146 | cpu_relax(); | |
147 | ||
148 | /* The master has cleared me to execute */ | |
149 | if (data->smp_reg != ~0U) | |
150 | mtrr_if->set(data->smp_reg, data->smp_base, | |
151 | data->smp_size, data->smp_type); | |
152 | else | |
153 | mtrr_if->set_all(); | |
154 | ||
155 | atomic_dec(&data->count); | |
156 | while(atomic_read(&data->gate)) | |
157 | cpu_relax(); | |
158 | ||
159 | atomic_dec(&data->count); | |
160 | local_irq_restore(flags); | |
1da177e4 | 161 | #endif |
4e2947f1 | 162 | } |
1da177e4 | 163 | |
365bff80 JB |
164 | static inline int types_compatible(mtrr_type type1, mtrr_type type2) { |
165 | return type1 == MTRR_TYPE_UNCACHABLE || | |
166 | type2 == MTRR_TYPE_UNCACHABLE || | |
167 | (type1 == MTRR_TYPE_WRTHROUGH && type2 == MTRR_TYPE_WRBACK) || | |
168 | (type1 == MTRR_TYPE_WRBACK && type2 == MTRR_TYPE_WRTHROUGH); | |
169 | } | |
170 | ||
1da177e4 LT |
171 | /** |
172 | * set_mtrr - update mtrrs on all processors | |
173 | * @reg: mtrr in question | |
174 | * @base: mtrr base | |
175 | * @size: mtrr size | |
176 | * @type: mtrr type | |
177 | * | |
178 | * This is kinda tricky, but fortunately, Intel spelled it out for us cleanly: | |
179 | * | |
180 | * 1. Send IPI to do the following: | |
181 | * 2. Disable Interrupts | |
182 | * 3. Wait for all procs to do so | |
183 | * 4. Enter no-fill cache mode | |
184 | * 5. Flush caches | |
185 | * 6. Clear PGE bit | |
186 | * 7. Flush all TLBs | |
187 | * 8. Disable all range registers | |
188 | * 9. Update the MTRRs | |
189 | * 10. Enable all range registers | |
190 | * 11. Flush all TLBs and caches again | |
191 | * 12. Enter normal cache mode and reenable caching | |
192 | * 13. Set PGE | |
193 | * 14. Wait for buddies to catch up | |
194 | * 15. Enable interrupts. | |
195 | * | |
196 | * What does that mean for us? Well, first we set data.count to the number | |
197 | * of CPUs. As each CPU disables interrupts, it'll decrement it once. We wait | |
198 | * until it hits 0 and proceed. We set the data.gate flag and reset data.count. | |
199 | * Meanwhile, they are waiting for that flag to be set. Once it's set, each | |
200 | * CPU goes through the transition of updating MTRRs. The CPU vendors may each do it | |
201 | * differently, so we call mtrr_if->set() callback and let them take care of it. | |
202 | * When they're done, they again decrement data->count and wait for data.gate to | |
203 | * be reset. | |
204 | * When we finish, we wait for data.count to hit 0 and toggle the data.gate flag. | |
205 | * Everyone then enables interrupts and we all continue on. | |
206 | * | |
207 | * Note that the mechanism is the same for UP systems, too; all the SMP stuff | |
208 | * becomes nops. | |
209 | */ | |
210 | static void set_mtrr(unsigned int reg, unsigned long base, | |
211 | unsigned long size, mtrr_type type) | |
212 | { | |
213 | struct set_mtrr_data data; | |
214 | unsigned long flags; | |
215 | ||
216 | data.smp_reg = reg; | |
217 | data.smp_base = base; | |
218 | data.smp_size = size; | |
219 | data.smp_type = type; | |
220 | atomic_set(&data.count, num_booting_cpus() - 1); | |
d25c1ba2 LP |
221 | /* make sure data.count is visible before unleashing other CPUs */ |
222 | smp_wmb(); | |
1da177e4 LT |
223 | atomic_set(&data.gate,0); |
224 | ||
225 | /* Start the ball rolling on other CPUs */ | |
226 | if (smp_call_function(ipi_handler, &data, 1, 0) != 0) | |
227 | panic("mtrr: timed out waiting for other CPUs\n"); | |
228 | ||
229 | local_irq_save(flags); | |
230 | ||
231 | while(atomic_read(&data.count)) | |
232 | cpu_relax(); | |
233 | ||
234 | /* ok, reset count and toggle gate */ | |
235 | atomic_set(&data.count, num_booting_cpus() - 1); | |
d25c1ba2 | 236 | smp_wmb(); |
1da177e4 LT |
237 | atomic_set(&data.gate,1); |
238 | ||
239 | /* do our MTRR business */ | |
240 | ||
241 | /* HACK! | |
242 | * We use this same function to initialize the mtrrs on boot. | |
243 | * The state of the boot cpu's mtrrs has been saved, and we want | |
244 | * to replicate across all the APs. | |
245 | * If we're doing that @reg is set to something special... | |
246 | */ | |
247 | if (reg != ~0U) | |
248 | mtrr_if->set(reg,base,size,type); | |
249 | ||
250 | /* wait for the others */ | |
251 | while(atomic_read(&data.count)) | |
252 | cpu_relax(); | |
253 | ||
254 | atomic_set(&data.count, num_booting_cpus() - 1); | |
d25c1ba2 | 255 | smp_wmb(); |
1da177e4 LT |
256 | atomic_set(&data.gate,0); |
257 | ||
258 | /* | |
259 | * Wait here for everyone to have seen the gate change | |
260 | * So we're the last ones to touch 'data' | |
261 | */ | |
262 | while(atomic_read(&data.count)) | |
263 | cpu_relax(); | |
264 | ||
265 | local_irq_restore(flags); | |
266 | } | |
267 | ||
268 | /** | |
269 | * mtrr_add_page - Add a memory type region | |
9b483417 AM |
270 | * @base: Physical base address of region in pages (in units of 4 kB!) |
271 | * @size: Physical size of region in pages (4 kB) | |
1da177e4 LT |
272 | * @type: Type of MTRR desired |
273 | * @increment: If this is true do usage counting on the region | |
274 | * | |
275 | * Memory type region registers control the caching on newer Intel and | |
276 | * non Intel processors. This function allows drivers to request an | |
277 | * MTRR is added. The details and hardware specifics of each processor's | |
278 | * implementation are hidden from the caller, but nevertheless the | |
279 | * caller should expect to need to provide a power of two size on an | |
280 | * equivalent power of two boundary. | |
281 | * | |
282 | * If the region cannot be added either because all regions are in use | |
283 | * or the CPU cannot support it a negative value is returned. On success | |
284 | * the register number for this entry is returned, but should be treated | |
285 | * as a cookie only. | |
286 | * | |
287 | * On a multiprocessor machine the changes are made to all processors. | |
288 | * This is required on x86 by the Intel processors. | |
289 | * | |
290 | * The available types are | |
291 | * | |
292 | * %MTRR_TYPE_UNCACHABLE - No caching | |
293 | * | |
294 | * %MTRR_TYPE_WRBACK - Write data back in bursts whenever | |
295 | * | |
296 | * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts | |
297 | * | |
298 | * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes | |
299 | * | |
300 | * BUGS: Needs a quiet flag for the cases where drivers do not mind | |
301 | * failures and do not wish system log messages to be sent. | |
302 | */ | |
303 | ||
304 | int mtrr_add_page(unsigned long base, unsigned long size, | |
2d2ee8de | 305 | unsigned int type, bool increment) |
1da177e4 | 306 | { |
365bff80 | 307 | int i, replace, error; |
1da177e4 | 308 | mtrr_type ltype; |
365bff80 | 309 | unsigned long lbase, lsize; |
1da177e4 LT |
310 | |
311 | if (!mtrr_if) | |
312 | return -ENXIO; | |
313 | ||
314 | if ((error = mtrr_if->validate_add_page(base,size,type))) | |
315 | return error; | |
316 | ||
317 | if (type >= MTRR_NUM_TYPES) { | |
318 | printk(KERN_WARNING "mtrr: type: %u invalid\n", type); | |
319 | return -EINVAL; | |
320 | } | |
321 | ||
322 | /* If the type is WC, check that this processor supports it */ | |
323 | if ((type == MTRR_TYPE_WRCOMB) && !have_wrcomb()) { | |
324 | printk(KERN_WARNING | |
325 | "mtrr: your processor doesn't support write-combining\n"); | |
326 | return -ENOSYS; | |
327 | } | |
328 | ||
365bff80 JB |
329 | if (!size) { |
330 | printk(KERN_WARNING "mtrr: zero sized request\n"); | |
331 | return -EINVAL; | |
332 | } | |
333 | ||
1da177e4 LT |
334 | if (base & size_or_mask || size & size_or_mask) { |
335 | printk(KERN_WARNING "mtrr: base or size exceeds the MTRR width\n"); | |
336 | return -EINVAL; | |
337 | } | |
338 | ||
339 | error = -EINVAL; | |
365bff80 | 340 | replace = -1; |
1da177e4 | 341 | |
3b520b23 | 342 | /* No CPU hotplug when we change MTRR entries */ |
86ef5c9a | 343 | get_online_cpus(); |
1da177e4 | 344 | /* Search for existing MTRR */ |
14cc3e2b | 345 | mutex_lock(&mtrr_mutex); |
1da177e4 LT |
346 | for (i = 0; i < num_var_ranges; ++i) { |
347 | mtrr_if->get(i, &lbase, &lsize, <ype); | |
365bff80 | 348 | if (!lsize || base > lbase + lsize - 1 || base + size - 1 < lbase) |
1da177e4 LT |
349 | continue; |
350 | /* At this point we know there is some kind of overlap/enclosure */ | |
365bff80 JB |
351 | if (base < lbase || base + size - 1 > lbase + lsize - 1) { |
352 | if (base <= lbase && base + size - 1 >= lbase + lsize - 1) { | |
353 | /* New region encloses an existing region */ | |
354 | if (type == ltype) { | |
355 | replace = replace == -1 ? i : -2; | |
356 | continue; | |
357 | } | |
358 | else if (types_compatible(type, ltype)) | |
359 | continue; | |
360 | } | |
1da177e4 LT |
361 | printk(KERN_WARNING |
362 | "mtrr: 0x%lx000,0x%lx000 overlaps existing" | |
365bff80 | 363 | " 0x%lx000,0x%lx000\n", base, size, lbase, |
1da177e4 LT |
364 | lsize); |
365 | goto out; | |
366 | } | |
367 | /* New region is enclosed by an existing region */ | |
368 | if (ltype != type) { | |
365bff80 | 369 | if (types_compatible(type, ltype)) |
1da177e4 LT |
370 | continue; |
371 | printk (KERN_WARNING "mtrr: type mismatch for %lx000,%lx000 old: %s new: %s\n", | |
372 | base, size, mtrr_attrib_to_str(ltype), | |
373 | mtrr_attrib_to_str(type)); | |
374 | goto out; | |
375 | } | |
376 | if (increment) | |
99fc8d42 | 377 | ++mtrr_usage_table[i]; |
1da177e4 LT |
378 | error = i; |
379 | goto out; | |
380 | } | |
381 | /* Search for an empty MTRR */ | |
365bff80 | 382 | i = mtrr_if->get_free_region(base, size, replace); |
1da177e4 LT |
383 | if (i >= 0) { |
384 | set_mtrr(i, base, size, type); | |
99fc8d42 JB |
385 | if (likely(replace < 0)) { |
386 | mtrr_usage_table[i] = 1; | |
387 | } else { | |
388 | mtrr_usage_table[i] = mtrr_usage_table[replace]; | |
2d2ee8de | 389 | if (increment) |
99fc8d42 | 390 | mtrr_usage_table[i]++; |
365bff80 JB |
391 | if (unlikely(replace != i)) { |
392 | set_mtrr(replace, 0, 0, 0); | |
99fc8d42 | 393 | mtrr_usage_table[replace] = 0; |
365bff80 JB |
394 | } |
395 | } | |
1da177e4 LT |
396 | } else |
397 | printk(KERN_INFO "mtrr: no more MTRRs available\n"); | |
398 | error = i; | |
399 | out: | |
14cc3e2b | 400 | mutex_unlock(&mtrr_mutex); |
86ef5c9a | 401 | put_online_cpus(); |
1da177e4 LT |
402 | return error; |
403 | } | |
404 | ||
c92c6ffd AM |
405 | static int mtrr_check(unsigned long base, unsigned long size) |
406 | { | |
407 | if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) { | |
408 | printk(KERN_WARNING | |
409 | "mtrr: size and base must be multiples of 4 kiB\n"); | |
410 | printk(KERN_DEBUG | |
411 | "mtrr: size: 0x%lx base: 0x%lx\n", size, base); | |
412 | dump_stack(); | |
413 | return -1; | |
414 | } | |
415 | return 0; | |
416 | } | |
417 | ||
1da177e4 LT |
418 | /** |
419 | * mtrr_add - Add a memory type region | |
420 | * @base: Physical base address of region | |
421 | * @size: Physical size of region | |
422 | * @type: Type of MTRR desired | |
423 | * @increment: If this is true do usage counting on the region | |
424 | * | |
425 | * Memory type region registers control the caching on newer Intel and | |
426 | * non Intel processors. This function allows drivers to request an | |
427 | * MTRR is added. The details and hardware specifics of each processor's | |
428 | * implementation are hidden from the caller, but nevertheless the | |
429 | * caller should expect to need to provide a power of two size on an | |
430 | * equivalent power of two boundary. | |
431 | * | |
432 | * If the region cannot be added either because all regions are in use | |
433 | * or the CPU cannot support it a negative value is returned. On success | |
434 | * the register number for this entry is returned, but should be treated | |
435 | * as a cookie only. | |
436 | * | |
437 | * On a multiprocessor machine the changes are made to all processors. | |
438 | * This is required on x86 by the Intel processors. | |
439 | * | |
440 | * The available types are | |
441 | * | |
442 | * %MTRR_TYPE_UNCACHABLE - No caching | |
443 | * | |
444 | * %MTRR_TYPE_WRBACK - Write data back in bursts whenever | |
445 | * | |
446 | * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts | |
447 | * | |
448 | * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes | |
449 | * | |
450 | * BUGS: Needs a quiet flag for the cases where drivers do not mind | |
451 | * failures and do not wish system log messages to be sent. | |
452 | */ | |
453 | ||
454 | int | |
455 | mtrr_add(unsigned long base, unsigned long size, unsigned int type, | |
2d2ee8de | 456 | bool increment) |
1da177e4 | 457 | { |
c92c6ffd | 458 | if (mtrr_check(base, size)) |
1da177e4 | 459 | return -EINVAL; |
1da177e4 LT |
460 | return mtrr_add_page(base >> PAGE_SHIFT, size >> PAGE_SHIFT, type, |
461 | increment); | |
462 | } | |
463 | ||
464 | /** | |
465 | * mtrr_del_page - delete a memory type region | |
466 | * @reg: Register returned by mtrr_add | |
467 | * @base: Physical base address | |
468 | * @size: Size of region | |
469 | * | |
470 | * If register is supplied then base and size are ignored. This is | |
471 | * how drivers should call it. | |
472 | * | |
473 | * Releases an MTRR region. If the usage count drops to zero the | |
474 | * register is freed and the region returns to default state. | |
475 | * On success the register is returned, on failure a negative error | |
476 | * code. | |
477 | */ | |
478 | ||
479 | int mtrr_del_page(int reg, unsigned long base, unsigned long size) | |
480 | { | |
481 | int i, max; | |
482 | mtrr_type ltype; | |
365bff80 | 483 | unsigned long lbase, lsize; |
1da177e4 LT |
484 | int error = -EINVAL; |
485 | ||
486 | if (!mtrr_if) | |
487 | return -ENXIO; | |
488 | ||
489 | max = num_var_ranges; | |
3b520b23 | 490 | /* No CPU hotplug when we change MTRR entries */ |
86ef5c9a | 491 | get_online_cpus(); |
14cc3e2b | 492 | mutex_lock(&mtrr_mutex); |
1da177e4 LT |
493 | if (reg < 0) { |
494 | /* Search for existing MTRR */ | |
495 | for (i = 0; i < max; ++i) { | |
496 | mtrr_if->get(i, &lbase, &lsize, <ype); | |
497 | if (lbase == base && lsize == size) { | |
498 | reg = i; | |
499 | break; | |
500 | } | |
501 | } | |
502 | if (reg < 0) { | |
503 | printk(KERN_DEBUG "mtrr: no MTRR for %lx000,%lx000 found\n", base, | |
504 | size); | |
505 | goto out; | |
506 | } | |
507 | } | |
508 | if (reg >= max) { | |
509 | printk(KERN_WARNING "mtrr: register: %d too big\n", reg); | |
510 | goto out; | |
511 | } | |
1da177e4 LT |
512 | mtrr_if->get(reg, &lbase, &lsize, <ype); |
513 | if (lsize < 1) { | |
514 | printk(KERN_WARNING "mtrr: MTRR %d not used\n", reg); | |
515 | goto out; | |
516 | } | |
99fc8d42 | 517 | if (mtrr_usage_table[reg] < 1) { |
1da177e4 LT |
518 | printk(KERN_WARNING "mtrr: reg: %d has count=0\n", reg); |
519 | goto out; | |
520 | } | |
99fc8d42 | 521 | if (--mtrr_usage_table[reg] < 1) |
1da177e4 LT |
522 | set_mtrr(reg, 0, 0, 0); |
523 | error = reg; | |
524 | out: | |
14cc3e2b | 525 | mutex_unlock(&mtrr_mutex); |
86ef5c9a | 526 | put_online_cpus(); |
1da177e4 LT |
527 | return error; |
528 | } | |
529 | /** | |
530 | * mtrr_del - delete a memory type region | |
531 | * @reg: Register returned by mtrr_add | |
532 | * @base: Physical base address | |
533 | * @size: Size of region | |
534 | * | |
535 | * If register is supplied then base and size are ignored. This is | |
536 | * how drivers should call it. | |
537 | * | |
538 | * Releases an MTRR region. If the usage count drops to zero the | |
539 | * register is freed and the region returns to default state. | |
540 | * On success the register is returned, on failure a negative error | |
541 | * code. | |
542 | */ | |
543 | ||
544 | int | |
545 | mtrr_del(int reg, unsigned long base, unsigned long size) | |
546 | { | |
c92c6ffd | 547 | if (mtrr_check(base, size)) |
1da177e4 | 548 | return -EINVAL; |
1da177e4 LT |
549 | return mtrr_del_page(reg, base >> PAGE_SHIFT, size >> PAGE_SHIFT); |
550 | } | |
551 | ||
552 | EXPORT_SYMBOL(mtrr_add); | |
553 | EXPORT_SYMBOL(mtrr_del); | |
554 | ||
555 | /* HACK ALERT! | |
556 | * These should be called implicitly, but we can't yet until all the initcall | |
557 | * stuff is done... | |
558 | */ | |
1da177e4 LT |
559 | static void __init init_ifs(void) |
560 | { | |
475850c8 | 561 | #ifndef CONFIG_X86_64 |
1da177e4 LT |
562 | amd_init_mtrr(); |
563 | cyrix_init_mtrr(); | |
564 | centaur_init_mtrr(); | |
475850c8 | 565 | #endif |
1da177e4 LT |
566 | } |
567 | ||
3b520b23 SL |
568 | /* The suspend/resume methods are only for CPU without MTRR. CPU using generic |
569 | * MTRR driver doesn't require this | |
570 | */ | |
1da177e4 LT |
571 | struct mtrr_value { |
572 | mtrr_type ltype; | |
573 | unsigned long lbase; | |
365bff80 | 574 | unsigned long lsize; |
1da177e4 LT |
575 | }; |
576 | ||
99fc8d42 | 577 | static struct mtrr_value mtrr_state[MAX_VAR_RANGES]; |
1da177e4 | 578 | |
829ca9a3 | 579 | static int mtrr_save(struct sys_device * sysdev, pm_message_t state) |
1da177e4 LT |
580 | { |
581 | int i; | |
1da177e4 LT |
582 | |
583 | for (i = 0; i < num_var_ranges; i++) { | |
584 | mtrr_if->get(i, | |
585 | &mtrr_state[i].lbase, | |
586 | &mtrr_state[i].lsize, | |
587 | &mtrr_state[i].ltype); | |
588 | } | |
589 | return 0; | |
590 | } | |
591 | ||
592 | static int mtrr_restore(struct sys_device * sysdev) | |
593 | { | |
594 | int i; | |
595 | ||
596 | for (i = 0; i < num_var_ranges; i++) { | |
597 | if (mtrr_state[i].lsize) | |
598 | set_mtrr(i, | |
599 | mtrr_state[i].lbase, | |
600 | mtrr_state[i].lsize, | |
601 | mtrr_state[i].ltype); | |
602 | } | |
1da177e4 LT |
603 | return 0; |
604 | } | |
605 | ||
606 | ||
607 | ||
608 | static struct sysdev_driver mtrr_sysdev_driver = { | |
609 | .suspend = mtrr_save, | |
610 | .resume = mtrr_restore, | |
611 | }; | |
612 | ||
95ffa243 | 613 | #ifdef CONFIG_MTRR_SANITIZER |
f5098d62 | 614 | static int enable_mtrr_cleanup __initdata = CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT; |
95ffa243 | 615 | #else |
95ffa243 | 616 | static int enable_mtrr_cleanup __initdata = -1; |
95ffa243 YL |
617 | #endif |
618 | ||
619 | static int __init disable_mtrr_cleanup_setup(char *str) | |
620 | { | |
621 | if (enable_mtrr_cleanup != -1) | |
622 | enable_mtrr_cleanup = 0; | |
623 | return 0; | |
624 | } | |
625 | early_param("disable_mtrr_cleanup", disable_mtrr_cleanup_setup); | |
626 | ||
627 | static int __init enable_mtrr_cleanup_setup(char *str) | |
628 | { | |
629 | if (enable_mtrr_cleanup != -1) | |
630 | enable_mtrr_cleanup = 1; | |
631 | return 0; | |
632 | } | |
633 | early_param("enble_mtrr_cleanup", enable_mtrr_cleanup_setup); | |
634 | ||
f5098d62 | 635 | /* should be related to MTRR_VAR_RANGES nums */ |
95ffa243 YL |
636 | #define RANGE_NUM 256 |
637 | ||
638 | struct res_range { | |
639 | unsigned long start; | |
640 | unsigned long end; | |
641 | }; | |
642 | ||
f5098d62 YL |
643 | static int __init |
644 | add_range(struct res_range *range, int nr_range, unsigned long start, | |
645 | unsigned long end) | |
95ffa243 | 646 | { |
f5098d62 YL |
647 | /* out of slots */ |
648 | if (nr_range >= RANGE_NUM) | |
649 | return nr_range; | |
95ffa243 | 650 | |
f5098d62 YL |
651 | range[nr_range].start = start; |
652 | range[nr_range].end = end; | |
653 | ||
654 | nr_range++; | |
655 | ||
656 | return nr_range; | |
657 | } | |
658 | ||
659 | static int __init | |
660 | add_range_with_merge(struct res_range *range, int nr_range, unsigned long start, | |
661 | unsigned long end) | |
662 | { | |
663 | int i; | |
95ffa243 YL |
664 | |
665 | /* try to merge it with old one */ | |
666 | for (i = 0; i < nr_range; i++) { | |
667 | unsigned long final_start, final_end; | |
668 | unsigned long common_start, common_end; | |
669 | ||
670 | if (!range[i].end) | |
671 | continue; | |
672 | ||
673 | common_start = max(range[i].start, start); | |
674 | common_end = min(range[i].end, end); | |
675 | if (common_start > common_end + 1) | |
676 | continue; | |
677 | ||
678 | final_start = min(range[i].start, start); | |
679 | final_end = max(range[i].end, end); | |
680 | ||
681 | range[i].start = final_start; | |
682 | range[i].end = final_end; | |
683 | return nr_range; | |
684 | } | |
685 | ||
95ffa243 | 686 | /* need to add that */ |
f5098d62 | 687 | return add_range(range, nr_range, start, end); |
95ffa243 | 688 | } |
f5098d62 YL |
689 | |
690 | static void __init | |
691 | subtract_range(struct res_range *range, unsigned long start, unsigned long end) | |
95ffa243 | 692 | { |
f5098d62 | 693 | int i, j; |
95ffa243 YL |
694 | |
695 | for (j = 0; j < RANGE_NUM; j++) { | |
696 | if (!range[j].end) | |
697 | continue; | |
698 | ||
699 | if (start <= range[j].start && end >= range[j].end) { | |
700 | range[j].start = 0; | |
701 | range[j].end = 0; | |
702 | continue; | |
703 | } | |
704 | ||
705 | if (start <= range[j].start && end < range[j].end && range[j].start < end + 1) { | |
706 | range[j].start = end + 1; | |
707 | continue; | |
708 | } | |
709 | ||
710 | ||
711 | if (start > range[j].start && end >= range[j].end && range[j].end > start - 1) { | |
712 | range[j].end = start - 1; | |
713 | continue; | |
714 | } | |
715 | ||
716 | if (start > range[j].start && end < range[j].end) { | |
717 | /* find the new spare */ | |
718 | for (i = 0; i < RANGE_NUM; i++) { | |
719 | if (range[i].end == 0) | |
720 | break; | |
721 | } | |
722 | if (i < RANGE_NUM) { | |
723 | range[i].end = range[j].end; | |
724 | range[i].start = end + 1; | |
725 | } else { | |
726 | printk(KERN_ERR "run of slot in ranges\n"); | |
727 | } | |
728 | range[j].end = start - 1; | |
729 | continue; | |
730 | } | |
731 | } | |
732 | } | |
733 | ||
734 | static int __init cmp_range(const void *x1, const void *x2) | |
735 | { | |
736 | const struct res_range *r1 = x1; | |
737 | const struct res_range *r2 = x2; | |
738 | long start1, start2; | |
739 | ||
740 | start1 = r1->start; | |
741 | start2 = r2->start; | |
742 | ||
743 | return start1 - start2; | |
744 | } | |
745 | ||
746 | struct var_mtrr_state { | |
f5098d62 YL |
747 | unsigned long range_startk; |
748 | unsigned long range_sizek; | |
749 | unsigned long chunk_sizek; | |
750 | unsigned long gran_sizek; | |
751 | unsigned int reg; | |
752 | unsigned int address_bits; | |
95ffa243 YL |
753 | }; |
754 | ||
f5098d62 YL |
755 | static void __init |
756 | set_var_mtrr(unsigned int reg, unsigned long basek, unsigned long sizek, | |
757 | unsigned char type, unsigned address_bits) | |
95ffa243 YL |
758 | { |
759 | u32 base_lo, base_hi, mask_lo, mask_hi; | |
f5098d62 | 760 | u64 base, mask; |
95ffa243 YL |
761 | |
762 | if (!sizek) { | |
763 | fill_mtrr_var_range(reg, 0, 0, 0, 0); | |
764 | return; | |
765 | } | |
766 | ||
f5098d62 YL |
767 | mask = (1ULL << address_bits) - 1; |
768 | mask &= ~((((u64)sizek) << 10) - 1); | |
95ffa243 | 769 | |
f5098d62 | 770 | base = ((u64)basek) << 10; |
95ffa243 | 771 | |
f5098d62 YL |
772 | base |= type; |
773 | mask |= 0x800; | |
774 | ||
775 | base_lo = base & ((1ULL<<32) - 1); | |
776 | base_hi = base >> 32; | |
777 | ||
778 | mask_lo = mask & ((1ULL<<32) - 1); | |
779 | mask_hi = mask >> 32; | |
95ffa243 | 780 | |
95ffa243 YL |
781 | fill_mtrr_var_range(reg, base_lo, base_hi, mask_lo, mask_hi); |
782 | } | |
783 | ||
f5098d62 YL |
784 | static unsigned int __init |
785 | range_to_mtrr(unsigned int reg, unsigned long range_startk, | |
786 | unsigned long range_sizek, unsigned char type, | |
787 | unsigned address_bits) | |
95ffa243 YL |
788 | { |
789 | if (!range_sizek || (reg >= num_var_ranges)) | |
790 | return reg; | |
791 | ||
792 | while (range_sizek) { | |
793 | unsigned long max_align, align; | |
794 | unsigned long sizek; | |
f5098d62 | 795 | |
95ffa243 YL |
796 | /* Compute the maximum size I can make a range */ |
797 | if (range_startk) | |
798 | max_align = ffs(range_startk) - 1; | |
799 | else | |
800 | max_align = 32; | |
801 | align = fls(range_sizek) - 1; | |
802 | if (align > max_align) | |
803 | align = max_align; | |
804 | ||
805 | sizek = 1 << align; | |
806 | printk(KERN_INFO "Setting variable MTRR %d, base: %ldMB, range: %ldMB, type %s\n", | |
807 | reg, range_startk >> 10, sizek >> 10, | |
808 | (type == MTRR_TYPE_UNCACHABLE)?"UC": | |
809 | ((type == MTRR_TYPE_WRBACK)?"WB":"Other") | |
810 | ); | |
811 | set_var_mtrr(reg++, range_startk, sizek, type, address_bits); | |
812 | range_startk += sizek; | |
813 | range_sizek -= sizek; | |
814 | if (reg >= num_var_ranges) | |
815 | break; | |
816 | } | |
817 | return reg; | |
818 | } | |
819 | ||
f5098d62 YL |
820 | static void __init |
821 | range_to_mtrr_with_hole(struct var_mtrr_state *state, unsigned long basek) | |
95ffa243 YL |
822 | { |
823 | unsigned long hole_basek, hole_sizek; | |
824 | unsigned long range0_basek, range0_sizek; | |
825 | unsigned long range_basek, range_sizek; | |
826 | unsigned long chunk_sizek; | |
827 | unsigned long gran_sizek; | |
828 | ||
829 | hole_basek = 0; | |
830 | hole_sizek = 0; | |
831 | chunk_sizek = state->chunk_sizek; | |
832 | gran_sizek = state->gran_sizek; | |
833 | ||
834 | /* align with gran size, prevent small block used up MTRRs */ | |
835 | range_basek = ALIGN(state->range_startk, gran_sizek); | |
836 | if ((range_basek > basek) && basek) | |
837 | return; | |
838 | range_sizek = ALIGN(state->range_sizek - (range_basek - state->range_startk), gran_sizek); | |
839 | ||
840 | while (range_basek + range_sizek > (state->range_startk + state->range_sizek)) { | |
841 | range_sizek -= gran_sizek; | |
842 | if (!range_sizek) | |
843 | return; | |
844 | } | |
845 | state->range_startk = range_basek; | |
846 | state->range_sizek = range_sizek; | |
847 | ||
848 | /* try to append some small hole */ | |
849 | range0_basek = state->range_startk; | |
850 | range0_sizek = ALIGN(state->range_sizek, chunk_sizek); | |
f5098d62 | 851 | if (range0_sizek == state->range_sizek) { |
95ffa243 YL |
852 | printk(KERN_INFO "rangeX: %016lx - %016lx\n", range0_basek<<10, (range0_basek + state->range_sizek)<<10); |
853 | state->reg = range_to_mtrr(state->reg, range0_basek, | |
854 | state->range_sizek, MTRR_TYPE_WRBACK, state->address_bits); | |
855 | return; | |
f5098d62 YL |
856 | } else if (basek) { |
857 | while (range0_basek + range0_sizek - chunk_sizek > basek) { | |
858 | range0_sizek -= chunk_sizek; | |
859 | if (!range0_sizek) | |
860 | break; | |
861 | } | |
95ffa243 YL |
862 | } |
863 | ||
864 | ||
f5098d62 YL |
865 | if (range0_sizek > chunk_sizek) |
866 | range0_sizek -= chunk_sizek; | |
95ffa243 YL |
867 | printk(KERN_INFO "range0: %016lx - %016lx\n", range0_basek<<10, (range0_basek + range0_sizek)<<10); |
868 | state->reg = range_to_mtrr(state->reg, range0_basek, | |
869 | range0_sizek, MTRR_TYPE_WRBACK, state->address_bits); | |
870 | ||
871 | range_basek = range0_basek + range0_sizek; | |
872 | range_sizek = chunk_sizek; | |
f5098d62 YL |
873 | |
874 | if ((range_sizek - (state->range_sizek - range0_sizek) < (chunk_sizek >> 1)) && | |
875 | (range_basek + range_sizek <= basek)) { | |
95ffa243 YL |
876 | hole_sizek = range_sizek - (state->range_sizek - range0_sizek); |
877 | hole_basek = range_basek + range_sizek - hole_sizek; | |
878 | } else | |
879 | range_sizek = state->range_sizek - range0_sizek; | |
880 | ||
881 | printk(KERN_INFO "range: %016lx - %016lx\n", range_basek<<10, (range_basek + range_sizek)<<10); | |
882 | state->reg = range_to_mtrr(state->reg, range_basek, | |
883 | range_sizek, MTRR_TYPE_WRBACK, state->address_bits); | |
884 | if (hole_sizek) { | |
885 | printk(KERN_INFO "hole: %016lx - %016lx\n", hole_basek<<10, (hole_basek + hole_sizek)<<10); | |
886 | state->reg = range_to_mtrr(state->reg, hole_basek, | |
887 | hole_sizek, MTRR_TYPE_UNCACHABLE, state->address_bits); | |
888 | } | |
889 | } | |
890 | ||
f5098d62 YL |
891 | static void __init |
892 | set_var_mtrr_range(struct var_mtrr_state *state, unsigned long base_pfn, | |
893 | unsigned long size_pfn) | |
95ffa243 YL |
894 | { |
895 | unsigned long basek, sizek; | |
896 | ||
897 | if (state->reg >= num_var_ranges) | |
898 | return; | |
899 | ||
900 | basek = base_pfn << (PAGE_SHIFT - 10); | |
901 | sizek = size_pfn << (PAGE_SHIFT - 10); | |
902 | ||
903 | /* See if I can merge with the last range */ | |
904 | if ((basek <= 1024) || (state->range_startk + state->range_sizek == basek)) { | |
905 | unsigned long endk = basek + sizek; | |
906 | state->range_sizek = endk - state->range_startk; | |
907 | return; | |
908 | } | |
909 | /* Write the range mtrrs */ | |
910 | if (state->range_sizek != 0) { | |
911 | range_to_mtrr_with_hole(state, basek); | |
912 | ||
913 | state->range_startk = 0; | |
914 | state->range_sizek = 0; | |
915 | } | |
916 | /* Allocate an msr */ | |
917 | state->range_startk = basek; | |
918 | state->range_sizek = sizek; | |
919 | } | |
920 | ||
921 | /* mininum size of mtrr block that can take hole */ | |
922 | static u64 mtrr_chunk_size __initdata = (256ULL<<20); | |
923 | ||
924 | static int __init parse_mtrr_chunk_size_opt(char *p) | |
925 | { | |
926 | if (!p) | |
927 | return -EINVAL; | |
928 | mtrr_chunk_size = memparse(p, &p); | |
929 | return 0; | |
930 | } | |
931 | early_param("mtrr_chunk_size", parse_mtrr_chunk_size_opt); | |
932 | ||
933 | /* granity of mtrr of block */ | |
f5098d62 | 934 | static u64 mtrr_gran_size __initdata = (1ULL<<20); |
95ffa243 YL |
935 | |
936 | static int __init parse_mtrr_gran_size_opt(char *p) | |
937 | { | |
938 | if (!p) | |
939 | return -EINVAL; | |
940 | mtrr_gran_size = memparse(p, &p); | |
941 | return 0; | |
942 | } | |
943 | early_param("mtrr_gran_size", parse_mtrr_gran_size_opt); | |
944 | ||
f5098d62 YL |
945 | static void __init |
946 | x86_setup_var_mtrrs(struct res_range *range, int nr_range, | |
947 | unsigned address_bits) | |
95ffa243 YL |
948 | { |
949 | struct var_mtrr_state var_state; | |
950 | int i; | |
951 | ||
f5098d62 YL |
952 | var_state.range_startk = 0; |
953 | var_state.range_sizek = 0; | |
954 | var_state.reg = 0; | |
955 | var_state.address_bits = address_bits; | |
956 | var_state.chunk_sizek = mtrr_chunk_size >> 10; | |
957 | var_state.gran_sizek = mtrr_gran_size >> 10; | |
95ffa243 YL |
958 | |
959 | /* Write the range etc */ | |
960 | for (i = 0; i < nr_range; i++) | |
961 | set_var_mtrr_range(&var_state, range[i].start, range[i].end - range[i].start + 1); | |
962 | ||
963 | /* Write the last range */ | |
964 | range_to_mtrr_with_hole(&var_state, 0); | |
965 | printk(KERN_INFO "DONE variable MTRRs\n"); | |
966 | /* Clear out the extra MTRR's */ | |
f5098d62 YL |
967 | while (var_state.reg < num_var_ranges) { |
968 | set_var_mtrr(var_state.reg, 0, 0, 0, var_state.address_bits); | |
969 | var_state.reg++; | |
970 | } | |
95ffa243 YL |
971 | } |
972 | ||
f5098d62 YL |
973 | static int __init |
974 | x86_get_mtrr_mem_range(struct res_range *range, int nr_range, | |
975 | unsigned long extra_remove_base, | |
976 | unsigned long extra_remove_size) | |
95ffa243 YL |
977 | { |
978 | unsigned long i, base, size; | |
979 | mtrr_type type; | |
980 | ||
981 | for (i = 0; i < num_var_ranges; i++) { | |
982 | mtrr_if->get(i, &base, &size, &type); | |
983 | if (type != MTRR_TYPE_WRBACK) | |
984 | continue; | |
f5098d62 | 985 | nr_range = add_range_with_merge(range, nr_range, base, base + size - 1); |
95ffa243 YL |
986 | } |
987 | printk(KERN_INFO "After WB checking\n"); | |
988 | for (i = 0; i < nr_range; i++) | |
989 | printk(KERN_INFO "MTRR MAP PFN: %016lx - %016lx\n", range[i].start, range[i].end + 1); | |
990 | ||
991 | /* take out UC ranges */ | |
992 | for (i = 0; i < num_var_ranges; i++) { | |
993 | mtrr_if->get(i, &base, &size, &type); | |
994 | if (type != MTRR_TYPE_UNCACHABLE) | |
995 | continue; | |
996 | if (!size) | |
997 | continue; | |
998 | subtract_range(range, base, base + size - 1); | |
999 | } | |
1000 | if (extra_remove_size) | |
1001 | subtract_range(range, extra_remove_base, extra_remove_base + extra_remove_size - 1); | |
1002 | ||
1003 | /* get new range num */ | |
1004 | nr_range = 0; | |
1005 | for (i = 0; i < RANGE_NUM; i++) { | |
1006 | if (!range[i].end) | |
1007 | continue; | |
1008 | nr_range++; | |
1009 | } | |
1010 | printk(KERN_INFO "After UC checking\n"); | |
1011 | for (i = 0; i < nr_range; i++) | |
1012 | printk(KERN_INFO "MTRR MAP PFN: %016lx - %016lx\n", range[i].start, range[i].end + 1); | |
1013 | ||
1014 | /* sort the ranges */ | |
1015 | sort(range, nr_range, sizeof(struct res_range), cmp_range, NULL); | |
1016 | printk(KERN_INFO "After sorting\n"); | |
1017 | for (i = 0; i < nr_range; i++) | |
1018 | printk(KERN_INFO "MTRR MAP PFN: %016lx - %016lx\n", range[i].start, range[i].end + 1); | |
1019 | ||
1020 | return nr_range; | |
1021 | } | |
1022 | ||
1023 | static int __init mtrr_cleanup(unsigned address_bits) | |
1024 | { | |
f5098d62 | 1025 | unsigned long extra_remove_base, extra_remove_size; |
95ffa243 | 1026 | unsigned long i, base, size, def, dummy; |
95ffa243 | 1027 | struct res_range range[RANGE_NUM]; |
f5098d62 | 1028 | mtrr_type type; |
95ffa243 | 1029 | int nr_range; |
95ffa243 YL |
1030 | |
1031 | /* extra one for all 0 */ | |
1032 | int num[MTRR_NUM_TYPES + 1]; | |
1033 | ||
1034 | if (!is_cpu(INTEL) || enable_mtrr_cleanup < 1) | |
1035 | return 0; | |
1036 | rdmsr(MTRRdefType_MSR, def, dummy); | |
1037 | def &= 0xff; | |
1038 | if (def != MTRR_TYPE_UNCACHABLE) | |
1039 | return 0; | |
1040 | ||
1041 | /* check entries number */ | |
1042 | memset(num, 0, sizeof(num)); | |
1043 | for (i = 0; i < num_var_ranges; i++) { | |
1044 | mtrr_if->get(i, &base, &size, &type); | |
1045 | if (type >= MTRR_NUM_TYPES) | |
1046 | continue; | |
1047 | if (!size) | |
1048 | type = MTRR_NUM_TYPES; | |
1049 | num[type]++; | |
1050 | } | |
1051 | ||
1052 | /* check if we got UC entries */ | |
1053 | if (!num[MTRR_TYPE_UNCACHABLE]) | |
1054 | return 0; | |
1055 | ||
1056 | /* check if we only had WB and UC */ | |
1057 | if (num[MTRR_TYPE_WRBACK] + num[MTRR_TYPE_UNCACHABLE] != | |
1058 | num_var_ranges - num[MTRR_NUM_TYPES]) | |
1059 | return 0; | |
1060 | ||
1061 | memset(range, 0, sizeof(range)); | |
1062 | extra_remove_size = 0; | |
1063 | if (mtrr_tom2) { | |
1064 | extra_remove_base = 1 << (32 - PAGE_SHIFT); | |
1065 | extra_remove_size = (mtrr_tom2>>PAGE_SHIFT) - extra_remove_base; | |
1066 | } | |
1067 | nr_range = x86_get_mtrr_mem_range(range, 0, extra_remove_base, extra_remove_size); | |
1068 | ||
1069 | /* convert ranges to var ranges state */ | |
1070 | x86_setup_var_mtrrs(range, nr_range, address_bits); | |
1071 | ||
1072 | return 1; | |
95ffa243 YL |
1073 | } |
1074 | ||
99fc8d42 JB |
1075 | static int disable_mtrr_trim; |
1076 | ||
1077 | static int __init disable_mtrr_trim_setup(char *str) | |
1078 | { | |
1079 | disable_mtrr_trim = 1; | |
1080 | return 0; | |
1081 | } | |
1082 | early_param("disable_mtrr_trim", disable_mtrr_trim_setup); | |
1083 | ||
1084 | /* | |
1085 | * Newer AMD K8s and later CPUs have a special magic MSR way to force WB | |
1086 | * for memory >4GB. Check for that here. | |
1087 | * Note this won't check if the MTRRs < 4GB where the magic bit doesn't | |
1088 | * apply to are wrong, but so far we don't know of any such case in the wild. | |
1089 | */ | |
1090 | #define Tom2Enabled (1U << 21) | |
1091 | #define Tom2ForceMemTypeWB (1U << 22) | |
1092 | ||
35605a10 | 1093 | int __init amd_special_default_mtrr(void) |
99fc8d42 JB |
1094 | { |
1095 | u32 l, h; | |
1096 | ||
99fc8d42 JB |
1097 | if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) |
1098 | return 0; | |
1099 | if (boot_cpu_data.x86 < 0xf || boot_cpu_data.x86 > 0x11) | |
1100 | return 0; | |
1101 | /* In case some hypervisor doesn't pass SYSCFG through */ | |
1102 | if (rdmsr_safe(MSR_K8_SYSCFG, &l, &h) < 0) | |
1103 | return 0; | |
1104 | /* | |
1105 | * Memory between 4GB and top of mem is forced WB by this magic bit. | |
1106 | * Reserved before K8RevF, but should be zero there. | |
1107 | */ | |
1108 | if ((l & (Tom2Enabled | Tom2ForceMemTypeWB)) == | |
1109 | (Tom2Enabled | Tom2ForceMemTypeWB)) | |
1110 | return 1; | |
1111 | return 0; | |
1112 | } | |
1113 | ||
42651f15 YL |
1114 | static u64 __init real_trim_memory(unsigned long start_pfn, unsigned long limit_pfn) |
1115 | { | |
1116 | u64 trim_start, trim_size; | |
8a374026 | 1117 | trim_start = start_pfn; |
42651f15 YL |
1118 | trim_start <<= PAGE_SHIFT; |
1119 | trim_size = limit_pfn; | |
1120 | trim_size <<= PAGE_SHIFT; | |
1121 | trim_size -= trim_start; | |
8a374026 | 1122 | |
42651f15 YL |
1123 | return update_memory_range(trim_start, trim_size, E820_RAM, |
1124 | E820_RESERVED); | |
1125 | } | |
99fc8d42 JB |
1126 | /** |
1127 | * mtrr_trim_uncached_memory - trim RAM not covered by MTRRs | |
f5106d91 | 1128 | * @end_pfn: ending page frame number |
99fc8d42 JB |
1129 | * |
1130 | * Some buggy BIOSes don't setup the MTRRs properly for systems with certain | |
1131 | * memory configurations. This routine checks that the highest MTRR matches | |
1132 | * the end of memory, to make sure the MTRRs having a write back type cover | |
1133 | * all of the memory the kernel is intending to use. If not, it'll trim any | |
1134 | * memory off the end by adjusting end_pfn, removing it from the kernel's | |
1135 | * allocation pools, warning the user with an obnoxious message. | |
1136 | */ | |
1137 | int __init mtrr_trim_uncached_memory(unsigned long end_pfn) | |
1138 | { | |
20651af9 | 1139 | unsigned long i, base, size, highest_pfn = 0, def, dummy; |
99fc8d42 | 1140 | mtrr_type type; |
42651f15 YL |
1141 | struct res_range range[RANGE_NUM]; |
1142 | int nr_range; | |
1143 | u64 total_real_trim_size; | |
99fc8d42 | 1144 | |
42651f15 YL |
1145 | /* extra one for all 0 */ |
1146 | int num[MTRR_NUM_TYPES + 1]; | |
99fc8d42 JB |
1147 | /* |
1148 | * Make sure we only trim uncachable memory on machines that | |
1149 | * support the Intel MTRR architecture: | |
1150 | */ | |
093af8d7 YL |
1151 | if (!is_cpu(INTEL) || disable_mtrr_trim) |
1152 | return 0; | |
99fc8d42 JB |
1153 | rdmsr(MTRRdefType_MSR, def, dummy); |
1154 | def &= 0xff; | |
093af8d7 YL |
1155 | if (def != MTRR_TYPE_UNCACHABLE) |
1156 | return 0; | |
1157 | ||
99fc8d42 JB |
1158 | /* Find highest cached pfn */ |
1159 | for (i = 0; i < num_var_ranges; i++) { | |
1160 | mtrr_if->get(i, &base, &size, &type); | |
1161 | if (type != MTRR_TYPE_WRBACK) | |
1162 | continue; | |
20651af9 YL |
1163 | if (highest_pfn < base + size) |
1164 | highest_pfn = base + size; | |
99fc8d42 JB |
1165 | } |
1166 | ||
093af8d7 | 1167 | /* kvm/qemu doesn't have mtrr set right, don't trim them all */ |
20651af9 | 1168 | if (!highest_pfn) { |
4147c874 JR |
1169 | if (!kvm_para_available()) { |
1170 | printk(KERN_WARNING | |
1171 | "WARNING: strange, CPU MTRRs all blank?\n"); | |
1172 | WARN_ON(1); | |
1173 | } | |
99fc8d42 | 1174 | return 0; |
093af8d7 | 1175 | } |
99fc8d42 | 1176 | |
42651f15 YL |
1177 | /* check entries number */ |
1178 | memset(num, 0, sizeof(num)); | |
1179 | for (i = 0; i < num_var_ranges; i++) { | |
1180 | mtrr_if->get(i, &base, &size, &type); | |
1181 | if (type >= MTRR_NUM_TYPES) | |
1182 | continue; | |
1183 | if (!size) | |
1184 | type = MTRR_NUM_TYPES; | |
1185 | num[type]++; | |
1186 | } | |
1187 | ||
1188 | /* no entry for WB? */ | |
1189 | if (!num[MTRR_TYPE_WRBACK]) | |
1190 | return 0; | |
1191 | ||
1192 | /* check if we only had WB and UC */ | |
1193 | if (num[MTRR_TYPE_WRBACK] + num[MTRR_TYPE_UNCACHABLE] != | |
1194 | num_var_ranges - num[MTRR_NUM_TYPES]) | |
1195 | return 0; | |
1196 | ||
1197 | memset(range, 0, sizeof(range)); | |
1198 | nr_range = 0; | |
1199 | if (mtrr_tom2) { | |
1200 | range[nr_range].start = (1ULL<<(32 - PAGE_SHIFT)); | |
1201 | range[nr_range].end = (mtrr_tom2 >> PAGE_SHIFT) - 1; | |
1202 | if (highest_pfn < range[nr_range].end + 1) | |
1203 | highest_pfn = range[nr_range].end + 1; | |
1204 | nr_range++; | |
1205 | } | |
1206 | nr_range = x86_get_mtrr_mem_range(range, nr_range, 0, 0); | |
1207 | ||
42651f15 | 1208 | total_real_trim_size = 0; |
8a374026 | 1209 | /* check the head */ |
42651f15 YL |
1210 | if (range[0].start) |
1211 | total_real_trim_size += real_trim_memory(0, range[0].start); | |
8a374026 YL |
1212 | /* check the holes */ |
1213 | for (i = 0; i < nr_range - 1; i++) { | |
42651f15 YL |
1214 | if (range[i].end + 1 < range[i+1].start) |
1215 | total_real_trim_size += real_trim_memory(range[i].end + 1, range[i+1].start); | |
1216 | } | |
8a374026 YL |
1217 | /* check the top */ |
1218 | i = nr_range - 1; | |
1219 | if (range[i].end + 1 < end_pfn) | |
1220 | total_real_trim_size += real_trim_memory(range[i].end + 1, end_pfn); | |
42651f15 YL |
1221 | |
1222 | if (total_real_trim_size) { | |
1223 | printk(KERN_WARNING "WARNING: BIOS bug: CPU MTRRs don't cover" | |
1224 | " all of memory, losing %lluMB of RAM.\n", | |
1225 | total_real_trim_size >> 20); | |
1226 | ||
8a374026 YL |
1227 | if (enable_mtrr_cleanup < 1) |
1228 | WARN_ON(1); | |
42651f15 | 1229 | |
8a374026 | 1230 | printk(KERN_INFO "update e820 for mtrr\n"); |
42651f15 | 1231 | update_e820(); |
8a374026 YL |
1232 | |
1233 | return 1; | |
42651f15 YL |
1234 | } |
1235 | ||
8a374026 | 1236 | return 0; |
99fc8d42 | 1237 | } |
1da177e4 LT |
1238 | |
1239 | /** | |
3b520b23 | 1240 | * mtrr_bp_init - initialize mtrrs on the boot CPU |
1da177e4 LT |
1241 | * |
1242 | * This needs to be called early; before any of the other CPUs are | |
1243 | * initialized (i.e. before smp_init()). | |
1244 | * | |
1245 | */ | |
9ef231a4 | 1246 | void __init mtrr_bp_init(void) |
1da177e4 | 1247 | { |
95ffa243 | 1248 | u32 phys_addr; |
1da177e4 LT |
1249 | init_ifs(); |
1250 | ||
95ffa243 YL |
1251 | phys_addr = 32; |
1252 | ||
1da177e4 LT |
1253 | if (cpu_has_mtrr) { |
1254 | mtrr_if = &generic_mtrr_ops; | |
1255 | size_or_mask = 0xff000000; /* 36 bits */ | |
1256 | size_and_mask = 0x00f00000; | |
95ffa243 | 1257 | phys_addr = 36; |
1f2c958a AK |
1258 | |
1259 | /* This is an AMD specific MSR, but we assume(hope?) that | |
1260 | Intel will implement it to when they extend the address | |
1261 | bus of the Xeon. */ | |
1262 | if (cpuid_eax(0x80000000) >= 0x80000008) { | |
1f2c958a | 1263 | phys_addr = cpuid_eax(0x80000008) & 0xff; |
af9c142d SL |
1264 | /* CPUID workaround for Intel 0F33/0F34 CPU */ |
1265 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
1266 | boot_cpu_data.x86 == 0xF && | |
1267 | boot_cpu_data.x86_model == 0x3 && | |
1268 | (boot_cpu_data.x86_mask == 0x3 || | |
1269 | boot_cpu_data.x86_mask == 0x4)) | |
1270 | phys_addr = 36; | |
1271 | ||
6c5806ca AH |
1272 | size_or_mask = ~((1ULL << (phys_addr - PAGE_SHIFT)) - 1); |
1273 | size_and_mask = ~size_or_mask & 0xfffff00000ULL; | |
1f2c958a AK |
1274 | } else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR && |
1275 | boot_cpu_data.x86 == 6) { | |
1276 | /* VIA C* family have Intel style MTRRs, but | |
1277 | don't support PAE */ | |
1278 | size_or_mask = 0xfff00000; /* 32 bits */ | |
1279 | size_and_mask = 0; | |
95ffa243 | 1280 | phys_addr = 32; |
1da177e4 LT |
1281 | } |
1282 | } else { | |
1283 | switch (boot_cpu_data.x86_vendor) { | |
1284 | case X86_VENDOR_AMD: | |
1285 | if (cpu_has_k6_mtrr) { | |
1286 | /* Pre-Athlon (K6) AMD CPU MTRRs */ | |
1287 | mtrr_if = mtrr_ops[X86_VENDOR_AMD]; | |
1288 | size_or_mask = 0xfff00000; /* 32 bits */ | |
1289 | size_and_mask = 0; | |
1290 | } | |
1291 | break; | |
1292 | case X86_VENDOR_CENTAUR: | |
1293 | if (cpu_has_centaur_mcr) { | |
1294 | mtrr_if = mtrr_ops[X86_VENDOR_CENTAUR]; | |
1295 | size_or_mask = 0xfff00000; /* 32 bits */ | |
1296 | size_and_mask = 0; | |
1297 | } | |
1298 | break; | |
1299 | case X86_VENDOR_CYRIX: | |
1300 | if (cpu_has_cyrix_arr) { | |
1301 | mtrr_if = mtrr_ops[X86_VENDOR_CYRIX]; | |
1302 | size_or_mask = 0xfff00000; /* 32 bits */ | |
1303 | size_and_mask = 0; | |
1304 | } | |
1305 | break; | |
1306 | default: | |
1307 | break; | |
1308 | } | |
1309 | } | |
1da177e4 LT |
1310 | |
1311 | if (mtrr_if) { | |
1312 | set_num_var_ranges(); | |
1313 | init_table(); | |
95ffa243 | 1314 | if (use_intel()) { |
3b520b23 | 1315 | get_mtrr_state(); |
95ffa243 YL |
1316 | |
1317 | if (mtrr_cleanup(phys_addr)) | |
1318 | mtrr_if->set_all(); | |
1319 | ||
1320 | } | |
1da177e4 | 1321 | } |
1da177e4 LT |
1322 | } |
1323 | ||
3b520b23 SL |
1324 | void mtrr_ap_init(void) |
1325 | { | |
1326 | unsigned long flags; | |
1327 | ||
1328 | if (!mtrr_if || !use_intel()) | |
1329 | return; | |
1330 | /* | |
14cc3e2b | 1331 | * Ideally we should hold mtrr_mutex here to avoid mtrr entries changed, |
3b520b23 SL |
1332 | * but this routine will be called in cpu boot time, holding the lock |
1333 | * breaks it. This routine is called in two cases: 1.very earily time | |
1334 | * of software resume, when there absolutely isn't mtrr entry changes; | |
1335 | * 2.cpu hotadd time. We let mtrr_add/del_page hold cpuhotplug lock to | |
1336 | * prevent mtrr entry changes | |
1337 | */ | |
1338 | local_irq_save(flags); | |
1339 | ||
1340 | mtrr_if->set_all(); | |
1341 | ||
1342 | local_irq_restore(flags); | |
1343 | } | |
1344 | ||
2b1f6278 BK |
1345 | /** |
1346 | * Save current fixed-range MTRR state of the BSP | |
1347 | */ | |
1348 | void mtrr_save_state(void) | |
1349 | { | |
c8f2518e | 1350 | smp_call_function_single(0, mtrr_save_fixed_ranges, NULL, 1, 1); |
2b1f6278 BK |
1351 | } |
1352 | ||
3b520b23 SL |
1353 | static int __init mtrr_init_finialize(void) |
1354 | { | |
1355 | if (!mtrr_if) | |
1356 | return 0; | |
95ffa243 YL |
1357 | if (use_intel()) { |
1358 | if (enable_mtrr_cleanup < 1) | |
1359 | mtrr_state_warn(); | |
1360 | } else { | |
27b46d76 | 1361 | /* The CPUs haven't MTRR and seem to not support SMP. They have |
3b520b23 SL |
1362 | * specific drivers, we use a tricky method to support |
1363 | * suspend/resume for them. | |
1364 | * TBD: is there any system with such CPU which supports | |
1365 | * suspend/resume? if no, we should remove the code. | |
1366 | */ | |
1367 | sysdev_driver_register(&cpu_sysdev_class, | |
1368 | &mtrr_sysdev_driver); | |
1369 | } | |
1370 | return 0; | |
1371 | } | |
1372 | subsys_initcall(mtrr_init_finialize); |