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Commit | Line | Data |
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1da177e4 LT |
1 | /* Generic MTRR (Memory Type Range Register) driver. |
2 | ||
3 | Copyright (C) 1997-2000 Richard Gooch | |
4 | Copyright (c) 2002 Patrick Mochel | |
5 | ||
6 | This library is free software; you can redistribute it and/or | |
7 | modify it under the terms of the GNU Library General Public | |
8 | License as published by the Free Software Foundation; either | |
9 | version 2 of the License, or (at your option) any later version. | |
10 | ||
11 | This library is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | Library General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU Library General Public | |
17 | License along with this library; if not, write to the Free | |
18 | Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | ||
20 | Richard Gooch may be reached by email at rgooch@atnf.csiro.au | |
21 | The postal address is: | |
22 | Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia. | |
23 | ||
24 | Source: "Pentium Pro Family Developer's Manual, Volume 3: | |
25 | Operating System Writer's Guide" (Intel document number 242692), | |
26 | section 11.11.7 | |
27 | ||
dbd51be0 JSR |
28 | This was cleaned and made readable by Patrick Mochel <mochel@osdl.org> |
29 | on 6-7 March 2002. | |
30 | Source: Intel Architecture Software Developers Manual, Volume 3: | |
1da177e4 LT |
31 | System Programming Guide; Section 9.11. (1997 edition - PPro). |
32 | */ | |
33 | ||
dbd51be0 JSR |
34 | #define DEBUG |
35 | ||
36 | #include <linux/types.h> /* FIXME: kvm_para.h needs this */ | |
37 | ||
68f202e4 | 38 | #include <linux/stop_machine.h> |
dbd51be0 JSR |
39 | #include <linux/kvm_para.h> |
40 | #include <linux/uaccess.h> | |
1da177e4 | 41 | #include <linux/module.h> |
dbd51be0 | 42 | #include <linux/mutex.h> |
1da177e4 | 43 | #include <linux/init.h> |
dbd51be0 JSR |
44 | #include <linux/sort.h> |
45 | #include <linux/cpu.h> | |
1da177e4 LT |
46 | #include <linux/pci.h> |
47 | #include <linux/smp.h> | |
f3c6ea1b | 48 | #include <linux/syscore_ops.h> |
1da177e4 | 49 | |
dbd51be0 | 50 | #include <asm/processor.h> |
99fc8d42 | 51 | #include <asm/e820.h> |
1da177e4 | 52 | #include <asm/mtrr.h> |
1da177e4 | 53 | #include <asm/msr.h> |
d0d98eed | 54 | #include <asm/pat.h> |
dbd51be0 | 55 | |
1da177e4 LT |
56 | #include "mtrr.h" |
57 | ||
d0d98eed AL |
58 | /* arch_phys_wc_add returns an MTRR register index plus this offset. */ |
59 | #define MTRR_TO_PHYS_WC_OFFSET 1000 | |
60 | ||
dbd51be0 | 61 | u32 num_var_ranges; |
f9626104 LR |
62 | static bool __mtrr_enabled; |
63 | ||
64 | static bool mtrr_enabled(void) | |
65 | { | |
66 | return __mtrr_enabled; | |
67 | } | |
1da177e4 | 68 | |
b558bc0a | 69 | unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES]; |
14cc3e2b | 70 | static DEFINE_MUTEX(mtrr_mutex); |
1da177e4 | 71 | |
6c5806ca | 72 | u64 size_or_mask, size_and_mask; |
5400743d | 73 | static bool mtrr_aps_delayed_init; |
1da177e4 | 74 | |
3b9cfc0a | 75 | static const struct mtrr_ops *mtrr_ops[X86_VENDOR_NUM]; |
1da177e4 | 76 | |
3b9cfc0a | 77 | const struct mtrr_ops *mtrr_if; |
1da177e4 LT |
78 | |
79 | static void set_mtrr(unsigned int reg, unsigned long base, | |
80 | unsigned long size, mtrr_type type); | |
81 | ||
3b9cfc0a | 82 | void set_mtrr_ops(const struct mtrr_ops *ops) |
1da177e4 LT |
83 | { |
84 | if (ops->vendor && ops->vendor < X86_VENDOR_NUM) | |
85 | mtrr_ops[ops->vendor] = ops; | |
86 | } | |
87 | ||
88 | /* Returns non-zero if we have the write-combining memory type */ | |
89 | static int have_wrcomb(void) | |
90 | { | |
91 | struct pci_dev *dev; | |
dbd51be0 JSR |
92 | |
93 | dev = pci_get_class(PCI_CLASS_BRIDGE_HOST << 8, NULL); | |
94 | if (dev != NULL) { | |
95 | /* | |
96 | * ServerWorks LE chipsets < rev 6 have problems with | |
97 | * write-combining. Don't allow it and leave room for other | |
98 | * chipsets to be tagged | |
99 | */ | |
1da177e4 | 100 | if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS && |
50c31e4a SS |
101 | dev->device == PCI_DEVICE_ID_SERVERWORKS_LE && |
102 | dev->revision <= 5) { | |
103 | pr_info("mtrr: Serverworks LE rev < 6 detected. Write-combining disabled.\n"); | |
104 | pci_dev_put(dev); | |
105 | return 0; | |
1da177e4 | 106 | } |
dbd51be0 JSR |
107 | /* |
108 | * Intel 450NX errata # 23. Non ascending cacheline evictions to | |
109 | * write combining memory may resulting in data corruption | |
110 | */ | |
1da177e4 LT |
111 | if (dev->vendor == PCI_VENDOR_ID_INTEL && |
112 | dev->device == PCI_DEVICE_ID_INTEL_82451NX) { | |
dbd51be0 | 113 | pr_info("mtrr: Intel 450NX MMC detected. Write-combining disabled.\n"); |
1da177e4 LT |
114 | pci_dev_put(dev); |
115 | return 0; | |
116 | } | |
117 | pci_dev_put(dev); | |
dbd51be0 JSR |
118 | } |
119 | return mtrr_if->have_wrcomb ? mtrr_if->have_wrcomb() : 0; | |
1da177e4 LT |
120 | } |
121 | ||
122 | /* This function returns the number of variable MTRRs */ | |
123 | static void __init set_num_var_ranges(void) | |
124 | { | |
125 | unsigned long config = 0, dummy; | |
126 | ||
dbd51be0 | 127 | if (use_intel()) |
d9bcc01d | 128 | rdmsr(MSR_MTRRcap, config, dummy); |
dbd51be0 | 129 | else if (is_cpu(AMD)) |
1da177e4 LT |
130 | config = 2; |
131 | else if (is_cpu(CYRIX) || is_cpu(CENTAUR)) | |
132 | config = 8; | |
dbd51be0 | 133 | |
1da177e4 LT |
134 | num_var_ranges = config & 0xff; |
135 | } | |
136 | ||
137 | static void __init init_table(void) | |
138 | { | |
139 | int i, max; | |
140 | ||
141 | max = num_var_ranges; | |
1da177e4 | 142 | for (i = 0; i < max; i++) |
99fc8d42 | 143 | mtrr_usage_table[i] = 1; |
1da177e4 LT |
144 | } |
145 | ||
146 | struct set_mtrr_data { | |
1da177e4 LT |
147 | unsigned long smp_base; |
148 | unsigned long smp_size; | |
149 | unsigned int smp_reg; | |
150 | mtrr_type smp_type; | |
151 | }; | |
152 | ||
dbd51be0 | 153 | /** |
192d8857 SS |
154 | * mtrr_rendezvous_handler - Work done in the synchronization handler. Executed |
155 | * by all the CPUs. | |
6c550ee4 | 156 | * @info: pointer to mtrr configuration data |
dbd51be0 JSR |
157 | * |
158 | * Returns nothing. | |
159 | */ | |
192d8857 | 160 | static int mtrr_rendezvous_handler(void *info) |
1da177e4 LT |
161 | { |
162 | struct set_mtrr_data *data = info; | |
1da177e4 | 163 | |
192d8857 SS |
164 | /* |
165 | * We use this same function to initialize the mtrrs during boot, | |
166 | * resume, runtime cpu online and on an explicit request to set a | |
167 | * specific MTRR. | |
168 | * | |
169 | * During boot or suspend, the state of the boot cpu's mtrrs has been | |
170 | * saved, and we want to replicate that across all the cpus that come | |
171 | * online (either at the end of boot or resume or during a runtime cpu | |
172 | * online). If we're doing that, @reg is set to something special and on | |
173 | * all the cpu's we do mtrr_if->set_all() (On the logical cpu that | |
174 | * started the boot/resume sequence, this might be a duplicate | |
175 | * set_all()). | |
176 | */ | |
dbd51be0 JSR |
177 | if (data->smp_reg != ~0U) { |
178 | mtrr_if->set(data->smp_reg, data->smp_base, | |
1da177e4 | 179 | data->smp_size, data->smp_type); |
192d8857 | 180 | } else if (mtrr_aps_delayed_init || !cpu_online(smp_processor_id())) { |
1da177e4 | 181 | mtrr_if->set_all(); |
dbd51be0 | 182 | } |
68f202e4 | 183 | return 0; |
4e2947f1 | 184 | } |
1da177e4 | 185 | |
dbd51be0 JSR |
186 | static inline int types_compatible(mtrr_type type1, mtrr_type type2) |
187 | { | |
365bff80 JB |
188 | return type1 == MTRR_TYPE_UNCACHABLE || |
189 | type2 == MTRR_TYPE_UNCACHABLE || | |
190 | (type1 == MTRR_TYPE_WRTHROUGH && type2 == MTRR_TYPE_WRBACK) || | |
191 | (type1 == MTRR_TYPE_WRBACK && type2 == MTRR_TYPE_WRTHROUGH); | |
192 | } | |
193 | ||
1da177e4 LT |
194 | /** |
195 | * set_mtrr - update mtrrs on all processors | |
196 | * @reg: mtrr in question | |
197 | * @base: mtrr base | |
198 | * @size: mtrr size | |
199 | * @type: mtrr type | |
200 | * | |
201 | * This is kinda tricky, but fortunately, Intel spelled it out for us cleanly: | |
dbd51be0 | 202 | * |
68f202e4 | 203 | * 1. Queue work to do the following on all processors: |
1da177e4 | 204 | * 2. Disable Interrupts |
dbd51be0 | 205 | * 3. Wait for all procs to do so |
1da177e4 LT |
206 | * 4. Enter no-fill cache mode |
207 | * 5. Flush caches | |
208 | * 6. Clear PGE bit | |
209 | * 7. Flush all TLBs | |
210 | * 8. Disable all range registers | |
211 | * 9. Update the MTRRs | |
212 | * 10. Enable all range registers | |
213 | * 11. Flush all TLBs and caches again | |
214 | * 12. Enter normal cache mode and reenable caching | |
dbd51be0 | 215 | * 13. Set PGE |
1da177e4 LT |
216 | * 14. Wait for buddies to catch up |
217 | * 15. Enable interrupts. | |
dbd51be0 | 218 | * |
192d8857 SS |
219 | * What does that mean for us? Well, stop_machine() will ensure that |
220 | * the rendezvous handler is started on each CPU. And in lockstep they | |
221 | * do the state transition of disabling interrupts, updating MTRR's | |
222 | * (the CPU vendors may each do it differently, so we call mtrr_if->set() | |
223 | * callback and let them take care of it.) and enabling interrupts. | |
1da177e4 LT |
224 | * |
225 | * Note that the mechanism is the same for UP systems, too; all the SMP stuff | |
226 | * becomes nops. | |
227 | */ | |
dbd51be0 JSR |
228 | static void |
229 | set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type) | |
1da177e4 | 230 | { |
192d8857 SS |
231 | struct set_mtrr_data data = { .smp_reg = reg, |
232 | .smp_base = base, | |
233 | .smp_size = size, | |
234 | .smp_type = type | |
235 | }; | |
68f202e4 | 236 | |
192d8857 SS |
237 | stop_machine(mtrr_rendezvous_handler, &data, cpu_online_mask); |
238 | } | |
1da177e4 | 239 | |
192d8857 SS |
240 | static void set_mtrr_from_inactive_cpu(unsigned int reg, unsigned long base, |
241 | unsigned long size, mtrr_type type) | |
242 | { | |
243 | struct set_mtrr_data data = { .smp_reg = reg, | |
244 | .smp_base = base, | |
245 | .smp_size = size, | |
246 | .smp_type = type | |
247 | }; | |
248 | ||
249 | stop_machine_from_inactive_cpu(mtrr_rendezvous_handler, &data, | |
250 | cpu_callout_mask); | |
1da177e4 LT |
251 | } |
252 | ||
253 | /** | |
dbd51be0 JSR |
254 | * mtrr_add_page - Add a memory type region |
255 | * @base: Physical base address of region in pages (in units of 4 kB!) | |
256 | * @size: Physical size of region in pages (4 kB) | |
257 | * @type: Type of MTRR desired | |
258 | * @increment: If this is true do usage counting on the region | |
1da177e4 | 259 | * |
dbd51be0 JSR |
260 | * Memory type region registers control the caching on newer Intel and |
261 | * non Intel processors. This function allows drivers to request an | |
262 | * MTRR is added. The details and hardware specifics of each processor's | |
263 | * implementation are hidden from the caller, but nevertheless the | |
264 | * caller should expect to need to provide a power of two size on an | |
265 | * equivalent power of two boundary. | |
1da177e4 | 266 | * |
dbd51be0 JSR |
267 | * If the region cannot be added either because all regions are in use |
268 | * or the CPU cannot support it a negative value is returned. On success | |
269 | * the register number for this entry is returned, but should be treated | |
270 | * as a cookie only. | |
1da177e4 | 271 | * |
dbd51be0 JSR |
272 | * On a multiprocessor machine the changes are made to all processors. |
273 | * This is required on x86 by the Intel processors. | |
1da177e4 | 274 | * |
dbd51be0 | 275 | * The available types are |
1da177e4 | 276 | * |
dbd51be0 | 277 | * %MTRR_TYPE_UNCACHABLE - No caching |
1da177e4 | 278 | * |
dbd51be0 | 279 | * %MTRR_TYPE_WRBACK - Write data back in bursts whenever |
1da177e4 | 280 | * |
dbd51be0 | 281 | * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts |
1da177e4 | 282 | * |
dbd51be0 | 283 | * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes |
1da177e4 | 284 | * |
dbd51be0 JSR |
285 | * BUGS: Needs a quiet flag for the cases where drivers do not mind |
286 | * failures and do not wish system log messages to be sent. | |
1da177e4 | 287 | */ |
dbd51be0 | 288 | int mtrr_add_page(unsigned long base, unsigned long size, |
2d2ee8de | 289 | unsigned int type, bool increment) |
1da177e4 | 290 | { |
dbd51be0 | 291 | unsigned long lbase, lsize; |
365bff80 | 292 | int i, replace, error; |
1da177e4 | 293 | mtrr_type ltype; |
1da177e4 | 294 | |
f9626104 | 295 | if (!mtrr_enabled()) |
1da177e4 | 296 | return -ENXIO; |
dbd51be0 JSR |
297 | |
298 | error = mtrr_if->validate_add_page(base, size, type); | |
299 | if (error) | |
1da177e4 LT |
300 | return error; |
301 | ||
302 | if (type >= MTRR_NUM_TYPES) { | |
dbd51be0 | 303 | pr_warning("mtrr: type: %u invalid\n", type); |
1da177e4 LT |
304 | return -EINVAL; |
305 | } | |
306 | ||
dbd51be0 | 307 | /* If the type is WC, check that this processor supports it */ |
1da177e4 | 308 | if ((type == MTRR_TYPE_WRCOMB) && !have_wrcomb()) { |
dbd51be0 | 309 | pr_warning("mtrr: your processor doesn't support write-combining\n"); |
1da177e4 LT |
310 | return -ENOSYS; |
311 | } | |
312 | ||
365bff80 | 313 | if (!size) { |
dbd51be0 | 314 | pr_warning("mtrr: zero sized request\n"); |
365bff80 JB |
315 | return -EINVAL; |
316 | } | |
317 | ||
d5c78673 YL |
318 | if ((base | (base + size - 1)) >> |
319 | (boot_cpu_data.x86_phys_bits - PAGE_SHIFT)) { | |
dbd51be0 | 320 | pr_warning("mtrr: base or size exceeds the MTRR width\n"); |
1da177e4 LT |
321 | return -EINVAL; |
322 | } | |
323 | ||
324 | error = -EINVAL; | |
365bff80 | 325 | replace = -1; |
1da177e4 | 326 | |
3b520b23 | 327 | /* No CPU hotplug when we change MTRR entries */ |
86ef5c9a | 328 | get_online_cpus(); |
dbd51be0 JSR |
329 | |
330 | /* Search for existing MTRR */ | |
14cc3e2b | 331 | mutex_lock(&mtrr_mutex); |
1da177e4 LT |
332 | for (i = 0; i < num_var_ranges; ++i) { |
333 | mtrr_if->get(i, &lbase, &lsize, <ype); | |
dbd51be0 JSR |
334 | if (!lsize || base > lbase + lsize - 1 || |
335 | base + size - 1 < lbase) | |
1da177e4 | 336 | continue; |
dbd51be0 JSR |
337 | /* |
338 | * At this point we know there is some kind of | |
339 | * overlap/enclosure | |
340 | */ | |
365bff80 | 341 | if (base < lbase || base + size - 1 > lbase + lsize - 1) { |
dbd51be0 JSR |
342 | if (base <= lbase && |
343 | base + size - 1 >= lbase + lsize - 1) { | |
365bff80 JB |
344 | /* New region encloses an existing region */ |
345 | if (type == ltype) { | |
346 | replace = replace == -1 ? i : -2; | |
347 | continue; | |
dbd51be0 | 348 | } else if (types_compatible(type, ltype)) |
365bff80 JB |
349 | continue; |
350 | } | |
dbd51be0 JSR |
351 | pr_warning("mtrr: 0x%lx000,0x%lx000 overlaps existing" |
352 | " 0x%lx000,0x%lx000\n", base, size, lbase, | |
353 | lsize); | |
1da177e4 LT |
354 | goto out; |
355 | } | |
dbd51be0 | 356 | /* New region is enclosed by an existing region */ |
1da177e4 | 357 | if (ltype != type) { |
365bff80 | 358 | if (types_compatible(type, ltype)) |
1da177e4 | 359 | continue; |
dbd51be0 JSR |
360 | pr_warning("mtrr: type mismatch for %lx000,%lx000 old: %s new: %s\n", |
361 | base, size, mtrr_attrib_to_str(ltype), | |
362 | mtrr_attrib_to_str(type)); | |
1da177e4 LT |
363 | goto out; |
364 | } | |
365 | if (increment) | |
99fc8d42 | 366 | ++mtrr_usage_table[i]; |
1da177e4 LT |
367 | error = i; |
368 | goto out; | |
369 | } | |
dbd51be0 | 370 | /* Search for an empty MTRR */ |
365bff80 | 371 | i = mtrr_if->get_free_region(base, size, replace); |
1da177e4 LT |
372 | if (i >= 0) { |
373 | set_mtrr(i, base, size, type); | |
99fc8d42 JB |
374 | if (likely(replace < 0)) { |
375 | mtrr_usage_table[i] = 1; | |
376 | } else { | |
377 | mtrr_usage_table[i] = mtrr_usage_table[replace]; | |
2d2ee8de | 378 | if (increment) |
99fc8d42 | 379 | mtrr_usage_table[i]++; |
365bff80 JB |
380 | if (unlikely(replace != i)) { |
381 | set_mtrr(replace, 0, 0, 0); | |
99fc8d42 | 382 | mtrr_usage_table[replace] = 0; |
365bff80 JB |
383 | } |
384 | } | |
dbd51be0 JSR |
385 | } else { |
386 | pr_info("mtrr: no more MTRRs available\n"); | |
387 | } | |
1da177e4 LT |
388 | error = i; |
389 | out: | |
14cc3e2b | 390 | mutex_unlock(&mtrr_mutex); |
86ef5c9a | 391 | put_online_cpus(); |
1da177e4 LT |
392 | return error; |
393 | } | |
394 | ||
c92c6ffd AM |
395 | static int mtrr_check(unsigned long base, unsigned long size) |
396 | { | |
397 | if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) { | |
dbd51be0 JSR |
398 | pr_warning("mtrr: size and base must be multiples of 4 kiB\n"); |
399 | pr_debug("mtrr: size: 0x%lx base: 0x%lx\n", size, base); | |
c92c6ffd AM |
400 | dump_stack(); |
401 | return -1; | |
402 | } | |
403 | return 0; | |
404 | } | |
405 | ||
1da177e4 | 406 | /** |
dbd51be0 JSR |
407 | * mtrr_add - Add a memory type region |
408 | * @base: Physical base address of region | |
409 | * @size: Physical size of region | |
410 | * @type: Type of MTRR desired | |
411 | * @increment: If this is true do usage counting on the region | |
1da177e4 | 412 | * |
dbd51be0 JSR |
413 | * Memory type region registers control the caching on newer Intel and |
414 | * non Intel processors. This function allows drivers to request an | |
415 | * MTRR is added. The details and hardware specifics of each processor's | |
416 | * implementation are hidden from the caller, but nevertheless the | |
417 | * caller should expect to need to provide a power of two size on an | |
418 | * equivalent power of two boundary. | |
1da177e4 | 419 | * |
dbd51be0 JSR |
420 | * If the region cannot be added either because all regions are in use |
421 | * or the CPU cannot support it a negative value is returned. On success | |
422 | * the register number for this entry is returned, but should be treated | |
423 | * as a cookie only. | |
1da177e4 | 424 | * |
dbd51be0 JSR |
425 | * On a multiprocessor machine the changes are made to all processors. |
426 | * This is required on x86 by the Intel processors. | |
1da177e4 | 427 | * |
dbd51be0 | 428 | * The available types are |
1da177e4 | 429 | * |
dbd51be0 | 430 | * %MTRR_TYPE_UNCACHABLE - No caching |
1da177e4 | 431 | * |
dbd51be0 | 432 | * %MTRR_TYPE_WRBACK - Write data back in bursts whenever |
1da177e4 | 433 | * |
dbd51be0 | 434 | * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts |
1da177e4 | 435 | * |
dbd51be0 | 436 | * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes |
1da177e4 | 437 | * |
dbd51be0 JSR |
438 | * BUGS: Needs a quiet flag for the cases where drivers do not mind |
439 | * failures and do not wish system log messages to be sent. | |
1da177e4 | 440 | */ |
dbd51be0 JSR |
441 | int mtrr_add(unsigned long base, unsigned long size, unsigned int type, |
442 | bool increment) | |
1da177e4 | 443 | { |
f9626104 LR |
444 | if (!mtrr_enabled()) |
445 | return -ENODEV; | |
c92c6ffd | 446 | if (mtrr_check(base, size)) |
1da177e4 | 447 | return -EINVAL; |
1da177e4 LT |
448 | return mtrr_add_page(base >> PAGE_SHIFT, size >> PAGE_SHIFT, type, |
449 | increment); | |
450 | } | |
dbd51be0 | 451 | EXPORT_SYMBOL(mtrr_add); |
1da177e4 LT |
452 | |
453 | /** | |
dbd51be0 JSR |
454 | * mtrr_del_page - delete a memory type region |
455 | * @reg: Register returned by mtrr_add | |
456 | * @base: Physical base address | |
457 | * @size: Size of region | |
1da177e4 | 458 | * |
dbd51be0 JSR |
459 | * If register is supplied then base and size are ignored. This is |
460 | * how drivers should call it. | |
1da177e4 | 461 | * |
dbd51be0 JSR |
462 | * Releases an MTRR region. If the usage count drops to zero the |
463 | * register is freed and the region returns to default state. | |
464 | * On success the register is returned, on failure a negative error | |
465 | * code. | |
1da177e4 | 466 | */ |
1da177e4 LT |
467 | int mtrr_del_page(int reg, unsigned long base, unsigned long size) |
468 | { | |
469 | int i, max; | |
470 | mtrr_type ltype; | |
365bff80 | 471 | unsigned long lbase, lsize; |
1da177e4 LT |
472 | int error = -EINVAL; |
473 | ||
f9626104 LR |
474 | if (!mtrr_enabled()) |
475 | return -ENODEV; | |
1da177e4 LT |
476 | |
477 | max = num_var_ranges; | |
3b520b23 | 478 | /* No CPU hotplug when we change MTRR entries */ |
86ef5c9a | 479 | get_online_cpus(); |
14cc3e2b | 480 | mutex_lock(&mtrr_mutex); |
1da177e4 LT |
481 | if (reg < 0) { |
482 | /* Search for existing MTRR */ | |
483 | for (i = 0; i < max; ++i) { | |
484 | mtrr_if->get(i, &lbase, &lsize, <ype); | |
485 | if (lbase == base && lsize == size) { | |
486 | reg = i; | |
487 | break; | |
488 | } | |
489 | } | |
490 | if (reg < 0) { | |
dbd51be0 JSR |
491 | pr_debug("mtrr: no MTRR for %lx000,%lx000 found\n", |
492 | base, size); | |
1da177e4 LT |
493 | goto out; |
494 | } | |
495 | } | |
496 | if (reg >= max) { | |
dbd51be0 | 497 | pr_warning("mtrr: register: %d too big\n", reg); |
1da177e4 LT |
498 | goto out; |
499 | } | |
1da177e4 LT |
500 | mtrr_if->get(reg, &lbase, &lsize, <ype); |
501 | if (lsize < 1) { | |
dbd51be0 | 502 | pr_warning("mtrr: MTRR %d not used\n", reg); |
1da177e4 LT |
503 | goto out; |
504 | } | |
99fc8d42 | 505 | if (mtrr_usage_table[reg] < 1) { |
dbd51be0 | 506 | pr_warning("mtrr: reg: %d has count=0\n", reg); |
1da177e4 LT |
507 | goto out; |
508 | } | |
99fc8d42 | 509 | if (--mtrr_usage_table[reg] < 1) |
1da177e4 LT |
510 | set_mtrr(reg, 0, 0, 0); |
511 | error = reg; | |
512 | out: | |
14cc3e2b | 513 | mutex_unlock(&mtrr_mutex); |
86ef5c9a | 514 | put_online_cpus(); |
1da177e4 LT |
515 | return error; |
516 | } | |
dbd51be0 | 517 | |
1da177e4 | 518 | /** |
dbd51be0 JSR |
519 | * mtrr_del - delete a memory type region |
520 | * @reg: Register returned by mtrr_add | |
521 | * @base: Physical base address | |
522 | * @size: Size of region | |
1da177e4 | 523 | * |
dbd51be0 JSR |
524 | * If register is supplied then base and size are ignored. This is |
525 | * how drivers should call it. | |
1da177e4 | 526 | * |
dbd51be0 JSR |
527 | * Releases an MTRR region. If the usage count drops to zero the |
528 | * register is freed and the region returns to default state. | |
529 | * On success the register is returned, on failure a negative error | |
530 | * code. | |
1da177e4 | 531 | */ |
dbd51be0 | 532 | int mtrr_del(int reg, unsigned long base, unsigned long size) |
1da177e4 | 533 | { |
f9626104 LR |
534 | if (!mtrr_enabled()) |
535 | return -ENODEV; | |
c92c6ffd | 536 | if (mtrr_check(base, size)) |
1da177e4 | 537 | return -EINVAL; |
1da177e4 LT |
538 | return mtrr_del_page(reg, base >> PAGE_SHIFT, size >> PAGE_SHIFT); |
539 | } | |
1da177e4 LT |
540 | EXPORT_SYMBOL(mtrr_del); |
541 | ||
d0d98eed AL |
542 | /** |
543 | * arch_phys_wc_add - add a WC MTRR and handle errors if PAT is unavailable | |
544 | * @base: Physical base address | |
545 | * @size: Size of region | |
546 | * | |
547 | * If PAT is available, this does nothing. If PAT is unavailable, it | |
548 | * attempts to add a WC MTRR covering size bytes starting at base and | |
549 | * logs an error if this fails. | |
550 | * | |
2f9e8973 LR |
551 | * The called should provide a power of two size on an equivalent |
552 | * power of two boundary. | |
553 | * | |
d0d98eed AL |
554 | * Drivers must store the return value to pass to mtrr_del_wc_if_needed, |
555 | * but drivers should not try to interpret that return value. | |
556 | */ | |
557 | int arch_phys_wc_add(unsigned long base, unsigned long size) | |
558 | { | |
559 | int ret; | |
560 | ||
f9626104 | 561 | if (pat_enabled || !mtrr_enabled()) |
d0d98eed AL |
562 | return 0; /* Success! (We don't need to do anything.) */ |
563 | ||
564 | ret = mtrr_add(base, size, MTRR_TYPE_WRCOMB, true); | |
565 | if (ret < 0) { | |
566 | pr_warn("Failed to add WC MTRR for [%p-%p]; performance may suffer.", | |
567 | (void *)base, (void *)(base + size - 1)); | |
568 | return ret; | |
569 | } | |
570 | return ret + MTRR_TO_PHYS_WC_OFFSET; | |
571 | } | |
572 | EXPORT_SYMBOL(arch_phys_wc_add); | |
573 | ||
574 | /* | |
575 | * arch_phys_wc_del - undoes arch_phys_wc_add | |
576 | * @handle: Return value from arch_phys_wc_add | |
577 | * | |
578 | * This cleans up after mtrr_add_wc_if_needed. | |
579 | * | |
580 | * The API guarantees that mtrr_del_wc_if_needed(error code) and | |
581 | * mtrr_del_wc_if_needed(0) do nothing. | |
582 | */ | |
583 | void arch_phys_wc_del(int handle) | |
584 | { | |
585 | if (handle >= 1) { | |
586 | WARN_ON(handle < MTRR_TO_PHYS_WC_OFFSET); | |
587 | mtrr_del(handle - MTRR_TO_PHYS_WC_OFFSET, 0, 0); | |
588 | } | |
589 | } | |
590 | EXPORT_SYMBOL(arch_phys_wc_del); | |
591 | ||
592 | /* | |
7d010fdf | 593 | * arch_phys_wc_index - translates arch_phys_wc_add's return value |
d0d98eed AL |
594 | * @handle: Return value from arch_phys_wc_add |
595 | * | |
596 | * This will turn the return value from arch_phys_wc_add into an mtrr | |
597 | * index suitable for debugging. | |
598 | * | |
599 | * Note: There is no legitimate use for this function, except possibly | |
600 | * in printk line. Alas there is an illegitimate use in some ancient | |
601 | * drm ioctls. | |
602 | */ | |
7d010fdf | 603 | int arch_phys_wc_index(int handle) |
d0d98eed AL |
604 | { |
605 | if (handle < MTRR_TO_PHYS_WC_OFFSET) | |
606 | return -1; | |
607 | else | |
608 | return handle - MTRR_TO_PHYS_WC_OFFSET; | |
609 | } | |
7d010fdf | 610 | EXPORT_SYMBOL_GPL(arch_phys_wc_index); |
d0d98eed | 611 | |
dbd51be0 JSR |
612 | /* |
613 | * HACK ALERT! | |
1da177e4 LT |
614 | * These should be called implicitly, but we can't yet until all the initcall |
615 | * stuff is done... | |
616 | */ | |
1da177e4 LT |
617 | static void __init init_ifs(void) |
618 | { | |
475850c8 | 619 | #ifndef CONFIG_X86_64 |
1da177e4 LT |
620 | amd_init_mtrr(); |
621 | cyrix_init_mtrr(); | |
622 | centaur_init_mtrr(); | |
475850c8 | 623 | #endif |
1da177e4 LT |
624 | } |
625 | ||
3b520b23 SL |
626 | /* The suspend/resume methods are only for CPU without MTRR. CPU using generic |
627 | * MTRR driver doesn't require this | |
628 | */ | |
1da177e4 LT |
629 | struct mtrr_value { |
630 | mtrr_type ltype; | |
631 | unsigned long lbase; | |
365bff80 | 632 | unsigned long lsize; |
1da177e4 LT |
633 | }; |
634 | ||
f0348c43 | 635 | static struct mtrr_value mtrr_value[MTRR_MAX_VAR_RANGES]; |
1da177e4 | 636 | |
f3c6ea1b | 637 | static int mtrr_save(void) |
1da177e4 LT |
638 | { |
639 | int i; | |
1da177e4 LT |
640 | |
641 | for (i = 0; i < num_var_ranges; i++) { | |
dbd51be0 JSR |
642 | mtrr_if->get(i, &mtrr_value[i].lbase, |
643 | &mtrr_value[i].lsize, | |
644 | &mtrr_value[i].ltype); | |
1da177e4 LT |
645 | } |
646 | return 0; | |
647 | } | |
648 | ||
f3c6ea1b | 649 | static void mtrr_restore(void) |
1da177e4 LT |
650 | { |
651 | int i; | |
652 | ||
653 | for (i = 0; i < num_var_ranges; i++) { | |
dbd51be0 JSR |
654 | if (mtrr_value[i].lsize) { |
655 | set_mtrr(i, mtrr_value[i].lbase, | |
656 | mtrr_value[i].lsize, | |
657 | mtrr_value[i].ltype); | |
658 | } | |
1da177e4 | 659 | } |
1da177e4 LT |
660 | } |
661 | ||
662 | ||
663 | ||
f3c6ea1b | 664 | static struct syscore_ops mtrr_syscore_ops = { |
1da177e4 LT |
665 | .suspend = mtrr_save, |
666 | .resume = mtrr_restore, | |
667 | }; | |
668 | ||
0d890355 | 669 | int __initdata changed_by_mtrr_cleanup; |
1da177e4 | 670 | |
d5c78673 | 671 | #define SIZE_OR_MASK_BITS(n) (~((1ULL << ((n) - PAGE_SHIFT)) - 1)) |
1da177e4 | 672 | /** |
3b520b23 | 673 | * mtrr_bp_init - initialize mtrrs on the boot CPU |
1da177e4 | 674 | * |
dbd51be0 | 675 | * This needs to be called early; before any of the other CPUs are |
1da177e4 | 676 | * initialized (i.e. before smp_init()). |
dbd51be0 | 677 | * |
1da177e4 | 678 | */ |
9ef231a4 | 679 | void __init mtrr_bp_init(void) |
1da177e4 | 680 | { |
95ffa243 | 681 | u32 phys_addr; |
dbd51be0 | 682 | |
1da177e4 LT |
683 | init_ifs(); |
684 | ||
95ffa243 YL |
685 | phys_addr = 32; |
686 | ||
1da177e4 LT |
687 | if (cpu_has_mtrr) { |
688 | mtrr_if = &generic_mtrr_ops; | |
d5c78673 | 689 | size_or_mask = SIZE_OR_MASK_BITS(36); |
1da177e4 | 690 | size_and_mask = 0x00f00000; |
95ffa243 | 691 | phys_addr = 36; |
1f2c958a | 692 | |
dbd51be0 JSR |
693 | /* |
694 | * This is an AMD specific MSR, but we assume(hope?) that | |
4319eb4f | 695 | * Intel will implement it too when they extend the address |
dbd51be0 JSR |
696 | * bus of the Xeon. |
697 | */ | |
1f2c958a | 698 | if (cpuid_eax(0x80000000) >= 0x80000008) { |
1f2c958a | 699 | phys_addr = cpuid_eax(0x80000008) & 0xff; |
af9c142d SL |
700 | /* CPUID workaround for Intel 0F33/0F34 CPU */ |
701 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
702 | boot_cpu_data.x86 == 0xF && | |
703 | boot_cpu_data.x86_model == 0x3 && | |
704 | (boot_cpu_data.x86_mask == 0x3 || | |
705 | boot_cpu_data.x86_mask == 0x4)) | |
706 | phys_addr = 36; | |
707 | ||
d5c78673 | 708 | size_or_mask = SIZE_OR_MASK_BITS(phys_addr); |
6c5806ca | 709 | size_and_mask = ~size_or_mask & 0xfffff00000ULL; |
1f2c958a AK |
710 | } else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR && |
711 | boot_cpu_data.x86 == 6) { | |
dbd51be0 JSR |
712 | /* |
713 | * VIA C* family have Intel style MTRRs, | |
714 | * but don't support PAE | |
715 | */ | |
d5c78673 | 716 | size_or_mask = SIZE_OR_MASK_BITS(32); |
1f2c958a | 717 | size_and_mask = 0; |
95ffa243 | 718 | phys_addr = 32; |
1da177e4 LT |
719 | } |
720 | } else { | |
721 | switch (boot_cpu_data.x86_vendor) { | |
722 | case X86_VENDOR_AMD: | |
9298b815 | 723 | if (cpu_feature_enabled(X86_FEATURE_K6_MTRR)) { |
1da177e4 LT |
724 | /* Pre-Athlon (K6) AMD CPU MTRRs */ |
725 | mtrr_if = mtrr_ops[X86_VENDOR_AMD]; | |
d5c78673 | 726 | size_or_mask = SIZE_OR_MASK_BITS(32); |
1da177e4 LT |
727 | size_and_mask = 0; |
728 | } | |
729 | break; | |
730 | case X86_VENDOR_CENTAUR: | |
9298b815 | 731 | if (cpu_feature_enabled(X86_FEATURE_CENTAUR_MCR)) { |
1da177e4 | 732 | mtrr_if = mtrr_ops[X86_VENDOR_CENTAUR]; |
d5c78673 | 733 | size_or_mask = SIZE_OR_MASK_BITS(32); |
1da177e4 LT |
734 | size_and_mask = 0; |
735 | } | |
736 | break; | |
737 | case X86_VENDOR_CYRIX: | |
9298b815 | 738 | if (cpu_feature_enabled(X86_FEATURE_CYRIX_ARR)) { |
1da177e4 | 739 | mtrr_if = mtrr_ops[X86_VENDOR_CYRIX]; |
d5c78673 | 740 | size_or_mask = SIZE_OR_MASK_BITS(32); |
1da177e4 LT |
741 | size_and_mask = 0; |
742 | } | |
743 | break; | |
744 | default: | |
745 | break; | |
746 | } | |
747 | } | |
1da177e4 LT |
748 | |
749 | if (mtrr_if) { | |
f9626104 | 750 | __mtrr_enabled = true; |
1da177e4 LT |
751 | set_num_var_ranges(); |
752 | init_table(); | |
95ffa243 | 753 | if (use_intel()) { |
f9626104 LR |
754 | /* BIOS may override */ |
755 | __mtrr_enabled = get_mtrr_state(); | |
95ffa243 | 756 | |
12031a62 YL |
757 | if (mtrr_cleanup(phys_addr)) { |
758 | changed_by_mtrr_cleanup = 1; | |
95ffa243 | 759 | mtrr_if->set_all(); |
12031a62 | 760 | } |
95ffa243 | 761 | } |
1da177e4 | 762 | } |
f9626104 LR |
763 | |
764 | if (!mtrr_enabled()) | |
765 | pr_info("MTRR: Disabled\n"); | |
1da177e4 LT |
766 | } |
767 | ||
3b520b23 SL |
768 | void mtrr_ap_init(void) |
769 | { | |
f9626104 LR |
770 | if (!mtrr_enabled()) |
771 | return; | |
772 | ||
d0af9eed | 773 | if (!use_intel() || mtrr_aps_delayed_init) |
3b520b23 SL |
774 | return; |
775 | /* | |
dbd51be0 JSR |
776 | * Ideally we should hold mtrr_mutex here to avoid mtrr entries |
777 | * changed, but this routine will be called in cpu boot time, | |
778 | * holding the lock breaks it. | |
779 | * | |
780 | * This routine is called in two cases: | |
781 | * | |
782 | * 1. very earily time of software resume, when there absolutely | |
783 | * isn't mtrr entry changes; | |
784 | * | |
785 | * 2. cpu hotadd time. We let mtrr_add/del_page hold cpuhotplug | |
786 | * lock to prevent mtrr entry changes | |
3b520b23 | 787 | */ |
192d8857 | 788 | set_mtrr_from_inactive_cpu(~0U, 0, 0, 0); |
3b520b23 SL |
789 | } |
790 | ||
2b1f6278 | 791 | /** |
30242aa6 | 792 | * Save current fixed-range MTRR state of the first cpu in cpu_online_mask. |
2b1f6278 BK |
793 | */ |
794 | void mtrr_save_state(void) | |
795 | { | |
30242aa6 FY |
796 | int first_cpu; |
797 | ||
f9626104 LR |
798 | if (!mtrr_enabled()) |
799 | return; | |
800 | ||
30242aa6 FY |
801 | get_online_cpus(); |
802 | first_cpu = cpumask_first(cpu_online_mask); | |
803 | smp_call_function_single(first_cpu, mtrr_save_fixed_ranges, NULL, 1); | |
804 | put_online_cpus(); | |
2b1f6278 BK |
805 | } |
806 | ||
d0af9eed SS |
807 | void set_mtrr_aps_delayed_init(void) |
808 | { | |
f9626104 LR |
809 | if (!mtrr_enabled()) |
810 | return; | |
d0af9eed SS |
811 | if (!use_intel()) |
812 | return; | |
813 | ||
5400743d | 814 | mtrr_aps_delayed_init = true; |
d0af9eed SS |
815 | } |
816 | ||
817 | /* | |
f7448548 | 818 | * Delayed MTRR initialization for all AP's |
d0af9eed SS |
819 | */ |
820 | void mtrr_aps_init(void) | |
821 | { | |
f9626104 | 822 | if (!use_intel() || !mtrr_enabled()) |
d0af9eed SS |
823 | return; |
824 | ||
f7448548 SS |
825 | /* |
826 | * Check if someone has requested the delay of AP MTRR initialization, | |
827 | * by doing set_mtrr_aps_delayed_init(), prior to this point. If not, | |
828 | * then we are done. | |
829 | */ | |
830 | if (!mtrr_aps_delayed_init) | |
831 | return; | |
832 | ||
d0af9eed | 833 | set_mtrr(~0U, 0, 0, 0); |
5400743d | 834 | mtrr_aps_delayed_init = false; |
d0af9eed SS |
835 | } |
836 | ||
837 | void mtrr_bp_restore(void) | |
838 | { | |
f9626104 | 839 | if (!use_intel() || !mtrr_enabled()) |
d0af9eed SS |
840 | return; |
841 | ||
842 | mtrr_if->set_all(); | |
843 | } | |
844 | ||
3b520b23 SL |
845 | static int __init mtrr_init_finialize(void) |
846 | { | |
f9626104 | 847 | if (!mtrr_enabled()) |
3b520b23 | 848 | return 0; |
dbd51be0 | 849 | |
95ffa243 | 850 | if (use_intel()) { |
12031a62 | 851 | if (!changed_by_mtrr_cleanup) |
95ffa243 | 852 | mtrr_state_warn(); |
dbd51be0 | 853 | return 0; |
3b520b23 | 854 | } |
dbd51be0 JSR |
855 | |
856 | /* | |
857 | * The CPU has no MTRR and seems to not support SMP. They have | |
858 | * specific drivers, we use a tricky method to support | |
859 | * suspend/resume for them. | |
860 | * | |
861 | * TBD: is there any system with such CPU which supports | |
862 | * suspend/resume? If no, we should remove the code. | |
863 | */ | |
f3c6ea1b | 864 | register_syscore_ops(&mtrr_syscore_ops); |
dbd51be0 | 865 | |
3b520b23 SL |
866 | return 0; |
867 | } | |
868 | subsys_initcall(mtrr_init_finialize); |