]>
Commit | Line | Data |
---|---|---|
241771ef IM |
1 | /* |
2 | * Performance counter x86 architecture code | |
3 | * | |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
241771ef IM |
9 | * |
10 | * For licencing details see kernel-base/COPYING | |
11 | */ | |
12 | ||
13 | #include <linux/perf_counter.h> | |
14 | #include <linux/capability.h> | |
15 | #include <linux/notifier.h> | |
16 | #include <linux/hardirq.h> | |
17 | #include <linux/kprobes.h> | |
4ac13294 | 18 | #include <linux/module.h> |
241771ef IM |
19 | #include <linux/kdebug.h> |
20 | #include <linux/sched.h> | |
d7d59fb3 | 21 | #include <linux/uaccess.h> |
74193ef0 | 22 | #include <linux/highmem.h> |
241771ef | 23 | |
241771ef | 24 | #include <asm/apic.h> |
d7d59fb3 | 25 | #include <asm/stacktrace.h> |
4e935e47 | 26 | #include <asm/nmi.h> |
241771ef | 27 | |
862a1a5f | 28 | static u64 perf_counter_mask __read_mostly; |
703e937c | 29 | |
241771ef | 30 | struct cpu_hw_counters { |
862a1a5f | 31 | struct perf_counter *counters[X86_PMC_IDX_MAX]; |
43f6201a RR |
32 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
33 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
4b39fd96 | 34 | unsigned long interrupts; |
b0f3f28e | 35 | int enabled; |
241771ef IM |
36 | }; |
37 | ||
38 | /* | |
5f4ec28f | 39 | * struct x86_pmu - generic x86 pmu |
241771ef | 40 | */ |
5f4ec28f | 41 | struct x86_pmu { |
faa28ae0 RR |
42 | const char *name; |
43 | int version; | |
a3288106 | 44 | int (*handle_irq)(struct pt_regs *); |
9e35ad38 PZ |
45 | void (*disable_all)(void); |
46 | void (*enable_all)(void); | |
7c90cc45 | 47 | void (*enable)(struct hw_perf_counter *, int); |
d4369891 | 48 | void (*disable)(struct hw_perf_counter *, int); |
169e41eb JSR |
49 | unsigned eventsel; |
50 | unsigned perfctr; | |
b0f3f28e PZ |
51 | u64 (*event_map)(int); |
52 | u64 (*raw_event)(u64); | |
169e41eb | 53 | int max_events; |
0933e5c6 RR |
54 | int num_counters; |
55 | int num_counters_fixed; | |
56 | int counter_bits; | |
57 | u64 counter_mask; | |
c619b8ff | 58 | u64 max_period; |
9e35ad38 | 59 | u64 intel_ctrl; |
b56a3802 JSR |
60 | }; |
61 | ||
4a06bd85 | 62 | static struct x86_pmu x86_pmu __read_mostly; |
b56a3802 | 63 | |
b0f3f28e PZ |
64 | static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = { |
65 | .enabled = 1, | |
66 | }; | |
241771ef | 67 | |
11d1578f VW |
68 | /* |
69 | * Not sure about some of these | |
70 | */ | |
71 | static const u64 p6_perfmon_event_map[] = | |
72 | { | |
73 | [PERF_COUNT_HW_CPU_CYCLES] = 0x0079, | |
74 | [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, | |
75 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0000, | |
76 | [PERF_COUNT_HW_CACHE_MISSES] = 0x0000, | |
77 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, | |
78 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, | |
79 | [PERF_COUNT_HW_BUS_CYCLES] = 0x0062, | |
80 | }; | |
81 | ||
82 | static u64 p6_pmu_event_map(int event) | |
83 | { | |
84 | return p6_perfmon_event_map[event]; | |
85 | } | |
86 | ||
9c74fb50 PZ |
87 | /* |
88 | * Counter setting that is specified not to count anything. | |
89 | * We use this to effectively disable a counter. | |
90 | * | |
91 | * L2_RQSTS with 0 MESI unit mask. | |
92 | */ | |
93 | #define P6_NOP_COUNTER 0x0000002EULL | |
94 | ||
11d1578f VW |
95 | static u64 p6_pmu_raw_event(u64 event) |
96 | { | |
97 | #define P6_EVNTSEL_EVENT_MASK 0x000000FFULL | |
98 | #define P6_EVNTSEL_UNIT_MASK 0x0000FF00ULL | |
99 | #define P6_EVNTSEL_EDGE_MASK 0x00040000ULL | |
100 | #define P6_EVNTSEL_INV_MASK 0x00800000ULL | |
101 | #define P6_EVNTSEL_COUNTER_MASK 0xFF000000ULL | |
102 | ||
103 | #define P6_EVNTSEL_MASK \ | |
104 | (P6_EVNTSEL_EVENT_MASK | \ | |
105 | P6_EVNTSEL_UNIT_MASK | \ | |
106 | P6_EVNTSEL_EDGE_MASK | \ | |
107 | P6_EVNTSEL_INV_MASK | \ | |
108 | P6_EVNTSEL_COUNTER_MASK) | |
109 | ||
110 | return event & P6_EVNTSEL_MASK; | |
111 | } | |
112 | ||
113 | ||
b56a3802 JSR |
114 | /* |
115 | * Intel PerfMon v3. Used on Core2 and later. | |
116 | */ | |
b0f3f28e | 117 | static const u64 intel_perfmon_event_map[] = |
241771ef | 118 | { |
f4dbfa8f PZ |
119 | [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, |
120 | [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, | |
121 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, | |
122 | [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, | |
123 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, | |
124 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, | |
125 | [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, | |
241771ef IM |
126 | }; |
127 | ||
5f4ec28f | 128 | static u64 intel_pmu_event_map(int event) |
b56a3802 JSR |
129 | { |
130 | return intel_perfmon_event_map[event]; | |
131 | } | |
241771ef | 132 | |
8326f44d IM |
133 | /* |
134 | * Generalized hw caching related event table, filled | |
135 | * in on a per model basis. A value of 0 means | |
136 | * 'not supported', -1 means 'event makes no sense on | |
137 | * this CPU', any other value means the raw event | |
138 | * ID. | |
139 | */ | |
140 | ||
141 | #define C(x) PERF_COUNT_HW_CACHE_##x | |
142 | ||
143 | static u64 __read_mostly hw_cache_event_ids | |
144 | [PERF_COUNT_HW_CACHE_MAX] | |
145 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
146 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
147 | ||
148 | static const u64 nehalem_hw_cache_event_ids | |
149 | [PERF_COUNT_HW_CACHE_MAX] | |
150 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
151 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
152 | { | |
153 | [ C(L1D) ] = { | |
154 | [ C(OP_READ) ] = { | |
155 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ | |
156 | [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ | |
157 | }, | |
158 | [ C(OP_WRITE) ] = { | |
159 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ | |
160 | [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ | |
161 | }, | |
162 | [ C(OP_PREFETCH) ] = { | |
163 | [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ | |
164 | [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ | |
165 | }, | |
166 | }, | |
167 | [ C(L1I ) ] = { | |
168 | [ C(OP_READ) ] = { | |
fecc8ac8 | 169 | [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ |
8326f44d IM |
170 | [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ |
171 | }, | |
172 | [ C(OP_WRITE) ] = { | |
173 | [ C(RESULT_ACCESS) ] = -1, | |
174 | [ C(RESULT_MISS) ] = -1, | |
175 | }, | |
176 | [ C(OP_PREFETCH) ] = { | |
177 | [ C(RESULT_ACCESS) ] = 0x0, | |
178 | [ C(RESULT_MISS) ] = 0x0, | |
179 | }, | |
180 | }, | |
8be6e8f3 | 181 | [ C(LL ) ] = { |
8326f44d IM |
182 | [ C(OP_READ) ] = { |
183 | [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS */ | |
184 | [ C(RESULT_MISS) ] = 0x0224, /* L2_RQSTS.LD_MISS */ | |
185 | }, | |
186 | [ C(OP_WRITE) ] = { | |
187 | [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS */ | |
188 | [ C(RESULT_MISS) ] = 0x0824, /* L2_RQSTS.RFO_MISS */ | |
189 | }, | |
190 | [ C(OP_PREFETCH) ] = { | |
8be6e8f3 PZ |
191 | [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference */ |
192 | [ C(RESULT_MISS) ] = 0x412e, /* LLC Misses */ | |
8326f44d IM |
193 | }, |
194 | }, | |
195 | [ C(DTLB) ] = { | |
196 | [ C(OP_READ) ] = { | |
197 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ | |
198 | [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ | |
199 | }, | |
200 | [ C(OP_WRITE) ] = { | |
201 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ | |
202 | [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ | |
203 | }, | |
204 | [ C(OP_PREFETCH) ] = { | |
205 | [ C(RESULT_ACCESS) ] = 0x0, | |
206 | [ C(RESULT_MISS) ] = 0x0, | |
207 | }, | |
208 | }, | |
209 | [ C(ITLB) ] = { | |
210 | [ C(OP_READ) ] = { | |
211 | [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ | |
fecc8ac8 | 212 | [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ |
8326f44d IM |
213 | }, |
214 | [ C(OP_WRITE) ] = { | |
215 | [ C(RESULT_ACCESS) ] = -1, | |
216 | [ C(RESULT_MISS) ] = -1, | |
217 | }, | |
218 | [ C(OP_PREFETCH) ] = { | |
219 | [ C(RESULT_ACCESS) ] = -1, | |
220 | [ C(RESULT_MISS) ] = -1, | |
221 | }, | |
222 | }, | |
223 | [ C(BPU ) ] = { | |
224 | [ C(OP_READ) ] = { | |
225 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ | |
226 | [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ | |
227 | }, | |
228 | [ C(OP_WRITE) ] = { | |
229 | [ C(RESULT_ACCESS) ] = -1, | |
230 | [ C(RESULT_MISS) ] = -1, | |
231 | }, | |
232 | [ C(OP_PREFETCH) ] = { | |
233 | [ C(RESULT_ACCESS) ] = -1, | |
234 | [ C(RESULT_MISS) ] = -1, | |
235 | }, | |
236 | }, | |
237 | }; | |
238 | ||
239 | static const u64 core2_hw_cache_event_ids | |
240 | [PERF_COUNT_HW_CACHE_MAX] | |
241 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
242 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
243 | { | |
0312af84 TG |
244 | [ C(L1D) ] = { |
245 | [ C(OP_READ) ] = { | |
246 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ | |
247 | [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ | |
248 | }, | |
249 | [ C(OP_WRITE) ] = { | |
250 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ | |
251 | [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ | |
252 | }, | |
253 | [ C(OP_PREFETCH) ] = { | |
254 | [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ | |
255 | [ C(RESULT_MISS) ] = 0, | |
256 | }, | |
257 | }, | |
258 | [ C(L1I ) ] = { | |
259 | [ C(OP_READ) ] = { | |
260 | [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ | |
261 | [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ | |
262 | }, | |
263 | [ C(OP_WRITE) ] = { | |
264 | [ C(RESULT_ACCESS) ] = -1, | |
265 | [ C(RESULT_MISS) ] = -1, | |
266 | }, | |
267 | [ C(OP_PREFETCH) ] = { | |
268 | [ C(RESULT_ACCESS) ] = 0, | |
269 | [ C(RESULT_MISS) ] = 0, | |
270 | }, | |
271 | }, | |
8be6e8f3 | 272 | [ C(LL ) ] = { |
0312af84 TG |
273 | [ C(OP_READ) ] = { |
274 | [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ | |
275 | [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ | |
276 | }, | |
277 | [ C(OP_WRITE) ] = { | |
278 | [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ | |
279 | [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ | |
280 | }, | |
281 | [ C(OP_PREFETCH) ] = { | |
282 | [ C(RESULT_ACCESS) ] = 0, | |
283 | [ C(RESULT_MISS) ] = 0, | |
284 | }, | |
285 | }, | |
286 | [ C(DTLB) ] = { | |
287 | [ C(OP_READ) ] = { | |
288 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ | |
289 | [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ | |
290 | }, | |
291 | [ C(OP_WRITE) ] = { | |
292 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ | |
293 | [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ | |
294 | }, | |
295 | [ C(OP_PREFETCH) ] = { | |
296 | [ C(RESULT_ACCESS) ] = 0, | |
297 | [ C(RESULT_MISS) ] = 0, | |
298 | }, | |
299 | }, | |
300 | [ C(ITLB) ] = { | |
301 | [ C(OP_READ) ] = { | |
302 | [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ | |
303 | [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ | |
304 | }, | |
305 | [ C(OP_WRITE) ] = { | |
306 | [ C(RESULT_ACCESS) ] = -1, | |
307 | [ C(RESULT_MISS) ] = -1, | |
308 | }, | |
309 | [ C(OP_PREFETCH) ] = { | |
310 | [ C(RESULT_ACCESS) ] = -1, | |
311 | [ C(RESULT_MISS) ] = -1, | |
312 | }, | |
313 | }, | |
314 | [ C(BPU ) ] = { | |
315 | [ C(OP_READ) ] = { | |
316 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ | |
317 | [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ | |
318 | }, | |
319 | [ C(OP_WRITE) ] = { | |
320 | [ C(RESULT_ACCESS) ] = -1, | |
321 | [ C(RESULT_MISS) ] = -1, | |
322 | }, | |
323 | [ C(OP_PREFETCH) ] = { | |
324 | [ C(RESULT_ACCESS) ] = -1, | |
325 | [ C(RESULT_MISS) ] = -1, | |
326 | }, | |
327 | }, | |
8326f44d IM |
328 | }; |
329 | ||
330 | static const u64 atom_hw_cache_event_ids | |
331 | [PERF_COUNT_HW_CACHE_MAX] | |
332 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
333 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
334 | { | |
ad689220 TG |
335 | [ C(L1D) ] = { |
336 | [ C(OP_READ) ] = { | |
337 | [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ | |
338 | [ C(RESULT_MISS) ] = 0, | |
339 | }, | |
340 | [ C(OP_WRITE) ] = { | |
fecc8ac8 | 341 | [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ |
ad689220 TG |
342 | [ C(RESULT_MISS) ] = 0, |
343 | }, | |
344 | [ C(OP_PREFETCH) ] = { | |
345 | [ C(RESULT_ACCESS) ] = 0x0, | |
346 | [ C(RESULT_MISS) ] = 0, | |
347 | }, | |
348 | }, | |
349 | [ C(L1I ) ] = { | |
350 | [ C(OP_READ) ] = { | |
fecc8ac8 YW |
351 | [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ |
352 | [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ | |
ad689220 TG |
353 | }, |
354 | [ C(OP_WRITE) ] = { | |
355 | [ C(RESULT_ACCESS) ] = -1, | |
356 | [ C(RESULT_MISS) ] = -1, | |
357 | }, | |
358 | [ C(OP_PREFETCH) ] = { | |
359 | [ C(RESULT_ACCESS) ] = 0, | |
360 | [ C(RESULT_MISS) ] = 0, | |
361 | }, | |
362 | }, | |
8be6e8f3 | 363 | [ C(LL ) ] = { |
ad689220 TG |
364 | [ C(OP_READ) ] = { |
365 | [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ | |
366 | [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ | |
367 | }, | |
368 | [ C(OP_WRITE) ] = { | |
369 | [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ | |
370 | [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ | |
371 | }, | |
372 | [ C(OP_PREFETCH) ] = { | |
373 | [ C(RESULT_ACCESS) ] = 0, | |
374 | [ C(RESULT_MISS) ] = 0, | |
375 | }, | |
376 | }, | |
377 | [ C(DTLB) ] = { | |
378 | [ C(OP_READ) ] = { | |
fecc8ac8 | 379 | [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ |
ad689220 TG |
380 | [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ |
381 | }, | |
382 | [ C(OP_WRITE) ] = { | |
fecc8ac8 | 383 | [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ |
ad689220 TG |
384 | [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ |
385 | }, | |
386 | [ C(OP_PREFETCH) ] = { | |
387 | [ C(RESULT_ACCESS) ] = 0, | |
388 | [ C(RESULT_MISS) ] = 0, | |
389 | }, | |
390 | }, | |
391 | [ C(ITLB) ] = { | |
392 | [ C(OP_READ) ] = { | |
393 | [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ | |
394 | [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ | |
395 | }, | |
396 | [ C(OP_WRITE) ] = { | |
397 | [ C(RESULT_ACCESS) ] = -1, | |
398 | [ C(RESULT_MISS) ] = -1, | |
399 | }, | |
400 | [ C(OP_PREFETCH) ] = { | |
401 | [ C(RESULT_ACCESS) ] = -1, | |
402 | [ C(RESULT_MISS) ] = -1, | |
403 | }, | |
404 | }, | |
405 | [ C(BPU ) ] = { | |
406 | [ C(OP_READ) ] = { | |
407 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ | |
408 | [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ | |
409 | }, | |
410 | [ C(OP_WRITE) ] = { | |
411 | [ C(RESULT_ACCESS) ] = -1, | |
412 | [ C(RESULT_MISS) ] = -1, | |
413 | }, | |
414 | [ C(OP_PREFETCH) ] = { | |
415 | [ C(RESULT_ACCESS) ] = -1, | |
416 | [ C(RESULT_MISS) ] = -1, | |
417 | }, | |
418 | }, | |
8326f44d IM |
419 | }; |
420 | ||
5f4ec28f | 421 | static u64 intel_pmu_raw_event(u64 event) |
b0f3f28e | 422 | { |
82bae4f8 PZ |
423 | #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL |
424 | #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL | |
ff99be57 PZ |
425 | #define CORE_EVNTSEL_EDGE_MASK 0x00040000ULL |
426 | #define CORE_EVNTSEL_INV_MASK 0x00800000ULL | |
82bae4f8 | 427 | #define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL |
b0f3f28e | 428 | |
128f048f | 429 | #define CORE_EVNTSEL_MASK \ |
b0f3f28e PZ |
430 | (CORE_EVNTSEL_EVENT_MASK | \ |
431 | CORE_EVNTSEL_UNIT_MASK | \ | |
ff99be57 PZ |
432 | CORE_EVNTSEL_EDGE_MASK | \ |
433 | CORE_EVNTSEL_INV_MASK | \ | |
b0f3f28e PZ |
434 | CORE_EVNTSEL_COUNTER_MASK) |
435 | ||
436 | return event & CORE_EVNTSEL_MASK; | |
437 | } | |
438 | ||
f4db43a3 | 439 | static const u64 amd_hw_cache_event_ids |
f86748e9 TG |
440 | [PERF_COUNT_HW_CACHE_MAX] |
441 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
442 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
443 | { | |
444 | [ C(L1D) ] = { | |
445 | [ C(OP_READ) ] = { | |
f4db43a3 JSR |
446 | [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */ |
447 | [ C(RESULT_MISS) ] = 0x0041, /* Data Cache Misses */ | |
f86748e9 TG |
448 | }, |
449 | [ C(OP_WRITE) ] = { | |
d9f2a5ec | 450 | [ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */ |
f86748e9 TG |
451 | [ C(RESULT_MISS) ] = 0, |
452 | }, | |
453 | [ C(OP_PREFETCH) ] = { | |
f4db43a3 JSR |
454 | [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */ |
455 | [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */ | |
f86748e9 TG |
456 | }, |
457 | }, | |
458 | [ C(L1I ) ] = { | |
459 | [ C(OP_READ) ] = { | |
460 | [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches */ | |
461 | [ C(RESULT_MISS) ] = 0x0081, /* Instruction cache misses */ | |
462 | }, | |
463 | [ C(OP_WRITE) ] = { | |
464 | [ C(RESULT_ACCESS) ] = -1, | |
465 | [ C(RESULT_MISS) ] = -1, | |
466 | }, | |
467 | [ C(OP_PREFETCH) ] = { | |
f4db43a3 | 468 | [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */ |
f86748e9 TG |
469 | [ C(RESULT_MISS) ] = 0, |
470 | }, | |
471 | }, | |
8be6e8f3 | 472 | [ C(LL ) ] = { |
f86748e9 | 473 | [ C(OP_READ) ] = { |
f4db43a3 JSR |
474 | [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */ |
475 | [ C(RESULT_MISS) ] = 0x037E, /* L2 Cache Misses : IC+DC */ | |
f86748e9 TG |
476 | }, |
477 | [ C(OP_WRITE) ] = { | |
f4db43a3 | 478 | [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback */ |
f86748e9 TG |
479 | [ C(RESULT_MISS) ] = 0, |
480 | }, | |
481 | [ C(OP_PREFETCH) ] = { | |
482 | [ C(RESULT_ACCESS) ] = 0, | |
483 | [ C(RESULT_MISS) ] = 0, | |
484 | }, | |
485 | }, | |
486 | [ C(DTLB) ] = { | |
487 | [ C(OP_READ) ] = { | |
f4db43a3 JSR |
488 | [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */ |
489 | [ C(RESULT_MISS) ] = 0x0046, /* L1 DTLB and L2 DLTB Miss */ | |
f86748e9 TG |
490 | }, |
491 | [ C(OP_WRITE) ] = { | |
492 | [ C(RESULT_ACCESS) ] = 0, | |
493 | [ C(RESULT_MISS) ] = 0, | |
494 | }, | |
495 | [ C(OP_PREFETCH) ] = { | |
496 | [ C(RESULT_ACCESS) ] = 0, | |
497 | [ C(RESULT_MISS) ] = 0, | |
498 | }, | |
499 | }, | |
500 | [ C(ITLB) ] = { | |
501 | [ C(OP_READ) ] = { | |
502 | [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes */ | |
503 | [ C(RESULT_MISS) ] = 0x0085, /* Instr. fetch ITLB misses */ | |
504 | }, | |
505 | [ C(OP_WRITE) ] = { | |
506 | [ C(RESULT_ACCESS) ] = -1, | |
507 | [ C(RESULT_MISS) ] = -1, | |
508 | }, | |
509 | [ C(OP_PREFETCH) ] = { | |
510 | [ C(RESULT_ACCESS) ] = -1, | |
511 | [ C(RESULT_MISS) ] = -1, | |
512 | }, | |
513 | }, | |
514 | [ C(BPU ) ] = { | |
515 | [ C(OP_READ) ] = { | |
516 | [ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr. */ | |
517 | [ C(RESULT_MISS) ] = 0x00c3, /* Retired Mispredicted BI */ | |
518 | }, | |
519 | [ C(OP_WRITE) ] = { | |
520 | [ C(RESULT_ACCESS) ] = -1, | |
521 | [ C(RESULT_MISS) ] = -1, | |
522 | }, | |
523 | [ C(OP_PREFETCH) ] = { | |
524 | [ C(RESULT_ACCESS) ] = -1, | |
525 | [ C(RESULT_MISS) ] = -1, | |
526 | }, | |
527 | }, | |
528 | }; | |
529 | ||
f87ad35d JSR |
530 | /* |
531 | * AMD Performance Monitor K7 and later. | |
532 | */ | |
b0f3f28e | 533 | static const u64 amd_perfmon_event_map[] = |
f87ad35d | 534 | { |
f4dbfa8f PZ |
535 | [PERF_COUNT_HW_CPU_CYCLES] = 0x0076, |
536 | [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, | |
537 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0080, | |
538 | [PERF_COUNT_HW_CACHE_MISSES] = 0x0081, | |
539 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, | |
540 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, | |
f87ad35d JSR |
541 | }; |
542 | ||
5f4ec28f | 543 | static u64 amd_pmu_event_map(int event) |
f87ad35d JSR |
544 | { |
545 | return amd_perfmon_event_map[event]; | |
546 | } | |
547 | ||
5f4ec28f | 548 | static u64 amd_pmu_raw_event(u64 event) |
b0f3f28e | 549 | { |
82bae4f8 PZ |
550 | #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL |
551 | #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL | |
ff99be57 PZ |
552 | #define K7_EVNTSEL_EDGE_MASK 0x000040000ULL |
553 | #define K7_EVNTSEL_INV_MASK 0x000800000ULL | |
82bae4f8 | 554 | #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL |
b0f3f28e PZ |
555 | |
556 | #define K7_EVNTSEL_MASK \ | |
557 | (K7_EVNTSEL_EVENT_MASK | \ | |
558 | K7_EVNTSEL_UNIT_MASK | \ | |
ff99be57 PZ |
559 | K7_EVNTSEL_EDGE_MASK | \ |
560 | K7_EVNTSEL_INV_MASK | \ | |
b0f3f28e PZ |
561 | K7_EVNTSEL_COUNTER_MASK) |
562 | ||
563 | return event & K7_EVNTSEL_MASK; | |
564 | } | |
565 | ||
ee06094f IM |
566 | /* |
567 | * Propagate counter elapsed time into the generic counter. | |
568 | * Can only be executed on the CPU where the counter is active. | |
569 | * Returns the delta events processed. | |
570 | */ | |
4b7bfd0d | 571 | static u64 |
ee06094f IM |
572 | x86_perf_counter_update(struct perf_counter *counter, |
573 | struct hw_perf_counter *hwc, int idx) | |
574 | { | |
ec3232bd PZ |
575 | int shift = 64 - x86_pmu.counter_bits; |
576 | u64 prev_raw_count, new_raw_count; | |
577 | s64 delta; | |
ee06094f | 578 | |
ee06094f IM |
579 | /* |
580 | * Careful: an NMI might modify the previous counter value. | |
581 | * | |
582 | * Our tactic to handle this is to first atomically read and | |
583 | * exchange a new raw count - then add that new-prev delta | |
584 | * count to the generic counter atomically: | |
585 | */ | |
586 | again: | |
587 | prev_raw_count = atomic64_read(&hwc->prev_count); | |
588 | rdmsrl(hwc->counter_base + idx, new_raw_count); | |
589 | ||
590 | if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count, | |
591 | new_raw_count) != prev_raw_count) | |
592 | goto again; | |
593 | ||
594 | /* | |
595 | * Now we have the new raw value and have updated the prev | |
596 | * timestamp already. We can now calculate the elapsed delta | |
597 | * (counter-)time and add that to the generic counter. | |
598 | * | |
599 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 600 | * of the count. |
ee06094f | 601 | */ |
ec3232bd PZ |
602 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
603 | delta >>= shift; | |
ee06094f IM |
604 | |
605 | atomic64_add(delta, &counter->count); | |
606 | atomic64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
607 | |
608 | return new_raw_count; | |
ee06094f IM |
609 | } |
610 | ||
ba77813a | 611 | static atomic_t active_counters; |
4e935e47 PZ |
612 | static DEFINE_MUTEX(pmc_reserve_mutex); |
613 | ||
614 | static bool reserve_pmc_hardware(void) | |
615 | { | |
616 | int i; | |
617 | ||
618 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
619 | disable_lapic_nmi_watchdog(); | |
620 | ||
0933e5c6 | 621 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 | 622 | if (!reserve_perfctr_nmi(x86_pmu.perfctr + i)) |
4e935e47 PZ |
623 | goto perfctr_fail; |
624 | } | |
625 | ||
0933e5c6 | 626 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 | 627 | if (!reserve_evntsel_nmi(x86_pmu.eventsel + i)) |
4e935e47 PZ |
628 | goto eventsel_fail; |
629 | } | |
630 | ||
631 | return true; | |
632 | ||
633 | eventsel_fail: | |
634 | for (i--; i >= 0; i--) | |
4a06bd85 | 635 | release_evntsel_nmi(x86_pmu.eventsel + i); |
4e935e47 | 636 | |
0933e5c6 | 637 | i = x86_pmu.num_counters; |
4e935e47 PZ |
638 | |
639 | perfctr_fail: | |
640 | for (i--; i >= 0; i--) | |
4a06bd85 | 641 | release_perfctr_nmi(x86_pmu.perfctr + i); |
4e935e47 PZ |
642 | |
643 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
644 | enable_lapic_nmi_watchdog(); | |
645 | ||
646 | return false; | |
647 | } | |
648 | ||
649 | static void release_pmc_hardware(void) | |
650 | { | |
651 | int i; | |
652 | ||
0933e5c6 | 653 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 RR |
654 | release_perfctr_nmi(x86_pmu.perfctr + i); |
655 | release_evntsel_nmi(x86_pmu.eventsel + i); | |
4e935e47 PZ |
656 | } |
657 | ||
658 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
659 | enable_lapic_nmi_watchdog(); | |
660 | } | |
661 | ||
662 | static void hw_perf_counter_destroy(struct perf_counter *counter) | |
663 | { | |
ba77813a | 664 | if (atomic_dec_and_mutex_lock(&active_counters, &pmc_reserve_mutex)) { |
4e935e47 PZ |
665 | release_pmc_hardware(); |
666 | mutex_unlock(&pmc_reserve_mutex); | |
667 | } | |
668 | } | |
669 | ||
85cf9dba RR |
670 | static inline int x86_pmu_initialized(void) |
671 | { | |
672 | return x86_pmu.handle_irq != NULL; | |
673 | } | |
674 | ||
8326f44d IM |
675 | static inline int |
676 | set_ext_hw_attr(struct hw_perf_counter *hwc, struct perf_counter_attr *attr) | |
677 | { | |
678 | unsigned int cache_type, cache_op, cache_result; | |
679 | u64 config, val; | |
680 | ||
681 | config = attr->config; | |
682 | ||
683 | cache_type = (config >> 0) & 0xff; | |
684 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
685 | return -EINVAL; | |
686 | ||
687 | cache_op = (config >> 8) & 0xff; | |
688 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
689 | return -EINVAL; | |
690 | ||
691 | cache_result = (config >> 16) & 0xff; | |
692 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
693 | return -EINVAL; | |
694 | ||
695 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
696 | ||
697 | if (val == 0) | |
698 | return -ENOENT; | |
699 | ||
700 | if (val == -1) | |
701 | return -EINVAL; | |
702 | ||
703 | hwc->config |= val; | |
704 | ||
705 | return 0; | |
706 | } | |
707 | ||
241771ef | 708 | /* |
0d48696f | 709 | * Setup the hardware configuration for a given attr_type |
241771ef | 710 | */ |
621a01ea | 711 | static int __hw_perf_counter_init(struct perf_counter *counter) |
241771ef | 712 | { |
0d48696f | 713 | struct perf_counter_attr *attr = &counter->attr; |
241771ef | 714 | struct hw_perf_counter *hwc = &counter->hw; |
9c74fb50 | 715 | u64 config; |
4e935e47 | 716 | int err; |
241771ef | 717 | |
85cf9dba RR |
718 | if (!x86_pmu_initialized()) |
719 | return -ENODEV; | |
241771ef | 720 | |
4e935e47 | 721 | err = 0; |
ba77813a | 722 | if (!atomic_inc_not_zero(&active_counters)) { |
4e935e47 | 723 | mutex_lock(&pmc_reserve_mutex); |
ba77813a | 724 | if (atomic_read(&active_counters) == 0 && !reserve_pmc_hardware()) |
4e935e47 PZ |
725 | err = -EBUSY; |
726 | else | |
ba77813a | 727 | atomic_inc(&active_counters); |
4e935e47 PZ |
728 | mutex_unlock(&pmc_reserve_mutex); |
729 | } | |
730 | if (err) | |
731 | return err; | |
732 | ||
241771ef | 733 | /* |
0475f9ea | 734 | * Generate PMC IRQs: |
241771ef IM |
735 | * (keep 'enabled' bit clear for now) |
736 | */ | |
0475f9ea | 737 | hwc->config = ARCH_PERFMON_EVENTSEL_INT; |
241771ef IM |
738 | |
739 | /* | |
0475f9ea | 740 | * Count user and OS events unless requested not to. |
241771ef | 741 | */ |
0d48696f | 742 | if (!attr->exclude_user) |
0475f9ea | 743 | hwc->config |= ARCH_PERFMON_EVENTSEL_USR; |
0d48696f | 744 | if (!attr->exclude_kernel) |
241771ef | 745 | hwc->config |= ARCH_PERFMON_EVENTSEL_OS; |
0475f9ea | 746 | |
bd2b5b12 | 747 | if (!hwc->sample_period) { |
b23f3325 | 748 | hwc->sample_period = x86_pmu.max_period; |
9e350de3 | 749 | hwc->last_period = hwc->sample_period; |
bd2b5b12 PZ |
750 | atomic64_set(&hwc->period_left, hwc->sample_period); |
751 | } | |
d2517a49 | 752 | |
8326f44d | 753 | counter->destroy = hw_perf_counter_destroy; |
241771ef IM |
754 | |
755 | /* | |
dfa7c899 | 756 | * Raw event type provide the config in the event structure |
241771ef | 757 | */ |
a21ca2ca IM |
758 | if (attr->type == PERF_TYPE_RAW) { |
759 | hwc->config |= x86_pmu.raw_event(attr->config); | |
8326f44d | 760 | return 0; |
241771ef | 761 | } |
241771ef | 762 | |
8326f44d IM |
763 | if (attr->type == PERF_TYPE_HW_CACHE) |
764 | return set_ext_hw_attr(hwc, attr); | |
765 | ||
766 | if (attr->config >= x86_pmu.max_events) | |
767 | return -EINVAL; | |
9c74fb50 | 768 | |
8326f44d IM |
769 | /* |
770 | * The generic map: | |
771 | */ | |
9c74fb50 PZ |
772 | config = x86_pmu.event_map(attr->config); |
773 | ||
774 | if (config == 0) | |
775 | return -ENOENT; | |
776 | ||
777 | if (config == -1LL) | |
778 | return -EINVAL; | |
779 | ||
780 | hwc->config |= config; | |
4e935e47 | 781 | |
241771ef IM |
782 | return 0; |
783 | } | |
784 | ||
11d1578f VW |
785 | static void p6_pmu_disable_all(void) |
786 | { | |
787 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
9c74fb50 | 788 | u64 val; |
11d1578f VW |
789 | |
790 | if (!cpuc->enabled) | |
791 | return; | |
792 | ||
793 | cpuc->enabled = 0; | |
794 | barrier(); | |
795 | ||
796 | /* p6 only has one enable register */ | |
797 | rdmsrl(MSR_P6_EVNTSEL0, val); | |
798 | val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE; | |
799 | wrmsrl(MSR_P6_EVNTSEL0, val); | |
800 | } | |
801 | ||
9e35ad38 | 802 | static void intel_pmu_disable_all(void) |
4ac13294 | 803 | { |
862a1a5f | 804 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); |
241771ef | 805 | } |
b56a3802 | 806 | |
9e35ad38 | 807 | static void amd_pmu_disable_all(void) |
f87ad35d | 808 | { |
b0f3f28e | 809 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
9e35ad38 PZ |
810 | int idx; |
811 | ||
812 | if (!cpuc->enabled) | |
813 | return; | |
b0f3f28e | 814 | |
b0f3f28e | 815 | cpuc->enabled = 0; |
60b3df9c PZ |
816 | /* |
817 | * ensure we write the disable before we start disabling the | |
5f4ec28f RR |
818 | * counters proper, so that amd_pmu_enable_counter() does the |
819 | * right thing. | |
60b3df9c | 820 | */ |
b0f3f28e | 821 | barrier(); |
f87ad35d | 822 | |
0933e5c6 | 823 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
824 | u64 val; |
825 | ||
43f6201a | 826 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 827 | continue; |
f87ad35d | 828 | rdmsrl(MSR_K7_EVNTSEL0 + idx, val); |
4295ee62 RR |
829 | if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE)) |
830 | continue; | |
831 | val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE; | |
832 | wrmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
f87ad35d | 833 | } |
f87ad35d JSR |
834 | } |
835 | ||
9e35ad38 | 836 | void hw_perf_disable(void) |
b56a3802 | 837 | { |
85cf9dba | 838 | if (!x86_pmu_initialized()) |
9e35ad38 PZ |
839 | return; |
840 | return x86_pmu.disable_all(); | |
b56a3802 | 841 | } |
241771ef | 842 | |
11d1578f VW |
843 | static void p6_pmu_enable_all(void) |
844 | { | |
845 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
846 | unsigned long val; | |
847 | ||
848 | if (cpuc->enabled) | |
849 | return; | |
850 | ||
851 | cpuc->enabled = 1; | |
852 | barrier(); | |
853 | ||
854 | /* p6 only has one enable register */ | |
855 | rdmsrl(MSR_P6_EVNTSEL0, val); | |
856 | val |= ARCH_PERFMON_EVENTSEL0_ENABLE; | |
857 | wrmsrl(MSR_P6_EVNTSEL0, val); | |
858 | } | |
859 | ||
9e35ad38 | 860 | static void intel_pmu_enable_all(void) |
b56a3802 | 861 | { |
9e35ad38 | 862 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl); |
b56a3802 JSR |
863 | } |
864 | ||
9e35ad38 | 865 | static void amd_pmu_enable_all(void) |
f87ad35d | 866 | { |
b0f3f28e | 867 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
f87ad35d JSR |
868 | int idx; |
869 | ||
9e35ad38 | 870 | if (cpuc->enabled) |
b0f3f28e PZ |
871 | return; |
872 | ||
9e35ad38 PZ |
873 | cpuc->enabled = 1; |
874 | barrier(); | |
875 | ||
0933e5c6 | 876 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
984b838c | 877 | struct perf_counter *counter = cpuc->counters[idx]; |
4295ee62 | 878 | u64 val; |
b0f3f28e | 879 | |
43f6201a | 880 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 881 | continue; |
984b838c PZ |
882 | |
883 | val = counter->hw.config; | |
4295ee62 RR |
884 | val |= ARCH_PERFMON_EVENTSEL0_ENABLE; |
885 | wrmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
f87ad35d JSR |
886 | } |
887 | } | |
888 | ||
9e35ad38 | 889 | void hw_perf_enable(void) |
ee06094f | 890 | { |
85cf9dba | 891 | if (!x86_pmu_initialized()) |
2b9ff0db | 892 | return; |
9e35ad38 | 893 | x86_pmu.enable_all(); |
ee06094f | 894 | } |
ee06094f | 895 | |
19d84dab | 896 | static inline u64 intel_pmu_get_status(void) |
b0f3f28e PZ |
897 | { |
898 | u64 status; | |
899 | ||
b7f8859a | 900 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); |
b0f3f28e | 901 | |
b7f8859a | 902 | return status; |
b0f3f28e PZ |
903 | } |
904 | ||
dee5d906 | 905 | static inline void intel_pmu_ack_status(u64 ack) |
b0f3f28e PZ |
906 | { |
907 | wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); | |
908 | } | |
909 | ||
7c90cc45 | 910 | static inline void x86_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) |
b0f3f28e | 911 | { |
11d1578f | 912 | (void)checking_wrmsrl(hwc->config_base + idx, |
7c90cc45 | 913 | hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE); |
b0f3f28e PZ |
914 | } |
915 | ||
d4369891 | 916 | static inline void x86_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) |
b0f3f28e | 917 | { |
11d1578f | 918 | (void)checking_wrmsrl(hwc->config_base + idx, hwc->config); |
b0f3f28e PZ |
919 | } |
920 | ||
2f18d1e8 | 921 | static inline void |
d4369891 | 922 | intel_pmu_disable_fixed(struct hw_perf_counter *hwc, int __idx) |
2f18d1e8 IM |
923 | { |
924 | int idx = __idx - X86_PMC_IDX_FIXED; | |
925 | u64 ctrl_val, mask; | |
2f18d1e8 IM |
926 | |
927 | mask = 0xfULL << (idx * 4); | |
928 | ||
929 | rdmsrl(hwc->config_base, ctrl_val); | |
930 | ctrl_val &= ~mask; | |
11d1578f VW |
931 | (void)checking_wrmsrl(hwc->config_base, ctrl_val); |
932 | } | |
933 | ||
934 | static inline void | |
935 | p6_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) | |
936 | { | |
937 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
9c74fb50 | 938 | u64 val = P6_NOP_COUNTER; |
11d1578f | 939 | |
9c74fb50 PZ |
940 | if (cpuc->enabled) |
941 | val |= ARCH_PERFMON_EVENTSEL0_ENABLE; | |
11d1578f VW |
942 | |
943 | (void)checking_wrmsrl(hwc->config_base + idx, val); | |
2f18d1e8 IM |
944 | } |
945 | ||
7e2ae347 | 946 | static inline void |
d4369891 | 947 | intel_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) |
7e2ae347 | 948 | { |
d4369891 RR |
949 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { |
950 | intel_pmu_disable_fixed(hwc, idx); | |
951 | return; | |
952 | } | |
953 | ||
954 | x86_pmu_disable_counter(hwc, idx); | |
955 | } | |
956 | ||
957 | static inline void | |
958 | amd_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) | |
959 | { | |
960 | x86_pmu_disable_counter(hwc, idx); | |
7e2ae347 IM |
961 | } |
962 | ||
2f18d1e8 | 963 | static DEFINE_PER_CPU(u64, prev_left[X86_PMC_IDX_MAX]); |
241771ef | 964 | |
ee06094f IM |
965 | /* |
966 | * Set the next IRQ period, based on the hwc->period_left value. | |
967 | * To be called with the counter disabled in hw: | |
968 | */ | |
e4abb5d4 | 969 | static int |
26816c28 | 970 | x86_perf_counter_set_period(struct perf_counter *counter, |
ee06094f | 971 | struct hw_perf_counter *hwc, int idx) |
241771ef | 972 | { |
2f18d1e8 | 973 | s64 left = atomic64_read(&hwc->period_left); |
e4abb5d4 PZ |
974 | s64 period = hwc->sample_period; |
975 | int err, ret = 0; | |
ee06094f | 976 | |
ee06094f IM |
977 | /* |
978 | * If we are way outside a reasoable range then just skip forward: | |
979 | */ | |
980 | if (unlikely(left <= -period)) { | |
981 | left = period; | |
982 | atomic64_set(&hwc->period_left, left); | |
9e350de3 | 983 | hwc->last_period = period; |
e4abb5d4 | 984 | ret = 1; |
ee06094f IM |
985 | } |
986 | ||
987 | if (unlikely(left <= 0)) { | |
988 | left += period; | |
989 | atomic64_set(&hwc->period_left, left); | |
9e350de3 | 990 | hwc->last_period = period; |
e4abb5d4 | 991 | ret = 1; |
ee06094f | 992 | } |
1c80f4b5 IM |
993 | /* |
994 | * Quirk: certain CPUs dont like it if just 1 event is left: | |
995 | */ | |
996 | if (unlikely(left < 2)) | |
997 | left = 2; | |
241771ef | 998 | |
e4abb5d4 PZ |
999 | if (left > x86_pmu.max_period) |
1000 | left = x86_pmu.max_period; | |
1001 | ||
ee06094f IM |
1002 | per_cpu(prev_left[idx], smp_processor_id()) = left; |
1003 | ||
1004 | /* | |
1005 | * The hw counter starts counting from this counter offset, | |
1006 | * mark it to be able to extra future deltas: | |
1007 | */ | |
2f18d1e8 | 1008 | atomic64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 1009 | |
2f18d1e8 | 1010 | err = checking_wrmsrl(hwc->counter_base + idx, |
0933e5c6 | 1011 | (u64)(-left) & x86_pmu.counter_mask); |
e4abb5d4 | 1012 | |
194002b2 PZ |
1013 | perf_counter_update_userpage(counter); |
1014 | ||
e4abb5d4 | 1015 | return ret; |
2f18d1e8 IM |
1016 | } |
1017 | ||
1018 | static inline void | |
7c90cc45 | 1019 | intel_pmu_enable_fixed(struct hw_perf_counter *hwc, int __idx) |
2f18d1e8 IM |
1020 | { |
1021 | int idx = __idx - X86_PMC_IDX_FIXED; | |
1022 | u64 ctrl_val, bits, mask; | |
1023 | int err; | |
1024 | ||
1025 | /* | |
0475f9ea PM |
1026 | * Enable IRQ generation (0x8), |
1027 | * and enable ring-3 counting (0x2) and ring-0 counting (0x1) | |
1028 | * if requested: | |
2f18d1e8 | 1029 | */ |
0475f9ea PM |
1030 | bits = 0x8ULL; |
1031 | if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) | |
1032 | bits |= 0x2; | |
2f18d1e8 IM |
1033 | if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) |
1034 | bits |= 0x1; | |
1035 | bits <<= (idx * 4); | |
1036 | mask = 0xfULL << (idx * 4); | |
1037 | ||
1038 | rdmsrl(hwc->config_base, ctrl_val); | |
1039 | ctrl_val &= ~mask; | |
1040 | ctrl_val |= bits; | |
1041 | err = checking_wrmsrl(hwc->config_base, ctrl_val); | |
7e2ae347 IM |
1042 | } |
1043 | ||
11d1578f VW |
1044 | static void p6_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) |
1045 | { | |
1046 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
984b838c | 1047 | u64 val; |
11d1578f | 1048 | |
984b838c | 1049 | val = hwc->config; |
11d1578f | 1050 | if (cpuc->enabled) |
984b838c PZ |
1051 | val |= ARCH_PERFMON_EVENTSEL0_ENABLE; |
1052 | ||
1053 | (void)checking_wrmsrl(hwc->config_base + idx, val); | |
11d1578f VW |
1054 | } |
1055 | ||
1056 | ||
7c90cc45 | 1057 | static void intel_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) |
7e2ae347 | 1058 | { |
7c90cc45 RR |
1059 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { |
1060 | intel_pmu_enable_fixed(hwc, idx); | |
1061 | return; | |
1062 | } | |
1063 | ||
1064 | x86_pmu_enable_counter(hwc, idx); | |
1065 | } | |
1066 | ||
1067 | static void amd_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) | |
1068 | { | |
1069 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
1070 | ||
1071 | if (cpuc->enabled) | |
1072 | x86_pmu_enable_counter(hwc, idx); | |
241771ef IM |
1073 | } |
1074 | ||
2f18d1e8 IM |
1075 | static int |
1076 | fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc) | |
862a1a5f | 1077 | { |
2f18d1e8 IM |
1078 | unsigned int event; |
1079 | ||
ef7b3e09 | 1080 | if (!x86_pmu.num_counters_fixed) |
f87ad35d JSR |
1081 | return -1; |
1082 | ||
2f18d1e8 IM |
1083 | event = hwc->config & ARCH_PERFMON_EVENT_MASK; |
1084 | ||
f4dbfa8f | 1085 | if (unlikely(event == x86_pmu.event_map(PERF_COUNT_HW_INSTRUCTIONS))) |
2f18d1e8 | 1086 | return X86_PMC_IDX_FIXED_INSTRUCTIONS; |
f4dbfa8f | 1087 | if (unlikely(event == x86_pmu.event_map(PERF_COUNT_HW_CPU_CYCLES))) |
2f18d1e8 | 1088 | return X86_PMC_IDX_FIXED_CPU_CYCLES; |
f4dbfa8f | 1089 | if (unlikely(event == x86_pmu.event_map(PERF_COUNT_HW_BUS_CYCLES))) |
2f18d1e8 IM |
1090 | return X86_PMC_IDX_FIXED_BUS_CYCLES; |
1091 | ||
862a1a5f IM |
1092 | return -1; |
1093 | } | |
1094 | ||
ee06094f IM |
1095 | /* |
1096 | * Find a PMC slot for the freshly enabled / scheduled in counter: | |
1097 | */ | |
4aeb0b42 | 1098 | static int x86_pmu_enable(struct perf_counter *counter) |
241771ef IM |
1099 | { |
1100 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
1101 | struct hw_perf_counter *hwc = &counter->hw; | |
2f18d1e8 | 1102 | int idx; |
241771ef | 1103 | |
2f18d1e8 IM |
1104 | idx = fixed_mode_idx(counter, hwc); |
1105 | if (idx >= 0) { | |
1106 | /* | |
1107 | * Try to get the fixed counter, if that is already taken | |
1108 | * then try to get a generic counter: | |
1109 | */ | |
43f6201a | 1110 | if (test_and_set_bit(idx, cpuc->used_mask)) |
2f18d1e8 | 1111 | goto try_generic; |
0dff86aa | 1112 | |
2f18d1e8 IM |
1113 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
1114 | /* | |
1115 | * We set it so that counter_base + idx in wrmsr/rdmsr maps to | |
1116 | * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2: | |
1117 | */ | |
1118 | hwc->counter_base = | |
1119 | MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED; | |
241771ef | 1120 | hwc->idx = idx; |
2f18d1e8 IM |
1121 | } else { |
1122 | idx = hwc->idx; | |
1123 | /* Try to get the previous generic counter again */ | |
43f6201a | 1124 | if (test_and_set_bit(idx, cpuc->used_mask)) { |
2f18d1e8 | 1125 | try_generic: |
43f6201a | 1126 | idx = find_first_zero_bit(cpuc->used_mask, |
0933e5c6 RR |
1127 | x86_pmu.num_counters); |
1128 | if (idx == x86_pmu.num_counters) | |
2f18d1e8 IM |
1129 | return -EAGAIN; |
1130 | ||
43f6201a | 1131 | set_bit(idx, cpuc->used_mask); |
2f18d1e8 IM |
1132 | hwc->idx = idx; |
1133 | } | |
4a06bd85 RR |
1134 | hwc->config_base = x86_pmu.eventsel; |
1135 | hwc->counter_base = x86_pmu.perfctr; | |
241771ef IM |
1136 | } |
1137 | ||
c323d95f | 1138 | perf_counters_lapic_init(); |
53b441a5 | 1139 | |
d4369891 | 1140 | x86_pmu.disable(hwc, idx); |
241771ef | 1141 | |
862a1a5f | 1142 | cpuc->counters[idx] = counter; |
43f6201a | 1143 | set_bit(idx, cpuc->active_mask); |
7e2ae347 | 1144 | |
26816c28 | 1145 | x86_perf_counter_set_period(counter, hwc, idx); |
7c90cc45 | 1146 | x86_pmu.enable(hwc, idx); |
95cdd2e7 | 1147 | |
194002b2 PZ |
1148 | perf_counter_update_userpage(counter); |
1149 | ||
95cdd2e7 | 1150 | return 0; |
241771ef IM |
1151 | } |
1152 | ||
a78ac325 PZ |
1153 | static void x86_pmu_unthrottle(struct perf_counter *counter) |
1154 | { | |
1155 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
1156 | struct hw_perf_counter *hwc = &counter->hw; | |
1157 | ||
1158 | if (WARN_ON_ONCE(hwc->idx >= X86_PMC_IDX_MAX || | |
1159 | cpuc->counters[hwc->idx] != counter)) | |
1160 | return; | |
1161 | ||
1162 | x86_pmu.enable(hwc, hwc->idx); | |
1163 | } | |
1164 | ||
241771ef IM |
1165 | void perf_counter_print_debug(void) |
1166 | { | |
2f18d1e8 | 1167 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
0dff86aa | 1168 | struct cpu_hw_counters *cpuc; |
5bb9efe3 | 1169 | unsigned long flags; |
1e125676 IM |
1170 | int cpu, idx; |
1171 | ||
0933e5c6 | 1172 | if (!x86_pmu.num_counters) |
1e125676 | 1173 | return; |
241771ef | 1174 | |
5bb9efe3 | 1175 | local_irq_save(flags); |
241771ef IM |
1176 | |
1177 | cpu = smp_processor_id(); | |
0dff86aa | 1178 | cpuc = &per_cpu(cpu_hw_counters, cpu); |
241771ef | 1179 | |
faa28ae0 | 1180 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1181 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1182 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1183 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1184 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
1185 | ||
1186 | pr_info("\n"); | |
1187 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1188 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1189 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1190 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
f87ad35d | 1191 | } |
43f6201a | 1192 | pr_info("CPU#%d: used: %016llx\n", cpu, *(u64 *)cpuc->used_mask); |
241771ef | 1193 | |
0933e5c6 | 1194 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
4a06bd85 RR |
1195 | rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl); |
1196 | rdmsrl(x86_pmu.perfctr + idx, pmc_count); | |
241771ef | 1197 | |
ee06094f | 1198 | prev_left = per_cpu(prev_left[idx], cpu); |
241771ef | 1199 | |
a1ef58f4 | 1200 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1201 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1202 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1203 | cpu, idx, pmc_count); |
a1ef58f4 | 1204 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1205 | cpu, idx, prev_left); |
241771ef | 1206 | } |
0933e5c6 | 1207 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
1208 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1209 | ||
a1ef58f4 | 1210 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1211 | cpu, idx, pmc_count); |
1212 | } | |
5bb9efe3 | 1213 | local_irq_restore(flags); |
241771ef IM |
1214 | } |
1215 | ||
4aeb0b42 | 1216 | static void x86_pmu_disable(struct perf_counter *counter) |
241771ef IM |
1217 | { |
1218 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
1219 | struct hw_perf_counter *hwc = &counter->hw; | |
6f00cada | 1220 | int idx = hwc->idx; |
241771ef | 1221 | |
09534238 RR |
1222 | /* |
1223 | * Must be done before we disable, otherwise the nmi handler | |
1224 | * could reenable again: | |
1225 | */ | |
43f6201a | 1226 | clear_bit(idx, cpuc->active_mask); |
d4369891 | 1227 | x86_pmu.disable(hwc, idx); |
241771ef | 1228 | |
2f18d1e8 IM |
1229 | /* |
1230 | * Make sure the cleared pointer becomes visible before we | |
1231 | * (potentially) free the counter: | |
1232 | */ | |
527e26af | 1233 | barrier(); |
241771ef | 1234 | |
ee06094f IM |
1235 | /* |
1236 | * Drain the remaining delta count out of a counter | |
1237 | * that we are disabling: | |
1238 | */ | |
1239 | x86_perf_counter_update(counter, hwc, idx); | |
09534238 | 1240 | cpuc->counters[idx] = NULL; |
43f6201a | 1241 | clear_bit(idx, cpuc->used_mask); |
194002b2 PZ |
1242 | |
1243 | perf_counter_update_userpage(counter); | |
241771ef IM |
1244 | } |
1245 | ||
7e2ae347 | 1246 | /* |
ee06094f IM |
1247 | * Save and restart an expired counter. Called by NMI contexts, |
1248 | * so it has to be careful about preempting normal counter ops: | |
7e2ae347 | 1249 | */ |
e4abb5d4 | 1250 | static int intel_pmu_save_and_restart(struct perf_counter *counter) |
241771ef IM |
1251 | { |
1252 | struct hw_perf_counter *hwc = &counter->hw; | |
1253 | int idx = hwc->idx; | |
e4abb5d4 | 1254 | int ret; |
241771ef | 1255 | |
ee06094f | 1256 | x86_perf_counter_update(counter, hwc, idx); |
e4abb5d4 | 1257 | ret = x86_perf_counter_set_period(counter, hwc, idx); |
7e2ae347 | 1258 | |
2f18d1e8 | 1259 | if (counter->state == PERF_COUNTER_STATE_ACTIVE) |
7c90cc45 | 1260 | intel_pmu_enable_counter(hwc, idx); |
e4abb5d4 PZ |
1261 | |
1262 | return ret; | |
241771ef IM |
1263 | } |
1264 | ||
aaba9801 IM |
1265 | static void intel_pmu_reset(void) |
1266 | { | |
1267 | unsigned long flags; | |
1268 | int idx; | |
1269 | ||
1270 | if (!x86_pmu.num_counters) | |
1271 | return; | |
1272 | ||
1273 | local_irq_save(flags); | |
1274 | ||
1275 | printk("clearing PMU state on CPU#%d\n", smp_processor_id()); | |
1276 | ||
1277 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { | |
1278 | checking_wrmsrl(x86_pmu.eventsel + idx, 0ull); | |
1279 | checking_wrmsrl(x86_pmu.perfctr + idx, 0ull); | |
1280 | } | |
1281 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { | |
1282 | checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); | |
1283 | } | |
1284 | ||
1285 | local_irq_restore(flags); | |
1286 | } | |
1287 | ||
11d1578f VW |
1288 | static int p6_pmu_handle_irq(struct pt_regs *regs) |
1289 | { | |
1290 | struct perf_sample_data data; | |
1291 | struct cpu_hw_counters *cpuc; | |
1292 | struct perf_counter *counter; | |
1293 | struct hw_perf_counter *hwc; | |
1294 | int idx, handled = 0; | |
1295 | u64 val; | |
1296 | ||
1297 | data.regs = regs; | |
1298 | data.addr = 0; | |
1299 | ||
1300 | cpuc = &__get_cpu_var(cpu_hw_counters); | |
1301 | ||
1302 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { | |
1303 | if (!test_bit(idx, cpuc->active_mask)) | |
1304 | continue; | |
1305 | ||
1306 | counter = cpuc->counters[idx]; | |
1307 | hwc = &counter->hw; | |
1308 | ||
1309 | val = x86_perf_counter_update(counter, hwc, idx); | |
1310 | if (val & (1ULL << (x86_pmu.counter_bits - 1))) | |
1311 | continue; | |
1312 | ||
1313 | /* | |
1314 | * counter overflow | |
1315 | */ | |
1316 | handled = 1; | |
1317 | data.period = counter->hw.last_period; | |
1318 | ||
1319 | if (!x86_perf_counter_set_period(counter, hwc, idx)) | |
1320 | continue; | |
1321 | ||
1322 | if (perf_counter_overflow(counter, 1, &data)) | |
1323 | p6_pmu_disable_counter(hwc, idx); | |
1324 | } | |
1325 | ||
1326 | if (handled) | |
1327 | inc_irq_stat(apic_perf_irqs); | |
1328 | ||
1329 | return handled; | |
1330 | } | |
aaba9801 | 1331 | |
241771ef IM |
1332 | /* |
1333 | * This handler is triggered by the local APIC, so the APIC IRQ handling | |
1334 | * rules apply: | |
1335 | */ | |
a3288106 | 1336 | static int intel_pmu_handle_irq(struct pt_regs *regs) |
241771ef | 1337 | { |
df1a132b | 1338 | struct perf_sample_data data; |
9029a5e3 | 1339 | struct cpu_hw_counters *cpuc; |
11d1578f | 1340 | int bit, loops; |
4b39fd96 | 1341 | u64 ack, status; |
9029a5e3 | 1342 | |
df1a132b PZ |
1343 | data.regs = regs; |
1344 | data.addr = 0; | |
1345 | ||
11d1578f | 1346 | cpuc = &__get_cpu_var(cpu_hw_counters); |
241771ef | 1347 | |
9e35ad38 | 1348 | perf_disable(); |
19d84dab | 1349 | status = intel_pmu_get_status(); |
9e35ad38 PZ |
1350 | if (!status) { |
1351 | perf_enable(); | |
1352 | return 0; | |
1353 | } | |
87b9cf46 | 1354 | |
9029a5e3 | 1355 | loops = 0; |
241771ef | 1356 | again: |
9029a5e3 IM |
1357 | if (++loops > 100) { |
1358 | WARN_ONCE(1, "perfcounters: irq loop stuck!\n"); | |
34adc806 | 1359 | perf_counter_print_debug(); |
aaba9801 IM |
1360 | intel_pmu_reset(); |
1361 | perf_enable(); | |
9029a5e3 IM |
1362 | return 1; |
1363 | } | |
1364 | ||
d278c484 | 1365 | inc_irq_stat(apic_perf_irqs); |
241771ef | 1366 | ack = status; |
2f18d1e8 | 1367 | for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { |
862a1a5f | 1368 | struct perf_counter *counter = cpuc->counters[bit]; |
241771ef IM |
1369 | |
1370 | clear_bit(bit, (unsigned long *) &status); | |
43f6201a | 1371 | if (!test_bit(bit, cpuc->active_mask)) |
241771ef IM |
1372 | continue; |
1373 | ||
e4abb5d4 PZ |
1374 | if (!intel_pmu_save_and_restart(counter)) |
1375 | continue; | |
1376 | ||
60f916de PZ |
1377 | data.period = counter->hw.last_period; |
1378 | ||
df1a132b | 1379 | if (perf_counter_overflow(counter, 1, &data)) |
d4369891 | 1380 | intel_pmu_disable_counter(&counter->hw, bit); |
241771ef IM |
1381 | } |
1382 | ||
dee5d906 | 1383 | intel_pmu_ack_status(ack); |
241771ef IM |
1384 | |
1385 | /* | |
1386 | * Repeat if there is more work to be done: | |
1387 | */ | |
19d84dab | 1388 | status = intel_pmu_get_status(); |
241771ef IM |
1389 | if (status) |
1390 | goto again; | |
b0f3f28e | 1391 | |
48e22d56 | 1392 | perf_enable(); |
9e35ad38 PZ |
1393 | |
1394 | return 1; | |
1b023a96 MG |
1395 | } |
1396 | ||
a3288106 | 1397 | static int amd_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1398 | { |
df1a132b | 1399 | struct perf_sample_data data; |
9029a5e3 | 1400 | struct cpu_hw_counters *cpuc; |
a29aa8a7 RR |
1401 | struct perf_counter *counter; |
1402 | struct hw_perf_counter *hwc; | |
11d1578f | 1403 | int idx, handled = 0; |
9029a5e3 IM |
1404 | u64 val; |
1405 | ||
df1a132b PZ |
1406 | data.regs = regs; |
1407 | data.addr = 0; | |
1408 | ||
11d1578f | 1409 | cpuc = &__get_cpu_var(cpu_hw_counters); |
962bf7a6 | 1410 | |
a29aa8a7 | 1411 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
43f6201a | 1412 | if (!test_bit(idx, cpuc->active_mask)) |
a29aa8a7 | 1413 | continue; |
962bf7a6 | 1414 | |
a29aa8a7 RR |
1415 | counter = cpuc->counters[idx]; |
1416 | hwc = &counter->hw; | |
a4016a79 | 1417 | |
4b7bfd0d | 1418 | val = x86_perf_counter_update(counter, hwc, idx); |
a29aa8a7 | 1419 | if (val & (1ULL << (x86_pmu.counter_bits - 1))) |
48e22d56 | 1420 | continue; |
962bf7a6 | 1421 | |
9e350de3 PZ |
1422 | /* |
1423 | * counter overflow | |
1424 | */ | |
1425 | handled = 1; | |
1426 | data.period = counter->hw.last_period; | |
1427 | ||
e4abb5d4 PZ |
1428 | if (!x86_perf_counter_set_period(counter, hwc, idx)) |
1429 | continue; | |
1430 | ||
df1a132b | 1431 | if (perf_counter_overflow(counter, 1, &data)) |
a29aa8a7 | 1432 | amd_pmu_disable_counter(hwc, idx); |
a29aa8a7 | 1433 | } |
962bf7a6 | 1434 | |
9e350de3 PZ |
1435 | if (handled) |
1436 | inc_irq_stat(apic_perf_irqs); | |
1437 | ||
a29aa8a7 RR |
1438 | return handled; |
1439 | } | |
39d81eab | 1440 | |
b6276f35 PZ |
1441 | void smp_perf_pending_interrupt(struct pt_regs *regs) |
1442 | { | |
1443 | irq_enter(); | |
1444 | ack_APIC_irq(); | |
1445 | inc_irq_stat(apic_pending_irqs); | |
1446 | perf_counter_do_pending(); | |
1447 | irq_exit(); | |
1448 | } | |
1449 | ||
1450 | void set_perf_counter_pending(void) | |
1451 | { | |
1452 | apic->send_IPI_self(LOCAL_PENDING_VECTOR); | |
1453 | } | |
1454 | ||
c323d95f | 1455 | void perf_counters_lapic_init(void) |
241771ef | 1456 | { |
85cf9dba | 1457 | if (!x86_pmu_initialized()) |
241771ef | 1458 | return; |
85cf9dba | 1459 | |
241771ef | 1460 | /* |
c323d95f | 1461 | * Always use NMI for PMU |
241771ef | 1462 | */ |
c323d95f | 1463 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1464 | } |
1465 | ||
1466 | static int __kprobes | |
1467 | perf_counter_nmi_handler(struct notifier_block *self, | |
1468 | unsigned long cmd, void *__args) | |
1469 | { | |
1470 | struct die_args *args = __args; | |
1471 | struct pt_regs *regs; | |
b0f3f28e | 1472 | |
ba77813a | 1473 | if (!atomic_read(&active_counters)) |
63a809a2 PZ |
1474 | return NOTIFY_DONE; |
1475 | ||
b0f3f28e PZ |
1476 | switch (cmd) { |
1477 | case DIE_NMI: | |
1478 | case DIE_NMI_IPI: | |
1479 | break; | |
241771ef | 1480 | |
b0f3f28e | 1481 | default: |
241771ef | 1482 | return NOTIFY_DONE; |
b0f3f28e | 1483 | } |
241771ef IM |
1484 | |
1485 | regs = args->regs; | |
1486 | ||
1487 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
a4016a79 PZ |
1488 | /* |
1489 | * Can't rely on the handled return value to say it was our NMI, two | |
1490 | * counters could trigger 'simultaneously' raising two back-to-back NMIs. | |
1491 | * | |
1492 | * If the first NMI handles both, the latter will be empty and daze | |
1493 | * the CPU. | |
1494 | */ | |
a3288106 | 1495 | x86_pmu.handle_irq(regs); |
241771ef | 1496 | |
a4016a79 | 1497 | return NOTIFY_STOP; |
241771ef IM |
1498 | } |
1499 | ||
1500 | static __read_mostly struct notifier_block perf_counter_nmi_notifier = { | |
5b75af0a MG |
1501 | .notifier_call = perf_counter_nmi_handler, |
1502 | .next = NULL, | |
1503 | .priority = 1 | |
241771ef IM |
1504 | }; |
1505 | ||
11d1578f VW |
1506 | static struct x86_pmu p6_pmu = { |
1507 | .name = "p6", | |
1508 | .handle_irq = p6_pmu_handle_irq, | |
1509 | .disable_all = p6_pmu_disable_all, | |
1510 | .enable_all = p6_pmu_enable_all, | |
1511 | .enable = p6_pmu_enable_counter, | |
1512 | .disable = p6_pmu_disable_counter, | |
1513 | .eventsel = MSR_P6_EVNTSEL0, | |
1514 | .perfctr = MSR_P6_PERFCTR0, | |
1515 | .event_map = p6_pmu_event_map, | |
1516 | .raw_event = p6_pmu_raw_event, | |
1517 | .max_events = ARRAY_SIZE(p6_perfmon_event_map), | |
1518 | .max_period = (1ULL << 31) - 1, | |
1519 | .version = 0, | |
1520 | .num_counters = 2, | |
1521 | /* | |
1522 | * Counters have 40 bits implemented. However they are designed such | |
1523 | * that bits [32-39] are sign extensions of bit 31. As such the | |
1524 | * effective width of a counter for P6-like PMU is 32 bits only. | |
1525 | * | |
1526 | * See IA-32 Intel Architecture Software developer manual Vol 3B | |
1527 | */ | |
1528 | .counter_bits = 32, | |
1529 | .counter_mask = (1ULL << 32) - 1, | |
1530 | }; | |
1531 | ||
5f4ec28f | 1532 | static struct x86_pmu intel_pmu = { |
faa28ae0 | 1533 | .name = "Intel", |
39d81eab | 1534 | .handle_irq = intel_pmu_handle_irq, |
9e35ad38 PZ |
1535 | .disable_all = intel_pmu_disable_all, |
1536 | .enable_all = intel_pmu_enable_all, | |
5f4ec28f RR |
1537 | .enable = intel_pmu_enable_counter, |
1538 | .disable = intel_pmu_disable_counter, | |
b56a3802 JSR |
1539 | .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, |
1540 | .perfctr = MSR_ARCH_PERFMON_PERFCTR0, | |
5f4ec28f RR |
1541 | .event_map = intel_pmu_event_map, |
1542 | .raw_event = intel_pmu_raw_event, | |
b56a3802 | 1543 | .max_events = ARRAY_SIZE(intel_perfmon_event_map), |
c619b8ff RR |
1544 | /* |
1545 | * Intel PMCs cannot be accessed sanely above 32 bit width, | |
1546 | * so we install an artificial 1<<31 period regardless of | |
1547 | * the generic counter period: | |
1548 | */ | |
1549 | .max_period = (1ULL << 31) - 1, | |
b56a3802 JSR |
1550 | }; |
1551 | ||
5f4ec28f | 1552 | static struct x86_pmu amd_pmu = { |
faa28ae0 | 1553 | .name = "AMD", |
39d81eab | 1554 | .handle_irq = amd_pmu_handle_irq, |
9e35ad38 PZ |
1555 | .disable_all = amd_pmu_disable_all, |
1556 | .enable_all = amd_pmu_enable_all, | |
5f4ec28f RR |
1557 | .enable = amd_pmu_enable_counter, |
1558 | .disable = amd_pmu_disable_counter, | |
f87ad35d JSR |
1559 | .eventsel = MSR_K7_EVNTSEL0, |
1560 | .perfctr = MSR_K7_PERFCTR0, | |
5f4ec28f RR |
1561 | .event_map = amd_pmu_event_map, |
1562 | .raw_event = amd_pmu_raw_event, | |
f87ad35d | 1563 | .max_events = ARRAY_SIZE(amd_perfmon_event_map), |
0933e5c6 RR |
1564 | .num_counters = 4, |
1565 | .counter_bits = 48, | |
1566 | .counter_mask = (1ULL << 48) - 1, | |
c619b8ff RR |
1567 | /* use highest bit to detect overflow */ |
1568 | .max_period = (1ULL << 47) - 1, | |
f87ad35d JSR |
1569 | }; |
1570 | ||
11d1578f VW |
1571 | static int p6_pmu_init(void) |
1572 | { | |
11d1578f VW |
1573 | switch (boot_cpu_data.x86_model) { |
1574 | case 1: | |
1575 | case 3: /* Pentium Pro */ | |
1576 | case 5: | |
1577 | case 6: /* Pentium II */ | |
1578 | case 7: | |
1579 | case 8: | |
1580 | case 11: /* Pentium III */ | |
1581 | break; | |
1582 | case 9: | |
1583 | case 13: | |
f1c6a581 DQ |
1584 | /* Pentium M */ |
1585 | break; | |
11d1578f VW |
1586 | default: |
1587 | pr_cont("unsupported p6 CPU model %d ", | |
1588 | boot_cpu_data.x86_model); | |
1589 | return -ENODEV; | |
1590 | } | |
1591 | ||
1592 | if (!cpu_has_apic) { | |
1593 | pr_info("no Local APIC, try rebooting with lapic"); | |
1594 | return -ENODEV; | |
1595 | } | |
1596 | ||
1597 | x86_pmu = p6_pmu; | |
1598 | ||
1599 | return 0; | |
1600 | } | |
1601 | ||
72eae04d | 1602 | static int intel_pmu_init(void) |
241771ef | 1603 | { |
7bb497bd | 1604 | union cpuid10_edx edx; |
241771ef | 1605 | union cpuid10_eax eax; |
703e937c | 1606 | unsigned int unused; |
7bb497bd | 1607 | unsigned int ebx; |
faa28ae0 | 1608 | int version; |
241771ef | 1609 | |
11d1578f VW |
1610 | if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { |
1611 | /* check for P6 processor family */ | |
1612 | if (boot_cpu_data.x86 == 6) { | |
1613 | return p6_pmu_init(); | |
1614 | } else { | |
72eae04d | 1615 | return -ENODEV; |
11d1578f VW |
1616 | } |
1617 | } | |
da1a776b | 1618 | |
241771ef IM |
1619 | /* |
1620 | * Check whether the Architectural PerfMon supports | |
1621 | * Branch Misses Retired Event or not. | |
1622 | */ | |
703e937c | 1623 | cpuid(10, &eax.full, &ebx, &unused, &edx.full); |
241771ef | 1624 | if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED) |
72eae04d | 1625 | return -ENODEV; |
241771ef | 1626 | |
faa28ae0 RR |
1627 | version = eax.split.version_id; |
1628 | if (version < 2) | |
72eae04d | 1629 | return -ENODEV; |
7bb497bd | 1630 | |
1123e3ad IM |
1631 | x86_pmu = intel_pmu; |
1632 | x86_pmu.version = version; | |
1633 | x86_pmu.num_counters = eax.split.num_counters; | |
1634 | x86_pmu.counter_bits = eax.split.bit_width; | |
1635 | x86_pmu.counter_mask = (1ULL << eax.split.bit_width) - 1; | |
066d7dea IM |
1636 | |
1637 | /* | |
1638 | * Quirk: v2 perfmon does not report fixed-purpose counters, so | |
1639 | * assume at least 3 counters: | |
1640 | */ | |
1123e3ad | 1641 | x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3); |
b56a3802 | 1642 | |
8326f44d | 1643 | /* |
1123e3ad | 1644 | * Install the hw-cache-events table: |
8326f44d IM |
1645 | */ |
1646 | switch (boot_cpu_data.x86_model) { | |
dc81081b YW |
1647 | case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */ |
1648 | case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */ | |
1649 | case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */ | |
1650 | case 29: /* six-core 45 nm xeon "Dunnington" */ | |
8326f44d | 1651 | memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, |
820a6442 | 1652 | sizeof(hw_cache_event_ids)); |
8326f44d | 1653 | |
1123e3ad | 1654 | pr_cont("Core2 events, "); |
8326f44d IM |
1655 | break; |
1656 | default: | |
1657 | case 26: | |
1658 | memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, | |
820a6442 | 1659 | sizeof(hw_cache_event_ids)); |
8326f44d | 1660 | |
1123e3ad | 1661 | pr_cont("Nehalem/Corei7 events, "); |
8326f44d IM |
1662 | break; |
1663 | case 28: | |
1664 | memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, | |
820a6442 | 1665 | sizeof(hw_cache_event_ids)); |
8326f44d | 1666 | |
1123e3ad | 1667 | pr_cont("Atom events, "); |
8326f44d IM |
1668 | break; |
1669 | } | |
72eae04d | 1670 | return 0; |
b56a3802 JSR |
1671 | } |
1672 | ||
72eae04d | 1673 | static int amd_pmu_init(void) |
f87ad35d | 1674 | { |
4d2be126 JSR |
1675 | /* Performance-monitoring supported from K7 and later: */ |
1676 | if (boot_cpu_data.x86 < 6) | |
1677 | return -ENODEV; | |
1678 | ||
4a06bd85 | 1679 | x86_pmu = amd_pmu; |
f86748e9 | 1680 | |
f4db43a3 JSR |
1681 | /* Events are common for all AMDs */ |
1682 | memcpy(hw_cache_event_ids, amd_hw_cache_event_ids, | |
1683 | sizeof(hw_cache_event_ids)); | |
f86748e9 | 1684 | |
72eae04d | 1685 | return 0; |
f87ad35d JSR |
1686 | } |
1687 | ||
b56a3802 JSR |
1688 | void __init init_hw_perf_counters(void) |
1689 | { | |
72eae04d RR |
1690 | int err; |
1691 | ||
1123e3ad IM |
1692 | pr_info("Performance Counters: "); |
1693 | ||
b56a3802 JSR |
1694 | switch (boot_cpu_data.x86_vendor) { |
1695 | case X86_VENDOR_INTEL: | |
72eae04d | 1696 | err = intel_pmu_init(); |
b56a3802 | 1697 | break; |
f87ad35d | 1698 | case X86_VENDOR_AMD: |
72eae04d | 1699 | err = amd_pmu_init(); |
f87ad35d | 1700 | break; |
4138960a RR |
1701 | default: |
1702 | return; | |
b56a3802 | 1703 | } |
1123e3ad IM |
1704 | if (err != 0) { |
1705 | pr_cont("no PMU driver, software counters only.\n"); | |
b56a3802 | 1706 | return; |
1123e3ad | 1707 | } |
b56a3802 | 1708 | |
1123e3ad | 1709 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1710 | |
0933e5c6 | 1711 | if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) { |
241771ef | 1712 | WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!", |
0933e5c6 | 1713 | x86_pmu.num_counters, X86_PMC_MAX_GENERIC); |
4078c444 | 1714 | x86_pmu.num_counters = X86_PMC_MAX_GENERIC; |
241771ef | 1715 | } |
0933e5c6 RR |
1716 | perf_counter_mask = (1 << x86_pmu.num_counters) - 1; |
1717 | perf_max_counters = x86_pmu.num_counters; | |
241771ef | 1718 | |
0933e5c6 | 1719 | if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { |
703e937c | 1720 | WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!", |
0933e5c6 | 1721 | x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED); |
4078c444 | 1722 | x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; |
703e937c | 1723 | } |
862a1a5f | 1724 | |
0933e5c6 RR |
1725 | perf_counter_mask |= |
1726 | ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED; | |
c14dab5c | 1727 | x86_pmu.intel_ctrl = perf_counter_mask; |
241771ef | 1728 | |
c323d95f | 1729 | perf_counters_lapic_init(); |
241771ef | 1730 | register_die_notifier(&perf_counter_nmi_notifier); |
1123e3ad IM |
1731 | |
1732 | pr_info("... version: %d\n", x86_pmu.version); | |
1733 | pr_info("... bit width: %d\n", x86_pmu.counter_bits); | |
1734 | pr_info("... generic counters: %d\n", x86_pmu.num_counters); | |
1735 | pr_info("... value mask: %016Lx\n", x86_pmu.counter_mask); | |
1736 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); | |
1737 | pr_info("... fixed-purpose counters: %d\n", x86_pmu.num_counters_fixed); | |
1738 | pr_info("... counter mask: %016Lx\n", perf_counter_mask); | |
241771ef | 1739 | } |
621a01ea | 1740 | |
bb775fc2 | 1741 | static inline void x86_pmu_read(struct perf_counter *counter) |
ee06094f IM |
1742 | { |
1743 | x86_perf_counter_update(counter, &counter->hw, counter->hw.idx); | |
1744 | } | |
1745 | ||
4aeb0b42 RR |
1746 | static const struct pmu pmu = { |
1747 | .enable = x86_pmu_enable, | |
1748 | .disable = x86_pmu_disable, | |
1749 | .read = x86_pmu_read, | |
a78ac325 | 1750 | .unthrottle = x86_pmu_unthrottle, |
621a01ea IM |
1751 | }; |
1752 | ||
4aeb0b42 | 1753 | const struct pmu *hw_perf_counter_init(struct perf_counter *counter) |
621a01ea IM |
1754 | { |
1755 | int err; | |
1756 | ||
1757 | err = __hw_perf_counter_init(counter); | |
1758 | if (err) | |
9ea98e19 | 1759 | return ERR_PTR(err); |
621a01ea | 1760 | |
4aeb0b42 | 1761 | return &pmu; |
621a01ea | 1762 | } |
d7d59fb3 PZ |
1763 | |
1764 | /* | |
1765 | * callchain support | |
1766 | */ | |
1767 | ||
1768 | static inline | |
f9188e02 | 1769 | void callchain_store(struct perf_callchain_entry *entry, u64 ip) |
d7d59fb3 | 1770 | { |
f9188e02 | 1771 | if (entry->nr < PERF_MAX_STACK_DEPTH) |
d7d59fb3 PZ |
1772 | entry->ip[entry->nr++] = ip; |
1773 | } | |
1774 | ||
1775 | static DEFINE_PER_CPU(struct perf_callchain_entry, irq_entry); | |
1776 | static DEFINE_PER_CPU(struct perf_callchain_entry, nmi_entry); | |
0406ca6d | 1777 | static DEFINE_PER_CPU(int, in_nmi_frame); |
d7d59fb3 PZ |
1778 | |
1779 | ||
1780 | static void | |
1781 | backtrace_warning_symbol(void *data, char *msg, unsigned long symbol) | |
1782 | { | |
1783 | /* Ignore warnings */ | |
1784 | } | |
1785 | ||
1786 | static void backtrace_warning(void *data, char *msg) | |
1787 | { | |
1788 | /* Ignore warnings */ | |
1789 | } | |
1790 | ||
1791 | static int backtrace_stack(void *data, char *name) | |
1792 | { | |
0406ca6d FW |
1793 | per_cpu(in_nmi_frame, smp_processor_id()) = |
1794 | x86_is_stack_id(NMI_STACK, name); | |
1795 | ||
038e836e | 1796 | return 0; |
d7d59fb3 PZ |
1797 | } |
1798 | ||
1799 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1800 | { | |
1801 | struct perf_callchain_entry *entry = data; | |
1802 | ||
0406ca6d FW |
1803 | if (per_cpu(in_nmi_frame, smp_processor_id())) |
1804 | return; | |
1805 | ||
d7d59fb3 PZ |
1806 | if (reliable) |
1807 | callchain_store(entry, addr); | |
1808 | } | |
1809 | ||
1810 | static const struct stacktrace_ops backtrace_ops = { | |
1811 | .warning = backtrace_warning, | |
1812 | .warning_symbol = backtrace_warning_symbol, | |
1813 | .stack = backtrace_stack, | |
1814 | .address = backtrace_address, | |
1815 | }; | |
1816 | ||
038e836e IM |
1817 | #include "../dumpstack.h" |
1818 | ||
d7d59fb3 PZ |
1819 | static void |
1820 | perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1821 | { | |
f9188e02 | 1822 | callchain_store(entry, PERF_CONTEXT_KERNEL); |
038e836e | 1823 | callchain_store(entry, regs->ip); |
d7d59fb3 | 1824 | |
f9188e02 | 1825 | dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry); |
d7d59fb3 PZ |
1826 | } |
1827 | ||
74193ef0 PZ |
1828 | /* |
1829 | * best effort, GUP based copy_from_user() that assumes IRQ or NMI context | |
1830 | */ | |
1831 | static unsigned long | |
1832 | copy_from_user_nmi(void *to, const void __user *from, unsigned long n) | |
d7d59fb3 | 1833 | { |
74193ef0 PZ |
1834 | unsigned long offset, addr = (unsigned long)from; |
1835 | int type = in_nmi() ? KM_NMI : KM_IRQ0; | |
1836 | unsigned long size, len = 0; | |
1837 | struct page *page; | |
1838 | void *map; | |
d7d59fb3 PZ |
1839 | int ret; |
1840 | ||
74193ef0 PZ |
1841 | do { |
1842 | ret = __get_user_pages_fast(addr, 1, 0, &page); | |
1843 | if (!ret) | |
1844 | break; | |
d7d59fb3 | 1845 | |
74193ef0 PZ |
1846 | offset = addr & (PAGE_SIZE - 1); |
1847 | size = min(PAGE_SIZE - offset, n - len); | |
d7d59fb3 | 1848 | |
74193ef0 PZ |
1849 | map = kmap_atomic(page, type); |
1850 | memcpy(to, map+offset, size); | |
1851 | kunmap_atomic(map, type); | |
1852 | put_page(page); | |
1853 | ||
1854 | len += size; | |
1855 | to += size; | |
1856 | addr += size; | |
1857 | ||
1858 | } while (len < n); | |
1859 | ||
1860 | return len; | |
1861 | } | |
1862 | ||
1863 | static int copy_stack_frame(const void __user *fp, struct stack_frame *frame) | |
1864 | { | |
1865 | unsigned long bytes; | |
1866 | ||
1867 | bytes = copy_from_user_nmi(frame, fp, sizeof(*frame)); | |
1868 | ||
1869 | return bytes == sizeof(*frame); | |
d7d59fb3 PZ |
1870 | } |
1871 | ||
1872 | static void | |
1873 | perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1874 | { | |
1875 | struct stack_frame frame; | |
1876 | const void __user *fp; | |
1877 | ||
5a6cec3a IM |
1878 | if (!user_mode(regs)) |
1879 | regs = task_pt_regs(current); | |
1880 | ||
74193ef0 | 1881 | fp = (void __user *)regs->bp; |
d7d59fb3 | 1882 | |
f9188e02 | 1883 | callchain_store(entry, PERF_CONTEXT_USER); |
d7d59fb3 PZ |
1884 | callchain_store(entry, regs->ip); |
1885 | ||
f9188e02 | 1886 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
038e836e | 1887 | frame.next_frame = NULL; |
d7d59fb3 PZ |
1888 | frame.return_address = 0; |
1889 | ||
1890 | if (!copy_stack_frame(fp, &frame)) | |
1891 | break; | |
1892 | ||
5a6cec3a | 1893 | if ((unsigned long)fp < regs->sp) |
d7d59fb3 PZ |
1894 | break; |
1895 | ||
1896 | callchain_store(entry, frame.return_address); | |
038e836e | 1897 | fp = frame.next_frame; |
d7d59fb3 PZ |
1898 | } |
1899 | } | |
1900 | ||
1901 | static void | |
1902 | perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1903 | { | |
1904 | int is_user; | |
1905 | ||
1906 | if (!regs) | |
1907 | return; | |
1908 | ||
1909 | is_user = user_mode(regs); | |
1910 | ||
1911 | if (!current || current->pid == 0) | |
1912 | return; | |
1913 | ||
1914 | if (is_user && current->state != TASK_RUNNING) | |
1915 | return; | |
1916 | ||
1917 | if (!is_user) | |
1918 | perf_callchain_kernel(regs, entry); | |
1919 | ||
1920 | if (current->mm) | |
1921 | perf_callchain_user(regs, entry); | |
1922 | } | |
1923 | ||
1924 | struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) | |
1925 | { | |
1926 | struct perf_callchain_entry *entry; | |
1927 | ||
1928 | if (in_nmi()) | |
1929 | entry = &__get_cpu_var(nmi_entry); | |
1930 | else | |
1931 | entry = &__get_cpu_var(irq_entry); | |
1932 | ||
1933 | entry->nr = 0; | |
1934 | ||
1935 | perf_do_callchain(regs, entry); | |
1936 | ||
1937 | return entry; | |
1938 | } |