]>
Commit | Line | Data |
---|---|---|
241771ef IM |
1 | /* |
2 | * Performance counter x86 architecture code | |
3 | * | |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
241771ef IM |
9 | * |
10 | * For licencing details see kernel-base/COPYING | |
11 | */ | |
12 | ||
13 | #include <linux/perf_counter.h> | |
14 | #include <linux/capability.h> | |
15 | #include <linux/notifier.h> | |
16 | #include <linux/hardirq.h> | |
17 | #include <linux/kprobes.h> | |
4ac13294 | 18 | #include <linux/module.h> |
241771ef IM |
19 | #include <linux/kdebug.h> |
20 | #include <linux/sched.h> | |
d7d59fb3 | 21 | #include <linux/uaccess.h> |
74193ef0 | 22 | #include <linux/highmem.h> |
241771ef | 23 | |
241771ef | 24 | #include <asm/apic.h> |
d7d59fb3 | 25 | #include <asm/stacktrace.h> |
4e935e47 | 26 | #include <asm/nmi.h> |
241771ef | 27 | |
862a1a5f | 28 | static u64 perf_counter_mask __read_mostly; |
703e937c | 29 | |
241771ef | 30 | struct cpu_hw_counters { |
862a1a5f | 31 | struct perf_counter *counters[X86_PMC_IDX_MAX]; |
43f6201a RR |
32 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
33 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
4b39fd96 | 34 | unsigned long interrupts; |
b0f3f28e | 35 | int enabled; |
241771ef IM |
36 | }; |
37 | ||
38 | /* | |
5f4ec28f | 39 | * struct x86_pmu - generic x86 pmu |
241771ef | 40 | */ |
5f4ec28f | 41 | struct x86_pmu { |
faa28ae0 RR |
42 | const char *name; |
43 | int version; | |
a3288106 | 44 | int (*handle_irq)(struct pt_regs *); |
9e35ad38 PZ |
45 | void (*disable_all)(void); |
46 | void (*enable_all)(void); | |
7c90cc45 | 47 | void (*enable)(struct hw_perf_counter *, int); |
d4369891 | 48 | void (*disable)(struct hw_perf_counter *, int); |
169e41eb JSR |
49 | unsigned eventsel; |
50 | unsigned perfctr; | |
b0f3f28e PZ |
51 | u64 (*event_map)(int); |
52 | u64 (*raw_event)(u64); | |
169e41eb | 53 | int max_events; |
0933e5c6 RR |
54 | int num_counters; |
55 | int num_counters_fixed; | |
56 | int counter_bits; | |
57 | u64 counter_mask; | |
c619b8ff | 58 | u64 max_period; |
9e35ad38 | 59 | u64 intel_ctrl; |
b56a3802 JSR |
60 | }; |
61 | ||
4a06bd85 | 62 | static struct x86_pmu x86_pmu __read_mostly; |
b56a3802 | 63 | |
b0f3f28e PZ |
64 | static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = { |
65 | .enabled = 1, | |
66 | }; | |
241771ef | 67 | |
b56a3802 JSR |
68 | /* |
69 | * Intel PerfMon v3. Used on Core2 and later. | |
70 | */ | |
b0f3f28e | 71 | static const u64 intel_perfmon_event_map[] = |
241771ef | 72 | { |
f4dbfa8f PZ |
73 | [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, |
74 | [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, | |
75 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, | |
76 | [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, | |
77 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, | |
78 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, | |
79 | [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, | |
241771ef IM |
80 | }; |
81 | ||
5f4ec28f | 82 | static u64 intel_pmu_event_map(int event) |
b56a3802 JSR |
83 | { |
84 | return intel_perfmon_event_map[event]; | |
85 | } | |
241771ef | 86 | |
8326f44d IM |
87 | /* |
88 | * Generalized hw caching related event table, filled | |
89 | * in on a per model basis. A value of 0 means | |
90 | * 'not supported', -1 means 'event makes no sense on | |
91 | * this CPU', any other value means the raw event | |
92 | * ID. | |
93 | */ | |
94 | ||
95 | #define C(x) PERF_COUNT_HW_CACHE_##x | |
96 | ||
97 | static u64 __read_mostly hw_cache_event_ids | |
98 | [PERF_COUNT_HW_CACHE_MAX] | |
99 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
100 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
101 | ||
102 | static const u64 nehalem_hw_cache_event_ids | |
103 | [PERF_COUNT_HW_CACHE_MAX] | |
104 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
105 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
106 | { | |
107 | [ C(L1D) ] = { | |
108 | [ C(OP_READ) ] = { | |
109 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ | |
110 | [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ | |
111 | }, | |
112 | [ C(OP_WRITE) ] = { | |
113 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ | |
114 | [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ | |
115 | }, | |
116 | [ C(OP_PREFETCH) ] = { | |
117 | [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ | |
118 | [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ | |
119 | }, | |
120 | }, | |
121 | [ C(L1I ) ] = { | |
122 | [ C(OP_READ) ] = { | |
fecc8ac8 | 123 | [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ |
8326f44d IM |
124 | [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ |
125 | }, | |
126 | [ C(OP_WRITE) ] = { | |
127 | [ C(RESULT_ACCESS) ] = -1, | |
128 | [ C(RESULT_MISS) ] = -1, | |
129 | }, | |
130 | [ C(OP_PREFETCH) ] = { | |
131 | [ C(RESULT_ACCESS) ] = 0x0, | |
132 | [ C(RESULT_MISS) ] = 0x0, | |
133 | }, | |
134 | }, | |
8be6e8f3 | 135 | [ C(LL ) ] = { |
8326f44d IM |
136 | [ C(OP_READ) ] = { |
137 | [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS */ | |
138 | [ C(RESULT_MISS) ] = 0x0224, /* L2_RQSTS.LD_MISS */ | |
139 | }, | |
140 | [ C(OP_WRITE) ] = { | |
141 | [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS */ | |
142 | [ C(RESULT_MISS) ] = 0x0824, /* L2_RQSTS.RFO_MISS */ | |
143 | }, | |
144 | [ C(OP_PREFETCH) ] = { | |
8be6e8f3 PZ |
145 | [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference */ |
146 | [ C(RESULT_MISS) ] = 0x412e, /* LLC Misses */ | |
8326f44d IM |
147 | }, |
148 | }, | |
149 | [ C(DTLB) ] = { | |
150 | [ C(OP_READ) ] = { | |
151 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ | |
152 | [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ | |
153 | }, | |
154 | [ C(OP_WRITE) ] = { | |
155 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ | |
156 | [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ | |
157 | }, | |
158 | [ C(OP_PREFETCH) ] = { | |
159 | [ C(RESULT_ACCESS) ] = 0x0, | |
160 | [ C(RESULT_MISS) ] = 0x0, | |
161 | }, | |
162 | }, | |
163 | [ C(ITLB) ] = { | |
164 | [ C(OP_READ) ] = { | |
165 | [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ | |
fecc8ac8 | 166 | [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ |
8326f44d IM |
167 | }, |
168 | [ C(OP_WRITE) ] = { | |
169 | [ C(RESULT_ACCESS) ] = -1, | |
170 | [ C(RESULT_MISS) ] = -1, | |
171 | }, | |
172 | [ C(OP_PREFETCH) ] = { | |
173 | [ C(RESULT_ACCESS) ] = -1, | |
174 | [ C(RESULT_MISS) ] = -1, | |
175 | }, | |
176 | }, | |
177 | [ C(BPU ) ] = { | |
178 | [ C(OP_READ) ] = { | |
179 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ | |
180 | [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ | |
181 | }, | |
182 | [ C(OP_WRITE) ] = { | |
183 | [ C(RESULT_ACCESS) ] = -1, | |
184 | [ C(RESULT_MISS) ] = -1, | |
185 | }, | |
186 | [ C(OP_PREFETCH) ] = { | |
187 | [ C(RESULT_ACCESS) ] = -1, | |
188 | [ C(RESULT_MISS) ] = -1, | |
189 | }, | |
190 | }, | |
191 | }; | |
192 | ||
193 | static const u64 core2_hw_cache_event_ids | |
194 | [PERF_COUNT_HW_CACHE_MAX] | |
195 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
196 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
197 | { | |
0312af84 TG |
198 | [ C(L1D) ] = { |
199 | [ C(OP_READ) ] = { | |
200 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ | |
201 | [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ | |
202 | }, | |
203 | [ C(OP_WRITE) ] = { | |
204 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ | |
205 | [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ | |
206 | }, | |
207 | [ C(OP_PREFETCH) ] = { | |
208 | [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ | |
209 | [ C(RESULT_MISS) ] = 0, | |
210 | }, | |
211 | }, | |
212 | [ C(L1I ) ] = { | |
213 | [ C(OP_READ) ] = { | |
214 | [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ | |
215 | [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ | |
216 | }, | |
217 | [ C(OP_WRITE) ] = { | |
218 | [ C(RESULT_ACCESS) ] = -1, | |
219 | [ C(RESULT_MISS) ] = -1, | |
220 | }, | |
221 | [ C(OP_PREFETCH) ] = { | |
222 | [ C(RESULT_ACCESS) ] = 0, | |
223 | [ C(RESULT_MISS) ] = 0, | |
224 | }, | |
225 | }, | |
8be6e8f3 | 226 | [ C(LL ) ] = { |
0312af84 TG |
227 | [ C(OP_READ) ] = { |
228 | [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ | |
229 | [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ | |
230 | }, | |
231 | [ C(OP_WRITE) ] = { | |
232 | [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ | |
233 | [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ | |
234 | }, | |
235 | [ C(OP_PREFETCH) ] = { | |
236 | [ C(RESULT_ACCESS) ] = 0, | |
237 | [ C(RESULT_MISS) ] = 0, | |
238 | }, | |
239 | }, | |
240 | [ C(DTLB) ] = { | |
241 | [ C(OP_READ) ] = { | |
242 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ | |
243 | [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ | |
244 | }, | |
245 | [ C(OP_WRITE) ] = { | |
246 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ | |
247 | [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ | |
248 | }, | |
249 | [ C(OP_PREFETCH) ] = { | |
250 | [ C(RESULT_ACCESS) ] = 0, | |
251 | [ C(RESULT_MISS) ] = 0, | |
252 | }, | |
253 | }, | |
254 | [ C(ITLB) ] = { | |
255 | [ C(OP_READ) ] = { | |
256 | [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ | |
257 | [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ | |
258 | }, | |
259 | [ C(OP_WRITE) ] = { | |
260 | [ C(RESULT_ACCESS) ] = -1, | |
261 | [ C(RESULT_MISS) ] = -1, | |
262 | }, | |
263 | [ C(OP_PREFETCH) ] = { | |
264 | [ C(RESULT_ACCESS) ] = -1, | |
265 | [ C(RESULT_MISS) ] = -1, | |
266 | }, | |
267 | }, | |
268 | [ C(BPU ) ] = { | |
269 | [ C(OP_READ) ] = { | |
270 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ | |
271 | [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ | |
272 | }, | |
273 | [ C(OP_WRITE) ] = { | |
274 | [ C(RESULT_ACCESS) ] = -1, | |
275 | [ C(RESULT_MISS) ] = -1, | |
276 | }, | |
277 | [ C(OP_PREFETCH) ] = { | |
278 | [ C(RESULT_ACCESS) ] = -1, | |
279 | [ C(RESULT_MISS) ] = -1, | |
280 | }, | |
281 | }, | |
8326f44d IM |
282 | }; |
283 | ||
284 | static const u64 atom_hw_cache_event_ids | |
285 | [PERF_COUNT_HW_CACHE_MAX] | |
286 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
287 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
288 | { | |
ad689220 TG |
289 | [ C(L1D) ] = { |
290 | [ C(OP_READ) ] = { | |
291 | [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ | |
292 | [ C(RESULT_MISS) ] = 0, | |
293 | }, | |
294 | [ C(OP_WRITE) ] = { | |
fecc8ac8 | 295 | [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ |
ad689220 TG |
296 | [ C(RESULT_MISS) ] = 0, |
297 | }, | |
298 | [ C(OP_PREFETCH) ] = { | |
299 | [ C(RESULT_ACCESS) ] = 0x0, | |
300 | [ C(RESULT_MISS) ] = 0, | |
301 | }, | |
302 | }, | |
303 | [ C(L1I ) ] = { | |
304 | [ C(OP_READ) ] = { | |
fecc8ac8 YW |
305 | [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ |
306 | [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ | |
ad689220 TG |
307 | }, |
308 | [ C(OP_WRITE) ] = { | |
309 | [ C(RESULT_ACCESS) ] = -1, | |
310 | [ C(RESULT_MISS) ] = -1, | |
311 | }, | |
312 | [ C(OP_PREFETCH) ] = { | |
313 | [ C(RESULT_ACCESS) ] = 0, | |
314 | [ C(RESULT_MISS) ] = 0, | |
315 | }, | |
316 | }, | |
8be6e8f3 | 317 | [ C(LL ) ] = { |
ad689220 TG |
318 | [ C(OP_READ) ] = { |
319 | [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ | |
320 | [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ | |
321 | }, | |
322 | [ C(OP_WRITE) ] = { | |
323 | [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ | |
324 | [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ | |
325 | }, | |
326 | [ C(OP_PREFETCH) ] = { | |
327 | [ C(RESULT_ACCESS) ] = 0, | |
328 | [ C(RESULT_MISS) ] = 0, | |
329 | }, | |
330 | }, | |
331 | [ C(DTLB) ] = { | |
332 | [ C(OP_READ) ] = { | |
fecc8ac8 | 333 | [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ |
ad689220 TG |
334 | [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ |
335 | }, | |
336 | [ C(OP_WRITE) ] = { | |
fecc8ac8 | 337 | [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ |
ad689220 TG |
338 | [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ |
339 | }, | |
340 | [ C(OP_PREFETCH) ] = { | |
341 | [ C(RESULT_ACCESS) ] = 0, | |
342 | [ C(RESULT_MISS) ] = 0, | |
343 | }, | |
344 | }, | |
345 | [ C(ITLB) ] = { | |
346 | [ C(OP_READ) ] = { | |
347 | [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ | |
348 | [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ | |
349 | }, | |
350 | [ C(OP_WRITE) ] = { | |
351 | [ C(RESULT_ACCESS) ] = -1, | |
352 | [ C(RESULT_MISS) ] = -1, | |
353 | }, | |
354 | [ C(OP_PREFETCH) ] = { | |
355 | [ C(RESULT_ACCESS) ] = -1, | |
356 | [ C(RESULT_MISS) ] = -1, | |
357 | }, | |
358 | }, | |
359 | [ C(BPU ) ] = { | |
360 | [ C(OP_READ) ] = { | |
361 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ | |
362 | [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ | |
363 | }, | |
364 | [ C(OP_WRITE) ] = { | |
365 | [ C(RESULT_ACCESS) ] = -1, | |
366 | [ C(RESULT_MISS) ] = -1, | |
367 | }, | |
368 | [ C(OP_PREFETCH) ] = { | |
369 | [ C(RESULT_ACCESS) ] = -1, | |
370 | [ C(RESULT_MISS) ] = -1, | |
371 | }, | |
372 | }, | |
8326f44d IM |
373 | }; |
374 | ||
5f4ec28f | 375 | static u64 intel_pmu_raw_event(u64 event) |
b0f3f28e | 376 | { |
82bae4f8 PZ |
377 | #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL |
378 | #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL | |
ff99be57 PZ |
379 | #define CORE_EVNTSEL_EDGE_MASK 0x00040000ULL |
380 | #define CORE_EVNTSEL_INV_MASK 0x00800000ULL | |
82bae4f8 | 381 | #define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL |
b0f3f28e | 382 | |
128f048f | 383 | #define CORE_EVNTSEL_MASK \ |
b0f3f28e PZ |
384 | (CORE_EVNTSEL_EVENT_MASK | \ |
385 | CORE_EVNTSEL_UNIT_MASK | \ | |
ff99be57 PZ |
386 | CORE_EVNTSEL_EDGE_MASK | \ |
387 | CORE_EVNTSEL_INV_MASK | \ | |
b0f3f28e PZ |
388 | CORE_EVNTSEL_COUNTER_MASK) |
389 | ||
390 | return event & CORE_EVNTSEL_MASK; | |
391 | } | |
392 | ||
f4db43a3 | 393 | static const u64 amd_hw_cache_event_ids |
f86748e9 TG |
394 | [PERF_COUNT_HW_CACHE_MAX] |
395 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
396 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
397 | { | |
398 | [ C(L1D) ] = { | |
399 | [ C(OP_READ) ] = { | |
f4db43a3 JSR |
400 | [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */ |
401 | [ C(RESULT_MISS) ] = 0x0041, /* Data Cache Misses */ | |
f86748e9 TG |
402 | }, |
403 | [ C(OP_WRITE) ] = { | |
d9f2a5ec | 404 | [ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */ |
f86748e9 TG |
405 | [ C(RESULT_MISS) ] = 0, |
406 | }, | |
407 | [ C(OP_PREFETCH) ] = { | |
f4db43a3 JSR |
408 | [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */ |
409 | [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */ | |
f86748e9 TG |
410 | }, |
411 | }, | |
412 | [ C(L1I ) ] = { | |
413 | [ C(OP_READ) ] = { | |
414 | [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches */ | |
415 | [ C(RESULT_MISS) ] = 0x0081, /* Instruction cache misses */ | |
416 | }, | |
417 | [ C(OP_WRITE) ] = { | |
418 | [ C(RESULT_ACCESS) ] = -1, | |
419 | [ C(RESULT_MISS) ] = -1, | |
420 | }, | |
421 | [ C(OP_PREFETCH) ] = { | |
f4db43a3 | 422 | [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */ |
f86748e9 TG |
423 | [ C(RESULT_MISS) ] = 0, |
424 | }, | |
425 | }, | |
8be6e8f3 | 426 | [ C(LL ) ] = { |
f86748e9 | 427 | [ C(OP_READ) ] = { |
f4db43a3 JSR |
428 | [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */ |
429 | [ C(RESULT_MISS) ] = 0x037E, /* L2 Cache Misses : IC+DC */ | |
f86748e9 TG |
430 | }, |
431 | [ C(OP_WRITE) ] = { | |
f4db43a3 | 432 | [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback */ |
f86748e9 TG |
433 | [ C(RESULT_MISS) ] = 0, |
434 | }, | |
435 | [ C(OP_PREFETCH) ] = { | |
436 | [ C(RESULT_ACCESS) ] = 0, | |
437 | [ C(RESULT_MISS) ] = 0, | |
438 | }, | |
439 | }, | |
440 | [ C(DTLB) ] = { | |
441 | [ C(OP_READ) ] = { | |
f4db43a3 JSR |
442 | [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */ |
443 | [ C(RESULT_MISS) ] = 0x0046, /* L1 DTLB and L2 DLTB Miss */ | |
f86748e9 TG |
444 | }, |
445 | [ C(OP_WRITE) ] = { | |
446 | [ C(RESULT_ACCESS) ] = 0, | |
447 | [ C(RESULT_MISS) ] = 0, | |
448 | }, | |
449 | [ C(OP_PREFETCH) ] = { | |
450 | [ C(RESULT_ACCESS) ] = 0, | |
451 | [ C(RESULT_MISS) ] = 0, | |
452 | }, | |
453 | }, | |
454 | [ C(ITLB) ] = { | |
455 | [ C(OP_READ) ] = { | |
456 | [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes */ | |
457 | [ C(RESULT_MISS) ] = 0x0085, /* Instr. fetch ITLB misses */ | |
458 | }, | |
459 | [ C(OP_WRITE) ] = { | |
460 | [ C(RESULT_ACCESS) ] = -1, | |
461 | [ C(RESULT_MISS) ] = -1, | |
462 | }, | |
463 | [ C(OP_PREFETCH) ] = { | |
464 | [ C(RESULT_ACCESS) ] = -1, | |
465 | [ C(RESULT_MISS) ] = -1, | |
466 | }, | |
467 | }, | |
468 | [ C(BPU ) ] = { | |
469 | [ C(OP_READ) ] = { | |
470 | [ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr. */ | |
471 | [ C(RESULT_MISS) ] = 0x00c3, /* Retired Mispredicted BI */ | |
472 | }, | |
473 | [ C(OP_WRITE) ] = { | |
474 | [ C(RESULT_ACCESS) ] = -1, | |
475 | [ C(RESULT_MISS) ] = -1, | |
476 | }, | |
477 | [ C(OP_PREFETCH) ] = { | |
478 | [ C(RESULT_ACCESS) ] = -1, | |
479 | [ C(RESULT_MISS) ] = -1, | |
480 | }, | |
481 | }, | |
482 | }; | |
483 | ||
f87ad35d JSR |
484 | /* |
485 | * AMD Performance Monitor K7 and later. | |
486 | */ | |
b0f3f28e | 487 | static const u64 amd_perfmon_event_map[] = |
f87ad35d | 488 | { |
f4dbfa8f PZ |
489 | [PERF_COUNT_HW_CPU_CYCLES] = 0x0076, |
490 | [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, | |
491 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0080, | |
492 | [PERF_COUNT_HW_CACHE_MISSES] = 0x0081, | |
493 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, | |
494 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, | |
f87ad35d JSR |
495 | }; |
496 | ||
5f4ec28f | 497 | static u64 amd_pmu_event_map(int event) |
f87ad35d JSR |
498 | { |
499 | return amd_perfmon_event_map[event]; | |
500 | } | |
501 | ||
5f4ec28f | 502 | static u64 amd_pmu_raw_event(u64 event) |
b0f3f28e | 503 | { |
82bae4f8 PZ |
504 | #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL |
505 | #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL | |
ff99be57 PZ |
506 | #define K7_EVNTSEL_EDGE_MASK 0x000040000ULL |
507 | #define K7_EVNTSEL_INV_MASK 0x000800000ULL | |
82bae4f8 | 508 | #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL |
b0f3f28e PZ |
509 | |
510 | #define K7_EVNTSEL_MASK \ | |
511 | (K7_EVNTSEL_EVENT_MASK | \ | |
512 | K7_EVNTSEL_UNIT_MASK | \ | |
ff99be57 PZ |
513 | K7_EVNTSEL_EDGE_MASK | \ |
514 | K7_EVNTSEL_INV_MASK | \ | |
b0f3f28e PZ |
515 | K7_EVNTSEL_COUNTER_MASK) |
516 | ||
517 | return event & K7_EVNTSEL_MASK; | |
518 | } | |
519 | ||
ee06094f IM |
520 | /* |
521 | * Propagate counter elapsed time into the generic counter. | |
522 | * Can only be executed on the CPU where the counter is active. | |
523 | * Returns the delta events processed. | |
524 | */ | |
4b7bfd0d | 525 | static u64 |
ee06094f IM |
526 | x86_perf_counter_update(struct perf_counter *counter, |
527 | struct hw_perf_counter *hwc, int idx) | |
528 | { | |
ec3232bd PZ |
529 | int shift = 64 - x86_pmu.counter_bits; |
530 | u64 prev_raw_count, new_raw_count; | |
531 | s64 delta; | |
ee06094f | 532 | |
ee06094f IM |
533 | /* |
534 | * Careful: an NMI might modify the previous counter value. | |
535 | * | |
536 | * Our tactic to handle this is to first atomically read and | |
537 | * exchange a new raw count - then add that new-prev delta | |
538 | * count to the generic counter atomically: | |
539 | */ | |
540 | again: | |
541 | prev_raw_count = atomic64_read(&hwc->prev_count); | |
542 | rdmsrl(hwc->counter_base + idx, new_raw_count); | |
543 | ||
544 | if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count, | |
545 | new_raw_count) != prev_raw_count) | |
546 | goto again; | |
547 | ||
548 | /* | |
549 | * Now we have the new raw value and have updated the prev | |
550 | * timestamp already. We can now calculate the elapsed delta | |
551 | * (counter-)time and add that to the generic counter. | |
552 | * | |
553 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 554 | * of the count. |
ee06094f | 555 | */ |
ec3232bd PZ |
556 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
557 | delta >>= shift; | |
ee06094f IM |
558 | |
559 | atomic64_add(delta, &counter->count); | |
560 | atomic64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
561 | |
562 | return new_raw_count; | |
ee06094f IM |
563 | } |
564 | ||
ba77813a | 565 | static atomic_t active_counters; |
4e935e47 PZ |
566 | static DEFINE_MUTEX(pmc_reserve_mutex); |
567 | ||
568 | static bool reserve_pmc_hardware(void) | |
569 | { | |
570 | int i; | |
571 | ||
572 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
573 | disable_lapic_nmi_watchdog(); | |
574 | ||
0933e5c6 | 575 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 | 576 | if (!reserve_perfctr_nmi(x86_pmu.perfctr + i)) |
4e935e47 PZ |
577 | goto perfctr_fail; |
578 | } | |
579 | ||
0933e5c6 | 580 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 | 581 | if (!reserve_evntsel_nmi(x86_pmu.eventsel + i)) |
4e935e47 PZ |
582 | goto eventsel_fail; |
583 | } | |
584 | ||
585 | return true; | |
586 | ||
587 | eventsel_fail: | |
588 | for (i--; i >= 0; i--) | |
4a06bd85 | 589 | release_evntsel_nmi(x86_pmu.eventsel + i); |
4e935e47 | 590 | |
0933e5c6 | 591 | i = x86_pmu.num_counters; |
4e935e47 PZ |
592 | |
593 | perfctr_fail: | |
594 | for (i--; i >= 0; i--) | |
4a06bd85 | 595 | release_perfctr_nmi(x86_pmu.perfctr + i); |
4e935e47 PZ |
596 | |
597 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
598 | enable_lapic_nmi_watchdog(); | |
599 | ||
600 | return false; | |
601 | } | |
602 | ||
603 | static void release_pmc_hardware(void) | |
604 | { | |
605 | int i; | |
606 | ||
0933e5c6 | 607 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 RR |
608 | release_perfctr_nmi(x86_pmu.perfctr + i); |
609 | release_evntsel_nmi(x86_pmu.eventsel + i); | |
4e935e47 PZ |
610 | } |
611 | ||
612 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
613 | enable_lapic_nmi_watchdog(); | |
614 | } | |
615 | ||
616 | static void hw_perf_counter_destroy(struct perf_counter *counter) | |
617 | { | |
ba77813a | 618 | if (atomic_dec_and_mutex_lock(&active_counters, &pmc_reserve_mutex)) { |
4e935e47 PZ |
619 | release_pmc_hardware(); |
620 | mutex_unlock(&pmc_reserve_mutex); | |
621 | } | |
622 | } | |
623 | ||
85cf9dba RR |
624 | static inline int x86_pmu_initialized(void) |
625 | { | |
626 | return x86_pmu.handle_irq != NULL; | |
627 | } | |
628 | ||
8326f44d IM |
629 | static inline int |
630 | set_ext_hw_attr(struct hw_perf_counter *hwc, struct perf_counter_attr *attr) | |
631 | { | |
632 | unsigned int cache_type, cache_op, cache_result; | |
633 | u64 config, val; | |
634 | ||
635 | config = attr->config; | |
636 | ||
637 | cache_type = (config >> 0) & 0xff; | |
638 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
639 | return -EINVAL; | |
640 | ||
641 | cache_op = (config >> 8) & 0xff; | |
642 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
643 | return -EINVAL; | |
644 | ||
645 | cache_result = (config >> 16) & 0xff; | |
646 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
647 | return -EINVAL; | |
648 | ||
649 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
650 | ||
651 | if (val == 0) | |
652 | return -ENOENT; | |
653 | ||
654 | if (val == -1) | |
655 | return -EINVAL; | |
656 | ||
657 | hwc->config |= val; | |
658 | ||
659 | return 0; | |
660 | } | |
661 | ||
241771ef | 662 | /* |
0d48696f | 663 | * Setup the hardware configuration for a given attr_type |
241771ef | 664 | */ |
621a01ea | 665 | static int __hw_perf_counter_init(struct perf_counter *counter) |
241771ef | 666 | { |
0d48696f | 667 | struct perf_counter_attr *attr = &counter->attr; |
241771ef | 668 | struct hw_perf_counter *hwc = &counter->hw; |
4e935e47 | 669 | int err; |
241771ef | 670 | |
85cf9dba RR |
671 | if (!x86_pmu_initialized()) |
672 | return -ENODEV; | |
241771ef | 673 | |
4e935e47 | 674 | err = 0; |
ba77813a | 675 | if (!atomic_inc_not_zero(&active_counters)) { |
4e935e47 | 676 | mutex_lock(&pmc_reserve_mutex); |
ba77813a | 677 | if (atomic_read(&active_counters) == 0 && !reserve_pmc_hardware()) |
4e935e47 PZ |
678 | err = -EBUSY; |
679 | else | |
ba77813a | 680 | atomic_inc(&active_counters); |
4e935e47 PZ |
681 | mutex_unlock(&pmc_reserve_mutex); |
682 | } | |
683 | if (err) | |
684 | return err; | |
685 | ||
241771ef | 686 | /* |
0475f9ea | 687 | * Generate PMC IRQs: |
241771ef IM |
688 | * (keep 'enabled' bit clear for now) |
689 | */ | |
0475f9ea | 690 | hwc->config = ARCH_PERFMON_EVENTSEL_INT; |
241771ef IM |
691 | |
692 | /* | |
0475f9ea | 693 | * Count user and OS events unless requested not to. |
241771ef | 694 | */ |
0d48696f | 695 | if (!attr->exclude_user) |
0475f9ea | 696 | hwc->config |= ARCH_PERFMON_EVENTSEL_USR; |
0d48696f | 697 | if (!attr->exclude_kernel) |
241771ef | 698 | hwc->config |= ARCH_PERFMON_EVENTSEL_OS; |
0475f9ea | 699 | |
bd2b5b12 | 700 | if (!hwc->sample_period) { |
b23f3325 | 701 | hwc->sample_period = x86_pmu.max_period; |
9e350de3 | 702 | hwc->last_period = hwc->sample_period; |
bd2b5b12 PZ |
703 | atomic64_set(&hwc->period_left, hwc->sample_period); |
704 | } | |
d2517a49 | 705 | |
8326f44d | 706 | counter->destroy = hw_perf_counter_destroy; |
241771ef IM |
707 | |
708 | /* | |
dfa7c899 | 709 | * Raw event type provide the config in the event structure |
241771ef | 710 | */ |
a21ca2ca IM |
711 | if (attr->type == PERF_TYPE_RAW) { |
712 | hwc->config |= x86_pmu.raw_event(attr->config); | |
8326f44d | 713 | return 0; |
241771ef | 714 | } |
241771ef | 715 | |
8326f44d IM |
716 | if (attr->type == PERF_TYPE_HW_CACHE) |
717 | return set_ext_hw_attr(hwc, attr); | |
718 | ||
719 | if (attr->config >= x86_pmu.max_events) | |
720 | return -EINVAL; | |
721 | /* | |
722 | * The generic map: | |
723 | */ | |
724 | hwc->config |= x86_pmu.event_map(attr->config); | |
4e935e47 | 725 | |
241771ef IM |
726 | return 0; |
727 | } | |
728 | ||
9e35ad38 | 729 | static void intel_pmu_disable_all(void) |
4ac13294 | 730 | { |
862a1a5f | 731 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); |
241771ef | 732 | } |
b56a3802 | 733 | |
9e35ad38 | 734 | static void amd_pmu_disable_all(void) |
f87ad35d | 735 | { |
b0f3f28e | 736 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
9e35ad38 PZ |
737 | int idx; |
738 | ||
739 | if (!cpuc->enabled) | |
740 | return; | |
b0f3f28e | 741 | |
b0f3f28e | 742 | cpuc->enabled = 0; |
60b3df9c PZ |
743 | /* |
744 | * ensure we write the disable before we start disabling the | |
5f4ec28f RR |
745 | * counters proper, so that amd_pmu_enable_counter() does the |
746 | * right thing. | |
60b3df9c | 747 | */ |
b0f3f28e | 748 | barrier(); |
f87ad35d | 749 | |
0933e5c6 | 750 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
751 | u64 val; |
752 | ||
43f6201a | 753 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 754 | continue; |
f87ad35d | 755 | rdmsrl(MSR_K7_EVNTSEL0 + idx, val); |
4295ee62 RR |
756 | if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE)) |
757 | continue; | |
758 | val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE; | |
759 | wrmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
f87ad35d | 760 | } |
f87ad35d JSR |
761 | } |
762 | ||
9e35ad38 | 763 | void hw_perf_disable(void) |
b56a3802 | 764 | { |
85cf9dba | 765 | if (!x86_pmu_initialized()) |
9e35ad38 PZ |
766 | return; |
767 | return x86_pmu.disable_all(); | |
b56a3802 | 768 | } |
241771ef | 769 | |
9e35ad38 | 770 | static void intel_pmu_enable_all(void) |
b56a3802 | 771 | { |
9e35ad38 | 772 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl); |
b56a3802 JSR |
773 | } |
774 | ||
9e35ad38 | 775 | static void amd_pmu_enable_all(void) |
f87ad35d | 776 | { |
b0f3f28e | 777 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
f87ad35d JSR |
778 | int idx; |
779 | ||
9e35ad38 | 780 | if (cpuc->enabled) |
b0f3f28e PZ |
781 | return; |
782 | ||
9e35ad38 PZ |
783 | cpuc->enabled = 1; |
784 | barrier(); | |
785 | ||
0933e5c6 | 786 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
4295ee62 | 787 | u64 val; |
b0f3f28e | 788 | |
43f6201a | 789 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 RR |
790 | continue; |
791 | rdmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
792 | if (val & ARCH_PERFMON_EVENTSEL0_ENABLE) | |
793 | continue; | |
794 | val |= ARCH_PERFMON_EVENTSEL0_ENABLE; | |
795 | wrmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
f87ad35d JSR |
796 | } |
797 | } | |
798 | ||
9e35ad38 | 799 | void hw_perf_enable(void) |
ee06094f | 800 | { |
85cf9dba | 801 | if (!x86_pmu_initialized()) |
2b9ff0db | 802 | return; |
9e35ad38 | 803 | x86_pmu.enable_all(); |
ee06094f | 804 | } |
ee06094f | 805 | |
19d84dab | 806 | static inline u64 intel_pmu_get_status(void) |
b0f3f28e PZ |
807 | { |
808 | u64 status; | |
809 | ||
b7f8859a | 810 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); |
b0f3f28e | 811 | |
b7f8859a | 812 | return status; |
b0f3f28e PZ |
813 | } |
814 | ||
dee5d906 | 815 | static inline void intel_pmu_ack_status(u64 ack) |
b0f3f28e PZ |
816 | { |
817 | wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); | |
818 | } | |
819 | ||
7c90cc45 | 820 | static inline void x86_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) |
b0f3f28e | 821 | { |
7c90cc45 | 822 | int err; |
7c90cc45 RR |
823 | err = checking_wrmsrl(hwc->config_base + idx, |
824 | hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE); | |
b0f3f28e PZ |
825 | } |
826 | ||
d4369891 | 827 | static inline void x86_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) |
b0f3f28e | 828 | { |
d4369891 | 829 | int err; |
d4369891 RR |
830 | err = checking_wrmsrl(hwc->config_base + idx, |
831 | hwc->config); | |
b0f3f28e PZ |
832 | } |
833 | ||
2f18d1e8 | 834 | static inline void |
d4369891 | 835 | intel_pmu_disable_fixed(struct hw_perf_counter *hwc, int __idx) |
2f18d1e8 IM |
836 | { |
837 | int idx = __idx - X86_PMC_IDX_FIXED; | |
838 | u64 ctrl_val, mask; | |
839 | int err; | |
840 | ||
841 | mask = 0xfULL << (idx * 4); | |
842 | ||
843 | rdmsrl(hwc->config_base, ctrl_val); | |
844 | ctrl_val &= ~mask; | |
845 | err = checking_wrmsrl(hwc->config_base, ctrl_val); | |
846 | } | |
847 | ||
7e2ae347 | 848 | static inline void |
d4369891 | 849 | intel_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) |
7e2ae347 | 850 | { |
d4369891 RR |
851 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { |
852 | intel_pmu_disable_fixed(hwc, idx); | |
853 | return; | |
854 | } | |
855 | ||
856 | x86_pmu_disable_counter(hwc, idx); | |
857 | } | |
858 | ||
859 | static inline void | |
860 | amd_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) | |
861 | { | |
862 | x86_pmu_disable_counter(hwc, idx); | |
7e2ae347 IM |
863 | } |
864 | ||
2f18d1e8 | 865 | static DEFINE_PER_CPU(u64, prev_left[X86_PMC_IDX_MAX]); |
241771ef | 866 | |
ee06094f IM |
867 | /* |
868 | * Set the next IRQ period, based on the hwc->period_left value. | |
869 | * To be called with the counter disabled in hw: | |
870 | */ | |
e4abb5d4 | 871 | static int |
26816c28 | 872 | x86_perf_counter_set_period(struct perf_counter *counter, |
ee06094f | 873 | struct hw_perf_counter *hwc, int idx) |
241771ef | 874 | { |
2f18d1e8 | 875 | s64 left = atomic64_read(&hwc->period_left); |
e4abb5d4 PZ |
876 | s64 period = hwc->sample_period; |
877 | int err, ret = 0; | |
ee06094f | 878 | |
ee06094f IM |
879 | /* |
880 | * If we are way outside a reasoable range then just skip forward: | |
881 | */ | |
882 | if (unlikely(left <= -period)) { | |
883 | left = period; | |
884 | atomic64_set(&hwc->period_left, left); | |
9e350de3 | 885 | hwc->last_period = period; |
e4abb5d4 | 886 | ret = 1; |
ee06094f IM |
887 | } |
888 | ||
889 | if (unlikely(left <= 0)) { | |
890 | left += period; | |
891 | atomic64_set(&hwc->period_left, left); | |
9e350de3 | 892 | hwc->last_period = period; |
e4abb5d4 | 893 | ret = 1; |
ee06094f | 894 | } |
1c80f4b5 IM |
895 | /* |
896 | * Quirk: certain CPUs dont like it if just 1 event is left: | |
897 | */ | |
898 | if (unlikely(left < 2)) | |
899 | left = 2; | |
241771ef | 900 | |
e4abb5d4 PZ |
901 | if (left > x86_pmu.max_period) |
902 | left = x86_pmu.max_period; | |
903 | ||
ee06094f IM |
904 | per_cpu(prev_left[idx], smp_processor_id()) = left; |
905 | ||
906 | /* | |
907 | * The hw counter starts counting from this counter offset, | |
908 | * mark it to be able to extra future deltas: | |
909 | */ | |
2f18d1e8 | 910 | atomic64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 911 | |
2f18d1e8 | 912 | err = checking_wrmsrl(hwc->counter_base + idx, |
0933e5c6 | 913 | (u64)(-left) & x86_pmu.counter_mask); |
e4abb5d4 | 914 | |
194002b2 PZ |
915 | perf_counter_update_userpage(counter); |
916 | ||
e4abb5d4 | 917 | return ret; |
2f18d1e8 IM |
918 | } |
919 | ||
920 | static inline void | |
7c90cc45 | 921 | intel_pmu_enable_fixed(struct hw_perf_counter *hwc, int __idx) |
2f18d1e8 IM |
922 | { |
923 | int idx = __idx - X86_PMC_IDX_FIXED; | |
924 | u64 ctrl_val, bits, mask; | |
925 | int err; | |
926 | ||
927 | /* | |
0475f9ea PM |
928 | * Enable IRQ generation (0x8), |
929 | * and enable ring-3 counting (0x2) and ring-0 counting (0x1) | |
930 | * if requested: | |
2f18d1e8 | 931 | */ |
0475f9ea PM |
932 | bits = 0x8ULL; |
933 | if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) | |
934 | bits |= 0x2; | |
2f18d1e8 IM |
935 | if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) |
936 | bits |= 0x1; | |
937 | bits <<= (idx * 4); | |
938 | mask = 0xfULL << (idx * 4); | |
939 | ||
940 | rdmsrl(hwc->config_base, ctrl_val); | |
941 | ctrl_val &= ~mask; | |
942 | ctrl_val |= bits; | |
943 | err = checking_wrmsrl(hwc->config_base, ctrl_val); | |
7e2ae347 IM |
944 | } |
945 | ||
7c90cc45 | 946 | static void intel_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) |
7e2ae347 | 947 | { |
7c90cc45 RR |
948 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { |
949 | intel_pmu_enable_fixed(hwc, idx); | |
950 | return; | |
951 | } | |
952 | ||
953 | x86_pmu_enable_counter(hwc, idx); | |
954 | } | |
955 | ||
956 | static void amd_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) | |
957 | { | |
958 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
959 | ||
960 | if (cpuc->enabled) | |
961 | x86_pmu_enable_counter(hwc, idx); | |
2b583d8b | 962 | else |
d4369891 | 963 | x86_pmu_disable_counter(hwc, idx); |
241771ef IM |
964 | } |
965 | ||
2f18d1e8 IM |
966 | static int |
967 | fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc) | |
862a1a5f | 968 | { |
2f18d1e8 IM |
969 | unsigned int event; |
970 | ||
ef7b3e09 | 971 | if (!x86_pmu.num_counters_fixed) |
f87ad35d JSR |
972 | return -1; |
973 | ||
2f18d1e8 IM |
974 | event = hwc->config & ARCH_PERFMON_EVENT_MASK; |
975 | ||
f4dbfa8f | 976 | if (unlikely(event == x86_pmu.event_map(PERF_COUNT_HW_INSTRUCTIONS))) |
2f18d1e8 | 977 | return X86_PMC_IDX_FIXED_INSTRUCTIONS; |
f4dbfa8f | 978 | if (unlikely(event == x86_pmu.event_map(PERF_COUNT_HW_CPU_CYCLES))) |
2f18d1e8 | 979 | return X86_PMC_IDX_FIXED_CPU_CYCLES; |
f4dbfa8f | 980 | if (unlikely(event == x86_pmu.event_map(PERF_COUNT_HW_BUS_CYCLES))) |
2f18d1e8 IM |
981 | return X86_PMC_IDX_FIXED_BUS_CYCLES; |
982 | ||
862a1a5f IM |
983 | return -1; |
984 | } | |
985 | ||
ee06094f IM |
986 | /* |
987 | * Find a PMC slot for the freshly enabled / scheduled in counter: | |
988 | */ | |
4aeb0b42 | 989 | static int x86_pmu_enable(struct perf_counter *counter) |
241771ef IM |
990 | { |
991 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
992 | struct hw_perf_counter *hwc = &counter->hw; | |
2f18d1e8 | 993 | int idx; |
241771ef | 994 | |
2f18d1e8 IM |
995 | idx = fixed_mode_idx(counter, hwc); |
996 | if (idx >= 0) { | |
997 | /* | |
998 | * Try to get the fixed counter, if that is already taken | |
999 | * then try to get a generic counter: | |
1000 | */ | |
43f6201a | 1001 | if (test_and_set_bit(idx, cpuc->used_mask)) |
2f18d1e8 | 1002 | goto try_generic; |
0dff86aa | 1003 | |
2f18d1e8 IM |
1004 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
1005 | /* | |
1006 | * We set it so that counter_base + idx in wrmsr/rdmsr maps to | |
1007 | * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2: | |
1008 | */ | |
1009 | hwc->counter_base = | |
1010 | MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED; | |
241771ef | 1011 | hwc->idx = idx; |
2f18d1e8 IM |
1012 | } else { |
1013 | idx = hwc->idx; | |
1014 | /* Try to get the previous generic counter again */ | |
43f6201a | 1015 | if (test_and_set_bit(idx, cpuc->used_mask)) { |
2f18d1e8 | 1016 | try_generic: |
43f6201a | 1017 | idx = find_first_zero_bit(cpuc->used_mask, |
0933e5c6 RR |
1018 | x86_pmu.num_counters); |
1019 | if (idx == x86_pmu.num_counters) | |
2f18d1e8 IM |
1020 | return -EAGAIN; |
1021 | ||
43f6201a | 1022 | set_bit(idx, cpuc->used_mask); |
2f18d1e8 IM |
1023 | hwc->idx = idx; |
1024 | } | |
4a06bd85 RR |
1025 | hwc->config_base = x86_pmu.eventsel; |
1026 | hwc->counter_base = x86_pmu.perfctr; | |
241771ef IM |
1027 | } |
1028 | ||
c323d95f | 1029 | perf_counters_lapic_init(); |
53b441a5 | 1030 | |
d4369891 | 1031 | x86_pmu.disable(hwc, idx); |
241771ef | 1032 | |
862a1a5f | 1033 | cpuc->counters[idx] = counter; |
43f6201a | 1034 | set_bit(idx, cpuc->active_mask); |
7e2ae347 | 1035 | |
26816c28 | 1036 | x86_perf_counter_set_period(counter, hwc, idx); |
7c90cc45 | 1037 | x86_pmu.enable(hwc, idx); |
95cdd2e7 | 1038 | |
194002b2 PZ |
1039 | perf_counter_update_userpage(counter); |
1040 | ||
95cdd2e7 | 1041 | return 0; |
241771ef IM |
1042 | } |
1043 | ||
a78ac325 PZ |
1044 | static void x86_pmu_unthrottle(struct perf_counter *counter) |
1045 | { | |
1046 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
1047 | struct hw_perf_counter *hwc = &counter->hw; | |
1048 | ||
1049 | if (WARN_ON_ONCE(hwc->idx >= X86_PMC_IDX_MAX || | |
1050 | cpuc->counters[hwc->idx] != counter)) | |
1051 | return; | |
1052 | ||
1053 | x86_pmu.enable(hwc, hwc->idx); | |
1054 | } | |
1055 | ||
241771ef IM |
1056 | void perf_counter_print_debug(void) |
1057 | { | |
2f18d1e8 | 1058 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
0dff86aa | 1059 | struct cpu_hw_counters *cpuc; |
5bb9efe3 | 1060 | unsigned long flags; |
1e125676 IM |
1061 | int cpu, idx; |
1062 | ||
0933e5c6 | 1063 | if (!x86_pmu.num_counters) |
1e125676 | 1064 | return; |
241771ef | 1065 | |
5bb9efe3 | 1066 | local_irq_save(flags); |
241771ef IM |
1067 | |
1068 | cpu = smp_processor_id(); | |
0dff86aa | 1069 | cpuc = &per_cpu(cpu_hw_counters, cpu); |
241771ef | 1070 | |
faa28ae0 | 1071 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1072 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1073 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1074 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1075 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
1076 | ||
1077 | pr_info("\n"); | |
1078 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1079 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1080 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1081 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
f87ad35d | 1082 | } |
43f6201a | 1083 | pr_info("CPU#%d: used: %016llx\n", cpu, *(u64 *)cpuc->used_mask); |
241771ef | 1084 | |
0933e5c6 | 1085 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
4a06bd85 RR |
1086 | rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl); |
1087 | rdmsrl(x86_pmu.perfctr + idx, pmc_count); | |
241771ef | 1088 | |
ee06094f | 1089 | prev_left = per_cpu(prev_left[idx], cpu); |
241771ef | 1090 | |
a1ef58f4 | 1091 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1092 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1093 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1094 | cpu, idx, pmc_count); |
a1ef58f4 | 1095 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1096 | cpu, idx, prev_left); |
241771ef | 1097 | } |
0933e5c6 | 1098 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
1099 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1100 | ||
a1ef58f4 | 1101 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1102 | cpu, idx, pmc_count); |
1103 | } | |
5bb9efe3 | 1104 | local_irq_restore(flags); |
241771ef IM |
1105 | } |
1106 | ||
4aeb0b42 | 1107 | static void x86_pmu_disable(struct perf_counter *counter) |
241771ef IM |
1108 | { |
1109 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
1110 | struct hw_perf_counter *hwc = &counter->hw; | |
6f00cada | 1111 | int idx = hwc->idx; |
241771ef | 1112 | |
09534238 RR |
1113 | /* |
1114 | * Must be done before we disable, otherwise the nmi handler | |
1115 | * could reenable again: | |
1116 | */ | |
43f6201a | 1117 | clear_bit(idx, cpuc->active_mask); |
d4369891 | 1118 | x86_pmu.disable(hwc, idx); |
241771ef | 1119 | |
2f18d1e8 IM |
1120 | /* |
1121 | * Make sure the cleared pointer becomes visible before we | |
1122 | * (potentially) free the counter: | |
1123 | */ | |
527e26af | 1124 | barrier(); |
241771ef | 1125 | |
ee06094f IM |
1126 | /* |
1127 | * Drain the remaining delta count out of a counter | |
1128 | * that we are disabling: | |
1129 | */ | |
1130 | x86_perf_counter_update(counter, hwc, idx); | |
09534238 | 1131 | cpuc->counters[idx] = NULL; |
43f6201a | 1132 | clear_bit(idx, cpuc->used_mask); |
194002b2 PZ |
1133 | |
1134 | perf_counter_update_userpage(counter); | |
241771ef IM |
1135 | } |
1136 | ||
7e2ae347 | 1137 | /* |
ee06094f IM |
1138 | * Save and restart an expired counter. Called by NMI contexts, |
1139 | * so it has to be careful about preempting normal counter ops: | |
7e2ae347 | 1140 | */ |
e4abb5d4 | 1141 | static int intel_pmu_save_and_restart(struct perf_counter *counter) |
241771ef IM |
1142 | { |
1143 | struct hw_perf_counter *hwc = &counter->hw; | |
1144 | int idx = hwc->idx; | |
e4abb5d4 | 1145 | int ret; |
241771ef | 1146 | |
ee06094f | 1147 | x86_perf_counter_update(counter, hwc, idx); |
e4abb5d4 | 1148 | ret = x86_perf_counter_set_period(counter, hwc, idx); |
7e2ae347 | 1149 | |
2f18d1e8 | 1150 | if (counter->state == PERF_COUNTER_STATE_ACTIVE) |
7c90cc45 | 1151 | intel_pmu_enable_counter(hwc, idx); |
e4abb5d4 PZ |
1152 | |
1153 | return ret; | |
241771ef IM |
1154 | } |
1155 | ||
aaba9801 IM |
1156 | static void intel_pmu_reset(void) |
1157 | { | |
1158 | unsigned long flags; | |
1159 | int idx; | |
1160 | ||
1161 | if (!x86_pmu.num_counters) | |
1162 | return; | |
1163 | ||
1164 | local_irq_save(flags); | |
1165 | ||
1166 | printk("clearing PMU state on CPU#%d\n", smp_processor_id()); | |
1167 | ||
1168 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { | |
1169 | checking_wrmsrl(x86_pmu.eventsel + idx, 0ull); | |
1170 | checking_wrmsrl(x86_pmu.perfctr + idx, 0ull); | |
1171 | } | |
1172 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { | |
1173 | checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); | |
1174 | } | |
1175 | ||
1176 | local_irq_restore(flags); | |
1177 | } | |
1178 | ||
1179 | ||
241771ef IM |
1180 | /* |
1181 | * This handler is triggered by the local APIC, so the APIC IRQ handling | |
1182 | * rules apply: | |
1183 | */ | |
a3288106 | 1184 | static int intel_pmu_handle_irq(struct pt_regs *regs) |
241771ef | 1185 | { |
df1a132b | 1186 | struct perf_sample_data data; |
9029a5e3 | 1187 | struct cpu_hw_counters *cpuc; |
9029a5e3 | 1188 | int bit, cpu, loops; |
4b39fd96 | 1189 | u64 ack, status; |
9029a5e3 | 1190 | |
df1a132b PZ |
1191 | data.regs = regs; |
1192 | data.addr = 0; | |
1193 | ||
9029a5e3 IM |
1194 | cpu = smp_processor_id(); |
1195 | cpuc = &per_cpu(cpu_hw_counters, cpu); | |
241771ef | 1196 | |
9e35ad38 | 1197 | perf_disable(); |
19d84dab | 1198 | status = intel_pmu_get_status(); |
9e35ad38 PZ |
1199 | if (!status) { |
1200 | perf_enable(); | |
1201 | return 0; | |
1202 | } | |
87b9cf46 | 1203 | |
9029a5e3 | 1204 | loops = 0; |
241771ef | 1205 | again: |
9029a5e3 IM |
1206 | if (++loops > 100) { |
1207 | WARN_ONCE(1, "perfcounters: irq loop stuck!\n"); | |
34adc806 | 1208 | perf_counter_print_debug(); |
aaba9801 IM |
1209 | intel_pmu_reset(); |
1210 | perf_enable(); | |
9029a5e3 IM |
1211 | return 1; |
1212 | } | |
1213 | ||
d278c484 | 1214 | inc_irq_stat(apic_perf_irqs); |
241771ef | 1215 | ack = status; |
2f18d1e8 | 1216 | for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { |
862a1a5f | 1217 | struct perf_counter *counter = cpuc->counters[bit]; |
241771ef IM |
1218 | |
1219 | clear_bit(bit, (unsigned long *) &status); | |
43f6201a | 1220 | if (!test_bit(bit, cpuc->active_mask)) |
241771ef IM |
1221 | continue; |
1222 | ||
e4abb5d4 PZ |
1223 | if (!intel_pmu_save_and_restart(counter)) |
1224 | continue; | |
1225 | ||
60f916de PZ |
1226 | data.period = counter->hw.last_period; |
1227 | ||
df1a132b | 1228 | if (perf_counter_overflow(counter, 1, &data)) |
d4369891 | 1229 | intel_pmu_disable_counter(&counter->hw, bit); |
241771ef IM |
1230 | } |
1231 | ||
dee5d906 | 1232 | intel_pmu_ack_status(ack); |
241771ef IM |
1233 | |
1234 | /* | |
1235 | * Repeat if there is more work to be done: | |
1236 | */ | |
19d84dab | 1237 | status = intel_pmu_get_status(); |
241771ef IM |
1238 | if (status) |
1239 | goto again; | |
b0f3f28e | 1240 | |
48e22d56 | 1241 | perf_enable(); |
9e35ad38 PZ |
1242 | |
1243 | return 1; | |
1b023a96 MG |
1244 | } |
1245 | ||
a3288106 | 1246 | static int amd_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1247 | { |
df1a132b | 1248 | struct perf_sample_data data; |
9029a5e3 | 1249 | struct cpu_hw_counters *cpuc; |
a29aa8a7 RR |
1250 | struct perf_counter *counter; |
1251 | struct hw_perf_counter *hwc; | |
df1a132b | 1252 | int cpu, idx, handled = 0; |
9029a5e3 IM |
1253 | u64 val; |
1254 | ||
df1a132b PZ |
1255 | data.regs = regs; |
1256 | data.addr = 0; | |
1257 | ||
9029a5e3 IM |
1258 | cpu = smp_processor_id(); |
1259 | cpuc = &per_cpu(cpu_hw_counters, cpu); | |
962bf7a6 | 1260 | |
a29aa8a7 | 1261 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
43f6201a | 1262 | if (!test_bit(idx, cpuc->active_mask)) |
a29aa8a7 | 1263 | continue; |
962bf7a6 | 1264 | |
a29aa8a7 RR |
1265 | counter = cpuc->counters[idx]; |
1266 | hwc = &counter->hw; | |
a4016a79 | 1267 | |
4b7bfd0d | 1268 | val = x86_perf_counter_update(counter, hwc, idx); |
a29aa8a7 | 1269 | if (val & (1ULL << (x86_pmu.counter_bits - 1))) |
48e22d56 | 1270 | continue; |
962bf7a6 | 1271 | |
9e350de3 PZ |
1272 | /* |
1273 | * counter overflow | |
1274 | */ | |
1275 | handled = 1; | |
1276 | data.period = counter->hw.last_period; | |
1277 | ||
e4abb5d4 PZ |
1278 | if (!x86_perf_counter_set_period(counter, hwc, idx)) |
1279 | continue; | |
1280 | ||
df1a132b | 1281 | if (perf_counter_overflow(counter, 1, &data)) |
a29aa8a7 | 1282 | amd_pmu_disable_counter(hwc, idx); |
a29aa8a7 | 1283 | } |
962bf7a6 | 1284 | |
9e350de3 PZ |
1285 | if (handled) |
1286 | inc_irq_stat(apic_perf_irqs); | |
1287 | ||
a29aa8a7 RR |
1288 | return handled; |
1289 | } | |
39d81eab | 1290 | |
b6276f35 PZ |
1291 | void smp_perf_pending_interrupt(struct pt_regs *regs) |
1292 | { | |
1293 | irq_enter(); | |
1294 | ack_APIC_irq(); | |
1295 | inc_irq_stat(apic_pending_irqs); | |
1296 | perf_counter_do_pending(); | |
1297 | irq_exit(); | |
1298 | } | |
1299 | ||
1300 | void set_perf_counter_pending(void) | |
1301 | { | |
1302 | apic->send_IPI_self(LOCAL_PENDING_VECTOR); | |
1303 | } | |
1304 | ||
c323d95f | 1305 | void perf_counters_lapic_init(void) |
241771ef | 1306 | { |
85cf9dba | 1307 | if (!x86_pmu_initialized()) |
241771ef | 1308 | return; |
85cf9dba | 1309 | |
241771ef | 1310 | /* |
c323d95f | 1311 | * Always use NMI for PMU |
241771ef | 1312 | */ |
c323d95f | 1313 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1314 | } |
1315 | ||
1316 | static int __kprobes | |
1317 | perf_counter_nmi_handler(struct notifier_block *self, | |
1318 | unsigned long cmd, void *__args) | |
1319 | { | |
1320 | struct die_args *args = __args; | |
1321 | struct pt_regs *regs; | |
b0f3f28e | 1322 | |
ba77813a | 1323 | if (!atomic_read(&active_counters)) |
63a809a2 PZ |
1324 | return NOTIFY_DONE; |
1325 | ||
b0f3f28e PZ |
1326 | switch (cmd) { |
1327 | case DIE_NMI: | |
1328 | case DIE_NMI_IPI: | |
1329 | break; | |
241771ef | 1330 | |
b0f3f28e | 1331 | default: |
241771ef | 1332 | return NOTIFY_DONE; |
b0f3f28e | 1333 | } |
241771ef IM |
1334 | |
1335 | regs = args->regs; | |
1336 | ||
1337 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
a4016a79 PZ |
1338 | /* |
1339 | * Can't rely on the handled return value to say it was our NMI, two | |
1340 | * counters could trigger 'simultaneously' raising two back-to-back NMIs. | |
1341 | * | |
1342 | * If the first NMI handles both, the latter will be empty and daze | |
1343 | * the CPU. | |
1344 | */ | |
a3288106 | 1345 | x86_pmu.handle_irq(regs); |
241771ef | 1346 | |
a4016a79 | 1347 | return NOTIFY_STOP; |
241771ef IM |
1348 | } |
1349 | ||
1350 | static __read_mostly struct notifier_block perf_counter_nmi_notifier = { | |
5b75af0a MG |
1351 | .notifier_call = perf_counter_nmi_handler, |
1352 | .next = NULL, | |
1353 | .priority = 1 | |
241771ef IM |
1354 | }; |
1355 | ||
5f4ec28f | 1356 | static struct x86_pmu intel_pmu = { |
faa28ae0 | 1357 | .name = "Intel", |
39d81eab | 1358 | .handle_irq = intel_pmu_handle_irq, |
9e35ad38 PZ |
1359 | .disable_all = intel_pmu_disable_all, |
1360 | .enable_all = intel_pmu_enable_all, | |
5f4ec28f RR |
1361 | .enable = intel_pmu_enable_counter, |
1362 | .disable = intel_pmu_disable_counter, | |
b56a3802 JSR |
1363 | .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, |
1364 | .perfctr = MSR_ARCH_PERFMON_PERFCTR0, | |
5f4ec28f RR |
1365 | .event_map = intel_pmu_event_map, |
1366 | .raw_event = intel_pmu_raw_event, | |
b56a3802 | 1367 | .max_events = ARRAY_SIZE(intel_perfmon_event_map), |
c619b8ff RR |
1368 | /* |
1369 | * Intel PMCs cannot be accessed sanely above 32 bit width, | |
1370 | * so we install an artificial 1<<31 period regardless of | |
1371 | * the generic counter period: | |
1372 | */ | |
1373 | .max_period = (1ULL << 31) - 1, | |
b56a3802 JSR |
1374 | }; |
1375 | ||
5f4ec28f | 1376 | static struct x86_pmu amd_pmu = { |
faa28ae0 | 1377 | .name = "AMD", |
39d81eab | 1378 | .handle_irq = amd_pmu_handle_irq, |
9e35ad38 PZ |
1379 | .disable_all = amd_pmu_disable_all, |
1380 | .enable_all = amd_pmu_enable_all, | |
5f4ec28f RR |
1381 | .enable = amd_pmu_enable_counter, |
1382 | .disable = amd_pmu_disable_counter, | |
f87ad35d JSR |
1383 | .eventsel = MSR_K7_EVNTSEL0, |
1384 | .perfctr = MSR_K7_PERFCTR0, | |
5f4ec28f RR |
1385 | .event_map = amd_pmu_event_map, |
1386 | .raw_event = amd_pmu_raw_event, | |
f87ad35d | 1387 | .max_events = ARRAY_SIZE(amd_perfmon_event_map), |
0933e5c6 RR |
1388 | .num_counters = 4, |
1389 | .counter_bits = 48, | |
1390 | .counter_mask = (1ULL << 48) - 1, | |
c619b8ff RR |
1391 | /* use highest bit to detect overflow */ |
1392 | .max_period = (1ULL << 47) - 1, | |
f87ad35d JSR |
1393 | }; |
1394 | ||
72eae04d | 1395 | static int intel_pmu_init(void) |
241771ef | 1396 | { |
7bb497bd | 1397 | union cpuid10_edx edx; |
241771ef | 1398 | union cpuid10_eax eax; |
703e937c | 1399 | unsigned int unused; |
7bb497bd | 1400 | unsigned int ebx; |
faa28ae0 | 1401 | int version; |
241771ef | 1402 | |
da1a776b | 1403 | if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) |
72eae04d | 1404 | return -ENODEV; |
da1a776b | 1405 | |
241771ef IM |
1406 | /* |
1407 | * Check whether the Architectural PerfMon supports | |
1408 | * Branch Misses Retired Event or not. | |
1409 | */ | |
703e937c | 1410 | cpuid(10, &eax.full, &ebx, &unused, &edx.full); |
241771ef | 1411 | if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED) |
72eae04d | 1412 | return -ENODEV; |
241771ef | 1413 | |
faa28ae0 RR |
1414 | version = eax.split.version_id; |
1415 | if (version < 2) | |
72eae04d | 1416 | return -ENODEV; |
7bb497bd | 1417 | |
1123e3ad IM |
1418 | x86_pmu = intel_pmu; |
1419 | x86_pmu.version = version; | |
1420 | x86_pmu.num_counters = eax.split.num_counters; | |
1421 | x86_pmu.counter_bits = eax.split.bit_width; | |
1422 | x86_pmu.counter_mask = (1ULL << eax.split.bit_width) - 1; | |
066d7dea IM |
1423 | |
1424 | /* | |
1425 | * Quirk: v2 perfmon does not report fixed-purpose counters, so | |
1426 | * assume at least 3 counters: | |
1427 | */ | |
1123e3ad | 1428 | x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3); |
b56a3802 | 1429 | |
8326f44d | 1430 | /* |
1123e3ad | 1431 | * Install the hw-cache-events table: |
8326f44d IM |
1432 | */ |
1433 | switch (boot_cpu_data.x86_model) { | |
dc81081b YW |
1434 | case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */ |
1435 | case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */ | |
1436 | case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */ | |
1437 | case 29: /* six-core 45 nm xeon "Dunnington" */ | |
8326f44d | 1438 | memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, |
820a6442 | 1439 | sizeof(hw_cache_event_ids)); |
8326f44d | 1440 | |
1123e3ad | 1441 | pr_cont("Core2 events, "); |
8326f44d IM |
1442 | break; |
1443 | default: | |
1444 | case 26: | |
1445 | memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, | |
820a6442 | 1446 | sizeof(hw_cache_event_ids)); |
8326f44d | 1447 | |
1123e3ad | 1448 | pr_cont("Nehalem/Corei7 events, "); |
8326f44d IM |
1449 | break; |
1450 | case 28: | |
1451 | memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, | |
820a6442 | 1452 | sizeof(hw_cache_event_ids)); |
8326f44d | 1453 | |
1123e3ad | 1454 | pr_cont("Atom events, "); |
8326f44d IM |
1455 | break; |
1456 | } | |
72eae04d | 1457 | return 0; |
b56a3802 JSR |
1458 | } |
1459 | ||
72eae04d | 1460 | static int amd_pmu_init(void) |
f87ad35d | 1461 | { |
4d2be126 JSR |
1462 | /* Performance-monitoring supported from K7 and later: */ |
1463 | if (boot_cpu_data.x86 < 6) | |
1464 | return -ENODEV; | |
1465 | ||
4a06bd85 | 1466 | x86_pmu = amd_pmu; |
f86748e9 | 1467 | |
f4db43a3 JSR |
1468 | /* Events are common for all AMDs */ |
1469 | memcpy(hw_cache_event_ids, amd_hw_cache_event_ids, | |
1470 | sizeof(hw_cache_event_ids)); | |
f86748e9 | 1471 | |
72eae04d | 1472 | return 0; |
f87ad35d JSR |
1473 | } |
1474 | ||
b56a3802 JSR |
1475 | void __init init_hw_perf_counters(void) |
1476 | { | |
72eae04d RR |
1477 | int err; |
1478 | ||
1123e3ad IM |
1479 | pr_info("Performance Counters: "); |
1480 | ||
b56a3802 JSR |
1481 | switch (boot_cpu_data.x86_vendor) { |
1482 | case X86_VENDOR_INTEL: | |
72eae04d | 1483 | err = intel_pmu_init(); |
b56a3802 | 1484 | break; |
f87ad35d | 1485 | case X86_VENDOR_AMD: |
72eae04d | 1486 | err = amd_pmu_init(); |
f87ad35d | 1487 | break; |
4138960a RR |
1488 | default: |
1489 | return; | |
b56a3802 | 1490 | } |
1123e3ad IM |
1491 | if (err != 0) { |
1492 | pr_cont("no PMU driver, software counters only.\n"); | |
b56a3802 | 1493 | return; |
1123e3ad | 1494 | } |
b56a3802 | 1495 | |
1123e3ad | 1496 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1497 | |
0933e5c6 | 1498 | if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) { |
241771ef | 1499 | WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!", |
0933e5c6 | 1500 | x86_pmu.num_counters, X86_PMC_MAX_GENERIC); |
4078c444 | 1501 | x86_pmu.num_counters = X86_PMC_MAX_GENERIC; |
241771ef | 1502 | } |
0933e5c6 RR |
1503 | perf_counter_mask = (1 << x86_pmu.num_counters) - 1; |
1504 | perf_max_counters = x86_pmu.num_counters; | |
241771ef | 1505 | |
0933e5c6 | 1506 | if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { |
703e937c | 1507 | WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!", |
0933e5c6 | 1508 | x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED); |
4078c444 | 1509 | x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; |
703e937c | 1510 | } |
862a1a5f | 1511 | |
0933e5c6 RR |
1512 | perf_counter_mask |= |
1513 | ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED; | |
c14dab5c | 1514 | x86_pmu.intel_ctrl = perf_counter_mask; |
241771ef | 1515 | |
c323d95f | 1516 | perf_counters_lapic_init(); |
241771ef | 1517 | register_die_notifier(&perf_counter_nmi_notifier); |
1123e3ad IM |
1518 | |
1519 | pr_info("... version: %d\n", x86_pmu.version); | |
1520 | pr_info("... bit width: %d\n", x86_pmu.counter_bits); | |
1521 | pr_info("... generic counters: %d\n", x86_pmu.num_counters); | |
1522 | pr_info("... value mask: %016Lx\n", x86_pmu.counter_mask); | |
1523 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); | |
1524 | pr_info("... fixed-purpose counters: %d\n", x86_pmu.num_counters_fixed); | |
1525 | pr_info("... counter mask: %016Lx\n", perf_counter_mask); | |
241771ef | 1526 | } |
621a01ea | 1527 | |
bb775fc2 | 1528 | static inline void x86_pmu_read(struct perf_counter *counter) |
ee06094f IM |
1529 | { |
1530 | x86_perf_counter_update(counter, &counter->hw, counter->hw.idx); | |
1531 | } | |
1532 | ||
4aeb0b42 RR |
1533 | static const struct pmu pmu = { |
1534 | .enable = x86_pmu_enable, | |
1535 | .disable = x86_pmu_disable, | |
1536 | .read = x86_pmu_read, | |
a78ac325 | 1537 | .unthrottle = x86_pmu_unthrottle, |
621a01ea IM |
1538 | }; |
1539 | ||
4aeb0b42 | 1540 | const struct pmu *hw_perf_counter_init(struct perf_counter *counter) |
621a01ea IM |
1541 | { |
1542 | int err; | |
1543 | ||
1544 | err = __hw_perf_counter_init(counter); | |
1545 | if (err) | |
9ea98e19 | 1546 | return ERR_PTR(err); |
621a01ea | 1547 | |
4aeb0b42 | 1548 | return &pmu; |
621a01ea | 1549 | } |
d7d59fb3 PZ |
1550 | |
1551 | /* | |
1552 | * callchain support | |
1553 | */ | |
1554 | ||
1555 | static inline | |
f9188e02 | 1556 | void callchain_store(struct perf_callchain_entry *entry, u64 ip) |
d7d59fb3 | 1557 | { |
f9188e02 | 1558 | if (entry->nr < PERF_MAX_STACK_DEPTH) |
d7d59fb3 PZ |
1559 | entry->ip[entry->nr++] = ip; |
1560 | } | |
1561 | ||
1562 | static DEFINE_PER_CPU(struct perf_callchain_entry, irq_entry); | |
1563 | static DEFINE_PER_CPU(struct perf_callchain_entry, nmi_entry); | |
0406ca6d | 1564 | static DEFINE_PER_CPU(int, in_nmi_frame); |
d7d59fb3 PZ |
1565 | |
1566 | ||
1567 | static void | |
1568 | backtrace_warning_symbol(void *data, char *msg, unsigned long symbol) | |
1569 | { | |
1570 | /* Ignore warnings */ | |
1571 | } | |
1572 | ||
1573 | static void backtrace_warning(void *data, char *msg) | |
1574 | { | |
1575 | /* Ignore warnings */ | |
1576 | } | |
1577 | ||
1578 | static int backtrace_stack(void *data, char *name) | |
1579 | { | |
0406ca6d FW |
1580 | per_cpu(in_nmi_frame, smp_processor_id()) = |
1581 | x86_is_stack_id(NMI_STACK, name); | |
1582 | ||
038e836e | 1583 | return 0; |
d7d59fb3 PZ |
1584 | } |
1585 | ||
1586 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1587 | { | |
1588 | struct perf_callchain_entry *entry = data; | |
1589 | ||
0406ca6d FW |
1590 | if (per_cpu(in_nmi_frame, smp_processor_id())) |
1591 | return; | |
1592 | ||
d7d59fb3 PZ |
1593 | if (reliable) |
1594 | callchain_store(entry, addr); | |
1595 | } | |
1596 | ||
1597 | static const struct stacktrace_ops backtrace_ops = { | |
1598 | .warning = backtrace_warning, | |
1599 | .warning_symbol = backtrace_warning_symbol, | |
1600 | .stack = backtrace_stack, | |
1601 | .address = backtrace_address, | |
1602 | }; | |
1603 | ||
038e836e IM |
1604 | #include "../dumpstack.h" |
1605 | ||
d7d59fb3 PZ |
1606 | static void |
1607 | perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1608 | { | |
f9188e02 | 1609 | callchain_store(entry, PERF_CONTEXT_KERNEL); |
038e836e | 1610 | callchain_store(entry, regs->ip); |
d7d59fb3 | 1611 | |
f9188e02 | 1612 | dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry); |
d7d59fb3 PZ |
1613 | } |
1614 | ||
74193ef0 PZ |
1615 | /* |
1616 | * best effort, GUP based copy_from_user() that assumes IRQ or NMI context | |
1617 | */ | |
1618 | static unsigned long | |
1619 | copy_from_user_nmi(void *to, const void __user *from, unsigned long n) | |
d7d59fb3 | 1620 | { |
74193ef0 PZ |
1621 | unsigned long offset, addr = (unsigned long)from; |
1622 | int type = in_nmi() ? KM_NMI : KM_IRQ0; | |
1623 | unsigned long size, len = 0; | |
1624 | struct page *page; | |
1625 | void *map; | |
d7d59fb3 PZ |
1626 | int ret; |
1627 | ||
74193ef0 PZ |
1628 | do { |
1629 | ret = __get_user_pages_fast(addr, 1, 0, &page); | |
1630 | if (!ret) | |
1631 | break; | |
d7d59fb3 | 1632 | |
74193ef0 PZ |
1633 | offset = addr & (PAGE_SIZE - 1); |
1634 | size = min(PAGE_SIZE - offset, n - len); | |
d7d59fb3 | 1635 | |
74193ef0 PZ |
1636 | map = kmap_atomic(page, type); |
1637 | memcpy(to, map+offset, size); | |
1638 | kunmap_atomic(map, type); | |
1639 | put_page(page); | |
1640 | ||
1641 | len += size; | |
1642 | to += size; | |
1643 | addr += size; | |
1644 | ||
1645 | } while (len < n); | |
1646 | ||
1647 | return len; | |
1648 | } | |
1649 | ||
1650 | static int copy_stack_frame(const void __user *fp, struct stack_frame *frame) | |
1651 | { | |
1652 | unsigned long bytes; | |
1653 | ||
1654 | bytes = copy_from_user_nmi(frame, fp, sizeof(*frame)); | |
1655 | ||
1656 | return bytes == sizeof(*frame); | |
d7d59fb3 PZ |
1657 | } |
1658 | ||
1659 | static void | |
1660 | perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1661 | { | |
1662 | struct stack_frame frame; | |
1663 | const void __user *fp; | |
1664 | ||
5a6cec3a IM |
1665 | if (!user_mode(regs)) |
1666 | regs = task_pt_regs(current); | |
1667 | ||
74193ef0 | 1668 | fp = (void __user *)regs->bp; |
d7d59fb3 | 1669 | |
f9188e02 | 1670 | callchain_store(entry, PERF_CONTEXT_USER); |
d7d59fb3 PZ |
1671 | callchain_store(entry, regs->ip); |
1672 | ||
f9188e02 | 1673 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
038e836e | 1674 | frame.next_frame = NULL; |
d7d59fb3 PZ |
1675 | frame.return_address = 0; |
1676 | ||
1677 | if (!copy_stack_frame(fp, &frame)) | |
1678 | break; | |
1679 | ||
5a6cec3a | 1680 | if ((unsigned long)fp < regs->sp) |
d7d59fb3 PZ |
1681 | break; |
1682 | ||
1683 | callchain_store(entry, frame.return_address); | |
038e836e | 1684 | fp = frame.next_frame; |
d7d59fb3 PZ |
1685 | } |
1686 | } | |
1687 | ||
1688 | static void | |
1689 | perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1690 | { | |
1691 | int is_user; | |
1692 | ||
1693 | if (!regs) | |
1694 | return; | |
1695 | ||
1696 | is_user = user_mode(regs); | |
1697 | ||
1698 | if (!current || current->pid == 0) | |
1699 | return; | |
1700 | ||
1701 | if (is_user && current->state != TASK_RUNNING) | |
1702 | return; | |
1703 | ||
1704 | if (!is_user) | |
1705 | perf_callchain_kernel(regs, entry); | |
1706 | ||
1707 | if (current->mm) | |
1708 | perf_callchain_user(regs, entry); | |
1709 | } | |
1710 | ||
1711 | struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) | |
1712 | { | |
1713 | struct perf_callchain_entry *entry; | |
1714 | ||
1715 | if (in_nmi()) | |
1716 | entry = &__get_cpu_var(nmi_entry); | |
1717 | else | |
1718 | entry = &__get_cpu_var(irq_entry); | |
1719 | ||
1720 | entry->nr = 0; | |
1721 | ||
1722 | perf_do_callchain(regs, entry); | |
1723 | ||
1724 | return entry; | |
1725 | } |