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Commit | Line | Data |
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241771ef IM |
1 | /* |
2 | * Performance counter x86 architecture code | |
3 | * | |
4 | * Copyright(C) 2008 Thomas Gleixner <tglx@linutronix.de> | |
5 | * Copyright(C) 2008 Red Hat, Inc., Ingo Molnar | |
b56a3802 | 6 | * Copyright(C) 2009 Jaswinder Singh Rajput |
39d81eab | 7 | * Copyright(C) 2009 Advanced Micro Devices, Inc., Robert Richter |
241771ef IM |
8 | * |
9 | * For licencing details see kernel-base/COPYING | |
10 | */ | |
11 | ||
12 | #include <linux/perf_counter.h> | |
13 | #include <linux/capability.h> | |
14 | #include <linux/notifier.h> | |
15 | #include <linux/hardirq.h> | |
16 | #include <linux/kprobes.h> | |
4ac13294 | 17 | #include <linux/module.h> |
241771ef IM |
18 | #include <linux/kdebug.h> |
19 | #include <linux/sched.h> | |
d7d59fb3 | 20 | #include <linux/uaccess.h> |
241771ef | 21 | |
241771ef | 22 | #include <asm/apic.h> |
d7d59fb3 | 23 | #include <asm/stacktrace.h> |
4e935e47 | 24 | #include <asm/nmi.h> |
241771ef IM |
25 | |
26 | static bool perf_counters_initialized __read_mostly; | |
27 | ||
28 | /* | |
29 | * Number of (generic) HW counters: | |
30 | */ | |
862a1a5f IM |
31 | static int nr_counters_generic __read_mostly; |
32 | static u64 perf_counter_mask __read_mostly; | |
2f18d1e8 | 33 | static u64 counter_value_mask __read_mostly; |
b0f3f28e | 34 | static int counter_value_bits __read_mostly; |
241771ef | 35 | |
862a1a5f | 36 | static int nr_counters_fixed __read_mostly; |
703e937c | 37 | |
241771ef | 38 | struct cpu_hw_counters { |
862a1a5f IM |
39 | struct perf_counter *counters[X86_PMC_IDX_MAX]; |
40 | unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
4b39fd96 | 41 | unsigned long interrupts; |
b0f3f28e | 42 | u64 throttle_ctrl; |
184fe4ab | 43 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
b0f3f28e | 44 | int enabled; |
241771ef IM |
45 | }; |
46 | ||
47 | /* | |
5f4ec28f | 48 | * struct x86_pmu - generic x86 pmu |
241771ef | 49 | */ |
5f4ec28f | 50 | struct x86_pmu { |
39d81eab | 51 | int (*handle_irq)(struct pt_regs *, int); |
169e41eb | 52 | u64 (*save_disable_all)(void); |
b0f3f28e | 53 | void (*restore_all)(u64); |
b0f3f28e PZ |
54 | void (*enable)(int, u64); |
55 | void (*disable)(int, u64); | |
169e41eb JSR |
56 | unsigned eventsel; |
57 | unsigned perfctr; | |
b0f3f28e PZ |
58 | u64 (*event_map)(int); |
59 | u64 (*raw_event)(u64); | |
169e41eb | 60 | int max_events; |
b56a3802 JSR |
61 | }; |
62 | ||
5f4ec28f | 63 | static struct x86_pmu *x86_pmu __read_mostly; |
b56a3802 | 64 | |
b0f3f28e PZ |
65 | static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = { |
66 | .enabled = 1, | |
67 | }; | |
241771ef | 68 | |
7bb497bd IM |
69 | static __read_mostly int intel_perfmon_version; |
70 | ||
b56a3802 JSR |
71 | /* |
72 | * Intel PerfMon v3. Used on Core2 and later. | |
73 | */ | |
b0f3f28e | 74 | static const u64 intel_perfmon_event_map[] = |
241771ef | 75 | { |
f650a672 | 76 | [PERF_COUNT_CPU_CYCLES] = 0x003c, |
241771ef IM |
77 | [PERF_COUNT_INSTRUCTIONS] = 0x00c0, |
78 | [PERF_COUNT_CACHE_REFERENCES] = 0x4f2e, | |
79 | [PERF_COUNT_CACHE_MISSES] = 0x412e, | |
80 | [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4, | |
81 | [PERF_COUNT_BRANCH_MISSES] = 0x00c5, | |
f650a672 | 82 | [PERF_COUNT_BUS_CYCLES] = 0x013c, |
241771ef IM |
83 | }; |
84 | ||
5f4ec28f | 85 | static u64 intel_pmu_event_map(int event) |
b56a3802 JSR |
86 | { |
87 | return intel_perfmon_event_map[event]; | |
88 | } | |
241771ef | 89 | |
5f4ec28f | 90 | static u64 intel_pmu_raw_event(u64 event) |
b0f3f28e | 91 | { |
82bae4f8 PZ |
92 | #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL |
93 | #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL | |
94 | #define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL | |
b0f3f28e PZ |
95 | |
96 | #define CORE_EVNTSEL_MASK \ | |
97 | (CORE_EVNTSEL_EVENT_MASK | \ | |
98 | CORE_EVNTSEL_UNIT_MASK | \ | |
99 | CORE_EVNTSEL_COUNTER_MASK) | |
100 | ||
101 | return event & CORE_EVNTSEL_MASK; | |
102 | } | |
103 | ||
f87ad35d JSR |
104 | /* |
105 | * AMD Performance Monitor K7 and later. | |
106 | */ | |
b0f3f28e | 107 | static const u64 amd_perfmon_event_map[] = |
f87ad35d JSR |
108 | { |
109 | [PERF_COUNT_CPU_CYCLES] = 0x0076, | |
110 | [PERF_COUNT_INSTRUCTIONS] = 0x00c0, | |
111 | [PERF_COUNT_CACHE_REFERENCES] = 0x0080, | |
112 | [PERF_COUNT_CACHE_MISSES] = 0x0081, | |
113 | [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4, | |
114 | [PERF_COUNT_BRANCH_MISSES] = 0x00c5, | |
115 | }; | |
116 | ||
5f4ec28f | 117 | static u64 amd_pmu_event_map(int event) |
f87ad35d JSR |
118 | { |
119 | return amd_perfmon_event_map[event]; | |
120 | } | |
121 | ||
5f4ec28f | 122 | static u64 amd_pmu_raw_event(u64 event) |
b0f3f28e | 123 | { |
82bae4f8 PZ |
124 | #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL |
125 | #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL | |
126 | #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL | |
b0f3f28e PZ |
127 | |
128 | #define K7_EVNTSEL_MASK \ | |
129 | (K7_EVNTSEL_EVENT_MASK | \ | |
130 | K7_EVNTSEL_UNIT_MASK | \ | |
131 | K7_EVNTSEL_COUNTER_MASK) | |
132 | ||
133 | return event & K7_EVNTSEL_MASK; | |
134 | } | |
135 | ||
ee06094f IM |
136 | /* |
137 | * Propagate counter elapsed time into the generic counter. | |
138 | * Can only be executed on the CPU where the counter is active. | |
139 | * Returns the delta events processed. | |
140 | */ | |
141 | static void | |
142 | x86_perf_counter_update(struct perf_counter *counter, | |
143 | struct hw_perf_counter *hwc, int idx) | |
144 | { | |
145 | u64 prev_raw_count, new_raw_count, delta; | |
146 | ||
ee06094f IM |
147 | /* |
148 | * Careful: an NMI might modify the previous counter value. | |
149 | * | |
150 | * Our tactic to handle this is to first atomically read and | |
151 | * exchange a new raw count - then add that new-prev delta | |
152 | * count to the generic counter atomically: | |
153 | */ | |
154 | again: | |
155 | prev_raw_count = atomic64_read(&hwc->prev_count); | |
156 | rdmsrl(hwc->counter_base + idx, new_raw_count); | |
157 | ||
158 | if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count, | |
159 | new_raw_count) != prev_raw_count) | |
160 | goto again; | |
161 | ||
162 | /* | |
163 | * Now we have the new raw value and have updated the prev | |
164 | * timestamp already. We can now calculate the elapsed delta | |
165 | * (counter-)time and add that to the generic counter. | |
166 | * | |
167 | * Careful, not all hw sign-extends above the physical width | |
168 | * of the count, so we do that by clipping the delta to 32 bits: | |
169 | */ | |
170 | delta = (u64)(u32)((s32)new_raw_count - (s32)prev_raw_count); | |
ee06094f IM |
171 | |
172 | atomic64_add(delta, &counter->count); | |
173 | atomic64_sub(delta, &hwc->period_left); | |
174 | } | |
175 | ||
4e935e47 PZ |
176 | static atomic_t num_counters; |
177 | static DEFINE_MUTEX(pmc_reserve_mutex); | |
178 | ||
179 | static bool reserve_pmc_hardware(void) | |
180 | { | |
181 | int i; | |
182 | ||
183 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
184 | disable_lapic_nmi_watchdog(); | |
185 | ||
186 | for (i = 0; i < nr_counters_generic; i++) { | |
5f4ec28f | 187 | if (!reserve_perfctr_nmi(x86_pmu->perfctr + i)) |
4e935e47 PZ |
188 | goto perfctr_fail; |
189 | } | |
190 | ||
191 | for (i = 0; i < nr_counters_generic; i++) { | |
5f4ec28f | 192 | if (!reserve_evntsel_nmi(x86_pmu->eventsel + i)) |
4e935e47 PZ |
193 | goto eventsel_fail; |
194 | } | |
195 | ||
196 | return true; | |
197 | ||
198 | eventsel_fail: | |
199 | for (i--; i >= 0; i--) | |
5f4ec28f | 200 | release_evntsel_nmi(x86_pmu->eventsel + i); |
4e935e47 PZ |
201 | |
202 | i = nr_counters_generic; | |
203 | ||
204 | perfctr_fail: | |
205 | for (i--; i >= 0; i--) | |
5f4ec28f | 206 | release_perfctr_nmi(x86_pmu->perfctr + i); |
4e935e47 PZ |
207 | |
208 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
209 | enable_lapic_nmi_watchdog(); | |
210 | ||
211 | return false; | |
212 | } | |
213 | ||
214 | static void release_pmc_hardware(void) | |
215 | { | |
216 | int i; | |
217 | ||
218 | for (i = 0; i < nr_counters_generic; i++) { | |
5f4ec28f RR |
219 | release_perfctr_nmi(x86_pmu->perfctr + i); |
220 | release_evntsel_nmi(x86_pmu->eventsel + i); | |
4e935e47 PZ |
221 | } |
222 | ||
223 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
224 | enable_lapic_nmi_watchdog(); | |
225 | } | |
226 | ||
227 | static void hw_perf_counter_destroy(struct perf_counter *counter) | |
228 | { | |
229 | if (atomic_dec_and_mutex_lock(&num_counters, &pmc_reserve_mutex)) { | |
230 | release_pmc_hardware(); | |
231 | mutex_unlock(&pmc_reserve_mutex); | |
232 | } | |
233 | } | |
234 | ||
241771ef IM |
235 | /* |
236 | * Setup the hardware configuration for a given hw_event_type | |
237 | */ | |
621a01ea | 238 | static int __hw_perf_counter_init(struct perf_counter *counter) |
241771ef | 239 | { |
9f66a381 | 240 | struct perf_counter_hw_event *hw_event = &counter->hw_event; |
241771ef | 241 | struct hw_perf_counter *hwc = &counter->hw; |
4e935e47 | 242 | int err; |
241771ef | 243 | |
39d81eab RR |
244 | /* disable temporarily */ |
245 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
246 | return -ENOSYS; | |
247 | ||
241771ef IM |
248 | if (unlikely(!perf_counters_initialized)) |
249 | return -EINVAL; | |
250 | ||
4e935e47 PZ |
251 | err = 0; |
252 | if (atomic_inc_not_zero(&num_counters)) { | |
253 | mutex_lock(&pmc_reserve_mutex); | |
254 | if (atomic_read(&num_counters) == 0 && !reserve_pmc_hardware()) | |
255 | err = -EBUSY; | |
256 | else | |
257 | atomic_inc(&num_counters); | |
258 | mutex_unlock(&pmc_reserve_mutex); | |
259 | } | |
260 | if (err) | |
261 | return err; | |
262 | ||
241771ef | 263 | /* |
0475f9ea | 264 | * Generate PMC IRQs: |
241771ef IM |
265 | * (keep 'enabled' bit clear for now) |
266 | */ | |
0475f9ea | 267 | hwc->config = ARCH_PERFMON_EVENTSEL_INT; |
241771ef IM |
268 | |
269 | /* | |
0475f9ea | 270 | * Count user and OS events unless requested not to. |
241771ef | 271 | */ |
0475f9ea PM |
272 | if (!hw_event->exclude_user) |
273 | hwc->config |= ARCH_PERFMON_EVENTSEL_USR; | |
274 | if (!hw_event->exclude_kernel) | |
241771ef | 275 | hwc->config |= ARCH_PERFMON_EVENTSEL_OS; |
0475f9ea PM |
276 | |
277 | /* | |
278 | * If privileged enough, allow NMI events: | |
279 | */ | |
280 | hwc->nmi = 0; | |
281 | if (capable(CAP_SYS_ADMIN) && hw_event->nmi) | |
282 | hwc->nmi = 1; | |
241771ef | 283 | |
9f66a381 | 284 | hwc->irq_period = hw_event->irq_period; |
241771ef IM |
285 | /* |
286 | * Intel PMCs cannot be accessed sanely above 32 bit width, | |
287 | * so we install an artificial 1<<31 period regardless of | |
288 | * the generic counter period: | |
289 | */ | |
f87ad35d JSR |
290 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
291 | if ((s64)hwc->irq_period <= 0 || hwc->irq_period > 0x7FFFFFFF) | |
292 | hwc->irq_period = 0x7FFFFFFF; | |
241771ef | 293 | |
ee06094f | 294 | atomic64_set(&hwc->period_left, hwc->irq_period); |
241771ef IM |
295 | |
296 | /* | |
dfa7c899 | 297 | * Raw event type provide the config in the event structure |
241771ef | 298 | */ |
f4a2deb4 | 299 | if (perf_event_raw(hw_event)) { |
5f4ec28f | 300 | hwc->config |= x86_pmu->raw_event(perf_event_config(hw_event)); |
241771ef | 301 | } else { |
5f4ec28f | 302 | if (perf_event_id(hw_event) >= x86_pmu->max_events) |
241771ef IM |
303 | return -EINVAL; |
304 | /* | |
305 | * The generic map: | |
306 | */ | |
5f4ec28f | 307 | hwc->config |= x86_pmu->event_map(perf_event_id(hw_event)); |
241771ef | 308 | } |
241771ef | 309 | |
4e935e47 PZ |
310 | counter->destroy = hw_perf_counter_destroy; |
311 | ||
241771ef IM |
312 | return 0; |
313 | } | |
314 | ||
5f4ec28f | 315 | static u64 intel_pmu_save_disable_all(void) |
4ac13294 TG |
316 | { |
317 | u64 ctrl; | |
318 | ||
319 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); | |
862a1a5f | 320 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); |
2b9ff0db | 321 | |
4ac13294 | 322 | return ctrl; |
241771ef | 323 | } |
b56a3802 | 324 | |
5f4ec28f | 325 | static u64 amd_pmu_save_disable_all(void) |
f87ad35d | 326 | { |
b0f3f28e PZ |
327 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
328 | int enabled, idx; | |
329 | ||
330 | enabled = cpuc->enabled; | |
331 | cpuc->enabled = 0; | |
60b3df9c PZ |
332 | /* |
333 | * ensure we write the disable before we start disabling the | |
5f4ec28f RR |
334 | * counters proper, so that amd_pmu_enable_counter() does the |
335 | * right thing. | |
60b3df9c | 336 | */ |
b0f3f28e | 337 | barrier(); |
f87ad35d JSR |
338 | |
339 | for (idx = 0; idx < nr_counters_generic; idx++) { | |
b0f3f28e PZ |
340 | u64 val; |
341 | ||
4295ee62 RR |
342 | if (!test_bit(idx, cpuc->active_mask)) |
343 | continue; | |
f87ad35d | 344 | rdmsrl(MSR_K7_EVNTSEL0 + idx, val); |
4295ee62 RR |
345 | if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE)) |
346 | continue; | |
347 | val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE; | |
348 | wrmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
f87ad35d JSR |
349 | } |
350 | ||
b0f3f28e | 351 | return enabled; |
f87ad35d JSR |
352 | } |
353 | ||
b56a3802 JSR |
354 | u64 hw_perf_save_disable(void) |
355 | { | |
356 | if (unlikely(!perf_counters_initialized)) | |
357 | return 0; | |
358 | ||
5f4ec28f | 359 | return x86_pmu->save_disable_all(); |
b56a3802 | 360 | } |
b0f3f28e PZ |
361 | /* |
362 | * Exported because of ACPI idle | |
363 | */ | |
01b2838c | 364 | EXPORT_SYMBOL_GPL(hw_perf_save_disable); |
241771ef | 365 | |
5f4ec28f | 366 | static void intel_pmu_restore_all(u64 ctrl) |
b56a3802 JSR |
367 | { |
368 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); | |
369 | } | |
370 | ||
5f4ec28f | 371 | static void amd_pmu_restore_all(u64 ctrl) |
f87ad35d | 372 | { |
b0f3f28e | 373 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
f87ad35d JSR |
374 | int idx; |
375 | ||
b0f3f28e PZ |
376 | cpuc->enabled = ctrl; |
377 | barrier(); | |
378 | if (!ctrl) | |
379 | return; | |
380 | ||
f87ad35d | 381 | for (idx = 0; idx < nr_counters_generic; idx++) { |
4295ee62 | 382 | u64 val; |
b0f3f28e | 383 | |
4295ee62 RR |
384 | if (!test_bit(idx, cpuc->active_mask)) |
385 | continue; | |
386 | rdmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
387 | if (val & ARCH_PERFMON_EVENTSEL0_ENABLE) | |
388 | continue; | |
389 | val |= ARCH_PERFMON_EVENTSEL0_ENABLE; | |
390 | wrmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
f87ad35d JSR |
391 | } |
392 | } | |
393 | ||
ee06094f IM |
394 | void hw_perf_restore(u64 ctrl) |
395 | { | |
2b9ff0db IM |
396 | if (unlikely(!perf_counters_initialized)) |
397 | return; | |
398 | ||
5f4ec28f | 399 | x86_pmu->restore_all(ctrl); |
ee06094f | 400 | } |
b0f3f28e PZ |
401 | /* |
402 | * Exported because of ACPI idle | |
403 | */ | |
ee06094f IM |
404 | EXPORT_SYMBOL_GPL(hw_perf_restore); |
405 | ||
b7f8859a | 406 | static inline u64 intel_pmu_get_status(u64 mask) |
b0f3f28e PZ |
407 | { |
408 | u64 status; | |
409 | ||
b0f3f28e PZ |
410 | if (unlikely(!perf_counters_initialized)) |
411 | return 0; | |
b7f8859a | 412 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); |
b0f3f28e | 413 | |
b7f8859a | 414 | return status; |
b0f3f28e PZ |
415 | } |
416 | ||
dee5d906 | 417 | static inline void intel_pmu_ack_status(u64 ack) |
b0f3f28e PZ |
418 | { |
419 | wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); | |
420 | } | |
421 | ||
5f4ec28f | 422 | static void intel_pmu_enable_counter(int idx, u64 config) |
b0f3f28e PZ |
423 | { |
424 | wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + idx, | |
425 | config | ARCH_PERFMON_EVENTSEL0_ENABLE); | |
426 | } | |
427 | ||
5f4ec28f | 428 | static void amd_pmu_enable_counter(int idx, u64 config) |
b0f3f28e PZ |
429 | { |
430 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
431 | ||
184fe4ab | 432 | set_bit(idx, cpuc->active_mask); |
b0f3f28e PZ |
433 | if (cpuc->enabled) |
434 | config |= ARCH_PERFMON_EVENTSEL0_ENABLE; | |
435 | ||
436 | wrmsrl(MSR_K7_EVNTSEL0 + idx, config); | |
437 | } | |
438 | ||
439 | static void hw_perf_enable(int idx, u64 config) | |
440 | { | |
441 | if (unlikely(!perf_counters_initialized)) | |
442 | return; | |
443 | ||
5f4ec28f | 444 | x86_pmu->enable(idx, config); |
b0f3f28e PZ |
445 | } |
446 | ||
5f4ec28f | 447 | static void intel_pmu_disable_counter(int idx, u64 config) |
b0f3f28e PZ |
448 | { |
449 | wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + idx, config); | |
450 | } | |
451 | ||
5f4ec28f | 452 | static void amd_pmu_disable_counter(int idx, u64 config) |
b0f3f28e PZ |
453 | { |
454 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
455 | ||
184fe4ab | 456 | clear_bit(idx, cpuc->active_mask); |
b0f3f28e PZ |
457 | wrmsrl(MSR_K7_EVNTSEL0 + idx, config); |
458 | ||
459 | } | |
460 | ||
461 | static void hw_perf_disable(int idx, u64 config) | |
462 | { | |
463 | if (unlikely(!perf_counters_initialized)) | |
464 | return; | |
465 | ||
5f4ec28f | 466 | x86_pmu->disable(idx, config); |
b0f3f28e PZ |
467 | } |
468 | ||
2f18d1e8 IM |
469 | static inline void |
470 | __pmc_fixed_disable(struct perf_counter *counter, | |
471 | struct hw_perf_counter *hwc, unsigned int __idx) | |
472 | { | |
473 | int idx = __idx - X86_PMC_IDX_FIXED; | |
474 | u64 ctrl_val, mask; | |
475 | int err; | |
476 | ||
477 | mask = 0xfULL << (idx * 4); | |
478 | ||
479 | rdmsrl(hwc->config_base, ctrl_val); | |
480 | ctrl_val &= ~mask; | |
481 | err = checking_wrmsrl(hwc->config_base, ctrl_val); | |
482 | } | |
483 | ||
7e2ae347 | 484 | static inline void |
4aeb0b42 RR |
485 | __x86_pmu_disable(struct perf_counter *counter, |
486 | struct hw_perf_counter *hwc, unsigned int idx) | |
7e2ae347 | 487 | { |
2f18d1e8 | 488 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) |
2b583d8b JSR |
489 | __pmc_fixed_disable(counter, hwc, idx); |
490 | else | |
b0f3f28e | 491 | hw_perf_disable(idx, hwc->config); |
7e2ae347 IM |
492 | } |
493 | ||
2f18d1e8 | 494 | static DEFINE_PER_CPU(u64, prev_left[X86_PMC_IDX_MAX]); |
241771ef | 495 | |
ee06094f IM |
496 | /* |
497 | * Set the next IRQ period, based on the hwc->period_left value. | |
498 | * To be called with the counter disabled in hw: | |
499 | */ | |
500 | static void | |
26816c28 | 501 | x86_perf_counter_set_period(struct perf_counter *counter, |
ee06094f | 502 | struct hw_perf_counter *hwc, int idx) |
241771ef | 503 | { |
2f18d1e8 | 504 | s64 left = atomic64_read(&hwc->period_left); |
595258aa | 505 | s64 period = hwc->irq_period; |
2f18d1e8 | 506 | int err; |
ee06094f | 507 | |
ee06094f IM |
508 | /* |
509 | * If we are way outside a reasoable range then just skip forward: | |
510 | */ | |
511 | if (unlikely(left <= -period)) { | |
512 | left = period; | |
513 | atomic64_set(&hwc->period_left, left); | |
514 | } | |
515 | ||
516 | if (unlikely(left <= 0)) { | |
517 | left += period; | |
518 | atomic64_set(&hwc->period_left, left); | |
519 | } | |
241771ef | 520 | |
ee06094f IM |
521 | per_cpu(prev_left[idx], smp_processor_id()) = left; |
522 | ||
523 | /* | |
524 | * The hw counter starts counting from this counter offset, | |
525 | * mark it to be able to extra future deltas: | |
526 | */ | |
2f18d1e8 | 527 | atomic64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 528 | |
2f18d1e8 IM |
529 | err = checking_wrmsrl(hwc->counter_base + idx, |
530 | (u64)(-left) & counter_value_mask); | |
531 | } | |
532 | ||
533 | static inline void | |
534 | __pmc_fixed_enable(struct perf_counter *counter, | |
535 | struct hw_perf_counter *hwc, unsigned int __idx) | |
536 | { | |
537 | int idx = __idx - X86_PMC_IDX_FIXED; | |
538 | u64 ctrl_val, bits, mask; | |
539 | int err; | |
540 | ||
541 | /* | |
0475f9ea PM |
542 | * Enable IRQ generation (0x8), |
543 | * and enable ring-3 counting (0x2) and ring-0 counting (0x1) | |
544 | * if requested: | |
2f18d1e8 | 545 | */ |
0475f9ea PM |
546 | bits = 0x8ULL; |
547 | if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) | |
548 | bits |= 0x2; | |
2f18d1e8 IM |
549 | if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) |
550 | bits |= 0x1; | |
551 | bits <<= (idx * 4); | |
552 | mask = 0xfULL << (idx * 4); | |
553 | ||
554 | rdmsrl(hwc->config_base, ctrl_val); | |
555 | ctrl_val &= ~mask; | |
556 | ctrl_val |= bits; | |
557 | err = checking_wrmsrl(hwc->config_base, ctrl_val); | |
7e2ae347 IM |
558 | } |
559 | ||
ee06094f | 560 | static void |
4aeb0b42 RR |
561 | __x86_pmu_enable(struct perf_counter *counter, |
562 | struct hw_perf_counter *hwc, int idx) | |
7e2ae347 | 563 | { |
2f18d1e8 | 564 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) |
2b583d8b JSR |
565 | __pmc_fixed_enable(counter, hwc, idx); |
566 | else | |
b0f3f28e | 567 | hw_perf_enable(idx, hwc->config); |
241771ef IM |
568 | } |
569 | ||
2f18d1e8 IM |
570 | static int |
571 | fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc) | |
862a1a5f | 572 | { |
2f18d1e8 IM |
573 | unsigned int event; |
574 | ||
f87ad35d JSR |
575 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
576 | return -1; | |
577 | ||
2f18d1e8 IM |
578 | if (unlikely(hwc->nmi)) |
579 | return -1; | |
580 | ||
581 | event = hwc->config & ARCH_PERFMON_EVENT_MASK; | |
582 | ||
5f4ec28f | 583 | if (unlikely(event == x86_pmu->event_map(PERF_COUNT_INSTRUCTIONS))) |
2f18d1e8 | 584 | return X86_PMC_IDX_FIXED_INSTRUCTIONS; |
5f4ec28f | 585 | if (unlikely(event == x86_pmu->event_map(PERF_COUNT_CPU_CYCLES))) |
2f18d1e8 | 586 | return X86_PMC_IDX_FIXED_CPU_CYCLES; |
5f4ec28f | 587 | if (unlikely(event == x86_pmu->event_map(PERF_COUNT_BUS_CYCLES))) |
2f18d1e8 IM |
588 | return X86_PMC_IDX_FIXED_BUS_CYCLES; |
589 | ||
862a1a5f IM |
590 | return -1; |
591 | } | |
592 | ||
ee06094f IM |
593 | /* |
594 | * Find a PMC slot for the freshly enabled / scheduled in counter: | |
595 | */ | |
4aeb0b42 | 596 | static int x86_pmu_enable(struct perf_counter *counter) |
241771ef IM |
597 | { |
598 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
599 | struct hw_perf_counter *hwc = &counter->hw; | |
2f18d1e8 | 600 | int idx; |
241771ef | 601 | |
2f18d1e8 IM |
602 | idx = fixed_mode_idx(counter, hwc); |
603 | if (idx >= 0) { | |
604 | /* | |
605 | * Try to get the fixed counter, if that is already taken | |
606 | * then try to get a generic counter: | |
607 | */ | |
608 | if (test_and_set_bit(idx, cpuc->used)) | |
609 | goto try_generic; | |
0dff86aa | 610 | |
2f18d1e8 IM |
611 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
612 | /* | |
613 | * We set it so that counter_base + idx in wrmsr/rdmsr maps to | |
614 | * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2: | |
615 | */ | |
616 | hwc->counter_base = | |
617 | MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED; | |
241771ef | 618 | hwc->idx = idx; |
2f18d1e8 IM |
619 | } else { |
620 | idx = hwc->idx; | |
621 | /* Try to get the previous generic counter again */ | |
622 | if (test_and_set_bit(idx, cpuc->used)) { | |
623 | try_generic: | |
624 | idx = find_first_zero_bit(cpuc->used, nr_counters_generic); | |
625 | if (idx == nr_counters_generic) | |
626 | return -EAGAIN; | |
627 | ||
628 | set_bit(idx, cpuc->used); | |
629 | hwc->idx = idx; | |
630 | } | |
5f4ec28f RR |
631 | hwc->config_base = x86_pmu->eventsel; |
632 | hwc->counter_base = x86_pmu->perfctr; | |
241771ef IM |
633 | } |
634 | ||
635 | perf_counters_lapic_init(hwc->nmi); | |
636 | ||
4aeb0b42 | 637 | __x86_pmu_disable(counter, hwc, idx); |
241771ef | 638 | |
862a1a5f | 639 | cpuc->counters[idx] = counter; |
2f18d1e8 IM |
640 | /* |
641 | * Make it visible before enabling the hw: | |
642 | */ | |
527e26af | 643 | barrier(); |
7e2ae347 | 644 | |
26816c28 | 645 | x86_perf_counter_set_period(counter, hwc, idx); |
4aeb0b42 | 646 | __x86_pmu_enable(counter, hwc, idx); |
95cdd2e7 IM |
647 | |
648 | return 0; | |
241771ef IM |
649 | } |
650 | ||
651 | void perf_counter_print_debug(void) | |
652 | { | |
2f18d1e8 | 653 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
0dff86aa | 654 | struct cpu_hw_counters *cpuc; |
1e125676 IM |
655 | int cpu, idx; |
656 | ||
862a1a5f | 657 | if (!nr_counters_generic) |
1e125676 | 658 | return; |
241771ef IM |
659 | |
660 | local_irq_disable(); | |
661 | ||
662 | cpu = smp_processor_id(); | |
0dff86aa | 663 | cpuc = &per_cpu(cpu_hw_counters, cpu); |
241771ef | 664 | |
7bb497bd | 665 | if (intel_perfmon_version >= 2) { |
a1ef58f4 JSR |
666 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
667 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
668 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
669 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
670 | ||
671 | pr_info("\n"); | |
672 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
673 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
674 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
675 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
f87ad35d | 676 | } |
a1ef58f4 | 677 | pr_info("CPU#%d: used: %016llx\n", cpu, *(u64 *)cpuc->used); |
241771ef | 678 | |
862a1a5f | 679 | for (idx = 0; idx < nr_counters_generic; idx++) { |
5f4ec28f RR |
680 | rdmsrl(x86_pmu->eventsel + idx, pmc_ctrl); |
681 | rdmsrl(x86_pmu->perfctr + idx, pmc_count); | |
241771ef | 682 | |
ee06094f | 683 | prev_left = per_cpu(prev_left[idx], cpu); |
241771ef | 684 | |
a1ef58f4 | 685 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 686 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 687 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 688 | cpu, idx, pmc_count); |
a1ef58f4 | 689 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 690 | cpu, idx, prev_left); |
241771ef | 691 | } |
2f18d1e8 IM |
692 | for (idx = 0; idx < nr_counters_fixed; idx++) { |
693 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); | |
694 | ||
a1ef58f4 | 695 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
696 | cpu, idx, pmc_count); |
697 | } | |
241771ef IM |
698 | local_irq_enable(); |
699 | } | |
700 | ||
4aeb0b42 | 701 | static void x86_pmu_disable(struct perf_counter *counter) |
241771ef IM |
702 | { |
703 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
704 | struct hw_perf_counter *hwc = &counter->hw; | |
705 | unsigned int idx = hwc->idx; | |
706 | ||
4aeb0b42 | 707 | __x86_pmu_disable(counter, hwc, idx); |
241771ef IM |
708 | |
709 | clear_bit(idx, cpuc->used); | |
862a1a5f | 710 | cpuc->counters[idx] = NULL; |
2f18d1e8 IM |
711 | /* |
712 | * Make sure the cleared pointer becomes visible before we | |
713 | * (potentially) free the counter: | |
714 | */ | |
527e26af | 715 | barrier(); |
241771ef | 716 | |
ee06094f IM |
717 | /* |
718 | * Drain the remaining delta count out of a counter | |
719 | * that we are disabling: | |
720 | */ | |
721 | x86_perf_counter_update(counter, hwc, idx); | |
241771ef IM |
722 | } |
723 | ||
7e2ae347 | 724 | /* |
ee06094f IM |
725 | * Save and restart an expired counter. Called by NMI contexts, |
726 | * so it has to be careful about preempting normal counter ops: | |
7e2ae347 | 727 | */ |
55de0f2e | 728 | static void intel_pmu_save_and_restart(struct perf_counter *counter) |
241771ef IM |
729 | { |
730 | struct hw_perf_counter *hwc = &counter->hw; | |
731 | int idx = hwc->idx; | |
241771ef | 732 | |
ee06094f | 733 | x86_perf_counter_update(counter, hwc, idx); |
26816c28 | 734 | x86_perf_counter_set_period(counter, hwc, idx); |
7e2ae347 | 735 | |
2f18d1e8 | 736 | if (counter->state == PERF_COUNTER_STATE_ACTIVE) |
4aeb0b42 | 737 | __x86_pmu_enable(counter, hwc, idx); |
241771ef IM |
738 | } |
739 | ||
4b39fd96 MG |
740 | /* |
741 | * Maximum interrupt frequency of 100KHz per CPU | |
742 | */ | |
169e41eb | 743 | #define PERFMON_MAX_INTERRUPTS (100000/HZ) |
4b39fd96 | 744 | |
241771ef IM |
745 | /* |
746 | * This handler is triggered by the local APIC, so the APIC IRQ handling | |
747 | * rules apply: | |
748 | */ | |
39d81eab | 749 | static int intel_pmu_handle_irq(struct pt_regs *regs, int nmi) |
241771ef IM |
750 | { |
751 | int bit, cpu = smp_processor_id(); | |
4b39fd96 | 752 | u64 ack, status; |
1b023a96 | 753 | struct cpu_hw_counters *cpuc = &per_cpu(cpu_hw_counters, cpu); |
b0f3f28e | 754 | int ret = 0; |
43874d23 | 755 | |
55de0f2e | 756 | cpuc->throttle_ctrl = intel_pmu_save_disable_all(); |
241771ef | 757 | |
b7f8859a | 758 | status = intel_pmu_get_status(cpuc->throttle_ctrl); |
87b9cf46 IM |
759 | if (!status) |
760 | goto out; | |
761 | ||
b0f3f28e | 762 | ret = 1; |
241771ef | 763 | again: |
d278c484 | 764 | inc_irq_stat(apic_perf_irqs); |
241771ef | 765 | ack = status; |
2f18d1e8 | 766 | for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { |
862a1a5f | 767 | struct perf_counter *counter = cpuc->counters[bit]; |
241771ef IM |
768 | |
769 | clear_bit(bit, (unsigned long *) &status); | |
770 | if (!counter) | |
771 | continue; | |
772 | ||
55de0f2e | 773 | intel_pmu_save_and_restart(counter); |
78f13e95 | 774 | if (perf_counter_overflow(counter, nmi, regs, 0)) |
4aeb0b42 | 775 | __x86_pmu_disable(counter, &counter->hw, bit); |
241771ef IM |
776 | } |
777 | ||
dee5d906 | 778 | intel_pmu_ack_status(ack); |
241771ef IM |
779 | |
780 | /* | |
781 | * Repeat if there is more work to be done: | |
782 | */ | |
b7f8859a | 783 | status = intel_pmu_get_status(cpuc->throttle_ctrl); |
241771ef IM |
784 | if (status) |
785 | goto again; | |
87b9cf46 | 786 | out: |
241771ef | 787 | /* |
1b023a96 | 788 | * Restore - do not reenable when global enable is off or throttled: |
241771ef | 789 | */ |
4b39fd96 | 790 | if (++cpuc->interrupts < PERFMON_MAX_INTERRUPTS) |
55de0f2e | 791 | intel_pmu_restore_all(cpuc->throttle_ctrl); |
b0f3f28e PZ |
792 | |
793 | return ret; | |
1b023a96 MG |
794 | } |
795 | ||
39d81eab RR |
796 | static int amd_pmu_handle_irq(struct pt_regs *regs, int nmi) { return 0; } |
797 | ||
1b023a96 MG |
798 | void perf_counter_unthrottle(void) |
799 | { | |
800 | struct cpu_hw_counters *cpuc; | |
801 | ||
802 | if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) | |
803 | return; | |
804 | ||
805 | if (unlikely(!perf_counters_initialized)) | |
806 | return; | |
807 | ||
b0f3f28e | 808 | cpuc = &__get_cpu_var(cpu_hw_counters); |
4b39fd96 | 809 | if (cpuc->interrupts >= PERFMON_MAX_INTERRUPTS) { |
1b023a96 | 810 | if (printk_ratelimit()) |
4b39fd96 | 811 | printk(KERN_WARNING "PERFMON: max interrupts exceeded!\n"); |
b0f3f28e | 812 | hw_perf_restore(cpuc->throttle_ctrl); |
1b023a96 | 813 | } |
4b39fd96 | 814 | cpuc->interrupts = 0; |
241771ef IM |
815 | } |
816 | ||
817 | void smp_perf_counter_interrupt(struct pt_regs *regs) | |
818 | { | |
819 | irq_enter(); | |
241771ef | 820 | apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR); |
b0f3f28e | 821 | ack_APIC_irq(); |
39d81eab | 822 | x86_pmu->handle_irq(regs, 0); |
241771ef IM |
823 | irq_exit(); |
824 | } | |
825 | ||
b6276f35 PZ |
826 | void smp_perf_pending_interrupt(struct pt_regs *regs) |
827 | { | |
828 | irq_enter(); | |
829 | ack_APIC_irq(); | |
830 | inc_irq_stat(apic_pending_irqs); | |
831 | perf_counter_do_pending(); | |
832 | irq_exit(); | |
833 | } | |
834 | ||
835 | void set_perf_counter_pending(void) | |
836 | { | |
837 | apic->send_IPI_self(LOCAL_PENDING_VECTOR); | |
838 | } | |
839 | ||
3415dd91 | 840 | void perf_counters_lapic_init(int nmi) |
241771ef IM |
841 | { |
842 | u32 apic_val; | |
843 | ||
844 | if (!perf_counters_initialized) | |
845 | return; | |
846 | /* | |
847 | * Enable the performance counter vector in the APIC LVT: | |
848 | */ | |
849 | apic_val = apic_read(APIC_LVTERR); | |
850 | ||
851 | apic_write(APIC_LVTERR, apic_val | APIC_LVT_MASKED); | |
852 | if (nmi) | |
853 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
854 | else | |
855 | apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR); | |
856 | apic_write(APIC_LVTERR, apic_val); | |
857 | } | |
858 | ||
859 | static int __kprobes | |
860 | perf_counter_nmi_handler(struct notifier_block *self, | |
861 | unsigned long cmd, void *__args) | |
862 | { | |
863 | struct die_args *args = __args; | |
864 | struct pt_regs *regs; | |
b0f3f28e PZ |
865 | int ret; |
866 | ||
867 | switch (cmd) { | |
868 | case DIE_NMI: | |
869 | case DIE_NMI_IPI: | |
870 | break; | |
241771ef | 871 | |
b0f3f28e | 872 | default: |
241771ef | 873 | return NOTIFY_DONE; |
b0f3f28e | 874 | } |
241771ef IM |
875 | |
876 | regs = args->regs; | |
877 | ||
878 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
39d81eab | 879 | ret = x86_pmu->handle_irq(regs, 1); |
241771ef | 880 | |
b0f3f28e | 881 | return ret ? NOTIFY_STOP : NOTIFY_OK; |
241771ef IM |
882 | } |
883 | ||
884 | static __read_mostly struct notifier_block perf_counter_nmi_notifier = { | |
5b75af0a MG |
885 | .notifier_call = perf_counter_nmi_handler, |
886 | .next = NULL, | |
887 | .priority = 1 | |
241771ef IM |
888 | }; |
889 | ||
5f4ec28f | 890 | static struct x86_pmu intel_pmu = { |
39d81eab | 891 | .handle_irq = intel_pmu_handle_irq, |
5f4ec28f RR |
892 | .save_disable_all = intel_pmu_save_disable_all, |
893 | .restore_all = intel_pmu_restore_all, | |
5f4ec28f RR |
894 | .enable = intel_pmu_enable_counter, |
895 | .disable = intel_pmu_disable_counter, | |
b56a3802 JSR |
896 | .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, |
897 | .perfctr = MSR_ARCH_PERFMON_PERFCTR0, | |
5f4ec28f RR |
898 | .event_map = intel_pmu_event_map, |
899 | .raw_event = intel_pmu_raw_event, | |
b56a3802 JSR |
900 | .max_events = ARRAY_SIZE(intel_perfmon_event_map), |
901 | }; | |
902 | ||
5f4ec28f | 903 | static struct x86_pmu amd_pmu = { |
39d81eab | 904 | .handle_irq = amd_pmu_handle_irq, |
5f4ec28f RR |
905 | .save_disable_all = amd_pmu_save_disable_all, |
906 | .restore_all = amd_pmu_restore_all, | |
5f4ec28f RR |
907 | .enable = amd_pmu_enable_counter, |
908 | .disable = amd_pmu_disable_counter, | |
f87ad35d JSR |
909 | .eventsel = MSR_K7_EVNTSEL0, |
910 | .perfctr = MSR_K7_PERFCTR0, | |
5f4ec28f RR |
911 | .event_map = amd_pmu_event_map, |
912 | .raw_event = amd_pmu_raw_event, | |
f87ad35d JSR |
913 | .max_events = ARRAY_SIZE(amd_perfmon_event_map), |
914 | }; | |
915 | ||
5f4ec28f | 916 | static struct x86_pmu *intel_pmu_init(void) |
241771ef | 917 | { |
7bb497bd | 918 | union cpuid10_edx edx; |
241771ef | 919 | union cpuid10_eax eax; |
703e937c | 920 | unsigned int unused; |
7bb497bd | 921 | unsigned int ebx; |
241771ef | 922 | |
da1a776b RR |
923 | if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) |
924 | return NULL; | |
925 | ||
241771ef IM |
926 | /* |
927 | * Check whether the Architectural PerfMon supports | |
928 | * Branch Misses Retired Event or not. | |
929 | */ | |
703e937c | 930 | cpuid(10, &eax.full, &ebx, &unused, &edx.full); |
241771ef | 931 | if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED) |
b56a3802 | 932 | return NULL; |
241771ef | 933 | |
7bb497bd IM |
934 | intel_perfmon_version = eax.split.version_id; |
935 | if (intel_perfmon_version < 2) | |
936 | return NULL; | |
937 | ||
a1ef58f4 | 938 | pr_info("Intel Performance Monitoring support detected.\n"); |
7bb497bd | 939 | pr_info("... version: %d\n", intel_perfmon_version); |
a1ef58f4 JSR |
940 | pr_info("... bit width: %d\n", eax.split.bit_width); |
941 | pr_info("... mask length: %d\n", eax.split.mask_length); | |
b56a3802 | 942 | |
862a1a5f | 943 | nr_counters_generic = eax.split.num_counters; |
b56a3802 JSR |
944 | nr_counters_fixed = edx.split.num_counters_fixed; |
945 | counter_value_mask = (1ULL << eax.split.bit_width) - 1; | |
946 | ||
5f4ec28f | 947 | return &intel_pmu; |
b56a3802 JSR |
948 | } |
949 | ||
5f4ec28f | 950 | static struct x86_pmu *amd_pmu_init(void) |
f87ad35d JSR |
951 | { |
952 | nr_counters_generic = 4; | |
953 | nr_counters_fixed = 0; | |
b5e8acf6 PZ |
954 | counter_value_mask = 0x0000FFFFFFFFFFFFULL; |
955 | counter_value_bits = 48; | |
f87ad35d | 956 | |
a1ef58f4 | 957 | pr_info("AMD Performance Monitoring support detected.\n"); |
f87ad35d | 958 | |
5f4ec28f | 959 | return &amd_pmu; |
f87ad35d JSR |
960 | } |
961 | ||
b56a3802 JSR |
962 | void __init init_hw_perf_counters(void) |
963 | { | |
b56a3802 JSR |
964 | switch (boot_cpu_data.x86_vendor) { |
965 | case X86_VENDOR_INTEL: | |
5f4ec28f | 966 | x86_pmu = intel_pmu_init(); |
b56a3802 | 967 | break; |
f87ad35d | 968 | case X86_VENDOR_AMD: |
5f4ec28f | 969 | x86_pmu = amd_pmu_init(); |
f87ad35d | 970 | break; |
4138960a RR |
971 | default: |
972 | return; | |
b56a3802 | 973 | } |
5f4ec28f | 974 | if (!x86_pmu) |
b56a3802 JSR |
975 | return; |
976 | ||
a1ef58f4 | 977 | pr_info("... num counters: %d\n", nr_counters_generic); |
862a1a5f IM |
978 | if (nr_counters_generic > X86_PMC_MAX_GENERIC) { |
979 | nr_counters_generic = X86_PMC_MAX_GENERIC; | |
241771ef | 980 | WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!", |
862a1a5f | 981 | nr_counters_generic, X86_PMC_MAX_GENERIC); |
241771ef | 982 | } |
862a1a5f IM |
983 | perf_counter_mask = (1 << nr_counters_generic) - 1; |
984 | perf_max_counters = nr_counters_generic; | |
241771ef | 985 | |
a1ef58f4 | 986 | pr_info("... value mask: %016Lx\n", counter_value_mask); |
2f18d1e8 | 987 | |
862a1a5f IM |
988 | if (nr_counters_fixed > X86_PMC_MAX_FIXED) { |
989 | nr_counters_fixed = X86_PMC_MAX_FIXED; | |
703e937c | 990 | WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!", |
862a1a5f | 991 | nr_counters_fixed, X86_PMC_MAX_FIXED); |
703e937c | 992 | } |
a1ef58f4 | 993 | pr_info("... fixed counters: %d\n", nr_counters_fixed); |
862a1a5f IM |
994 | |
995 | perf_counter_mask |= ((1LL << nr_counters_fixed)-1) << X86_PMC_IDX_FIXED; | |
241771ef | 996 | |
a1ef58f4 | 997 | pr_info("... counter mask: %016Lx\n", perf_counter_mask); |
75f224cf IM |
998 | perf_counters_initialized = true; |
999 | ||
241771ef IM |
1000 | perf_counters_lapic_init(0); |
1001 | register_die_notifier(&perf_counter_nmi_notifier); | |
241771ef | 1002 | } |
621a01ea | 1003 | |
4aeb0b42 | 1004 | static void x86_pmu_read(struct perf_counter *counter) |
ee06094f IM |
1005 | { |
1006 | x86_perf_counter_update(counter, &counter->hw, counter->hw.idx); | |
1007 | } | |
1008 | ||
4aeb0b42 RR |
1009 | static const struct pmu pmu = { |
1010 | .enable = x86_pmu_enable, | |
1011 | .disable = x86_pmu_disable, | |
1012 | .read = x86_pmu_read, | |
621a01ea IM |
1013 | }; |
1014 | ||
4aeb0b42 | 1015 | const struct pmu *hw_perf_counter_init(struct perf_counter *counter) |
621a01ea IM |
1016 | { |
1017 | int err; | |
1018 | ||
1019 | err = __hw_perf_counter_init(counter); | |
1020 | if (err) | |
9ea98e19 | 1021 | return ERR_PTR(err); |
621a01ea | 1022 | |
4aeb0b42 | 1023 | return &pmu; |
621a01ea | 1024 | } |
d7d59fb3 PZ |
1025 | |
1026 | /* | |
1027 | * callchain support | |
1028 | */ | |
1029 | ||
1030 | static inline | |
1031 | void callchain_store(struct perf_callchain_entry *entry, unsigned long ip) | |
1032 | { | |
1033 | if (entry->nr < MAX_STACK_DEPTH) | |
1034 | entry->ip[entry->nr++] = ip; | |
1035 | } | |
1036 | ||
1037 | static DEFINE_PER_CPU(struct perf_callchain_entry, irq_entry); | |
1038 | static DEFINE_PER_CPU(struct perf_callchain_entry, nmi_entry); | |
1039 | ||
1040 | ||
1041 | static void | |
1042 | backtrace_warning_symbol(void *data, char *msg, unsigned long symbol) | |
1043 | { | |
1044 | /* Ignore warnings */ | |
1045 | } | |
1046 | ||
1047 | static void backtrace_warning(void *data, char *msg) | |
1048 | { | |
1049 | /* Ignore warnings */ | |
1050 | } | |
1051 | ||
1052 | static int backtrace_stack(void *data, char *name) | |
1053 | { | |
1054 | /* Don't bother with IRQ stacks for now */ | |
1055 | return -1; | |
1056 | } | |
1057 | ||
1058 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1059 | { | |
1060 | struct perf_callchain_entry *entry = data; | |
1061 | ||
1062 | if (reliable) | |
1063 | callchain_store(entry, addr); | |
1064 | } | |
1065 | ||
1066 | static const struct stacktrace_ops backtrace_ops = { | |
1067 | .warning = backtrace_warning, | |
1068 | .warning_symbol = backtrace_warning_symbol, | |
1069 | .stack = backtrace_stack, | |
1070 | .address = backtrace_address, | |
1071 | }; | |
1072 | ||
1073 | static void | |
1074 | perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1075 | { | |
1076 | unsigned long bp; | |
1077 | char *stack; | |
5872bdb8 | 1078 | int nr = entry->nr; |
d7d59fb3 PZ |
1079 | |
1080 | callchain_store(entry, instruction_pointer(regs)); | |
1081 | ||
1082 | stack = ((char *)regs + sizeof(struct pt_regs)); | |
1083 | #ifdef CONFIG_FRAME_POINTER | |
1084 | bp = frame_pointer(regs); | |
1085 | #else | |
1086 | bp = 0; | |
1087 | #endif | |
1088 | ||
1089 | dump_trace(NULL, regs, (void *)stack, bp, &backtrace_ops, entry); | |
5872bdb8 PZ |
1090 | |
1091 | entry->kernel = entry->nr - nr; | |
d7d59fb3 PZ |
1092 | } |
1093 | ||
1094 | ||
1095 | struct stack_frame { | |
1096 | const void __user *next_fp; | |
1097 | unsigned long return_address; | |
1098 | }; | |
1099 | ||
1100 | static int copy_stack_frame(const void __user *fp, struct stack_frame *frame) | |
1101 | { | |
1102 | int ret; | |
1103 | ||
1104 | if (!access_ok(VERIFY_READ, fp, sizeof(*frame))) | |
1105 | return 0; | |
1106 | ||
1107 | ret = 1; | |
1108 | pagefault_disable(); | |
1109 | if (__copy_from_user_inatomic(frame, fp, sizeof(*frame))) | |
1110 | ret = 0; | |
1111 | pagefault_enable(); | |
1112 | ||
1113 | return ret; | |
1114 | } | |
1115 | ||
1116 | static void | |
1117 | perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1118 | { | |
1119 | struct stack_frame frame; | |
1120 | const void __user *fp; | |
5872bdb8 | 1121 | int nr = entry->nr; |
d7d59fb3 PZ |
1122 | |
1123 | regs = (struct pt_regs *)current->thread.sp0 - 1; | |
1124 | fp = (void __user *)regs->bp; | |
1125 | ||
1126 | callchain_store(entry, regs->ip); | |
1127 | ||
1128 | while (entry->nr < MAX_STACK_DEPTH) { | |
1129 | frame.next_fp = NULL; | |
1130 | frame.return_address = 0; | |
1131 | ||
1132 | if (!copy_stack_frame(fp, &frame)) | |
1133 | break; | |
1134 | ||
1135 | if ((unsigned long)fp < user_stack_pointer(regs)) | |
1136 | break; | |
1137 | ||
1138 | callchain_store(entry, frame.return_address); | |
1139 | fp = frame.next_fp; | |
1140 | } | |
5872bdb8 PZ |
1141 | |
1142 | entry->user = entry->nr - nr; | |
d7d59fb3 PZ |
1143 | } |
1144 | ||
1145 | static void | |
1146 | perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1147 | { | |
1148 | int is_user; | |
1149 | ||
1150 | if (!regs) | |
1151 | return; | |
1152 | ||
1153 | is_user = user_mode(regs); | |
1154 | ||
1155 | if (!current || current->pid == 0) | |
1156 | return; | |
1157 | ||
1158 | if (is_user && current->state != TASK_RUNNING) | |
1159 | return; | |
1160 | ||
1161 | if (!is_user) | |
1162 | perf_callchain_kernel(regs, entry); | |
1163 | ||
1164 | if (current->mm) | |
1165 | perf_callchain_user(regs, entry); | |
1166 | } | |
1167 | ||
1168 | struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) | |
1169 | { | |
1170 | struct perf_callchain_entry *entry; | |
1171 | ||
1172 | if (in_nmi()) | |
1173 | entry = &__get_cpu_var(nmi_entry); | |
1174 | else | |
1175 | entry = &__get_cpu_var(irq_entry); | |
1176 | ||
1177 | entry->nr = 0; | |
5872bdb8 PZ |
1178 | entry->hv = 0; |
1179 | entry->kernel = 0; | |
1180 | entry->user = 0; | |
d7d59fb3 PZ |
1181 | |
1182 | perf_do_callchain(regs, entry); | |
1183 | ||
1184 | return entry; | |
1185 | } |