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241771ef IM |
1 | /* |
2 | * Performance counter x86 architecture code | |
3 | * | |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
241771ef IM |
9 | * |
10 | * For licencing details see kernel-base/COPYING | |
11 | */ | |
12 | ||
13 | #include <linux/perf_counter.h> | |
14 | #include <linux/capability.h> | |
15 | #include <linux/notifier.h> | |
16 | #include <linux/hardirq.h> | |
17 | #include <linux/kprobes.h> | |
4ac13294 | 18 | #include <linux/module.h> |
241771ef IM |
19 | #include <linux/kdebug.h> |
20 | #include <linux/sched.h> | |
d7d59fb3 | 21 | #include <linux/uaccess.h> |
74193ef0 | 22 | #include <linux/highmem.h> |
241771ef | 23 | |
241771ef | 24 | #include <asm/apic.h> |
d7d59fb3 | 25 | #include <asm/stacktrace.h> |
4e935e47 | 26 | #include <asm/nmi.h> |
241771ef | 27 | |
862a1a5f | 28 | static u64 perf_counter_mask __read_mostly; |
703e937c | 29 | |
241771ef | 30 | struct cpu_hw_counters { |
862a1a5f | 31 | struct perf_counter *counters[X86_PMC_IDX_MAX]; |
43f6201a RR |
32 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
33 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
4b39fd96 | 34 | unsigned long interrupts; |
b0f3f28e | 35 | int enabled; |
241771ef IM |
36 | }; |
37 | ||
38 | /* | |
5f4ec28f | 39 | * struct x86_pmu - generic x86 pmu |
241771ef | 40 | */ |
5f4ec28f | 41 | struct x86_pmu { |
faa28ae0 RR |
42 | const char *name; |
43 | int version; | |
a3288106 | 44 | int (*handle_irq)(struct pt_regs *); |
9e35ad38 PZ |
45 | void (*disable_all)(void); |
46 | void (*enable_all)(void); | |
7c90cc45 | 47 | void (*enable)(struct hw_perf_counter *, int); |
d4369891 | 48 | void (*disable)(struct hw_perf_counter *, int); |
169e41eb JSR |
49 | unsigned eventsel; |
50 | unsigned perfctr; | |
b0f3f28e PZ |
51 | u64 (*event_map)(int); |
52 | u64 (*raw_event)(u64); | |
169e41eb | 53 | int max_events; |
0933e5c6 RR |
54 | int num_counters; |
55 | int num_counters_fixed; | |
56 | int counter_bits; | |
57 | u64 counter_mask; | |
c619b8ff | 58 | u64 max_period; |
9e35ad38 | 59 | u64 intel_ctrl; |
b56a3802 JSR |
60 | }; |
61 | ||
4a06bd85 | 62 | static struct x86_pmu x86_pmu __read_mostly; |
b56a3802 | 63 | |
b0f3f28e PZ |
64 | static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = { |
65 | .enabled = 1, | |
66 | }; | |
241771ef | 67 | |
b56a3802 JSR |
68 | /* |
69 | * Intel PerfMon v3. Used on Core2 and later. | |
70 | */ | |
b0f3f28e | 71 | static const u64 intel_perfmon_event_map[] = |
241771ef | 72 | { |
f4dbfa8f PZ |
73 | [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, |
74 | [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, | |
75 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, | |
76 | [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, | |
77 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, | |
78 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, | |
79 | [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, | |
241771ef IM |
80 | }; |
81 | ||
5f4ec28f | 82 | static u64 intel_pmu_event_map(int event) |
b56a3802 JSR |
83 | { |
84 | return intel_perfmon_event_map[event]; | |
85 | } | |
241771ef | 86 | |
8326f44d IM |
87 | /* |
88 | * Generalized hw caching related event table, filled | |
89 | * in on a per model basis. A value of 0 means | |
90 | * 'not supported', -1 means 'event makes no sense on | |
91 | * this CPU', any other value means the raw event | |
92 | * ID. | |
93 | */ | |
94 | ||
95 | #define C(x) PERF_COUNT_HW_CACHE_##x | |
96 | ||
97 | static u64 __read_mostly hw_cache_event_ids | |
98 | [PERF_COUNT_HW_CACHE_MAX] | |
99 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
100 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
101 | ||
102 | static const u64 nehalem_hw_cache_event_ids | |
103 | [PERF_COUNT_HW_CACHE_MAX] | |
104 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
105 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
106 | { | |
107 | [ C(L1D) ] = { | |
108 | [ C(OP_READ) ] = { | |
109 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ | |
110 | [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ | |
111 | }, | |
112 | [ C(OP_WRITE) ] = { | |
113 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ | |
114 | [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ | |
115 | }, | |
116 | [ C(OP_PREFETCH) ] = { | |
117 | [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ | |
118 | [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ | |
119 | }, | |
120 | }, | |
121 | [ C(L1I ) ] = { | |
122 | [ C(OP_READ) ] = { | |
fecc8ac8 | 123 | [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ |
8326f44d IM |
124 | [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ |
125 | }, | |
126 | [ C(OP_WRITE) ] = { | |
127 | [ C(RESULT_ACCESS) ] = -1, | |
128 | [ C(RESULT_MISS) ] = -1, | |
129 | }, | |
130 | [ C(OP_PREFETCH) ] = { | |
131 | [ C(RESULT_ACCESS) ] = 0x0, | |
132 | [ C(RESULT_MISS) ] = 0x0, | |
133 | }, | |
134 | }, | |
8be6e8f3 | 135 | [ C(LL ) ] = { |
8326f44d IM |
136 | [ C(OP_READ) ] = { |
137 | [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS */ | |
138 | [ C(RESULT_MISS) ] = 0x0224, /* L2_RQSTS.LD_MISS */ | |
139 | }, | |
140 | [ C(OP_WRITE) ] = { | |
141 | [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS */ | |
142 | [ C(RESULT_MISS) ] = 0x0824, /* L2_RQSTS.RFO_MISS */ | |
143 | }, | |
144 | [ C(OP_PREFETCH) ] = { | |
8be6e8f3 PZ |
145 | [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference */ |
146 | [ C(RESULT_MISS) ] = 0x412e, /* LLC Misses */ | |
8326f44d IM |
147 | }, |
148 | }, | |
149 | [ C(DTLB) ] = { | |
150 | [ C(OP_READ) ] = { | |
151 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ | |
152 | [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ | |
153 | }, | |
154 | [ C(OP_WRITE) ] = { | |
155 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ | |
156 | [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ | |
157 | }, | |
158 | [ C(OP_PREFETCH) ] = { | |
159 | [ C(RESULT_ACCESS) ] = 0x0, | |
160 | [ C(RESULT_MISS) ] = 0x0, | |
161 | }, | |
162 | }, | |
163 | [ C(ITLB) ] = { | |
164 | [ C(OP_READ) ] = { | |
165 | [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ | |
fecc8ac8 | 166 | [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ |
8326f44d IM |
167 | }, |
168 | [ C(OP_WRITE) ] = { | |
169 | [ C(RESULT_ACCESS) ] = -1, | |
170 | [ C(RESULT_MISS) ] = -1, | |
171 | }, | |
172 | [ C(OP_PREFETCH) ] = { | |
173 | [ C(RESULT_ACCESS) ] = -1, | |
174 | [ C(RESULT_MISS) ] = -1, | |
175 | }, | |
176 | }, | |
177 | [ C(BPU ) ] = { | |
178 | [ C(OP_READ) ] = { | |
179 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ | |
180 | [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ | |
181 | }, | |
182 | [ C(OP_WRITE) ] = { | |
183 | [ C(RESULT_ACCESS) ] = -1, | |
184 | [ C(RESULT_MISS) ] = -1, | |
185 | }, | |
186 | [ C(OP_PREFETCH) ] = { | |
187 | [ C(RESULT_ACCESS) ] = -1, | |
188 | [ C(RESULT_MISS) ] = -1, | |
189 | }, | |
190 | }, | |
191 | }; | |
192 | ||
193 | static const u64 core2_hw_cache_event_ids | |
194 | [PERF_COUNT_HW_CACHE_MAX] | |
195 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
196 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
197 | { | |
0312af84 TG |
198 | [ C(L1D) ] = { |
199 | [ C(OP_READ) ] = { | |
200 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ | |
201 | [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ | |
202 | }, | |
203 | [ C(OP_WRITE) ] = { | |
204 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ | |
205 | [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ | |
206 | }, | |
207 | [ C(OP_PREFETCH) ] = { | |
208 | [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ | |
209 | [ C(RESULT_MISS) ] = 0, | |
210 | }, | |
211 | }, | |
212 | [ C(L1I ) ] = { | |
213 | [ C(OP_READ) ] = { | |
214 | [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ | |
215 | [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ | |
216 | }, | |
217 | [ C(OP_WRITE) ] = { | |
218 | [ C(RESULT_ACCESS) ] = -1, | |
219 | [ C(RESULT_MISS) ] = -1, | |
220 | }, | |
221 | [ C(OP_PREFETCH) ] = { | |
222 | [ C(RESULT_ACCESS) ] = 0, | |
223 | [ C(RESULT_MISS) ] = 0, | |
224 | }, | |
225 | }, | |
8be6e8f3 | 226 | [ C(LL ) ] = { |
0312af84 TG |
227 | [ C(OP_READ) ] = { |
228 | [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ | |
229 | [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ | |
230 | }, | |
231 | [ C(OP_WRITE) ] = { | |
232 | [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ | |
233 | [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ | |
234 | }, | |
235 | [ C(OP_PREFETCH) ] = { | |
236 | [ C(RESULT_ACCESS) ] = 0, | |
237 | [ C(RESULT_MISS) ] = 0, | |
238 | }, | |
239 | }, | |
240 | [ C(DTLB) ] = { | |
241 | [ C(OP_READ) ] = { | |
242 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ | |
243 | [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ | |
244 | }, | |
245 | [ C(OP_WRITE) ] = { | |
246 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ | |
247 | [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ | |
248 | }, | |
249 | [ C(OP_PREFETCH) ] = { | |
250 | [ C(RESULT_ACCESS) ] = 0, | |
251 | [ C(RESULT_MISS) ] = 0, | |
252 | }, | |
253 | }, | |
254 | [ C(ITLB) ] = { | |
255 | [ C(OP_READ) ] = { | |
256 | [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ | |
257 | [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ | |
258 | }, | |
259 | [ C(OP_WRITE) ] = { | |
260 | [ C(RESULT_ACCESS) ] = -1, | |
261 | [ C(RESULT_MISS) ] = -1, | |
262 | }, | |
263 | [ C(OP_PREFETCH) ] = { | |
264 | [ C(RESULT_ACCESS) ] = -1, | |
265 | [ C(RESULT_MISS) ] = -1, | |
266 | }, | |
267 | }, | |
268 | [ C(BPU ) ] = { | |
269 | [ C(OP_READ) ] = { | |
270 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ | |
271 | [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ | |
272 | }, | |
273 | [ C(OP_WRITE) ] = { | |
274 | [ C(RESULT_ACCESS) ] = -1, | |
275 | [ C(RESULT_MISS) ] = -1, | |
276 | }, | |
277 | [ C(OP_PREFETCH) ] = { | |
278 | [ C(RESULT_ACCESS) ] = -1, | |
279 | [ C(RESULT_MISS) ] = -1, | |
280 | }, | |
281 | }, | |
8326f44d IM |
282 | }; |
283 | ||
284 | static const u64 atom_hw_cache_event_ids | |
285 | [PERF_COUNT_HW_CACHE_MAX] | |
286 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
287 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
288 | { | |
ad689220 TG |
289 | [ C(L1D) ] = { |
290 | [ C(OP_READ) ] = { | |
291 | [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ | |
292 | [ C(RESULT_MISS) ] = 0, | |
293 | }, | |
294 | [ C(OP_WRITE) ] = { | |
fecc8ac8 | 295 | [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ |
ad689220 TG |
296 | [ C(RESULT_MISS) ] = 0, |
297 | }, | |
298 | [ C(OP_PREFETCH) ] = { | |
299 | [ C(RESULT_ACCESS) ] = 0x0, | |
300 | [ C(RESULT_MISS) ] = 0, | |
301 | }, | |
302 | }, | |
303 | [ C(L1I ) ] = { | |
304 | [ C(OP_READ) ] = { | |
fecc8ac8 YW |
305 | [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ |
306 | [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ | |
ad689220 TG |
307 | }, |
308 | [ C(OP_WRITE) ] = { | |
309 | [ C(RESULT_ACCESS) ] = -1, | |
310 | [ C(RESULT_MISS) ] = -1, | |
311 | }, | |
312 | [ C(OP_PREFETCH) ] = { | |
313 | [ C(RESULT_ACCESS) ] = 0, | |
314 | [ C(RESULT_MISS) ] = 0, | |
315 | }, | |
316 | }, | |
8be6e8f3 | 317 | [ C(LL ) ] = { |
ad689220 TG |
318 | [ C(OP_READ) ] = { |
319 | [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ | |
320 | [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ | |
321 | }, | |
322 | [ C(OP_WRITE) ] = { | |
323 | [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ | |
324 | [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ | |
325 | }, | |
326 | [ C(OP_PREFETCH) ] = { | |
327 | [ C(RESULT_ACCESS) ] = 0, | |
328 | [ C(RESULT_MISS) ] = 0, | |
329 | }, | |
330 | }, | |
331 | [ C(DTLB) ] = { | |
332 | [ C(OP_READ) ] = { | |
fecc8ac8 | 333 | [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ |
ad689220 TG |
334 | [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ |
335 | }, | |
336 | [ C(OP_WRITE) ] = { | |
fecc8ac8 | 337 | [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ |
ad689220 TG |
338 | [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ |
339 | }, | |
340 | [ C(OP_PREFETCH) ] = { | |
341 | [ C(RESULT_ACCESS) ] = 0, | |
342 | [ C(RESULT_MISS) ] = 0, | |
343 | }, | |
344 | }, | |
345 | [ C(ITLB) ] = { | |
346 | [ C(OP_READ) ] = { | |
347 | [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ | |
348 | [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ | |
349 | }, | |
350 | [ C(OP_WRITE) ] = { | |
351 | [ C(RESULT_ACCESS) ] = -1, | |
352 | [ C(RESULT_MISS) ] = -1, | |
353 | }, | |
354 | [ C(OP_PREFETCH) ] = { | |
355 | [ C(RESULT_ACCESS) ] = -1, | |
356 | [ C(RESULT_MISS) ] = -1, | |
357 | }, | |
358 | }, | |
359 | [ C(BPU ) ] = { | |
360 | [ C(OP_READ) ] = { | |
361 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ | |
362 | [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ | |
363 | }, | |
364 | [ C(OP_WRITE) ] = { | |
365 | [ C(RESULT_ACCESS) ] = -1, | |
366 | [ C(RESULT_MISS) ] = -1, | |
367 | }, | |
368 | [ C(OP_PREFETCH) ] = { | |
369 | [ C(RESULT_ACCESS) ] = -1, | |
370 | [ C(RESULT_MISS) ] = -1, | |
371 | }, | |
372 | }, | |
8326f44d IM |
373 | }; |
374 | ||
5f4ec28f | 375 | static u64 intel_pmu_raw_event(u64 event) |
b0f3f28e | 376 | { |
82bae4f8 PZ |
377 | #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL |
378 | #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL | |
ff99be57 PZ |
379 | #define CORE_EVNTSEL_EDGE_MASK 0x00040000ULL |
380 | #define CORE_EVNTSEL_INV_MASK 0x00800000ULL | |
82bae4f8 | 381 | #define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL |
b0f3f28e | 382 | |
128f048f | 383 | #define CORE_EVNTSEL_MASK \ |
b0f3f28e PZ |
384 | (CORE_EVNTSEL_EVENT_MASK | \ |
385 | CORE_EVNTSEL_UNIT_MASK | \ | |
ff99be57 PZ |
386 | CORE_EVNTSEL_EDGE_MASK | \ |
387 | CORE_EVNTSEL_INV_MASK | \ | |
b0f3f28e PZ |
388 | CORE_EVNTSEL_COUNTER_MASK) |
389 | ||
390 | return event & CORE_EVNTSEL_MASK; | |
391 | } | |
392 | ||
f4db43a3 | 393 | static const u64 amd_hw_cache_event_ids |
f86748e9 TG |
394 | [PERF_COUNT_HW_CACHE_MAX] |
395 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
396 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
397 | { | |
398 | [ C(L1D) ] = { | |
399 | [ C(OP_READ) ] = { | |
f4db43a3 JSR |
400 | [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */ |
401 | [ C(RESULT_MISS) ] = 0x0041, /* Data Cache Misses */ | |
f86748e9 TG |
402 | }, |
403 | [ C(OP_WRITE) ] = { | |
d9f2a5ec | 404 | [ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */ |
f86748e9 TG |
405 | [ C(RESULT_MISS) ] = 0, |
406 | }, | |
407 | [ C(OP_PREFETCH) ] = { | |
f4db43a3 JSR |
408 | [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */ |
409 | [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */ | |
f86748e9 TG |
410 | }, |
411 | }, | |
412 | [ C(L1I ) ] = { | |
413 | [ C(OP_READ) ] = { | |
414 | [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches */ | |
415 | [ C(RESULT_MISS) ] = 0x0081, /* Instruction cache misses */ | |
416 | }, | |
417 | [ C(OP_WRITE) ] = { | |
418 | [ C(RESULT_ACCESS) ] = -1, | |
419 | [ C(RESULT_MISS) ] = -1, | |
420 | }, | |
421 | [ C(OP_PREFETCH) ] = { | |
f4db43a3 | 422 | [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */ |
f86748e9 TG |
423 | [ C(RESULT_MISS) ] = 0, |
424 | }, | |
425 | }, | |
8be6e8f3 | 426 | [ C(LL ) ] = { |
f86748e9 | 427 | [ C(OP_READ) ] = { |
f4db43a3 JSR |
428 | [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */ |
429 | [ C(RESULT_MISS) ] = 0x037E, /* L2 Cache Misses : IC+DC */ | |
f86748e9 TG |
430 | }, |
431 | [ C(OP_WRITE) ] = { | |
f4db43a3 | 432 | [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback */ |
f86748e9 TG |
433 | [ C(RESULT_MISS) ] = 0, |
434 | }, | |
435 | [ C(OP_PREFETCH) ] = { | |
436 | [ C(RESULT_ACCESS) ] = 0, | |
437 | [ C(RESULT_MISS) ] = 0, | |
438 | }, | |
439 | }, | |
440 | [ C(DTLB) ] = { | |
441 | [ C(OP_READ) ] = { | |
f4db43a3 JSR |
442 | [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */ |
443 | [ C(RESULT_MISS) ] = 0x0046, /* L1 DTLB and L2 DLTB Miss */ | |
f86748e9 TG |
444 | }, |
445 | [ C(OP_WRITE) ] = { | |
446 | [ C(RESULT_ACCESS) ] = 0, | |
447 | [ C(RESULT_MISS) ] = 0, | |
448 | }, | |
449 | [ C(OP_PREFETCH) ] = { | |
450 | [ C(RESULT_ACCESS) ] = 0, | |
451 | [ C(RESULT_MISS) ] = 0, | |
452 | }, | |
453 | }, | |
454 | [ C(ITLB) ] = { | |
455 | [ C(OP_READ) ] = { | |
456 | [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes */ | |
457 | [ C(RESULT_MISS) ] = 0x0085, /* Instr. fetch ITLB misses */ | |
458 | }, | |
459 | [ C(OP_WRITE) ] = { | |
460 | [ C(RESULT_ACCESS) ] = -1, | |
461 | [ C(RESULT_MISS) ] = -1, | |
462 | }, | |
463 | [ C(OP_PREFETCH) ] = { | |
464 | [ C(RESULT_ACCESS) ] = -1, | |
465 | [ C(RESULT_MISS) ] = -1, | |
466 | }, | |
467 | }, | |
468 | [ C(BPU ) ] = { | |
469 | [ C(OP_READ) ] = { | |
470 | [ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr. */ | |
471 | [ C(RESULT_MISS) ] = 0x00c3, /* Retired Mispredicted BI */ | |
472 | }, | |
473 | [ C(OP_WRITE) ] = { | |
474 | [ C(RESULT_ACCESS) ] = -1, | |
475 | [ C(RESULT_MISS) ] = -1, | |
476 | }, | |
477 | [ C(OP_PREFETCH) ] = { | |
478 | [ C(RESULT_ACCESS) ] = -1, | |
479 | [ C(RESULT_MISS) ] = -1, | |
480 | }, | |
481 | }, | |
482 | }; | |
483 | ||
f87ad35d JSR |
484 | /* |
485 | * AMD Performance Monitor K7 and later. | |
486 | */ | |
b0f3f28e | 487 | static const u64 amd_perfmon_event_map[] = |
f87ad35d | 488 | { |
f4dbfa8f PZ |
489 | [PERF_COUNT_HW_CPU_CYCLES] = 0x0076, |
490 | [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, | |
491 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0080, | |
492 | [PERF_COUNT_HW_CACHE_MISSES] = 0x0081, | |
493 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, | |
494 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, | |
f87ad35d JSR |
495 | }; |
496 | ||
5f4ec28f | 497 | static u64 amd_pmu_event_map(int event) |
f87ad35d JSR |
498 | { |
499 | return amd_perfmon_event_map[event]; | |
500 | } | |
501 | ||
5f4ec28f | 502 | static u64 amd_pmu_raw_event(u64 event) |
b0f3f28e | 503 | { |
82bae4f8 PZ |
504 | #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL |
505 | #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL | |
ff99be57 PZ |
506 | #define K7_EVNTSEL_EDGE_MASK 0x000040000ULL |
507 | #define K7_EVNTSEL_INV_MASK 0x000800000ULL | |
82bae4f8 | 508 | #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL |
b0f3f28e PZ |
509 | |
510 | #define K7_EVNTSEL_MASK \ | |
511 | (K7_EVNTSEL_EVENT_MASK | \ | |
512 | K7_EVNTSEL_UNIT_MASK | \ | |
ff99be57 PZ |
513 | K7_EVNTSEL_EDGE_MASK | \ |
514 | K7_EVNTSEL_INV_MASK | \ | |
b0f3f28e PZ |
515 | K7_EVNTSEL_COUNTER_MASK) |
516 | ||
517 | return event & K7_EVNTSEL_MASK; | |
518 | } | |
519 | ||
ee06094f IM |
520 | /* |
521 | * Propagate counter elapsed time into the generic counter. | |
522 | * Can only be executed on the CPU where the counter is active. | |
523 | * Returns the delta events processed. | |
524 | */ | |
4b7bfd0d | 525 | static u64 |
ee06094f IM |
526 | x86_perf_counter_update(struct perf_counter *counter, |
527 | struct hw_perf_counter *hwc, int idx) | |
528 | { | |
ec3232bd PZ |
529 | int shift = 64 - x86_pmu.counter_bits; |
530 | u64 prev_raw_count, new_raw_count; | |
531 | s64 delta; | |
ee06094f | 532 | |
ee06094f IM |
533 | /* |
534 | * Careful: an NMI might modify the previous counter value. | |
535 | * | |
536 | * Our tactic to handle this is to first atomically read and | |
537 | * exchange a new raw count - then add that new-prev delta | |
538 | * count to the generic counter atomically: | |
539 | */ | |
540 | again: | |
541 | prev_raw_count = atomic64_read(&hwc->prev_count); | |
542 | rdmsrl(hwc->counter_base + idx, new_raw_count); | |
543 | ||
544 | if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count, | |
545 | new_raw_count) != prev_raw_count) | |
546 | goto again; | |
547 | ||
548 | /* | |
549 | * Now we have the new raw value and have updated the prev | |
550 | * timestamp already. We can now calculate the elapsed delta | |
551 | * (counter-)time and add that to the generic counter. | |
552 | * | |
553 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 554 | * of the count. |
ee06094f | 555 | */ |
ec3232bd PZ |
556 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
557 | delta >>= shift; | |
ee06094f IM |
558 | |
559 | atomic64_add(delta, &counter->count); | |
560 | atomic64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
561 | |
562 | return new_raw_count; | |
ee06094f IM |
563 | } |
564 | ||
ba77813a | 565 | static atomic_t active_counters; |
4e935e47 PZ |
566 | static DEFINE_MUTEX(pmc_reserve_mutex); |
567 | ||
568 | static bool reserve_pmc_hardware(void) | |
569 | { | |
570 | int i; | |
571 | ||
572 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
573 | disable_lapic_nmi_watchdog(); | |
574 | ||
0933e5c6 | 575 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 | 576 | if (!reserve_perfctr_nmi(x86_pmu.perfctr + i)) |
4e935e47 PZ |
577 | goto perfctr_fail; |
578 | } | |
579 | ||
0933e5c6 | 580 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 | 581 | if (!reserve_evntsel_nmi(x86_pmu.eventsel + i)) |
4e935e47 PZ |
582 | goto eventsel_fail; |
583 | } | |
584 | ||
585 | return true; | |
586 | ||
587 | eventsel_fail: | |
588 | for (i--; i >= 0; i--) | |
4a06bd85 | 589 | release_evntsel_nmi(x86_pmu.eventsel + i); |
4e935e47 | 590 | |
0933e5c6 | 591 | i = x86_pmu.num_counters; |
4e935e47 PZ |
592 | |
593 | perfctr_fail: | |
594 | for (i--; i >= 0; i--) | |
4a06bd85 | 595 | release_perfctr_nmi(x86_pmu.perfctr + i); |
4e935e47 PZ |
596 | |
597 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
598 | enable_lapic_nmi_watchdog(); | |
599 | ||
600 | return false; | |
601 | } | |
602 | ||
603 | static void release_pmc_hardware(void) | |
604 | { | |
605 | int i; | |
606 | ||
0933e5c6 | 607 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 RR |
608 | release_perfctr_nmi(x86_pmu.perfctr + i); |
609 | release_evntsel_nmi(x86_pmu.eventsel + i); | |
4e935e47 PZ |
610 | } |
611 | ||
612 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
613 | enable_lapic_nmi_watchdog(); | |
614 | } | |
615 | ||
616 | static void hw_perf_counter_destroy(struct perf_counter *counter) | |
617 | { | |
ba77813a | 618 | if (atomic_dec_and_mutex_lock(&active_counters, &pmc_reserve_mutex)) { |
4e935e47 PZ |
619 | release_pmc_hardware(); |
620 | mutex_unlock(&pmc_reserve_mutex); | |
621 | } | |
622 | } | |
623 | ||
85cf9dba RR |
624 | static inline int x86_pmu_initialized(void) |
625 | { | |
626 | return x86_pmu.handle_irq != NULL; | |
627 | } | |
628 | ||
8326f44d IM |
629 | static inline int |
630 | set_ext_hw_attr(struct hw_perf_counter *hwc, struct perf_counter_attr *attr) | |
631 | { | |
632 | unsigned int cache_type, cache_op, cache_result; | |
633 | u64 config, val; | |
634 | ||
635 | config = attr->config; | |
636 | ||
637 | cache_type = (config >> 0) & 0xff; | |
638 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
639 | return -EINVAL; | |
640 | ||
641 | cache_op = (config >> 8) & 0xff; | |
642 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
643 | return -EINVAL; | |
644 | ||
645 | cache_result = (config >> 16) & 0xff; | |
646 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
647 | return -EINVAL; | |
648 | ||
649 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
650 | ||
651 | if (val == 0) | |
652 | return -ENOENT; | |
653 | ||
654 | if (val == -1) | |
655 | return -EINVAL; | |
656 | ||
657 | hwc->config |= val; | |
658 | ||
659 | return 0; | |
660 | } | |
661 | ||
241771ef | 662 | /* |
0d48696f | 663 | * Setup the hardware configuration for a given attr_type |
241771ef | 664 | */ |
621a01ea | 665 | static int __hw_perf_counter_init(struct perf_counter *counter) |
241771ef | 666 | { |
0d48696f | 667 | struct perf_counter_attr *attr = &counter->attr; |
241771ef | 668 | struct hw_perf_counter *hwc = &counter->hw; |
4e935e47 | 669 | int err; |
241771ef | 670 | |
85cf9dba RR |
671 | if (!x86_pmu_initialized()) |
672 | return -ENODEV; | |
241771ef | 673 | |
4e935e47 | 674 | err = 0; |
ba77813a | 675 | if (!atomic_inc_not_zero(&active_counters)) { |
4e935e47 | 676 | mutex_lock(&pmc_reserve_mutex); |
ba77813a | 677 | if (atomic_read(&active_counters) == 0 && !reserve_pmc_hardware()) |
4e935e47 PZ |
678 | err = -EBUSY; |
679 | else | |
ba77813a | 680 | atomic_inc(&active_counters); |
4e935e47 PZ |
681 | mutex_unlock(&pmc_reserve_mutex); |
682 | } | |
683 | if (err) | |
684 | return err; | |
685 | ||
241771ef | 686 | /* |
0475f9ea | 687 | * Generate PMC IRQs: |
241771ef IM |
688 | * (keep 'enabled' bit clear for now) |
689 | */ | |
0475f9ea | 690 | hwc->config = ARCH_PERFMON_EVENTSEL_INT; |
241771ef IM |
691 | |
692 | /* | |
0475f9ea | 693 | * Count user and OS events unless requested not to. |
241771ef | 694 | */ |
0d48696f | 695 | if (!attr->exclude_user) |
0475f9ea | 696 | hwc->config |= ARCH_PERFMON_EVENTSEL_USR; |
0d48696f | 697 | if (!attr->exclude_kernel) |
241771ef | 698 | hwc->config |= ARCH_PERFMON_EVENTSEL_OS; |
0475f9ea | 699 | |
bd2b5b12 | 700 | if (!hwc->sample_period) { |
b23f3325 | 701 | hwc->sample_period = x86_pmu.max_period; |
9e350de3 | 702 | hwc->last_period = hwc->sample_period; |
bd2b5b12 PZ |
703 | atomic64_set(&hwc->period_left, hwc->sample_period); |
704 | } | |
d2517a49 | 705 | |
8326f44d | 706 | counter->destroy = hw_perf_counter_destroy; |
241771ef IM |
707 | |
708 | /* | |
dfa7c899 | 709 | * Raw event type provide the config in the event structure |
241771ef | 710 | */ |
a21ca2ca IM |
711 | if (attr->type == PERF_TYPE_RAW) { |
712 | hwc->config |= x86_pmu.raw_event(attr->config); | |
8326f44d | 713 | return 0; |
241771ef | 714 | } |
241771ef | 715 | |
8326f44d IM |
716 | if (attr->type == PERF_TYPE_HW_CACHE) |
717 | return set_ext_hw_attr(hwc, attr); | |
718 | ||
719 | if (attr->config >= x86_pmu.max_events) | |
720 | return -EINVAL; | |
721 | /* | |
722 | * The generic map: | |
723 | */ | |
724 | hwc->config |= x86_pmu.event_map(attr->config); | |
4e935e47 | 725 | |
241771ef IM |
726 | return 0; |
727 | } | |
728 | ||
9e35ad38 | 729 | static void intel_pmu_disable_all(void) |
4ac13294 | 730 | { |
862a1a5f | 731 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); |
241771ef | 732 | } |
b56a3802 | 733 | |
9e35ad38 | 734 | static void amd_pmu_disable_all(void) |
f87ad35d | 735 | { |
b0f3f28e | 736 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
9e35ad38 PZ |
737 | int idx; |
738 | ||
739 | if (!cpuc->enabled) | |
740 | return; | |
b0f3f28e | 741 | |
b0f3f28e | 742 | cpuc->enabled = 0; |
60b3df9c PZ |
743 | /* |
744 | * ensure we write the disable before we start disabling the | |
5f4ec28f RR |
745 | * counters proper, so that amd_pmu_enable_counter() does the |
746 | * right thing. | |
60b3df9c | 747 | */ |
b0f3f28e | 748 | barrier(); |
f87ad35d | 749 | |
0933e5c6 | 750 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
751 | u64 val; |
752 | ||
43f6201a | 753 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 754 | continue; |
f87ad35d | 755 | rdmsrl(MSR_K7_EVNTSEL0 + idx, val); |
4295ee62 RR |
756 | if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE)) |
757 | continue; | |
758 | val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE; | |
759 | wrmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
f87ad35d | 760 | } |
f87ad35d JSR |
761 | } |
762 | ||
9e35ad38 | 763 | void hw_perf_disable(void) |
b56a3802 | 764 | { |
85cf9dba | 765 | if (!x86_pmu_initialized()) |
9e35ad38 PZ |
766 | return; |
767 | return x86_pmu.disable_all(); | |
b56a3802 | 768 | } |
241771ef | 769 | |
9e35ad38 | 770 | static void intel_pmu_enable_all(void) |
b56a3802 | 771 | { |
9e35ad38 | 772 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl); |
b56a3802 JSR |
773 | } |
774 | ||
9e35ad38 | 775 | static void amd_pmu_enable_all(void) |
f87ad35d | 776 | { |
b0f3f28e | 777 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
f87ad35d JSR |
778 | int idx; |
779 | ||
9e35ad38 | 780 | if (cpuc->enabled) |
b0f3f28e PZ |
781 | return; |
782 | ||
9e35ad38 PZ |
783 | cpuc->enabled = 1; |
784 | barrier(); | |
785 | ||
0933e5c6 | 786 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
4295ee62 | 787 | u64 val; |
b0f3f28e | 788 | |
43f6201a | 789 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 RR |
790 | continue; |
791 | rdmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
792 | if (val & ARCH_PERFMON_EVENTSEL0_ENABLE) | |
793 | continue; | |
794 | val |= ARCH_PERFMON_EVENTSEL0_ENABLE; | |
795 | wrmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
f87ad35d JSR |
796 | } |
797 | } | |
798 | ||
9e35ad38 | 799 | void hw_perf_enable(void) |
ee06094f | 800 | { |
85cf9dba | 801 | if (!x86_pmu_initialized()) |
2b9ff0db | 802 | return; |
9e35ad38 | 803 | x86_pmu.enable_all(); |
ee06094f | 804 | } |
ee06094f | 805 | |
19d84dab | 806 | static inline u64 intel_pmu_get_status(void) |
b0f3f28e PZ |
807 | { |
808 | u64 status; | |
809 | ||
b7f8859a | 810 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); |
b0f3f28e | 811 | |
b7f8859a | 812 | return status; |
b0f3f28e PZ |
813 | } |
814 | ||
dee5d906 | 815 | static inline void intel_pmu_ack_status(u64 ack) |
b0f3f28e PZ |
816 | { |
817 | wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); | |
818 | } | |
819 | ||
7c90cc45 | 820 | static inline void x86_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) |
b0f3f28e | 821 | { |
7c90cc45 | 822 | int err; |
7c90cc45 RR |
823 | err = checking_wrmsrl(hwc->config_base + idx, |
824 | hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE); | |
b0f3f28e PZ |
825 | } |
826 | ||
d4369891 | 827 | static inline void x86_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) |
b0f3f28e | 828 | { |
d4369891 | 829 | int err; |
d4369891 RR |
830 | err = checking_wrmsrl(hwc->config_base + idx, |
831 | hwc->config); | |
b0f3f28e PZ |
832 | } |
833 | ||
2f18d1e8 | 834 | static inline void |
d4369891 | 835 | intel_pmu_disable_fixed(struct hw_perf_counter *hwc, int __idx) |
2f18d1e8 IM |
836 | { |
837 | int idx = __idx - X86_PMC_IDX_FIXED; | |
838 | u64 ctrl_val, mask; | |
839 | int err; | |
840 | ||
841 | mask = 0xfULL << (idx * 4); | |
842 | ||
843 | rdmsrl(hwc->config_base, ctrl_val); | |
844 | ctrl_val &= ~mask; | |
845 | err = checking_wrmsrl(hwc->config_base, ctrl_val); | |
846 | } | |
847 | ||
7e2ae347 | 848 | static inline void |
d4369891 | 849 | intel_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) |
7e2ae347 | 850 | { |
d4369891 RR |
851 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { |
852 | intel_pmu_disable_fixed(hwc, idx); | |
853 | return; | |
854 | } | |
855 | ||
856 | x86_pmu_disable_counter(hwc, idx); | |
857 | } | |
858 | ||
859 | static inline void | |
860 | amd_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) | |
861 | { | |
862 | x86_pmu_disable_counter(hwc, idx); | |
7e2ae347 IM |
863 | } |
864 | ||
2f18d1e8 | 865 | static DEFINE_PER_CPU(u64, prev_left[X86_PMC_IDX_MAX]); |
241771ef | 866 | |
ee06094f IM |
867 | /* |
868 | * Set the next IRQ period, based on the hwc->period_left value. | |
869 | * To be called with the counter disabled in hw: | |
870 | */ | |
e4abb5d4 | 871 | static int |
26816c28 | 872 | x86_perf_counter_set_period(struct perf_counter *counter, |
ee06094f | 873 | struct hw_perf_counter *hwc, int idx) |
241771ef | 874 | { |
2f18d1e8 | 875 | s64 left = atomic64_read(&hwc->period_left); |
e4abb5d4 PZ |
876 | s64 period = hwc->sample_period; |
877 | int err, ret = 0; | |
ee06094f | 878 | |
ee06094f IM |
879 | /* |
880 | * If we are way outside a reasoable range then just skip forward: | |
881 | */ | |
882 | if (unlikely(left <= -period)) { | |
883 | left = period; | |
884 | atomic64_set(&hwc->period_left, left); | |
9e350de3 | 885 | hwc->last_period = period; |
e4abb5d4 | 886 | ret = 1; |
ee06094f IM |
887 | } |
888 | ||
889 | if (unlikely(left <= 0)) { | |
890 | left += period; | |
891 | atomic64_set(&hwc->period_left, left); | |
9e350de3 | 892 | hwc->last_period = period; |
e4abb5d4 | 893 | ret = 1; |
ee06094f | 894 | } |
1c80f4b5 IM |
895 | /* |
896 | * Quirk: certain CPUs dont like it if just 1 event is left: | |
897 | */ | |
898 | if (unlikely(left < 2)) | |
899 | left = 2; | |
241771ef | 900 | |
e4abb5d4 PZ |
901 | if (left > x86_pmu.max_period) |
902 | left = x86_pmu.max_period; | |
903 | ||
ee06094f IM |
904 | per_cpu(prev_left[idx], smp_processor_id()) = left; |
905 | ||
906 | /* | |
907 | * The hw counter starts counting from this counter offset, | |
908 | * mark it to be able to extra future deltas: | |
909 | */ | |
2f18d1e8 | 910 | atomic64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 911 | |
2f18d1e8 | 912 | err = checking_wrmsrl(hwc->counter_base + idx, |
0933e5c6 | 913 | (u64)(-left) & x86_pmu.counter_mask); |
e4abb5d4 PZ |
914 | |
915 | return ret; | |
2f18d1e8 IM |
916 | } |
917 | ||
918 | static inline void | |
7c90cc45 | 919 | intel_pmu_enable_fixed(struct hw_perf_counter *hwc, int __idx) |
2f18d1e8 IM |
920 | { |
921 | int idx = __idx - X86_PMC_IDX_FIXED; | |
922 | u64 ctrl_val, bits, mask; | |
923 | int err; | |
924 | ||
925 | /* | |
0475f9ea PM |
926 | * Enable IRQ generation (0x8), |
927 | * and enable ring-3 counting (0x2) and ring-0 counting (0x1) | |
928 | * if requested: | |
2f18d1e8 | 929 | */ |
0475f9ea PM |
930 | bits = 0x8ULL; |
931 | if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) | |
932 | bits |= 0x2; | |
2f18d1e8 IM |
933 | if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) |
934 | bits |= 0x1; | |
935 | bits <<= (idx * 4); | |
936 | mask = 0xfULL << (idx * 4); | |
937 | ||
938 | rdmsrl(hwc->config_base, ctrl_val); | |
939 | ctrl_val &= ~mask; | |
940 | ctrl_val |= bits; | |
941 | err = checking_wrmsrl(hwc->config_base, ctrl_val); | |
7e2ae347 IM |
942 | } |
943 | ||
7c90cc45 | 944 | static void intel_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) |
7e2ae347 | 945 | { |
7c90cc45 RR |
946 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { |
947 | intel_pmu_enable_fixed(hwc, idx); | |
948 | return; | |
949 | } | |
950 | ||
951 | x86_pmu_enable_counter(hwc, idx); | |
952 | } | |
953 | ||
954 | static void amd_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) | |
955 | { | |
956 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
957 | ||
958 | if (cpuc->enabled) | |
959 | x86_pmu_enable_counter(hwc, idx); | |
2b583d8b | 960 | else |
d4369891 | 961 | x86_pmu_disable_counter(hwc, idx); |
241771ef IM |
962 | } |
963 | ||
2f18d1e8 IM |
964 | static int |
965 | fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc) | |
862a1a5f | 966 | { |
2f18d1e8 IM |
967 | unsigned int event; |
968 | ||
ef7b3e09 | 969 | if (!x86_pmu.num_counters_fixed) |
f87ad35d JSR |
970 | return -1; |
971 | ||
2f18d1e8 IM |
972 | event = hwc->config & ARCH_PERFMON_EVENT_MASK; |
973 | ||
f4dbfa8f | 974 | if (unlikely(event == x86_pmu.event_map(PERF_COUNT_HW_INSTRUCTIONS))) |
2f18d1e8 | 975 | return X86_PMC_IDX_FIXED_INSTRUCTIONS; |
f4dbfa8f | 976 | if (unlikely(event == x86_pmu.event_map(PERF_COUNT_HW_CPU_CYCLES))) |
2f18d1e8 | 977 | return X86_PMC_IDX_FIXED_CPU_CYCLES; |
f4dbfa8f | 978 | if (unlikely(event == x86_pmu.event_map(PERF_COUNT_HW_BUS_CYCLES))) |
2f18d1e8 IM |
979 | return X86_PMC_IDX_FIXED_BUS_CYCLES; |
980 | ||
862a1a5f IM |
981 | return -1; |
982 | } | |
983 | ||
ee06094f IM |
984 | /* |
985 | * Find a PMC slot for the freshly enabled / scheduled in counter: | |
986 | */ | |
4aeb0b42 | 987 | static int x86_pmu_enable(struct perf_counter *counter) |
241771ef IM |
988 | { |
989 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
990 | struct hw_perf_counter *hwc = &counter->hw; | |
2f18d1e8 | 991 | int idx; |
241771ef | 992 | |
2f18d1e8 IM |
993 | idx = fixed_mode_idx(counter, hwc); |
994 | if (idx >= 0) { | |
995 | /* | |
996 | * Try to get the fixed counter, if that is already taken | |
997 | * then try to get a generic counter: | |
998 | */ | |
43f6201a | 999 | if (test_and_set_bit(idx, cpuc->used_mask)) |
2f18d1e8 | 1000 | goto try_generic; |
0dff86aa | 1001 | |
2f18d1e8 IM |
1002 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
1003 | /* | |
1004 | * We set it so that counter_base + idx in wrmsr/rdmsr maps to | |
1005 | * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2: | |
1006 | */ | |
1007 | hwc->counter_base = | |
1008 | MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED; | |
241771ef | 1009 | hwc->idx = idx; |
2f18d1e8 IM |
1010 | } else { |
1011 | idx = hwc->idx; | |
1012 | /* Try to get the previous generic counter again */ | |
43f6201a | 1013 | if (test_and_set_bit(idx, cpuc->used_mask)) { |
2f18d1e8 | 1014 | try_generic: |
43f6201a | 1015 | idx = find_first_zero_bit(cpuc->used_mask, |
0933e5c6 RR |
1016 | x86_pmu.num_counters); |
1017 | if (idx == x86_pmu.num_counters) | |
2f18d1e8 IM |
1018 | return -EAGAIN; |
1019 | ||
43f6201a | 1020 | set_bit(idx, cpuc->used_mask); |
2f18d1e8 IM |
1021 | hwc->idx = idx; |
1022 | } | |
4a06bd85 RR |
1023 | hwc->config_base = x86_pmu.eventsel; |
1024 | hwc->counter_base = x86_pmu.perfctr; | |
241771ef IM |
1025 | } |
1026 | ||
c323d95f | 1027 | perf_counters_lapic_init(); |
53b441a5 | 1028 | |
d4369891 | 1029 | x86_pmu.disable(hwc, idx); |
241771ef | 1030 | |
862a1a5f | 1031 | cpuc->counters[idx] = counter; |
43f6201a | 1032 | set_bit(idx, cpuc->active_mask); |
7e2ae347 | 1033 | |
26816c28 | 1034 | x86_perf_counter_set_period(counter, hwc, idx); |
7c90cc45 | 1035 | x86_pmu.enable(hwc, idx); |
95cdd2e7 IM |
1036 | |
1037 | return 0; | |
241771ef IM |
1038 | } |
1039 | ||
a78ac325 PZ |
1040 | static void x86_pmu_unthrottle(struct perf_counter *counter) |
1041 | { | |
1042 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
1043 | struct hw_perf_counter *hwc = &counter->hw; | |
1044 | ||
1045 | if (WARN_ON_ONCE(hwc->idx >= X86_PMC_IDX_MAX || | |
1046 | cpuc->counters[hwc->idx] != counter)) | |
1047 | return; | |
1048 | ||
1049 | x86_pmu.enable(hwc, hwc->idx); | |
1050 | } | |
1051 | ||
241771ef IM |
1052 | void perf_counter_print_debug(void) |
1053 | { | |
2f18d1e8 | 1054 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
0dff86aa | 1055 | struct cpu_hw_counters *cpuc; |
5bb9efe3 | 1056 | unsigned long flags; |
1e125676 IM |
1057 | int cpu, idx; |
1058 | ||
0933e5c6 | 1059 | if (!x86_pmu.num_counters) |
1e125676 | 1060 | return; |
241771ef | 1061 | |
5bb9efe3 | 1062 | local_irq_save(flags); |
241771ef IM |
1063 | |
1064 | cpu = smp_processor_id(); | |
0dff86aa | 1065 | cpuc = &per_cpu(cpu_hw_counters, cpu); |
241771ef | 1066 | |
faa28ae0 | 1067 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1068 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1069 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1070 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1071 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
1072 | ||
1073 | pr_info("\n"); | |
1074 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1075 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1076 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1077 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
f87ad35d | 1078 | } |
43f6201a | 1079 | pr_info("CPU#%d: used: %016llx\n", cpu, *(u64 *)cpuc->used_mask); |
241771ef | 1080 | |
0933e5c6 | 1081 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
4a06bd85 RR |
1082 | rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl); |
1083 | rdmsrl(x86_pmu.perfctr + idx, pmc_count); | |
241771ef | 1084 | |
ee06094f | 1085 | prev_left = per_cpu(prev_left[idx], cpu); |
241771ef | 1086 | |
a1ef58f4 | 1087 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1088 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1089 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1090 | cpu, idx, pmc_count); |
a1ef58f4 | 1091 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1092 | cpu, idx, prev_left); |
241771ef | 1093 | } |
0933e5c6 | 1094 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
1095 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1096 | ||
a1ef58f4 | 1097 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1098 | cpu, idx, pmc_count); |
1099 | } | |
5bb9efe3 | 1100 | local_irq_restore(flags); |
241771ef IM |
1101 | } |
1102 | ||
4aeb0b42 | 1103 | static void x86_pmu_disable(struct perf_counter *counter) |
241771ef IM |
1104 | { |
1105 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
1106 | struct hw_perf_counter *hwc = &counter->hw; | |
6f00cada | 1107 | int idx = hwc->idx; |
241771ef | 1108 | |
09534238 RR |
1109 | /* |
1110 | * Must be done before we disable, otherwise the nmi handler | |
1111 | * could reenable again: | |
1112 | */ | |
43f6201a | 1113 | clear_bit(idx, cpuc->active_mask); |
d4369891 | 1114 | x86_pmu.disable(hwc, idx); |
241771ef | 1115 | |
2f18d1e8 IM |
1116 | /* |
1117 | * Make sure the cleared pointer becomes visible before we | |
1118 | * (potentially) free the counter: | |
1119 | */ | |
527e26af | 1120 | barrier(); |
241771ef | 1121 | |
ee06094f IM |
1122 | /* |
1123 | * Drain the remaining delta count out of a counter | |
1124 | * that we are disabling: | |
1125 | */ | |
1126 | x86_perf_counter_update(counter, hwc, idx); | |
09534238 | 1127 | cpuc->counters[idx] = NULL; |
43f6201a | 1128 | clear_bit(idx, cpuc->used_mask); |
241771ef IM |
1129 | } |
1130 | ||
7e2ae347 | 1131 | /* |
ee06094f IM |
1132 | * Save and restart an expired counter. Called by NMI contexts, |
1133 | * so it has to be careful about preempting normal counter ops: | |
7e2ae347 | 1134 | */ |
e4abb5d4 | 1135 | static int intel_pmu_save_and_restart(struct perf_counter *counter) |
241771ef IM |
1136 | { |
1137 | struct hw_perf_counter *hwc = &counter->hw; | |
1138 | int idx = hwc->idx; | |
e4abb5d4 | 1139 | int ret; |
241771ef | 1140 | |
ee06094f | 1141 | x86_perf_counter_update(counter, hwc, idx); |
e4abb5d4 | 1142 | ret = x86_perf_counter_set_period(counter, hwc, idx); |
7e2ae347 | 1143 | |
2f18d1e8 | 1144 | if (counter->state == PERF_COUNTER_STATE_ACTIVE) |
7c90cc45 | 1145 | intel_pmu_enable_counter(hwc, idx); |
e4abb5d4 PZ |
1146 | |
1147 | return ret; | |
241771ef IM |
1148 | } |
1149 | ||
aaba9801 IM |
1150 | static void intel_pmu_reset(void) |
1151 | { | |
1152 | unsigned long flags; | |
1153 | int idx; | |
1154 | ||
1155 | if (!x86_pmu.num_counters) | |
1156 | return; | |
1157 | ||
1158 | local_irq_save(flags); | |
1159 | ||
1160 | printk("clearing PMU state on CPU#%d\n", smp_processor_id()); | |
1161 | ||
1162 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { | |
1163 | checking_wrmsrl(x86_pmu.eventsel + idx, 0ull); | |
1164 | checking_wrmsrl(x86_pmu.perfctr + idx, 0ull); | |
1165 | } | |
1166 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { | |
1167 | checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); | |
1168 | } | |
1169 | ||
1170 | local_irq_restore(flags); | |
1171 | } | |
1172 | ||
1173 | ||
241771ef IM |
1174 | /* |
1175 | * This handler is triggered by the local APIC, so the APIC IRQ handling | |
1176 | * rules apply: | |
1177 | */ | |
a3288106 | 1178 | static int intel_pmu_handle_irq(struct pt_regs *regs) |
241771ef | 1179 | { |
df1a132b | 1180 | struct perf_sample_data data; |
9029a5e3 | 1181 | struct cpu_hw_counters *cpuc; |
9029a5e3 | 1182 | int bit, cpu, loops; |
4b39fd96 | 1183 | u64 ack, status; |
9029a5e3 | 1184 | |
df1a132b PZ |
1185 | data.regs = regs; |
1186 | data.addr = 0; | |
1187 | ||
9029a5e3 IM |
1188 | cpu = smp_processor_id(); |
1189 | cpuc = &per_cpu(cpu_hw_counters, cpu); | |
241771ef | 1190 | |
9e35ad38 | 1191 | perf_disable(); |
19d84dab | 1192 | status = intel_pmu_get_status(); |
9e35ad38 PZ |
1193 | if (!status) { |
1194 | perf_enable(); | |
1195 | return 0; | |
1196 | } | |
87b9cf46 | 1197 | |
9029a5e3 | 1198 | loops = 0; |
241771ef | 1199 | again: |
9029a5e3 IM |
1200 | if (++loops > 100) { |
1201 | WARN_ONCE(1, "perfcounters: irq loop stuck!\n"); | |
34adc806 | 1202 | perf_counter_print_debug(); |
aaba9801 IM |
1203 | intel_pmu_reset(); |
1204 | perf_enable(); | |
9029a5e3 IM |
1205 | return 1; |
1206 | } | |
1207 | ||
d278c484 | 1208 | inc_irq_stat(apic_perf_irqs); |
241771ef | 1209 | ack = status; |
2f18d1e8 | 1210 | for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { |
862a1a5f | 1211 | struct perf_counter *counter = cpuc->counters[bit]; |
241771ef IM |
1212 | |
1213 | clear_bit(bit, (unsigned long *) &status); | |
43f6201a | 1214 | if (!test_bit(bit, cpuc->active_mask)) |
241771ef IM |
1215 | continue; |
1216 | ||
e4abb5d4 PZ |
1217 | if (!intel_pmu_save_and_restart(counter)) |
1218 | continue; | |
1219 | ||
60f916de PZ |
1220 | data.period = counter->hw.last_period; |
1221 | ||
df1a132b | 1222 | if (perf_counter_overflow(counter, 1, &data)) |
d4369891 | 1223 | intel_pmu_disable_counter(&counter->hw, bit); |
241771ef IM |
1224 | } |
1225 | ||
dee5d906 | 1226 | intel_pmu_ack_status(ack); |
241771ef IM |
1227 | |
1228 | /* | |
1229 | * Repeat if there is more work to be done: | |
1230 | */ | |
19d84dab | 1231 | status = intel_pmu_get_status(); |
241771ef IM |
1232 | if (status) |
1233 | goto again; | |
b0f3f28e | 1234 | |
48e22d56 | 1235 | perf_enable(); |
9e35ad38 PZ |
1236 | |
1237 | return 1; | |
1b023a96 MG |
1238 | } |
1239 | ||
a3288106 | 1240 | static int amd_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1241 | { |
df1a132b | 1242 | struct perf_sample_data data; |
9029a5e3 | 1243 | struct cpu_hw_counters *cpuc; |
a29aa8a7 RR |
1244 | struct perf_counter *counter; |
1245 | struct hw_perf_counter *hwc; | |
df1a132b | 1246 | int cpu, idx, handled = 0; |
9029a5e3 IM |
1247 | u64 val; |
1248 | ||
df1a132b PZ |
1249 | data.regs = regs; |
1250 | data.addr = 0; | |
1251 | ||
9029a5e3 IM |
1252 | cpu = smp_processor_id(); |
1253 | cpuc = &per_cpu(cpu_hw_counters, cpu); | |
962bf7a6 | 1254 | |
a29aa8a7 | 1255 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
43f6201a | 1256 | if (!test_bit(idx, cpuc->active_mask)) |
a29aa8a7 | 1257 | continue; |
962bf7a6 | 1258 | |
a29aa8a7 RR |
1259 | counter = cpuc->counters[idx]; |
1260 | hwc = &counter->hw; | |
a4016a79 | 1261 | |
4b7bfd0d | 1262 | val = x86_perf_counter_update(counter, hwc, idx); |
a29aa8a7 | 1263 | if (val & (1ULL << (x86_pmu.counter_bits - 1))) |
48e22d56 | 1264 | continue; |
962bf7a6 | 1265 | |
9e350de3 PZ |
1266 | /* |
1267 | * counter overflow | |
1268 | */ | |
1269 | handled = 1; | |
1270 | data.period = counter->hw.last_period; | |
1271 | ||
e4abb5d4 PZ |
1272 | if (!x86_perf_counter_set_period(counter, hwc, idx)) |
1273 | continue; | |
1274 | ||
df1a132b | 1275 | if (perf_counter_overflow(counter, 1, &data)) |
a29aa8a7 | 1276 | amd_pmu_disable_counter(hwc, idx); |
a29aa8a7 | 1277 | } |
962bf7a6 | 1278 | |
9e350de3 PZ |
1279 | if (handled) |
1280 | inc_irq_stat(apic_perf_irqs); | |
1281 | ||
a29aa8a7 RR |
1282 | return handled; |
1283 | } | |
39d81eab | 1284 | |
b6276f35 PZ |
1285 | void smp_perf_pending_interrupt(struct pt_regs *regs) |
1286 | { | |
1287 | irq_enter(); | |
1288 | ack_APIC_irq(); | |
1289 | inc_irq_stat(apic_pending_irqs); | |
1290 | perf_counter_do_pending(); | |
1291 | irq_exit(); | |
1292 | } | |
1293 | ||
1294 | void set_perf_counter_pending(void) | |
1295 | { | |
1296 | apic->send_IPI_self(LOCAL_PENDING_VECTOR); | |
1297 | } | |
1298 | ||
c323d95f | 1299 | void perf_counters_lapic_init(void) |
241771ef | 1300 | { |
85cf9dba | 1301 | if (!x86_pmu_initialized()) |
241771ef | 1302 | return; |
85cf9dba | 1303 | |
241771ef | 1304 | /* |
c323d95f | 1305 | * Always use NMI for PMU |
241771ef | 1306 | */ |
c323d95f | 1307 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1308 | } |
1309 | ||
1310 | static int __kprobes | |
1311 | perf_counter_nmi_handler(struct notifier_block *self, | |
1312 | unsigned long cmd, void *__args) | |
1313 | { | |
1314 | struct die_args *args = __args; | |
1315 | struct pt_regs *regs; | |
b0f3f28e | 1316 | |
ba77813a | 1317 | if (!atomic_read(&active_counters)) |
63a809a2 PZ |
1318 | return NOTIFY_DONE; |
1319 | ||
b0f3f28e PZ |
1320 | switch (cmd) { |
1321 | case DIE_NMI: | |
1322 | case DIE_NMI_IPI: | |
1323 | break; | |
241771ef | 1324 | |
b0f3f28e | 1325 | default: |
241771ef | 1326 | return NOTIFY_DONE; |
b0f3f28e | 1327 | } |
241771ef IM |
1328 | |
1329 | regs = args->regs; | |
1330 | ||
1331 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
a4016a79 PZ |
1332 | /* |
1333 | * Can't rely on the handled return value to say it was our NMI, two | |
1334 | * counters could trigger 'simultaneously' raising two back-to-back NMIs. | |
1335 | * | |
1336 | * If the first NMI handles both, the latter will be empty and daze | |
1337 | * the CPU. | |
1338 | */ | |
a3288106 | 1339 | x86_pmu.handle_irq(regs); |
241771ef | 1340 | |
a4016a79 | 1341 | return NOTIFY_STOP; |
241771ef IM |
1342 | } |
1343 | ||
1344 | static __read_mostly struct notifier_block perf_counter_nmi_notifier = { | |
5b75af0a MG |
1345 | .notifier_call = perf_counter_nmi_handler, |
1346 | .next = NULL, | |
1347 | .priority = 1 | |
241771ef IM |
1348 | }; |
1349 | ||
5f4ec28f | 1350 | static struct x86_pmu intel_pmu = { |
faa28ae0 | 1351 | .name = "Intel", |
39d81eab | 1352 | .handle_irq = intel_pmu_handle_irq, |
9e35ad38 PZ |
1353 | .disable_all = intel_pmu_disable_all, |
1354 | .enable_all = intel_pmu_enable_all, | |
5f4ec28f RR |
1355 | .enable = intel_pmu_enable_counter, |
1356 | .disable = intel_pmu_disable_counter, | |
b56a3802 JSR |
1357 | .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, |
1358 | .perfctr = MSR_ARCH_PERFMON_PERFCTR0, | |
5f4ec28f RR |
1359 | .event_map = intel_pmu_event_map, |
1360 | .raw_event = intel_pmu_raw_event, | |
b56a3802 | 1361 | .max_events = ARRAY_SIZE(intel_perfmon_event_map), |
c619b8ff RR |
1362 | /* |
1363 | * Intel PMCs cannot be accessed sanely above 32 bit width, | |
1364 | * so we install an artificial 1<<31 period regardless of | |
1365 | * the generic counter period: | |
1366 | */ | |
1367 | .max_period = (1ULL << 31) - 1, | |
b56a3802 JSR |
1368 | }; |
1369 | ||
5f4ec28f | 1370 | static struct x86_pmu amd_pmu = { |
faa28ae0 | 1371 | .name = "AMD", |
39d81eab | 1372 | .handle_irq = amd_pmu_handle_irq, |
9e35ad38 PZ |
1373 | .disable_all = amd_pmu_disable_all, |
1374 | .enable_all = amd_pmu_enable_all, | |
5f4ec28f RR |
1375 | .enable = amd_pmu_enable_counter, |
1376 | .disable = amd_pmu_disable_counter, | |
f87ad35d JSR |
1377 | .eventsel = MSR_K7_EVNTSEL0, |
1378 | .perfctr = MSR_K7_PERFCTR0, | |
5f4ec28f RR |
1379 | .event_map = amd_pmu_event_map, |
1380 | .raw_event = amd_pmu_raw_event, | |
f87ad35d | 1381 | .max_events = ARRAY_SIZE(amd_perfmon_event_map), |
0933e5c6 RR |
1382 | .num_counters = 4, |
1383 | .counter_bits = 48, | |
1384 | .counter_mask = (1ULL << 48) - 1, | |
c619b8ff RR |
1385 | /* use highest bit to detect overflow */ |
1386 | .max_period = (1ULL << 47) - 1, | |
f87ad35d JSR |
1387 | }; |
1388 | ||
72eae04d | 1389 | static int intel_pmu_init(void) |
241771ef | 1390 | { |
7bb497bd | 1391 | union cpuid10_edx edx; |
241771ef | 1392 | union cpuid10_eax eax; |
703e937c | 1393 | unsigned int unused; |
7bb497bd | 1394 | unsigned int ebx; |
faa28ae0 | 1395 | int version; |
241771ef | 1396 | |
da1a776b | 1397 | if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) |
72eae04d | 1398 | return -ENODEV; |
da1a776b | 1399 | |
241771ef IM |
1400 | /* |
1401 | * Check whether the Architectural PerfMon supports | |
1402 | * Branch Misses Retired Event or not. | |
1403 | */ | |
703e937c | 1404 | cpuid(10, &eax.full, &ebx, &unused, &edx.full); |
241771ef | 1405 | if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED) |
72eae04d | 1406 | return -ENODEV; |
241771ef | 1407 | |
faa28ae0 RR |
1408 | version = eax.split.version_id; |
1409 | if (version < 2) | |
72eae04d | 1410 | return -ENODEV; |
7bb497bd | 1411 | |
1123e3ad IM |
1412 | x86_pmu = intel_pmu; |
1413 | x86_pmu.version = version; | |
1414 | x86_pmu.num_counters = eax.split.num_counters; | |
1415 | x86_pmu.counter_bits = eax.split.bit_width; | |
1416 | x86_pmu.counter_mask = (1ULL << eax.split.bit_width) - 1; | |
066d7dea IM |
1417 | |
1418 | /* | |
1419 | * Quirk: v2 perfmon does not report fixed-purpose counters, so | |
1420 | * assume at least 3 counters: | |
1421 | */ | |
1123e3ad | 1422 | x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3); |
b56a3802 | 1423 | |
8326f44d | 1424 | /* |
1123e3ad | 1425 | * Install the hw-cache-events table: |
8326f44d IM |
1426 | */ |
1427 | switch (boot_cpu_data.x86_model) { | |
dc81081b YW |
1428 | case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */ |
1429 | case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */ | |
1430 | case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */ | |
1431 | case 29: /* six-core 45 nm xeon "Dunnington" */ | |
8326f44d | 1432 | memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, |
820a6442 | 1433 | sizeof(hw_cache_event_ids)); |
8326f44d | 1434 | |
1123e3ad | 1435 | pr_cont("Core2 events, "); |
8326f44d IM |
1436 | break; |
1437 | default: | |
1438 | case 26: | |
1439 | memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, | |
820a6442 | 1440 | sizeof(hw_cache_event_ids)); |
8326f44d | 1441 | |
1123e3ad | 1442 | pr_cont("Nehalem/Corei7 events, "); |
8326f44d IM |
1443 | break; |
1444 | case 28: | |
1445 | memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, | |
820a6442 | 1446 | sizeof(hw_cache_event_ids)); |
8326f44d | 1447 | |
1123e3ad | 1448 | pr_cont("Atom events, "); |
8326f44d IM |
1449 | break; |
1450 | } | |
72eae04d | 1451 | return 0; |
b56a3802 JSR |
1452 | } |
1453 | ||
72eae04d | 1454 | static int amd_pmu_init(void) |
f87ad35d | 1455 | { |
4d2be126 JSR |
1456 | /* Performance-monitoring supported from K7 and later: */ |
1457 | if (boot_cpu_data.x86 < 6) | |
1458 | return -ENODEV; | |
1459 | ||
4a06bd85 | 1460 | x86_pmu = amd_pmu; |
f86748e9 | 1461 | |
f4db43a3 JSR |
1462 | /* Events are common for all AMDs */ |
1463 | memcpy(hw_cache_event_ids, amd_hw_cache_event_ids, | |
1464 | sizeof(hw_cache_event_ids)); | |
f86748e9 | 1465 | |
72eae04d | 1466 | return 0; |
f87ad35d JSR |
1467 | } |
1468 | ||
b56a3802 JSR |
1469 | void __init init_hw_perf_counters(void) |
1470 | { | |
72eae04d RR |
1471 | int err; |
1472 | ||
1123e3ad IM |
1473 | pr_info("Performance Counters: "); |
1474 | ||
b56a3802 JSR |
1475 | switch (boot_cpu_data.x86_vendor) { |
1476 | case X86_VENDOR_INTEL: | |
72eae04d | 1477 | err = intel_pmu_init(); |
b56a3802 | 1478 | break; |
f87ad35d | 1479 | case X86_VENDOR_AMD: |
72eae04d | 1480 | err = amd_pmu_init(); |
f87ad35d | 1481 | break; |
4138960a RR |
1482 | default: |
1483 | return; | |
b56a3802 | 1484 | } |
1123e3ad IM |
1485 | if (err != 0) { |
1486 | pr_cont("no PMU driver, software counters only.\n"); | |
b56a3802 | 1487 | return; |
1123e3ad | 1488 | } |
b56a3802 | 1489 | |
1123e3ad | 1490 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1491 | |
0933e5c6 RR |
1492 | if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) { |
1493 | x86_pmu.num_counters = X86_PMC_MAX_GENERIC; | |
241771ef | 1494 | WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!", |
0933e5c6 | 1495 | x86_pmu.num_counters, X86_PMC_MAX_GENERIC); |
241771ef | 1496 | } |
0933e5c6 RR |
1497 | perf_counter_mask = (1 << x86_pmu.num_counters) - 1; |
1498 | perf_max_counters = x86_pmu.num_counters; | |
241771ef | 1499 | |
0933e5c6 RR |
1500 | if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { |
1501 | x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; | |
703e937c | 1502 | WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!", |
0933e5c6 | 1503 | x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED); |
703e937c | 1504 | } |
862a1a5f | 1505 | |
0933e5c6 RR |
1506 | perf_counter_mask |= |
1507 | ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED; | |
c14dab5c | 1508 | x86_pmu.intel_ctrl = perf_counter_mask; |
241771ef | 1509 | |
c323d95f | 1510 | perf_counters_lapic_init(); |
241771ef | 1511 | register_die_notifier(&perf_counter_nmi_notifier); |
1123e3ad IM |
1512 | |
1513 | pr_info("... version: %d\n", x86_pmu.version); | |
1514 | pr_info("... bit width: %d\n", x86_pmu.counter_bits); | |
1515 | pr_info("... generic counters: %d\n", x86_pmu.num_counters); | |
1516 | pr_info("... value mask: %016Lx\n", x86_pmu.counter_mask); | |
1517 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); | |
1518 | pr_info("... fixed-purpose counters: %d\n", x86_pmu.num_counters_fixed); | |
1519 | pr_info("... counter mask: %016Lx\n", perf_counter_mask); | |
241771ef | 1520 | } |
621a01ea | 1521 | |
bb775fc2 | 1522 | static inline void x86_pmu_read(struct perf_counter *counter) |
ee06094f IM |
1523 | { |
1524 | x86_perf_counter_update(counter, &counter->hw, counter->hw.idx); | |
1525 | } | |
1526 | ||
4aeb0b42 RR |
1527 | static const struct pmu pmu = { |
1528 | .enable = x86_pmu_enable, | |
1529 | .disable = x86_pmu_disable, | |
1530 | .read = x86_pmu_read, | |
a78ac325 | 1531 | .unthrottle = x86_pmu_unthrottle, |
621a01ea IM |
1532 | }; |
1533 | ||
4aeb0b42 | 1534 | const struct pmu *hw_perf_counter_init(struct perf_counter *counter) |
621a01ea IM |
1535 | { |
1536 | int err; | |
1537 | ||
1538 | err = __hw_perf_counter_init(counter); | |
1539 | if (err) | |
9ea98e19 | 1540 | return ERR_PTR(err); |
621a01ea | 1541 | |
4aeb0b42 | 1542 | return &pmu; |
621a01ea | 1543 | } |
d7d59fb3 PZ |
1544 | |
1545 | /* | |
1546 | * callchain support | |
1547 | */ | |
1548 | ||
1549 | static inline | |
f9188e02 | 1550 | void callchain_store(struct perf_callchain_entry *entry, u64 ip) |
d7d59fb3 | 1551 | { |
f9188e02 | 1552 | if (entry->nr < PERF_MAX_STACK_DEPTH) |
d7d59fb3 PZ |
1553 | entry->ip[entry->nr++] = ip; |
1554 | } | |
1555 | ||
1556 | static DEFINE_PER_CPU(struct perf_callchain_entry, irq_entry); | |
1557 | static DEFINE_PER_CPU(struct perf_callchain_entry, nmi_entry); | |
1558 | ||
1559 | ||
1560 | static void | |
1561 | backtrace_warning_symbol(void *data, char *msg, unsigned long symbol) | |
1562 | { | |
1563 | /* Ignore warnings */ | |
1564 | } | |
1565 | ||
1566 | static void backtrace_warning(void *data, char *msg) | |
1567 | { | |
1568 | /* Ignore warnings */ | |
1569 | } | |
1570 | ||
1571 | static int backtrace_stack(void *data, char *name) | |
1572 | { | |
038e836e IM |
1573 | /* Process all stacks: */ |
1574 | return 0; | |
d7d59fb3 PZ |
1575 | } |
1576 | ||
1577 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1578 | { | |
1579 | struct perf_callchain_entry *entry = data; | |
1580 | ||
1581 | if (reliable) | |
1582 | callchain_store(entry, addr); | |
1583 | } | |
1584 | ||
1585 | static const struct stacktrace_ops backtrace_ops = { | |
1586 | .warning = backtrace_warning, | |
1587 | .warning_symbol = backtrace_warning_symbol, | |
1588 | .stack = backtrace_stack, | |
1589 | .address = backtrace_address, | |
1590 | }; | |
1591 | ||
038e836e IM |
1592 | #include "../dumpstack.h" |
1593 | ||
d7d59fb3 PZ |
1594 | static void |
1595 | perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1596 | { | |
f9188e02 | 1597 | callchain_store(entry, PERF_CONTEXT_KERNEL); |
038e836e | 1598 | callchain_store(entry, regs->ip); |
d7d59fb3 | 1599 | |
f9188e02 | 1600 | dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry); |
d7d59fb3 PZ |
1601 | } |
1602 | ||
74193ef0 PZ |
1603 | /* |
1604 | * best effort, GUP based copy_from_user() that assumes IRQ or NMI context | |
1605 | */ | |
1606 | static unsigned long | |
1607 | copy_from_user_nmi(void *to, const void __user *from, unsigned long n) | |
d7d59fb3 | 1608 | { |
74193ef0 PZ |
1609 | unsigned long offset, addr = (unsigned long)from; |
1610 | int type = in_nmi() ? KM_NMI : KM_IRQ0; | |
1611 | unsigned long size, len = 0; | |
1612 | struct page *page; | |
1613 | void *map; | |
d7d59fb3 PZ |
1614 | int ret; |
1615 | ||
74193ef0 PZ |
1616 | do { |
1617 | ret = __get_user_pages_fast(addr, 1, 0, &page); | |
1618 | if (!ret) | |
1619 | break; | |
d7d59fb3 | 1620 | |
74193ef0 PZ |
1621 | offset = addr & (PAGE_SIZE - 1); |
1622 | size = min(PAGE_SIZE - offset, n - len); | |
d7d59fb3 | 1623 | |
74193ef0 PZ |
1624 | map = kmap_atomic(page, type); |
1625 | memcpy(to, map+offset, size); | |
1626 | kunmap_atomic(map, type); | |
1627 | put_page(page); | |
1628 | ||
1629 | len += size; | |
1630 | to += size; | |
1631 | addr += size; | |
1632 | ||
1633 | } while (len < n); | |
1634 | ||
1635 | return len; | |
1636 | } | |
1637 | ||
1638 | static int copy_stack_frame(const void __user *fp, struct stack_frame *frame) | |
1639 | { | |
1640 | unsigned long bytes; | |
1641 | ||
1642 | bytes = copy_from_user_nmi(frame, fp, sizeof(*frame)); | |
1643 | ||
1644 | return bytes == sizeof(*frame); | |
d7d59fb3 PZ |
1645 | } |
1646 | ||
1647 | static void | |
1648 | perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1649 | { | |
1650 | struct stack_frame frame; | |
1651 | const void __user *fp; | |
1652 | ||
5a6cec3a IM |
1653 | if (!user_mode(regs)) |
1654 | regs = task_pt_regs(current); | |
1655 | ||
74193ef0 | 1656 | fp = (void __user *)regs->bp; |
d7d59fb3 | 1657 | |
f9188e02 | 1658 | callchain_store(entry, PERF_CONTEXT_USER); |
d7d59fb3 PZ |
1659 | callchain_store(entry, regs->ip); |
1660 | ||
f9188e02 | 1661 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
038e836e | 1662 | frame.next_frame = NULL; |
d7d59fb3 PZ |
1663 | frame.return_address = 0; |
1664 | ||
1665 | if (!copy_stack_frame(fp, &frame)) | |
1666 | break; | |
1667 | ||
5a6cec3a | 1668 | if ((unsigned long)fp < regs->sp) |
d7d59fb3 PZ |
1669 | break; |
1670 | ||
1671 | callchain_store(entry, frame.return_address); | |
038e836e | 1672 | fp = frame.next_frame; |
d7d59fb3 PZ |
1673 | } |
1674 | } | |
1675 | ||
1676 | static void | |
1677 | perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1678 | { | |
1679 | int is_user; | |
1680 | ||
1681 | if (!regs) | |
1682 | return; | |
1683 | ||
1684 | is_user = user_mode(regs); | |
1685 | ||
1686 | if (!current || current->pid == 0) | |
1687 | return; | |
1688 | ||
1689 | if (is_user && current->state != TASK_RUNNING) | |
1690 | return; | |
1691 | ||
1692 | if (!is_user) | |
1693 | perf_callchain_kernel(regs, entry); | |
1694 | ||
1695 | if (current->mm) | |
1696 | perf_callchain_user(regs, entry); | |
1697 | } | |
1698 | ||
1699 | struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) | |
1700 | { | |
1701 | struct perf_callchain_entry *entry; | |
1702 | ||
1703 | if (in_nmi()) | |
1704 | entry = &__get_cpu_var(nmi_entry); | |
1705 | else | |
1706 | entry = &__get_cpu_var(irq_entry); | |
1707 | ||
1708 | entry->nr = 0; | |
1709 | ||
1710 | perf_do_callchain(regs, entry); | |
1711 | ||
1712 | return entry; | |
1713 | } |