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Commit | Line | Data |
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241771ef IM |
1 | /* |
2 | * Performance counter x86 architecture code | |
3 | * | |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
241771ef IM |
9 | * |
10 | * For licencing details see kernel-base/COPYING | |
11 | */ | |
12 | ||
13 | #include <linux/perf_counter.h> | |
14 | #include <linux/capability.h> | |
15 | #include <linux/notifier.h> | |
16 | #include <linux/hardirq.h> | |
17 | #include <linux/kprobes.h> | |
4ac13294 | 18 | #include <linux/module.h> |
241771ef IM |
19 | #include <linux/kdebug.h> |
20 | #include <linux/sched.h> | |
d7d59fb3 | 21 | #include <linux/uaccess.h> |
241771ef | 22 | |
241771ef | 23 | #include <asm/apic.h> |
d7d59fb3 | 24 | #include <asm/stacktrace.h> |
4e935e47 | 25 | #include <asm/nmi.h> |
241771ef | 26 | |
862a1a5f | 27 | static u64 perf_counter_mask __read_mostly; |
703e937c | 28 | |
241771ef | 29 | struct cpu_hw_counters { |
862a1a5f | 30 | struct perf_counter *counters[X86_PMC_IDX_MAX]; |
43f6201a RR |
31 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
32 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
4b39fd96 | 33 | unsigned long interrupts; |
b0f3f28e | 34 | int enabled; |
241771ef IM |
35 | }; |
36 | ||
37 | /* | |
5f4ec28f | 38 | * struct x86_pmu - generic x86 pmu |
241771ef | 39 | */ |
5f4ec28f | 40 | struct x86_pmu { |
faa28ae0 RR |
41 | const char *name; |
42 | int version; | |
39d81eab | 43 | int (*handle_irq)(struct pt_regs *, int); |
9e35ad38 PZ |
44 | void (*disable_all)(void); |
45 | void (*enable_all)(void); | |
7c90cc45 | 46 | void (*enable)(struct hw_perf_counter *, int); |
d4369891 | 47 | void (*disable)(struct hw_perf_counter *, int); |
169e41eb JSR |
48 | unsigned eventsel; |
49 | unsigned perfctr; | |
b0f3f28e PZ |
50 | u64 (*event_map)(int); |
51 | u64 (*raw_event)(u64); | |
169e41eb | 52 | int max_events; |
0933e5c6 RR |
53 | int num_counters; |
54 | int num_counters_fixed; | |
55 | int counter_bits; | |
56 | u64 counter_mask; | |
c619b8ff | 57 | u64 max_period; |
9e35ad38 | 58 | u64 intel_ctrl; |
b56a3802 JSR |
59 | }; |
60 | ||
4a06bd85 | 61 | static struct x86_pmu x86_pmu __read_mostly; |
b56a3802 | 62 | |
b0f3f28e PZ |
63 | static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = { |
64 | .enabled = 1, | |
65 | }; | |
241771ef | 66 | |
b56a3802 JSR |
67 | /* |
68 | * Intel PerfMon v3. Used on Core2 and later. | |
69 | */ | |
b0f3f28e | 70 | static const u64 intel_perfmon_event_map[] = |
241771ef | 71 | { |
f650a672 | 72 | [PERF_COUNT_CPU_CYCLES] = 0x003c, |
241771ef IM |
73 | [PERF_COUNT_INSTRUCTIONS] = 0x00c0, |
74 | [PERF_COUNT_CACHE_REFERENCES] = 0x4f2e, | |
75 | [PERF_COUNT_CACHE_MISSES] = 0x412e, | |
76 | [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4, | |
77 | [PERF_COUNT_BRANCH_MISSES] = 0x00c5, | |
f650a672 | 78 | [PERF_COUNT_BUS_CYCLES] = 0x013c, |
241771ef IM |
79 | }; |
80 | ||
5f4ec28f | 81 | static u64 intel_pmu_event_map(int event) |
b56a3802 JSR |
82 | { |
83 | return intel_perfmon_event_map[event]; | |
84 | } | |
241771ef | 85 | |
5f4ec28f | 86 | static u64 intel_pmu_raw_event(u64 event) |
b0f3f28e | 87 | { |
82bae4f8 PZ |
88 | #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL |
89 | #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL | |
90 | #define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL | |
b0f3f28e PZ |
91 | |
92 | #define CORE_EVNTSEL_MASK \ | |
93 | (CORE_EVNTSEL_EVENT_MASK | \ | |
94 | CORE_EVNTSEL_UNIT_MASK | \ | |
95 | CORE_EVNTSEL_COUNTER_MASK) | |
96 | ||
97 | return event & CORE_EVNTSEL_MASK; | |
98 | } | |
99 | ||
f87ad35d JSR |
100 | /* |
101 | * AMD Performance Monitor K7 and later. | |
102 | */ | |
b0f3f28e | 103 | static const u64 amd_perfmon_event_map[] = |
f87ad35d JSR |
104 | { |
105 | [PERF_COUNT_CPU_CYCLES] = 0x0076, | |
106 | [PERF_COUNT_INSTRUCTIONS] = 0x00c0, | |
107 | [PERF_COUNT_CACHE_REFERENCES] = 0x0080, | |
108 | [PERF_COUNT_CACHE_MISSES] = 0x0081, | |
109 | [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4, | |
110 | [PERF_COUNT_BRANCH_MISSES] = 0x00c5, | |
111 | }; | |
112 | ||
5f4ec28f | 113 | static u64 amd_pmu_event_map(int event) |
f87ad35d JSR |
114 | { |
115 | return amd_perfmon_event_map[event]; | |
116 | } | |
117 | ||
5f4ec28f | 118 | static u64 amd_pmu_raw_event(u64 event) |
b0f3f28e | 119 | { |
82bae4f8 PZ |
120 | #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL |
121 | #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL | |
122 | #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL | |
b0f3f28e PZ |
123 | |
124 | #define K7_EVNTSEL_MASK \ | |
125 | (K7_EVNTSEL_EVENT_MASK | \ | |
126 | K7_EVNTSEL_UNIT_MASK | \ | |
127 | K7_EVNTSEL_COUNTER_MASK) | |
128 | ||
129 | return event & K7_EVNTSEL_MASK; | |
130 | } | |
131 | ||
ee06094f IM |
132 | /* |
133 | * Propagate counter elapsed time into the generic counter. | |
134 | * Can only be executed on the CPU where the counter is active. | |
135 | * Returns the delta events processed. | |
136 | */ | |
4b7bfd0d | 137 | static u64 |
ee06094f IM |
138 | x86_perf_counter_update(struct perf_counter *counter, |
139 | struct hw_perf_counter *hwc, int idx) | |
140 | { | |
ec3232bd PZ |
141 | int shift = 64 - x86_pmu.counter_bits; |
142 | u64 prev_raw_count, new_raw_count; | |
143 | s64 delta; | |
ee06094f | 144 | |
ee06094f IM |
145 | /* |
146 | * Careful: an NMI might modify the previous counter value. | |
147 | * | |
148 | * Our tactic to handle this is to first atomically read and | |
149 | * exchange a new raw count - then add that new-prev delta | |
150 | * count to the generic counter atomically: | |
151 | */ | |
152 | again: | |
153 | prev_raw_count = atomic64_read(&hwc->prev_count); | |
154 | rdmsrl(hwc->counter_base + idx, new_raw_count); | |
155 | ||
156 | if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count, | |
157 | new_raw_count) != prev_raw_count) | |
158 | goto again; | |
159 | ||
160 | /* | |
161 | * Now we have the new raw value and have updated the prev | |
162 | * timestamp already. We can now calculate the elapsed delta | |
163 | * (counter-)time and add that to the generic counter. | |
164 | * | |
165 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 166 | * of the count. |
ee06094f | 167 | */ |
ec3232bd PZ |
168 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
169 | delta >>= shift; | |
ee06094f IM |
170 | |
171 | atomic64_add(delta, &counter->count); | |
172 | atomic64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
173 | |
174 | return new_raw_count; | |
ee06094f IM |
175 | } |
176 | ||
ba77813a | 177 | static atomic_t active_counters; |
4e935e47 PZ |
178 | static DEFINE_MUTEX(pmc_reserve_mutex); |
179 | ||
180 | static bool reserve_pmc_hardware(void) | |
181 | { | |
182 | int i; | |
183 | ||
184 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
185 | disable_lapic_nmi_watchdog(); | |
186 | ||
0933e5c6 | 187 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 | 188 | if (!reserve_perfctr_nmi(x86_pmu.perfctr + i)) |
4e935e47 PZ |
189 | goto perfctr_fail; |
190 | } | |
191 | ||
0933e5c6 | 192 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 | 193 | if (!reserve_evntsel_nmi(x86_pmu.eventsel + i)) |
4e935e47 PZ |
194 | goto eventsel_fail; |
195 | } | |
196 | ||
197 | return true; | |
198 | ||
199 | eventsel_fail: | |
200 | for (i--; i >= 0; i--) | |
4a06bd85 | 201 | release_evntsel_nmi(x86_pmu.eventsel + i); |
4e935e47 | 202 | |
0933e5c6 | 203 | i = x86_pmu.num_counters; |
4e935e47 PZ |
204 | |
205 | perfctr_fail: | |
206 | for (i--; i >= 0; i--) | |
4a06bd85 | 207 | release_perfctr_nmi(x86_pmu.perfctr + i); |
4e935e47 PZ |
208 | |
209 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
210 | enable_lapic_nmi_watchdog(); | |
211 | ||
212 | return false; | |
213 | } | |
214 | ||
215 | static void release_pmc_hardware(void) | |
216 | { | |
217 | int i; | |
218 | ||
0933e5c6 | 219 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 RR |
220 | release_perfctr_nmi(x86_pmu.perfctr + i); |
221 | release_evntsel_nmi(x86_pmu.eventsel + i); | |
4e935e47 PZ |
222 | } |
223 | ||
224 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
225 | enable_lapic_nmi_watchdog(); | |
226 | } | |
227 | ||
228 | static void hw_perf_counter_destroy(struct perf_counter *counter) | |
229 | { | |
ba77813a | 230 | if (atomic_dec_and_mutex_lock(&active_counters, &pmc_reserve_mutex)) { |
4e935e47 PZ |
231 | release_pmc_hardware(); |
232 | mutex_unlock(&pmc_reserve_mutex); | |
233 | } | |
234 | } | |
235 | ||
85cf9dba RR |
236 | static inline int x86_pmu_initialized(void) |
237 | { | |
238 | return x86_pmu.handle_irq != NULL; | |
239 | } | |
240 | ||
241771ef IM |
241 | /* |
242 | * Setup the hardware configuration for a given hw_event_type | |
243 | */ | |
621a01ea | 244 | static int __hw_perf_counter_init(struct perf_counter *counter) |
241771ef | 245 | { |
9f66a381 | 246 | struct perf_counter_hw_event *hw_event = &counter->hw_event; |
241771ef | 247 | struct hw_perf_counter *hwc = &counter->hw; |
4e935e47 | 248 | int err; |
241771ef | 249 | |
85cf9dba RR |
250 | if (!x86_pmu_initialized()) |
251 | return -ENODEV; | |
241771ef | 252 | |
4e935e47 | 253 | err = 0; |
ba77813a | 254 | if (!atomic_inc_not_zero(&active_counters)) { |
4e935e47 | 255 | mutex_lock(&pmc_reserve_mutex); |
ba77813a | 256 | if (atomic_read(&active_counters) == 0 && !reserve_pmc_hardware()) |
4e935e47 PZ |
257 | err = -EBUSY; |
258 | else | |
ba77813a | 259 | atomic_inc(&active_counters); |
4e935e47 PZ |
260 | mutex_unlock(&pmc_reserve_mutex); |
261 | } | |
262 | if (err) | |
263 | return err; | |
264 | ||
241771ef | 265 | /* |
0475f9ea | 266 | * Generate PMC IRQs: |
241771ef IM |
267 | * (keep 'enabled' bit clear for now) |
268 | */ | |
0475f9ea | 269 | hwc->config = ARCH_PERFMON_EVENTSEL_INT; |
241771ef IM |
270 | |
271 | /* | |
0475f9ea | 272 | * Count user and OS events unless requested not to. |
241771ef | 273 | */ |
0475f9ea PM |
274 | if (!hw_event->exclude_user) |
275 | hwc->config |= ARCH_PERFMON_EVENTSEL_USR; | |
276 | if (!hw_event->exclude_kernel) | |
241771ef | 277 | hwc->config |= ARCH_PERFMON_EVENTSEL_OS; |
0475f9ea PM |
278 | |
279 | /* | |
280 | * If privileged enough, allow NMI events: | |
281 | */ | |
282 | hwc->nmi = 0; | |
a026dfec PZ |
283 | if (hw_event->nmi) { |
284 | if (sysctl_perf_counter_priv && !capable(CAP_SYS_ADMIN)) | |
285 | return -EACCES; | |
0475f9ea | 286 | hwc->nmi = 1; |
a026dfec | 287 | } |
241771ef | 288 | |
ba77813a | 289 | hwc->irq_period = hw_event->irq_period; |
c619b8ff RR |
290 | if ((s64)hwc->irq_period <= 0 || hwc->irq_period > x86_pmu.max_period) |
291 | hwc->irq_period = x86_pmu.max_period; | |
241771ef | 292 | |
ee06094f | 293 | atomic64_set(&hwc->period_left, hwc->irq_period); |
241771ef IM |
294 | |
295 | /* | |
dfa7c899 | 296 | * Raw event type provide the config in the event structure |
241771ef | 297 | */ |
f4a2deb4 | 298 | if (perf_event_raw(hw_event)) { |
4a06bd85 | 299 | hwc->config |= x86_pmu.raw_event(perf_event_config(hw_event)); |
241771ef | 300 | } else { |
4a06bd85 | 301 | if (perf_event_id(hw_event) >= x86_pmu.max_events) |
241771ef IM |
302 | return -EINVAL; |
303 | /* | |
304 | * The generic map: | |
305 | */ | |
4a06bd85 | 306 | hwc->config |= x86_pmu.event_map(perf_event_id(hw_event)); |
241771ef | 307 | } |
241771ef | 308 | |
4e935e47 PZ |
309 | counter->destroy = hw_perf_counter_destroy; |
310 | ||
241771ef IM |
311 | return 0; |
312 | } | |
313 | ||
9e35ad38 | 314 | static void intel_pmu_disable_all(void) |
4ac13294 | 315 | { |
862a1a5f | 316 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); |
241771ef | 317 | } |
b56a3802 | 318 | |
9e35ad38 | 319 | static void amd_pmu_disable_all(void) |
f87ad35d | 320 | { |
b0f3f28e | 321 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
9e35ad38 PZ |
322 | int idx; |
323 | ||
324 | if (!cpuc->enabled) | |
325 | return; | |
b0f3f28e | 326 | |
b0f3f28e | 327 | cpuc->enabled = 0; |
60b3df9c PZ |
328 | /* |
329 | * ensure we write the disable before we start disabling the | |
5f4ec28f RR |
330 | * counters proper, so that amd_pmu_enable_counter() does the |
331 | * right thing. | |
60b3df9c | 332 | */ |
b0f3f28e | 333 | barrier(); |
f87ad35d | 334 | |
0933e5c6 | 335 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
336 | u64 val; |
337 | ||
43f6201a | 338 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 339 | continue; |
f87ad35d | 340 | rdmsrl(MSR_K7_EVNTSEL0 + idx, val); |
4295ee62 RR |
341 | if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE)) |
342 | continue; | |
343 | val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE; | |
344 | wrmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
f87ad35d | 345 | } |
f87ad35d JSR |
346 | } |
347 | ||
9e35ad38 | 348 | void hw_perf_disable(void) |
b56a3802 | 349 | { |
85cf9dba | 350 | if (!x86_pmu_initialized()) |
9e35ad38 PZ |
351 | return; |
352 | return x86_pmu.disable_all(); | |
b56a3802 | 353 | } |
241771ef | 354 | |
9e35ad38 | 355 | static void intel_pmu_enable_all(void) |
b56a3802 | 356 | { |
9e35ad38 | 357 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl); |
b56a3802 JSR |
358 | } |
359 | ||
9e35ad38 | 360 | static void amd_pmu_enable_all(void) |
f87ad35d | 361 | { |
b0f3f28e | 362 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
f87ad35d JSR |
363 | int idx; |
364 | ||
9e35ad38 | 365 | if (cpuc->enabled) |
b0f3f28e PZ |
366 | return; |
367 | ||
9e35ad38 PZ |
368 | cpuc->enabled = 1; |
369 | barrier(); | |
370 | ||
0933e5c6 | 371 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
4295ee62 | 372 | u64 val; |
b0f3f28e | 373 | |
43f6201a | 374 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 RR |
375 | continue; |
376 | rdmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
377 | if (val & ARCH_PERFMON_EVENTSEL0_ENABLE) | |
378 | continue; | |
379 | val |= ARCH_PERFMON_EVENTSEL0_ENABLE; | |
380 | wrmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
f87ad35d JSR |
381 | } |
382 | } | |
383 | ||
9e35ad38 | 384 | void hw_perf_enable(void) |
ee06094f | 385 | { |
85cf9dba | 386 | if (!x86_pmu_initialized()) |
2b9ff0db | 387 | return; |
9e35ad38 | 388 | x86_pmu.enable_all(); |
ee06094f | 389 | } |
ee06094f | 390 | |
19d84dab | 391 | static inline u64 intel_pmu_get_status(void) |
b0f3f28e PZ |
392 | { |
393 | u64 status; | |
394 | ||
b7f8859a | 395 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); |
b0f3f28e | 396 | |
b7f8859a | 397 | return status; |
b0f3f28e PZ |
398 | } |
399 | ||
dee5d906 | 400 | static inline void intel_pmu_ack_status(u64 ack) |
b0f3f28e PZ |
401 | { |
402 | wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); | |
403 | } | |
404 | ||
7c90cc45 | 405 | static inline void x86_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) |
b0f3f28e | 406 | { |
7c90cc45 | 407 | int err; |
7c90cc45 RR |
408 | err = checking_wrmsrl(hwc->config_base + idx, |
409 | hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE); | |
b0f3f28e PZ |
410 | } |
411 | ||
d4369891 | 412 | static inline void x86_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) |
b0f3f28e | 413 | { |
d4369891 | 414 | int err; |
d4369891 RR |
415 | err = checking_wrmsrl(hwc->config_base + idx, |
416 | hwc->config); | |
b0f3f28e PZ |
417 | } |
418 | ||
2f18d1e8 | 419 | static inline void |
d4369891 | 420 | intel_pmu_disable_fixed(struct hw_perf_counter *hwc, int __idx) |
2f18d1e8 IM |
421 | { |
422 | int idx = __idx - X86_PMC_IDX_FIXED; | |
423 | u64 ctrl_val, mask; | |
424 | int err; | |
425 | ||
426 | mask = 0xfULL << (idx * 4); | |
427 | ||
428 | rdmsrl(hwc->config_base, ctrl_val); | |
429 | ctrl_val &= ~mask; | |
430 | err = checking_wrmsrl(hwc->config_base, ctrl_val); | |
431 | } | |
432 | ||
7e2ae347 | 433 | static inline void |
d4369891 | 434 | intel_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) |
7e2ae347 | 435 | { |
d4369891 RR |
436 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { |
437 | intel_pmu_disable_fixed(hwc, idx); | |
438 | return; | |
439 | } | |
440 | ||
441 | x86_pmu_disable_counter(hwc, idx); | |
442 | } | |
443 | ||
444 | static inline void | |
445 | amd_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) | |
446 | { | |
447 | x86_pmu_disable_counter(hwc, idx); | |
7e2ae347 IM |
448 | } |
449 | ||
2f18d1e8 | 450 | static DEFINE_PER_CPU(u64, prev_left[X86_PMC_IDX_MAX]); |
241771ef | 451 | |
ee06094f IM |
452 | /* |
453 | * Set the next IRQ period, based on the hwc->period_left value. | |
454 | * To be called with the counter disabled in hw: | |
455 | */ | |
456 | static void | |
26816c28 | 457 | x86_perf_counter_set_period(struct perf_counter *counter, |
ee06094f | 458 | struct hw_perf_counter *hwc, int idx) |
241771ef | 459 | { |
2f18d1e8 | 460 | s64 left = atomic64_read(&hwc->period_left); |
595258aa | 461 | s64 period = hwc->irq_period; |
2f18d1e8 | 462 | int err; |
ee06094f | 463 | |
ee06094f IM |
464 | /* |
465 | * If we are way outside a reasoable range then just skip forward: | |
466 | */ | |
467 | if (unlikely(left <= -period)) { | |
468 | left = period; | |
469 | atomic64_set(&hwc->period_left, left); | |
470 | } | |
471 | ||
472 | if (unlikely(left <= 0)) { | |
473 | left += period; | |
474 | atomic64_set(&hwc->period_left, left); | |
475 | } | |
241771ef | 476 | |
ee06094f IM |
477 | per_cpu(prev_left[idx], smp_processor_id()) = left; |
478 | ||
479 | /* | |
480 | * The hw counter starts counting from this counter offset, | |
481 | * mark it to be able to extra future deltas: | |
482 | */ | |
2f18d1e8 | 483 | atomic64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 484 | |
2f18d1e8 | 485 | err = checking_wrmsrl(hwc->counter_base + idx, |
0933e5c6 | 486 | (u64)(-left) & x86_pmu.counter_mask); |
2f18d1e8 IM |
487 | } |
488 | ||
489 | static inline void | |
7c90cc45 | 490 | intel_pmu_enable_fixed(struct hw_perf_counter *hwc, int __idx) |
2f18d1e8 IM |
491 | { |
492 | int idx = __idx - X86_PMC_IDX_FIXED; | |
493 | u64 ctrl_val, bits, mask; | |
494 | int err; | |
495 | ||
496 | /* | |
0475f9ea PM |
497 | * Enable IRQ generation (0x8), |
498 | * and enable ring-3 counting (0x2) and ring-0 counting (0x1) | |
499 | * if requested: | |
2f18d1e8 | 500 | */ |
0475f9ea PM |
501 | bits = 0x8ULL; |
502 | if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) | |
503 | bits |= 0x2; | |
2f18d1e8 IM |
504 | if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) |
505 | bits |= 0x1; | |
506 | bits <<= (idx * 4); | |
507 | mask = 0xfULL << (idx * 4); | |
508 | ||
509 | rdmsrl(hwc->config_base, ctrl_val); | |
510 | ctrl_val &= ~mask; | |
511 | ctrl_val |= bits; | |
512 | err = checking_wrmsrl(hwc->config_base, ctrl_val); | |
7e2ae347 IM |
513 | } |
514 | ||
7c90cc45 | 515 | static void intel_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) |
7e2ae347 | 516 | { |
7c90cc45 RR |
517 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { |
518 | intel_pmu_enable_fixed(hwc, idx); | |
519 | return; | |
520 | } | |
521 | ||
522 | x86_pmu_enable_counter(hwc, idx); | |
523 | } | |
524 | ||
525 | static void amd_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) | |
526 | { | |
527 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
528 | ||
529 | if (cpuc->enabled) | |
530 | x86_pmu_enable_counter(hwc, idx); | |
2b583d8b | 531 | else |
d4369891 | 532 | x86_pmu_disable_counter(hwc, idx); |
241771ef IM |
533 | } |
534 | ||
2f18d1e8 IM |
535 | static int |
536 | fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc) | |
862a1a5f | 537 | { |
2f18d1e8 IM |
538 | unsigned int event; |
539 | ||
ef7b3e09 | 540 | if (!x86_pmu.num_counters_fixed) |
f87ad35d JSR |
541 | return -1; |
542 | ||
2f18d1e8 IM |
543 | if (unlikely(hwc->nmi)) |
544 | return -1; | |
545 | ||
546 | event = hwc->config & ARCH_PERFMON_EVENT_MASK; | |
547 | ||
4a06bd85 | 548 | if (unlikely(event == x86_pmu.event_map(PERF_COUNT_INSTRUCTIONS))) |
2f18d1e8 | 549 | return X86_PMC_IDX_FIXED_INSTRUCTIONS; |
4a06bd85 | 550 | if (unlikely(event == x86_pmu.event_map(PERF_COUNT_CPU_CYCLES))) |
2f18d1e8 | 551 | return X86_PMC_IDX_FIXED_CPU_CYCLES; |
4a06bd85 | 552 | if (unlikely(event == x86_pmu.event_map(PERF_COUNT_BUS_CYCLES))) |
2f18d1e8 IM |
553 | return X86_PMC_IDX_FIXED_BUS_CYCLES; |
554 | ||
862a1a5f IM |
555 | return -1; |
556 | } | |
557 | ||
ee06094f IM |
558 | /* |
559 | * Find a PMC slot for the freshly enabled / scheduled in counter: | |
560 | */ | |
4aeb0b42 | 561 | static int x86_pmu_enable(struct perf_counter *counter) |
241771ef IM |
562 | { |
563 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
564 | struct hw_perf_counter *hwc = &counter->hw; | |
2f18d1e8 | 565 | int idx; |
241771ef | 566 | |
2f18d1e8 IM |
567 | idx = fixed_mode_idx(counter, hwc); |
568 | if (idx >= 0) { | |
569 | /* | |
570 | * Try to get the fixed counter, if that is already taken | |
571 | * then try to get a generic counter: | |
572 | */ | |
43f6201a | 573 | if (test_and_set_bit(idx, cpuc->used_mask)) |
2f18d1e8 | 574 | goto try_generic; |
0dff86aa | 575 | |
2f18d1e8 IM |
576 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
577 | /* | |
578 | * We set it so that counter_base + idx in wrmsr/rdmsr maps to | |
579 | * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2: | |
580 | */ | |
581 | hwc->counter_base = | |
582 | MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED; | |
241771ef | 583 | hwc->idx = idx; |
2f18d1e8 IM |
584 | } else { |
585 | idx = hwc->idx; | |
586 | /* Try to get the previous generic counter again */ | |
43f6201a | 587 | if (test_and_set_bit(idx, cpuc->used_mask)) { |
2f18d1e8 | 588 | try_generic: |
43f6201a | 589 | idx = find_first_zero_bit(cpuc->used_mask, |
0933e5c6 RR |
590 | x86_pmu.num_counters); |
591 | if (idx == x86_pmu.num_counters) | |
2f18d1e8 IM |
592 | return -EAGAIN; |
593 | ||
43f6201a | 594 | set_bit(idx, cpuc->used_mask); |
2f18d1e8 IM |
595 | hwc->idx = idx; |
596 | } | |
4a06bd85 RR |
597 | hwc->config_base = x86_pmu.eventsel; |
598 | hwc->counter_base = x86_pmu.perfctr; | |
241771ef IM |
599 | } |
600 | ||
601 | perf_counters_lapic_init(hwc->nmi); | |
602 | ||
d4369891 | 603 | x86_pmu.disable(hwc, idx); |
241771ef | 604 | |
862a1a5f | 605 | cpuc->counters[idx] = counter; |
43f6201a | 606 | set_bit(idx, cpuc->active_mask); |
7e2ae347 | 607 | |
26816c28 | 608 | x86_perf_counter_set_period(counter, hwc, idx); |
7c90cc45 | 609 | x86_pmu.enable(hwc, idx); |
95cdd2e7 IM |
610 | |
611 | return 0; | |
241771ef IM |
612 | } |
613 | ||
614 | void perf_counter_print_debug(void) | |
615 | { | |
2f18d1e8 | 616 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
0dff86aa | 617 | struct cpu_hw_counters *cpuc; |
5bb9efe3 | 618 | unsigned long flags; |
1e125676 IM |
619 | int cpu, idx; |
620 | ||
0933e5c6 | 621 | if (!x86_pmu.num_counters) |
1e125676 | 622 | return; |
241771ef | 623 | |
5bb9efe3 | 624 | local_irq_save(flags); |
241771ef IM |
625 | |
626 | cpu = smp_processor_id(); | |
0dff86aa | 627 | cpuc = &per_cpu(cpu_hw_counters, cpu); |
241771ef | 628 | |
faa28ae0 | 629 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
630 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
631 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
632 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
633 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
634 | ||
635 | pr_info("\n"); | |
636 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
637 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
638 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
639 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
f87ad35d | 640 | } |
43f6201a | 641 | pr_info("CPU#%d: used: %016llx\n", cpu, *(u64 *)cpuc->used_mask); |
241771ef | 642 | |
0933e5c6 | 643 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
4a06bd85 RR |
644 | rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl); |
645 | rdmsrl(x86_pmu.perfctr + idx, pmc_count); | |
241771ef | 646 | |
ee06094f | 647 | prev_left = per_cpu(prev_left[idx], cpu); |
241771ef | 648 | |
a1ef58f4 | 649 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 650 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 651 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 652 | cpu, idx, pmc_count); |
a1ef58f4 | 653 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 654 | cpu, idx, prev_left); |
241771ef | 655 | } |
0933e5c6 | 656 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
657 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
658 | ||
a1ef58f4 | 659 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
660 | cpu, idx, pmc_count); |
661 | } | |
5bb9efe3 | 662 | local_irq_restore(flags); |
241771ef IM |
663 | } |
664 | ||
4aeb0b42 | 665 | static void x86_pmu_disable(struct perf_counter *counter) |
241771ef IM |
666 | { |
667 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
668 | struct hw_perf_counter *hwc = &counter->hw; | |
6f00cada | 669 | int idx = hwc->idx; |
241771ef | 670 | |
09534238 RR |
671 | /* |
672 | * Must be done before we disable, otherwise the nmi handler | |
673 | * could reenable again: | |
674 | */ | |
43f6201a | 675 | clear_bit(idx, cpuc->active_mask); |
d4369891 | 676 | x86_pmu.disable(hwc, idx); |
241771ef | 677 | |
2f18d1e8 IM |
678 | /* |
679 | * Make sure the cleared pointer becomes visible before we | |
680 | * (potentially) free the counter: | |
681 | */ | |
527e26af | 682 | barrier(); |
241771ef | 683 | |
ee06094f IM |
684 | /* |
685 | * Drain the remaining delta count out of a counter | |
686 | * that we are disabling: | |
687 | */ | |
688 | x86_perf_counter_update(counter, hwc, idx); | |
09534238 | 689 | cpuc->counters[idx] = NULL; |
43f6201a | 690 | clear_bit(idx, cpuc->used_mask); |
241771ef IM |
691 | } |
692 | ||
7e2ae347 | 693 | /* |
ee06094f IM |
694 | * Save and restart an expired counter. Called by NMI contexts, |
695 | * so it has to be careful about preempting normal counter ops: | |
7e2ae347 | 696 | */ |
55de0f2e | 697 | static void intel_pmu_save_and_restart(struct perf_counter *counter) |
241771ef IM |
698 | { |
699 | struct hw_perf_counter *hwc = &counter->hw; | |
700 | int idx = hwc->idx; | |
241771ef | 701 | |
ee06094f | 702 | x86_perf_counter_update(counter, hwc, idx); |
26816c28 | 703 | x86_perf_counter_set_period(counter, hwc, idx); |
7e2ae347 | 704 | |
2f18d1e8 | 705 | if (counter->state == PERF_COUNTER_STATE_ACTIVE) |
7c90cc45 | 706 | intel_pmu_enable_counter(hwc, idx); |
241771ef IM |
707 | } |
708 | ||
4b39fd96 MG |
709 | /* |
710 | * Maximum interrupt frequency of 100KHz per CPU | |
711 | */ | |
169e41eb | 712 | #define PERFMON_MAX_INTERRUPTS (100000/HZ) |
4b39fd96 | 713 | |
241771ef IM |
714 | /* |
715 | * This handler is triggered by the local APIC, so the APIC IRQ handling | |
716 | * rules apply: | |
717 | */ | |
39d81eab | 718 | static int intel_pmu_handle_irq(struct pt_regs *regs, int nmi) |
241771ef IM |
719 | { |
720 | int bit, cpu = smp_processor_id(); | |
4b39fd96 | 721 | u64 ack, status; |
1b023a96 | 722 | struct cpu_hw_counters *cpuc = &per_cpu(cpu_hw_counters, cpu); |
241771ef | 723 | |
9e35ad38 | 724 | perf_disable(); |
19d84dab | 725 | status = intel_pmu_get_status(); |
9e35ad38 PZ |
726 | if (!status) { |
727 | perf_enable(); | |
728 | return 0; | |
729 | } | |
87b9cf46 | 730 | |
241771ef | 731 | again: |
d278c484 | 732 | inc_irq_stat(apic_perf_irqs); |
241771ef | 733 | ack = status; |
2f18d1e8 | 734 | for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { |
862a1a5f | 735 | struct perf_counter *counter = cpuc->counters[bit]; |
241771ef IM |
736 | |
737 | clear_bit(bit, (unsigned long *) &status); | |
43f6201a | 738 | if (!test_bit(bit, cpuc->active_mask)) |
241771ef IM |
739 | continue; |
740 | ||
55de0f2e | 741 | intel_pmu_save_and_restart(counter); |
78f13e95 | 742 | if (perf_counter_overflow(counter, nmi, regs, 0)) |
d4369891 | 743 | intel_pmu_disable_counter(&counter->hw, bit); |
241771ef IM |
744 | } |
745 | ||
dee5d906 | 746 | intel_pmu_ack_status(ack); |
241771ef IM |
747 | |
748 | /* | |
749 | * Repeat if there is more work to be done: | |
750 | */ | |
19d84dab | 751 | status = intel_pmu_get_status(); |
241771ef IM |
752 | if (status) |
753 | goto again; | |
b0f3f28e | 754 | |
9e35ad38 PZ |
755 | if (++cpuc->interrupts != PERFMON_MAX_INTERRUPTS) |
756 | perf_enable(); | |
757 | ||
758 | return 1; | |
1b023a96 MG |
759 | } |
760 | ||
a29aa8a7 RR |
761 | static int amd_pmu_handle_irq(struct pt_regs *regs, int nmi) |
762 | { | |
763 | int cpu = smp_processor_id(); | |
764 | struct cpu_hw_counters *cpuc = &per_cpu(cpu_hw_counters, cpu); | |
765 | u64 val; | |
766 | int handled = 0; | |
767 | struct perf_counter *counter; | |
768 | struct hw_perf_counter *hwc; | |
962bf7a6 PZ |
769 | int idx, throttle = 0; |
770 | ||
9e35ad38 PZ |
771 | if (++cpuc->interrupts == PERFMON_MAX_INTERRUPTS) { |
772 | throttle = 1; | |
773 | __perf_disable(); | |
774 | cpuc->enabled = 0; | |
775 | barrier(); | |
962bf7a6 | 776 | } |
a29aa8a7 | 777 | |
a29aa8a7 | 778 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
962bf7a6 PZ |
779 | int disable = 0; |
780 | ||
43f6201a | 781 | if (!test_bit(idx, cpuc->active_mask)) |
a29aa8a7 | 782 | continue; |
962bf7a6 | 783 | |
a29aa8a7 RR |
784 | counter = cpuc->counters[idx]; |
785 | hwc = &counter->hw; | |
a4016a79 PZ |
786 | |
787 | if (counter->hw_event.nmi != nmi) | |
788 | goto next; | |
789 | ||
4b7bfd0d | 790 | val = x86_perf_counter_update(counter, hwc, idx); |
a29aa8a7 | 791 | if (val & (1ULL << (x86_pmu.counter_bits - 1))) |
962bf7a6 PZ |
792 | goto next; |
793 | ||
a29aa8a7 RR |
794 | /* counter overflow */ |
795 | x86_perf_counter_set_period(counter, hwc, idx); | |
796 | handled = 1; | |
797 | inc_irq_stat(apic_perf_irqs); | |
962bf7a6 PZ |
798 | disable = perf_counter_overflow(counter, nmi, regs, 0); |
799 | ||
800 | next: | |
801 | if (disable || throttle) | |
a29aa8a7 | 802 | amd_pmu_disable_counter(hwc, idx); |
a29aa8a7 | 803 | } |
962bf7a6 | 804 | |
a29aa8a7 RR |
805 | return handled; |
806 | } | |
39d81eab | 807 | |
1b023a96 MG |
808 | void perf_counter_unthrottle(void) |
809 | { | |
810 | struct cpu_hw_counters *cpuc; | |
811 | ||
85cf9dba | 812 | if (!x86_pmu_initialized()) |
1b023a96 MG |
813 | return; |
814 | ||
b0f3f28e | 815 | cpuc = &__get_cpu_var(cpu_hw_counters); |
4b39fd96 | 816 | if (cpuc->interrupts >= PERFMON_MAX_INTERRUPTS) { |
f5a5a2f6 IM |
817 | /* |
818 | * Clear them before re-enabling irqs/NMIs again: | |
819 | */ | |
820 | cpuc->interrupts = 0; | |
9e35ad38 | 821 | perf_enable(); |
f5a5a2f6 IM |
822 | } else { |
823 | cpuc->interrupts = 0; | |
1b023a96 | 824 | } |
241771ef IM |
825 | } |
826 | ||
827 | void smp_perf_counter_interrupt(struct pt_regs *regs) | |
828 | { | |
829 | irq_enter(); | |
241771ef | 830 | apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR); |
b0f3f28e | 831 | ack_APIC_irq(); |
4a06bd85 | 832 | x86_pmu.handle_irq(regs, 0); |
241771ef IM |
833 | irq_exit(); |
834 | } | |
835 | ||
b6276f35 PZ |
836 | void smp_perf_pending_interrupt(struct pt_regs *regs) |
837 | { | |
838 | irq_enter(); | |
839 | ack_APIC_irq(); | |
840 | inc_irq_stat(apic_pending_irqs); | |
841 | perf_counter_do_pending(); | |
842 | irq_exit(); | |
843 | } | |
844 | ||
845 | void set_perf_counter_pending(void) | |
846 | { | |
847 | apic->send_IPI_self(LOCAL_PENDING_VECTOR); | |
848 | } | |
849 | ||
3415dd91 | 850 | void perf_counters_lapic_init(int nmi) |
241771ef IM |
851 | { |
852 | u32 apic_val; | |
853 | ||
85cf9dba | 854 | if (!x86_pmu_initialized()) |
241771ef | 855 | return; |
85cf9dba | 856 | |
241771ef IM |
857 | /* |
858 | * Enable the performance counter vector in the APIC LVT: | |
859 | */ | |
860 | apic_val = apic_read(APIC_LVTERR); | |
861 | ||
862 | apic_write(APIC_LVTERR, apic_val | APIC_LVT_MASKED); | |
863 | if (nmi) | |
864 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
865 | else | |
866 | apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR); | |
867 | apic_write(APIC_LVTERR, apic_val); | |
868 | } | |
869 | ||
870 | static int __kprobes | |
871 | perf_counter_nmi_handler(struct notifier_block *self, | |
872 | unsigned long cmd, void *__args) | |
873 | { | |
874 | struct die_args *args = __args; | |
875 | struct pt_regs *regs; | |
b0f3f28e | 876 | |
ba77813a | 877 | if (!atomic_read(&active_counters)) |
63a809a2 PZ |
878 | return NOTIFY_DONE; |
879 | ||
b0f3f28e PZ |
880 | switch (cmd) { |
881 | case DIE_NMI: | |
882 | case DIE_NMI_IPI: | |
883 | break; | |
241771ef | 884 | |
b0f3f28e | 885 | default: |
241771ef | 886 | return NOTIFY_DONE; |
b0f3f28e | 887 | } |
241771ef IM |
888 | |
889 | regs = args->regs; | |
890 | ||
891 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
a4016a79 PZ |
892 | /* |
893 | * Can't rely on the handled return value to say it was our NMI, two | |
894 | * counters could trigger 'simultaneously' raising two back-to-back NMIs. | |
895 | * | |
896 | * If the first NMI handles both, the latter will be empty and daze | |
897 | * the CPU. | |
898 | */ | |
899 | x86_pmu.handle_irq(regs, 1); | |
241771ef | 900 | |
a4016a79 | 901 | return NOTIFY_STOP; |
241771ef IM |
902 | } |
903 | ||
904 | static __read_mostly struct notifier_block perf_counter_nmi_notifier = { | |
5b75af0a MG |
905 | .notifier_call = perf_counter_nmi_handler, |
906 | .next = NULL, | |
907 | .priority = 1 | |
241771ef IM |
908 | }; |
909 | ||
5f4ec28f | 910 | static struct x86_pmu intel_pmu = { |
faa28ae0 | 911 | .name = "Intel", |
39d81eab | 912 | .handle_irq = intel_pmu_handle_irq, |
9e35ad38 PZ |
913 | .disable_all = intel_pmu_disable_all, |
914 | .enable_all = intel_pmu_enable_all, | |
5f4ec28f RR |
915 | .enable = intel_pmu_enable_counter, |
916 | .disable = intel_pmu_disable_counter, | |
b56a3802 JSR |
917 | .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, |
918 | .perfctr = MSR_ARCH_PERFMON_PERFCTR0, | |
5f4ec28f RR |
919 | .event_map = intel_pmu_event_map, |
920 | .raw_event = intel_pmu_raw_event, | |
b56a3802 | 921 | .max_events = ARRAY_SIZE(intel_perfmon_event_map), |
c619b8ff RR |
922 | /* |
923 | * Intel PMCs cannot be accessed sanely above 32 bit width, | |
924 | * so we install an artificial 1<<31 period regardless of | |
925 | * the generic counter period: | |
926 | */ | |
927 | .max_period = (1ULL << 31) - 1, | |
b56a3802 JSR |
928 | }; |
929 | ||
5f4ec28f | 930 | static struct x86_pmu amd_pmu = { |
faa28ae0 | 931 | .name = "AMD", |
39d81eab | 932 | .handle_irq = amd_pmu_handle_irq, |
9e35ad38 PZ |
933 | .disable_all = amd_pmu_disable_all, |
934 | .enable_all = amd_pmu_enable_all, | |
5f4ec28f RR |
935 | .enable = amd_pmu_enable_counter, |
936 | .disable = amd_pmu_disable_counter, | |
f87ad35d JSR |
937 | .eventsel = MSR_K7_EVNTSEL0, |
938 | .perfctr = MSR_K7_PERFCTR0, | |
5f4ec28f RR |
939 | .event_map = amd_pmu_event_map, |
940 | .raw_event = amd_pmu_raw_event, | |
f87ad35d | 941 | .max_events = ARRAY_SIZE(amd_perfmon_event_map), |
0933e5c6 RR |
942 | .num_counters = 4, |
943 | .counter_bits = 48, | |
944 | .counter_mask = (1ULL << 48) - 1, | |
c619b8ff RR |
945 | /* use highest bit to detect overflow */ |
946 | .max_period = (1ULL << 47) - 1, | |
f87ad35d JSR |
947 | }; |
948 | ||
72eae04d | 949 | static int intel_pmu_init(void) |
241771ef | 950 | { |
7bb497bd | 951 | union cpuid10_edx edx; |
241771ef | 952 | union cpuid10_eax eax; |
703e937c | 953 | unsigned int unused; |
7bb497bd | 954 | unsigned int ebx; |
faa28ae0 | 955 | int version; |
241771ef | 956 | |
da1a776b | 957 | if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) |
72eae04d | 958 | return -ENODEV; |
da1a776b | 959 | |
241771ef IM |
960 | /* |
961 | * Check whether the Architectural PerfMon supports | |
962 | * Branch Misses Retired Event or not. | |
963 | */ | |
703e937c | 964 | cpuid(10, &eax.full, &ebx, &unused, &edx.full); |
241771ef | 965 | if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED) |
72eae04d | 966 | return -ENODEV; |
241771ef | 967 | |
faa28ae0 RR |
968 | version = eax.split.version_id; |
969 | if (version < 2) | |
72eae04d | 970 | return -ENODEV; |
7bb497bd | 971 | |
4a06bd85 | 972 | x86_pmu = intel_pmu; |
faa28ae0 | 973 | x86_pmu.version = version; |
0933e5c6 | 974 | x86_pmu.num_counters = eax.split.num_counters; |
066d7dea IM |
975 | |
976 | /* | |
977 | * Quirk: v2 perfmon does not report fixed-purpose counters, so | |
978 | * assume at least 3 counters: | |
979 | */ | |
980 | x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3); | |
981 | ||
0933e5c6 RR |
982 | x86_pmu.counter_bits = eax.split.bit_width; |
983 | x86_pmu.counter_mask = (1ULL << eax.split.bit_width) - 1; | |
b56a3802 | 984 | |
9e35ad38 PZ |
985 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl); |
986 | ||
72eae04d | 987 | return 0; |
b56a3802 JSR |
988 | } |
989 | ||
72eae04d | 990 | static int amd_pmu_init(void) |
f87ad35d | 991 | { |
4a06bd85 | 992 | x86_pmu = amd_pmu; |
72eae04d | 993 | return 0; |
f87ad35d JSR |
994 | } |
995 | ||
b56a3802 JSR |
996 | void __init init_hw_perf_counters(void) |
997 | { | |
72eae04d RR |
998 | int err; |
999 | ||
b56a3802 JSR |
1000 | switch (boot_cpu_data.x86_vendor) { |
1001 | case X86_VENDOR_INTEL: | |
72eae04d | 1002 | err = intel_pmu_init(); |
b56a3802 | 1003 | break; |
f87ad35d | 1004 | case X86_VENDOR_AMD: |
72eae04d | 1005 | err = amd_pmu_init(); |
f87ad35d | 1006 | break; |
4138960a RR |
1007 | default: |
1008 | return; | |
b56a3802 | 1009 | } |
72eae04d | 1010 | if (err != 0) |
b56a3802 JSR |
1011 | return; |
1012 | ||
faa28ae0 RR |
1013 | pr_info("%s Performance Monitoring support detected.\n", x86_pmu.name); |
1014 | pr_info("... version: %d\n", x86_pmu.version); | |
1015 | pr_info("... bit width: %d\n", x86_pmu.counter_bits); | |
1016 | ||
0933e5c6 RR |
1017 | pr_info("... num counters: %d\n", x86_pmu.num_counters); |
1018 | if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) { | |
1019 | x86_pmu.num_counters = X86_PMC_MAX_GENERIC; | |
241771ef | 1020 | WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!", |
0933e5c6 | 1021 | x86_pmu.num_counters, X86_PMC_MAX_GENERIC); |
241771ef | 1022 | } |
0933e5c6 RR |
1023 | perf_counter_mask = (1 << x86_pmu.num_counters) - 1; |
1024 | perf_max_counters = x86_pmu.num_counters; | |
241771ef | 1025 | |
0933e5c6 | 1026 | pr_info("... value mask: %016Lx\n", x86_pmu.counter_mask); |
c619b8ff | 1027 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
2f18d1e8 | 1028 | |
0933e5c6 RR |
1029 | if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { |
1030 | x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; | |
703e937c | 1031 | WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!", |
0933e5c6 | 1032 | x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED); |
703e937c | 1033 | } |
0933e5c6 | 1034 | pr_info("... fixed counters: %d\n", x86_pmu.num_counters_fixed); |
862a1a5f | 1035 | |
0933e5c6 RR |
1036 | perf_counter_mask |= |
1037 | ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED; | |
241771ef | 1038 | |
a1ef58f4 | 1039 | pr_info("... counter mask: %016Lx\n", perf_counter_mask); |
75f224cf | 1040 | |
241771ef IM |
1041 | perf_counters_lapic_init(0); |
1042 | register_die_notifier(&perf_counter_nmi_notifier); | |
241771ef | 1043 | } |
621a01ea | 1044 | |
bb775fc2 | 1045 | static inline void x86_pmu_read(struct perf_counter *counter) |
ee06094f IM |
1046 | { |
1047 | x86_perf_counter_update(counter, &counter->hw, counter->hw.idx); | |
1048 | } | |
1049 | ||
4aeb0b42 RR |
1050 | static const struct pmu pmu = { |
1051 | .enable = x86_pmu_enable, | |
1052 | .disable = x86_pmu_disable, | |
1053 | .read = x86_pmu_read, | |
621a01ea IM |
1054 | }; |
1055 | ||
4aeb0b42 | 1056 | const struct pmu *hw_perf_counter_init(struct perf_counter *counter) |
621a01ea IM |
1057 | { |
1058 | int err; | |
1059 | ||
1060 | err = __hw_perf_counter_init(counter); | |
1061 | if (err) | |
9ea98e19 | 1062 | return ERR_PTR(err); |
621a01ea | 1063 | |
4aeb0b42 | 1064 | return &pmu; |
621a01ea | 1065 | } |
d7d59fb3 PZ |
1066 | |
1067 | /* | |
1068 | * callchain support | |
1069 | */ | |
1070 | ||
1071 | static inline | |
1072 | void callchain_store(struct perf_callchain_entry *entry, unsigned long ip) | |
1073 | { | |
1074 | if (entry->nr < MAX_STACK_DEPTH) | |
1075 | entry->ip[entry->nr++] = ip; | |
1076 | } | |
1077 | ||
1078 | static DEFINE_PER_CPU(struct perf_callchain_entry, irq_entry); | |
1079 | static DEFINE_PER_CPU(struct perf_callchain_entry, nmi_entry); | |
1080 | ||
1081 | ||
1082 | static void | |
1083 | backtrace_warning_symbol(void *data, char *msg, unsigned long symbol) | |
1084 | { | |
1085 | /* Ignore warnings */ | |
1086 | } | |
1087 | ||
1088 | static void backtrace_warning(void *data, char *msg) | |
1089 | { | |
1090 | /* Ignore warnings */ | |
1091 | } | |
1092 | ||
1093 | static int backtrace_stack(void *data, char *name) | |
1094 | { | |
1095 | /* Don't bother with IRQ stacks for now */ | |
1096 | return -1; | |
1097 | } | |
1098 | ||
1099 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1100 | { | |
1101 | struct perf_callchain_entry *entry = data; | |
1102 | ||
1103 | if (reliable) | |
1104 | callchain_store(entry, addr); | |
1105 | } | |
1106 | ||
1107 | static const struct stacktrace_ops backtrace_ops = { | |
1108 | .warning = backtrace_warning, | |
1109 | .warning_symbol = backtrace_warning_symbol, | |
1110 | .stack = backtrace_stack, | |
1111 | .address = backtrace_address, | |
1112 | }; | |
1113 | ||
1114 | static void | |
1115 | perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1116 | { | |
1117 | unsigned long bp; | |
1118 | char *stack; | |
5872bdb8 | 1119 | int nr = entry->nr; |
d7d59fb3 PZ |
1120 | |
1121 | callchain_store(entry, instruction_pointer(regs)); | |
1122 | ||
1123 | stack = ((char *)regs + sizeof(struct pt_regs)); | |
1124 | #ifdef CONFIG_FRAME_POINTER | |
1125 | bp = frame_pointer(regs); | |
1126 | #else | |
1127 | bp = 0; | |
1128 | #endif | |
1129 | ||
1130 | dump_trace(NULL, regs, (void *)stack, bp, &backtrace_ops, entry); | |
5872bdb8 PZ |
1131 | |
1132 | entry->kernel = entry->nr - nr; | |
d7d59fb3 PZ |
1133 | } |
1134 | ||
1135 | ||
1136 | struct stack_frame { | |
1137 | const void __user *next_fp; | |
1138 | unsigned long return_address; | |
1139 | }; | |
1140 | ||
1141 | static int copy_stack_frame(const void __user *fp, struct stack_frame *frame) | |
1142 | { | |
1143 | int ret; | |
1144 | ||
1145 | if (!access_ok(VERIFY_READ, fp, sizeof(*frame))) | |
1146 | return 0; | |
1147 | ||
1148 | ret = 1; | |
1149 | pagefault_disable(); | |
1150 | if (__copy_from_user_inatomic(frame, fp, sizeof(*frame))) | |
1151 | ret = 0; | |
1152 | pagefault_enable(); | |
1153 | ||
1154 | return ret; | |
1155 | } | |
1156 | ||
1157 | static void | |
1158 | perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1159 | { | |
1160 | struct stack_frame frame; | |
1161 | const void __user *fp; | |
5872bdb8 | 1162 | int nr = entry->nr; |
d7d59fb3 PZ |
1163 | |
1164 | regs = (struct pt_regs *)current->thread.sp0 - 1; | |
1165 | fp = (void __user *)regs->bp; | |
1166 | ||
1167 | callchain_store(entry, regs->ip); | |
1168 | ||
1169 | while (entry->nr < MAX_STACK_DEPTH) { | |
1170 | frame.next_fp = NULL; | |
1171 | frame.return_address = 0; | |
1172 | ||
1173 | if (!copy_stack_frame(fp, &frame)) | |
1174 | break; | |
1175 | ||
1176 | if ((unsigned long)fp < user_stack_pointer(regs)) | |
1177 | break; | |
1178 | ||
1179 | callchain_store(entry, frame.return_address); | |
1180 | fp = frame.next_fp; | |
1181 | } | |
5872bdb8 PZ |
1182 | |
1183 | entry->user = entry->nr - nr; | |
d7d59fb3 PZ |
1184 | } |
1185 | ||
1186 | static void | |
1187 | perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1188 | { | |
1189 | int is_user; | |
1190 | ||
1191 | if (!regs) | |
1192 | return; | |
1193 | ||
1194 | is_user = user_mode(regs); | |
1195 | ||
1196 | if (!current || current->pid == 0) | |
1197 | return; | |
1198 | ||
1199 | if (is_user && current->state != TASK_RUNNING) | |
1200 | return; | |
1201 | ||
1202 | if (!is_user) | |
1203 | perf_callchain_kernel(regs, entry); | |
1204 | ||
1205 | if (current->mm) | |
1206 | perf_callchain_user(regs, entry); | |
1207 | } | |
1208 | ||
1209 | struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) | |
1210 | { | |
1211 | struct perf_callchain_entry *entry; | |
1212 | ||
1213 | if (in_nmi()) | |
1214 | entry = &__get_cpu_var(nmi_entry); | |
1215 | else | |
1216 | entry = &__get_cpu_var(irq_entry); | |
1217 | ||
1218 | entry->nr = 0; | |
5872bdb8 PZ |
1219 | entry->hv = 0; |
1220 | entry->kernel = 0; | |
1221 | entry->user = 0; | |
d7d59fb3 PZ |
1222 | |
1223 | perf_do_callchain(regs, entry); | |
1224 | ||
1225 | return entry; | |
1226 | } |