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Commit | Line | Data |
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241771ef IM |
1 | /* |
2 | * Performance counter x86 architecture code | |
3 | * | |
4 | * Copyright(C) 2008 Thomas Gleixner <tglx@linutronix.de> | |
5 | * Copyright(C) 2008 Red Hat, Inc., Ingo Molnar | |
b56a3802 | 6 | * Copyright(C) 2009 Jaswinder Singh Rajput |
39d81eab | 7 | * Copyright(C) 2009 Advanced Micro Devices, Inc., Robert Richter |
241771ef IM |
8 | * |
9 | * For licencing details see kernel-base/COPYING | |
10 | */ | |
11 | ||
12 | #include <linux/perf_counter.h> | |
13 | #include <linux/capability.h> | |
14 | #include <linux/notifier.h> | |
15 | #include <linux/hardirq.h> | |
16 | #include <linux/kprobes.h> | |
4ac13294 | 17 | #include <linux/module.h> |
241771ef IM |
18 | #include <linux/kdebug.h> |
19 | #include <linux/sched.h> | |
d7d59fb3 | 20 | #include <linux/uaccess.h> |
241771ef | 21 | |
241771ef | 22 | #include <asm/apic.h> |
d7d59fb3 | 23 | #include <asm/stacktrace.h> |
4e935e47 | 24 | #include <asm/nmi.h> |
241771ef IM |
25 | |
26 | static bool perf_counters_initialized __read_mostly; | |
27 | ||
28 | /* | |
29 | * Number of (generic) HW counters: | |
30 | */ | |
862a1a5f IM |
31 | static int nr_counters_generic __read_mostly; |
32 | static u64 perf_counter_mask __read_mostly; | |
2f18d1e8 | 33 | static u64 counter_value_mask __read_mostly; |
b0f3f28e | 34 | static int counter_value_bits __read_mostly; |
241771ef | 35 | |
862a1a5f | 36 | static int nr_counters_fixed __read_mostly; |
703e937c | 37 | |
241771ef | 38 | struct cpu_hw_counters { |
862a1a5f IM |
39 | struct perf_counter *counters[X86_PMC_IDX_MAX]; |
40 | unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
4b39fd96 | 41 | unsigned long interrupts; |
b0f3f28e | 42 | u64 throttle_ctrl; |
184fe4ab | 43 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
b0f3f28e | 44 | int enabled; |
241771ef IM |
45 | }; |
46 | ||
47 | /* | |
5f4ec28f | 48 | * struct x86_pmu - generic x86 pmu |
241771ef | 49 | */ |
5f4ec28f | 50 | struct x86_pmu { |
39d81eab | 51 | int (*handle_irq)(struct pt_regs *, int); |
169e41eb | 52 | u64 (*save_disable_all)(void); |
b0f3f28e | 53 | void (*restore_all)(u64); |
b0f3f28e PZ |
54 | void (*ack_status)(u64); |
55 | void (*enable)(int, u64); | |
56 | void (*disable)(int, u64); | |
169e41eb JSR |
57 | unsigned eventsel; |
58 | unsigned perfctr; | |
b0f3f28e PZ |
59 | u64 (*event_map)(int); |
60 | u64 (*raw_event)(u64); | |
169e41eb | 61 | int max_events; |
b56a3802 JSR |
62 | }; |
63 | ||
5f4ec28f | 64 | static struct x86_pmu *x86_pmu __read_mostly; |
b56a3802 | 65 | |
b0f3f28e PZ |
66 | static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = { |
67 | .enabled = 1, | |
68 | }; | |
241771ef | 69 | |
7bb497bd IM |
70 | static __read_mostly int intel_perfmon_version; |
71 | ||
b56a3802 JSR |
72 | /* |
73 | * Intel PerfMon v3. Used on Core2 and later. | |
74 | */ | |
b0f3f28e | 75 | static const u64 intel_perfmon_event_map[] = |
241771ef | 76 | { |
f650a672 | 77 | [PERF_COUNT_CPU_CYCLES] = 0x003c, |
241771ef IM |
78 | [PERF_COUNT_INSTRUCTIONS] = 0x00c0, |
79 | [PERF_COUNT_CACHE_REFERENCES] = 0x4f2e, | |
80 | [PERF_COUNT_CACHE_MISSES] = 0x412e, | |
81 | [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4, | |
82 | [PERF_COUNT_BRANCH_MISSES] = 0x00c5, | |
f650a672 | 83 | [PERF_COUNT_BUS_CYCLES] = 0x013c, |
241771ef IM |
84 | }; |
85 | ||
5f4ec28f | 86 | static u64 intel_pmu_event_map(int event) |
b56a3802 JSR |
87 | { |
88 | return intel_perfmon_event_map[event]; | |
89 | } | |
241771ef | 90 | |
5f4ec28f | 91 | static u64 intel_pmu_raw_event(u64 event) |
b0f3f28e | 92 | { |
82bae4f8 PZ |
93 | #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL |
94 | #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL | |
95 | #define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL | |
b0f3f28e PZ |
96 | |
97 | #define CORE_EVNTSEL_MASK \ | |
98 | (CORE_EVNTSEL_EVENT_MASK | \ | |
99 | CORE_EVNTSEL_UNIT_MASK | \ | |
100 | CORE_EVNTSEL_COUNTER_MASK) | |
101 | ||
102 | return event & CORE_EVNTSEL_MASK; | |
103 | } | |
104 | ||
f87ad35d JSR |
105 | /* |
106 | * AMD Performance Monitor K7 and later. | |
107 | */ | |
b0f3f28e | 108 | static const u64 amd_perfmon_event_map[] = |
f87ad35d JSR |
109 | { |
110 | [PERF_COUNT_CPU_CYCLES] = 0x0076, | |
111 | [PERF_COUNT_INSTRUCTIONS] = 0x00c0, | |
112 | [PERF_COUNT_CACHE_REFERENCES] = 0x0080, | |
113 | [PERF_COUNT_CACHE_MISSES] = 0x0081, | |
114 | [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4, | |
115 | [PERF_COUNT_BRANCH_MISSES] = 0x00c5, | |
116 | }; | |
117 | ||
5f4ec28f | 118 | static u64 amd_pmu_event_map(int event) |
f87ad35d JSR |
119 | { |
120 | return amd_perfmon_event_map[event]; | |
121 | } | |
122 | ||
5f4ec28f | 123 | static u64 amd_pmu_raw_event(u64 event) |
b0f3f28e | 124 | { |
82bae4f8 PZ |
125 | #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL |
126 | #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL | |
127 | #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL | |
b0f3f28e PZ |
128 | |
129 | #define K7_EVNTSEL_MASK \ | |
130 | (K7_EVNTSEL_EVENT_MASK | \ | |
131 | K7_EVNTSEL_UNIT_MASK | \ | |
132 | K7_EVNTSEL_COUNTER_MASK) | |
133 | ||
134 | return event & K7_EVNTSEL_MASK; | |
135 | } | |
136 | ||
ee06094f IM |
137 | /* |
138 | * Propagate counter elapsed time into the generic counter. | |
139 | * Can only be executed on the CPU where the counter is active. | |
140 | * Returns the delta events processed. | |
141 | */ | |
142 | static void | |
143 | x86_perf_counter_update(struct perf_counter *counter, | |
144 | struct hw_perf_counter *hwc, int idx) | |
145 | { | |
146 | u64 prev_raw_count, new_raw_count, delta; | |
147 | ||
ee06094f IM |
148 | /* |
149 | * Careful: an NMI might modify the previous counter value. | |
150 | * | |
151 | * Our tactic to handle this is to first atomically read and | |
152 | * exchange a new raw count - then add that new-prev delta | |
153 | * count to the generic counter atomically: | |
154 | */ | |
155 | again: | |
156 | prev_raw_count = atomic64_read(&hwc->prev_count); | |
157 | rdmsrl(hwc->counter_base + idx, new_raw_count); | |
158 | ||
159 | if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count, | |
160 | new_raw_count) != prev_raw_count) | |
161 | goto again; | |
162 | ||
163 | /* | |
164 | * Now we have the new raw value and have updated the prev | |
165 | * timestamp already. We can now calculate the elapsed delta | |
166 | * (counter-)time and add that to the generic counter. | |
167 | * | |
168 | * Careful, not all hw sign-extends above the physical width | |
169 | * of the count, so we do that by clipping the delta to 32 bits: | |
170 | */ | |
171 | delta = (u64)(u32)((s32)new_raw_count - (s32)prev_raw_count); | |
ee06094f IM |
172 | |
173 | atomic64_add(delta, &counter->count); | |
174 | atomic64_sub(delta, &hwc->period_left); | |
175 | } | |
176 | ||
4e935e47 PZ |
177 | static atomic_t num_counters; |
178 | static DEFINE_MUTEX(pmc_reserve_mutex); | |
179 | ||
180 | static bool reserve_pmc_hardware(void) | |
181 | { | |
182 | int i; | |
183 | ||
184 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
185 | disable_lapic_nmi_watchdog(); | |
186 | ||
187 | for (i = 0; i < nr_counters_generic; i++) { | |
5f4ec28f | 188 | if (!reserve_perfctr_nmi(x86_pmu->perfctr + i)) |
4e935e47 PZ |
189 | goto perfctr_fail; |
190 | } | |
191 | ||
192 | for (i = 0; i < nr_counters_generic; i++) { | |
5f4ec28f | 193 | if (!reserve_evntsel_nmi(x86_pmu->eventsel + i)) |
4e935e47 PZ |
194 | goto eventsel_fail; |
195 | } | |
196 | ||
197 | return true; | |
198 | ||
199 | eventsel_fail: | |
200 | for (i--; i >= 0; i--) | |
5f4ec28f | 201 | release_evntsel_nmi(x86_pmu->eventsel + i); |
4e935e47 PZ |
202 | |
203 | i = nr_counters_generic; | |
204 | ||
205 | perfctr_fail: | |
206 | for (i--; i >= 0; i--) | |
5f4ec28f | 207 | release_perfctr_nmi(x86_pmu->perfctr + i); |
4e935e47 PZ |
208 | |
209 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
210 | enable_lapic_nmi_watchdog(); | |
211 | ||
212 | return false; | |
213 | } | |
214 | ||
215 | static void release_pmc_hardware(void) | |
216 | { | |
217 | int i; | |
218 | ||
219 | for (i = 0; i < nr_counters_generic; i++) { | |
5f4ec28f RR |
220 | release_perfctr_nmi(x86_pmu->perfctr + i); |
221 | release_evntsel_nmi(x86_pmu->eventsel + i); | |
4e935e47 PZ |
222 | } |
223 | ||
224 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
225 | enable_lapic_nmi_watchdog(); | |
226 | } | |
227 | ||
228 | static void hw_perf_counter_destroy(struct perf_counter *counter) | |
229 | { | |
230 | if (atomic_dec_and_mutex_lock(&num_counters, &pmc_reserve_mutex)) { | |
231 | release_pmc_hardware(); | |
232 | mutex_unlock(&pmc_reserve_mutex); | |
233 | } | |
234 | } | |
235 | ||
241771ef IM |
236 | /* |
237 | * Setup the hardware configuration for a given hw_event_type | |
238 | */ | |
621a01ea | 239 | static int __hw_perf_counter_init(struct perf_counter *counter) |
241771ef | 240 | { |
9f66a381 | 241 | struct perf_counter_hw_event *hw_event = &counter->hw_event; |
241771ef | 242 | struct hw_perf_counter *hwc = &counter->hw; |
4e935e47 | 243 | int err; |
241771ef | 244 | |
39d81eab RR |
245 | /* disable temporarily */ |
246 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
247 | return -ENOSYS; | |
248 | ||
241771ef IM |
249 | if (unlikely(!perf_counters_initialized)) |
250 | return -EINVAL; | |
251 | ||
4e935e47 PZ |
252 | err = 0; |
253 | if (atomic_inc_not_zero(&num_counters)) { | |
254 | mutex_lock(&pmc_reserve_mutex); | |
255 | if (atomic_read(&num_counters) == 0 && !reserve_pmc_hardware()) | |
256 | err = -EBUSY; | |
257 | else | |
258 | atomic_inc(&num_counters); | |
259 | mutex_unlock(&pmc_reserve_mutex); | |
260 | } | |
261 | if (err) | |
262 | return err; | |
263 | ||
241771ef | 264 | /* |
0475f9ea | 265 | * Generate PMC IRQs: |
241771ef IM |
266 | * (keep 'enabled' bit clear for now) |
267 | */ | |
0475f9ea | 268 | hwc->config = ARCH_PERFMON_EVENTSEL_INT; |
241771ef IM |
269 | |
270 | /* | |
0475f9ea | 271 | * Count user and OS events unless requested not to. |
241771ef | 272 | */ |
0475f9ea PM |
273 | if (!hw_event->exclude_user) |
274 | hwc->config |= ARCH_PERFMON_EVENTSEL_USR; | |
275 | if (!hw_event->exclude_kernel) | |
241771ef | 276 | hwc->config |= ARCH_PERFMON_EVENTSEL_OS; |
0475f9ea PM |
277 | |
278 | /* | |
279 | * If privileged enough, allow NMI events: | |
280 | */ | |
281 | hwc->nmi = 0; | |
282 | if (capable(CAP_SYS_ADMIN) && hw_event->nmi) | |
283 | hwc->nmi = 1; | |
241771ef | 284 | |
9f66a381 | 285 | hwc->irq_period = hw_event->irq_period; |
241771ef IM |
286 | /* |
287 | * Intel PMCs cannot be accessed sanely above 32 bit width, | |
288 | * so we install an artificial 1<<31 period regardless of | |
289 | * the generic counter period: | |
290 | */ | |
f87ad35d JSR |
291 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
292 | if ((s64)hwc->irq_period <= 0 || hwc->irq_period > 0x7FFFFFFF) | |
293 | hwc->irq_period = 0x7FFFFFFF; | |
241771ef | 294 | |
ee06094f | 295 | atomic64_set(&hwc->period_left, hwc->irq_period); |
241771ef IM |
296 | |
297 | /* | |
dfa7c899 | 298 | * Raw event type provide the config in the event structure |
241771ef | 299 | */ |
f4a2deb4 | 300 | if (perf_event_raw(hw_event)) { |
5f4ec28f | 301 | hwc->config |= x86_pmu->raw_event(perf_event_config(hw_event)); |
241771ef | 302 | } else { |
5f4ec28f | 303 | if (perf_event_id(hw_event) >= x86_pmu->max_events) |
241771ef IM |
304 | return -EINVAL; |
305 | /* | |
306 | * The generic map: | |
307 | */ | |
5f4ec28f | 308 | hwc->config |= x86_pmu->event_map(perf_event_id(hw_event)); |
241771ef | 309 | } |
241771ef | 310 | |
4e935e47 PZ |
311 | counter->destroy = hw_perf_counter_destroy; |
312 | ||
241771ef IM |
313 | return 0; |
314 | } | |
315 | ||
5f4ec28f | 316 | static u64 intel_pmu_save_disable_all(void) |
4ac13294 TG |
317 | { |
318 | u64 ctrl; | |
319 | ||
320 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); | |
862a1a5f | 321 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); |
2b9ff0db | 322 | |
4ac13294 | 323 | return ctrl; |
241771ef | 324 | } |
b56a3802 | 325 | |
5f4ec28f | 326 | static u64 amd_pmu_save_disable_all(void) |
f87ad35d | 327 | { |
b0f3f28e PZ |
328 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
329 | int enabled, idx; | |
330 | ||
331 | enabled = cpuc->enabled; | |
332 | cpuc->enabled = 0; | |
60b3df9c PZ |
333 | /* |
334 | * ensure we write the disable before we start disabling the | |
5f4ec28f RR |
335 | * counters proper, so that amd_pmu_enable_counter() does the |
336 | * right thing. | |
60b3df9c | 337 | */ |
b0f3f28e | 338 | barrier(); |
f87ad35d JSR |
339 | |
340 | for (idx = 0; idx < nr_counters_generic; idx++) { | |
b0f3f28e PZ |
341 | u64 val; |
342 | ||
4295ee62 RR |
343 | if (!test_bit(idx, cpuc->active_mask)) |
344 | continue; | |
f87ad35d | 345 | rdmsrl(MSR_K7_EVNTSEL0 + idx, val); |
4295ee62 RR |
346 | if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE)) |
347 | continue; | |
348 | val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE; | |
349 | wrmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
f87ad35d JSR |
350 | } |
351 | ||
b0f3f28e | 352 | return enabled; |
f87ad35d JSR |
353 | } |
354 | ||
b56a3802 JSR |
355 | u64 hw_perf_save_disable(void) |
356 | { | |
357 | if (unlikely(!perf_counters_initialized)) | |
358 | return 0; | |
359 | ||
5f4ec28f | 360 | return x86_pmu->save_disable_all(); |
b56a3802 | 361 | } |
b0f3f28e PZ |
362 | /* |
363 | * Exported because of ACPI idle | |
364 | */ | |
01b2838c | 365 | EXPORT_SYMBOL_GPL(hw_perf_save_disable); |
241771ef | 366 | |
5f4ec28f | 367 | static void intel_pmu_restore_all(u64 ctrl) |
b56a3802 JSR |
368 | { |
369 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); | |
370 | } | |
371 | ||
5f4ec28f | 372 | static void amd_pmu_restore_all(u64 ctrl) |
f87ad35d | 373 | { |
b0f3f28e | 374 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
f87ad35d JSR |
375 | int idx; |
376 | ||
b0f3f28e PZ |
377 | cpuc->enabled = ctrl; |
378 | barrier(); | |
379 | if (!ctrl) | |
380 | return; | |
381 | ||
f87ad35d | 382 | for (idx = 0; idx < nr_counters_generic; idx++) { |
4295ee62 | 383 | u64 val; |
b0f3f28e | 384 | |
4295ee62 RR |
385 | if (!test_bit(idx, cpuc->active_mask)) |
386 | continue; | |
387 | rdmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
388 | if (val & ARCH_PERFMON_EVENTSEL0_ENABLE) | |
389 | continue; | |
390 | val |= ARCH_PERFMON_EVENTSEL0_ENABLE; | |
391 | wrmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
f87ad35d JSR |
392 | } |
393 | } | |
394 | ||
ee06094f IM |
395 | void hw_perf_restore(u64 ctrl) |
396 | { | |
2b9ff0db IM |
397 | if (unlikely(!perf_counters_initialized)) |
398 | return; | |
399 | ||
5f4ec28f | 400 | x86_pmu->restore_all(ctrl); |
ee06094f | 401 | } |
b0f3f28e PZ |
402 | /* |
403 | * Exported because of ACPI idle | |
404 | */ | |
ee06094f IM |
405 | EXPORT_SYMBOL_GPL(hw_perf_restore); |
406 | ||
b7f8859a | 407 | static inline u64 intel_pmu_get_status(u64 mask) |
b0f3f28e PZ |
408 | { |
409 | u64 status; | |
410 | ||
b0f3f28e PZ |
411 | if (unlikely(!perf_counters_initialized)) |
412 | return 0; | |
b7f8859a | 413 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); |
b0f3f28e | 414 | |
b7f8859a | 415 | return status; |
b0f3f28e PZ |
416 | } |
417 | ||
5f4ec28f | 418 | static void intel_pmu_ack_status(u64 ack) |
b0f3f28e PZ |
419 | { |
420 | wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); | |
421 | } | |
422 | ||
5f4ec28f | 423 | static void amd_pmu_ack_status(u64 ack) |
b0f3f28e PZ |
424 | { |
425 | } | |
426 | ||
427 | static void hw_perf_ack_status(u64 ack) | |
428 | { | |
429 | if (unlikely(!perf_counters_initialized)) | |
430 | return; | |
431 | ||
5f4ec28f | 432 | x86_pmu->ack_status(ack); |
b0f3f28e PZ |
433 | } |
434 | ||
5f4ec28f | 435 | static void intel_pmu_enable_counter(int idx, u64 config) |
b0f3f28e PZ |
436 | { |
437 | wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + idx, | |
438 | config | ARCH_PERFMON_EVENTSEL0_ENABLE); | |
439 | } | |
440 | ||
5f4ec28f | 441 | static void amd_pmu_enable_counter(int idx, u64 config) |
b0f3f28e PZ |
442 | { |
443 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
444 | ||
184fe4ab | 445 | set_bit(idx, cpuc->active_mask); |
b0f3f28e PZ |
446 | if (cpuc->enabled) |
447 | config |= ARCH_PERFMON_EVENTSEL0_ENABLE; | |
448 | ||
449 | wrmsrl(MSR_K7_EVNTSEL0 + idx, config); | |
450 | } | |
451 | ||
452 | static void hw_perf_enable(int idx, u64 config) | |
453 | { | |
454 | if (unlikely(!perf_counters_initialized)) | |
455 | return; | |
456 | ||
5f4ec28f | 457 | x86_pmu->enable(idx, config); |
b0f3f28e PZ |
458 | } |
459 | ||
5f4ec28f | 460 | static void intel_pmu_disable_counter(int idx, u64 config) |
b0f3f28e PZ |
461 | { |
462 | wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + idx, config); | |
463 | } | |
464 | ||
5f4ec28f | 465 | static void amd_pmu_disable_counter(int idx, u64 config) |
b0f3f28e PZ |
466 | { |
467 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
468 | ||
184fe4ab | 469 | clear_bit(idx, cpuc->active_mask); |
b0f3f28e PZ |
470 | wrmsrl(MSR_K7_EVNTSEL0 + idx, config); |
471 | ||
472 | } | |
473 | ||
474 | static void hw_perf_disable(int idx, u64 config) | |
475 | { | |
476 | if (unlikely(!perf_counters_initialized)) | |
477 | return; | |
478 | ||
5f4ec28f | 479 | x86_pmu->disable(idx, config); |
b0f3f28e PZ |
480 | } |
481 | ||
2f18d1e8 IM |
482 | static inline void |
483 | __pmc_fixed_disable(struct perf_counter *counter, | |
484 | struct hw_perf_counter *hwc, unsigned int __idx) | |
485 | { | |
486 | int idx = __idx - X86_PMC_IDX_FIXED; | |
487 | u64 ctrl_val, mask; | |
488 | int err; | |
489 | ||
490 | mask = 0xfULL << (idx * 4); | |
491 | ||
492 | rdmsrl(hwc->config_base, ctrl_val); | |
493 | ctrl_val &= ~mask; | |
494 | err = checking_wrmsrl(hwc->config_base, ctrl_val); | |
495 | } | |
496 | ||
7e2ae347 | 497 | static inline void |
4aeb0b42 RR |
498 | __x86_pmu_disable(struct perf_counter *counter, |
499 | struct hw_perf_counter *hwc, unsigned int idx) | |
7e2ae347 | 500 | { |
2f18d1e8 | 501 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) |
2b583d8b JSR |
502 | __pmc_fixed_disable(counter, hwc, idx); |
503 | else | |
b0f3f28e | 504 | hw_perf_disable(idx, hwc->config); |
7e2ae347 IM |
505 | } |
506 | ||
2f18d1e8 | 507 | static DEFINE_PER_CPU(u64, prev_left[X86_PMC_IDX_MAX]); |
241771ef | 508 | |
ee06094f IM |
509 | /* |
510 | * Set the next IRQ period, based on the hwc->period_left value. | |
511 | * To be called with the counter disabled in hw: | |
512 | */ | |
513 | static void | |
514 | __hw_perf_counter_set_period(struct perf_counter *counter, | |
515 | struct hw_perf_counter *hwc, int idx) | |
241771ef | 516 | { |
2f18d1e8 | 517 | s64 left = atomic64_read(&hwc->period_left); |
595258aa | 518 | s64 period = hwc->irq_period; |
2f18d1e8 | 519 | int err; |
ee06094f | 520 | |
ee06094f IM |
521 | /* |
522 | * If we are way outside a reasoable range then just skip forward: | |
523 | */ | |
524 | if (unlikely(left <= -period)) { | |
525 | left = period; | |
526 | atomic64_set(&hwc->period_left, left); | |
527 | } | |
528 | ||
529 | if (unlikely(left <= 0)) { | |
530 | left += period; | |
531 | atomic64_set(&hwc->period_left, left); | |
532 | } | |
241771ef | 533 | |
ee06094f IM |
534 | per_cpu(prev_left[idx], smp_processor_id()) = left; |
535 | ||
536 | /* | |
537 | * The hw counter starts counting from this counter offset, | |
538 | * mark it to be able to extra future deltas: | |
539 | */ | |
2f18d1e8 | 540 | atomic64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 541 | |
2f18d1e8 IM |
542 | err = checking_wrmsrl(hwc->counter_base + idx, |
543 | (u64)(-left) & counter_value_mask); | |
544 | } | |
545 | ||
546 | static inline void | |
547 | __pmc_fixed_enable(struct perf_counter *counter, | |
548 | struct hw_perf_counter *hwc, unsigned int __idx) | |
549 | { | |
550 | int idx = __idx - X86_PMC_IDX_FIXED; | |
551 | u64 ctrl_val, bits, mask; | |
552 | int err; | |
553 | ||
554 | /* | |
0475f9ea PM |
555 | * Enable IRQ generation (0x8), |
556 | * and enable ring-3 counting (0x2) and ring-0 counting (0x1) | |
557 | * if requested: | |
2f18d1e8 | 558 | */ |
0475f9ea PM |
559 | bits = 0x8ULL; |
560 | if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) | |
561 | bits |= 0x2; | |
2f18d1e8 IM |
562 | if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) |
563 | bits |= 0x1; | |
564 | bits <<= (idx * 4); | |
565 | mask = 0xfULL << (idx * 4); | |
566 | ||
567 | rdmsrl(hwc->config_base, ctrl_val); | |
568 | ctrl_val &= ~mask; | |
569 | ctrl_val |= bits; | |
570 | err = checking_wrmsrl(hwc->config_base, ctrl_val); | |
7e2ae347 IM |
571 | } |
572 | ||
ee06094f | 573 | static void |
4aeb0b42 RR |
574 | __x86_pmu_enable(struct perf_counter *counter, |
575 | struct hw_perf_counter *hwc, int idx) | |
7e2ae347 | 576 | { |
2f18d1e8 | 577 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) |
2b583d8b JSR |
578 | __pmc_fixed_enable(counter, hwc, idx); |
579 | else | |
b0f3f28e | 580 | hw_perf_enable(idx, hwc->config); |
241771ef IM |
581 | } |
582 | ||
2f18d1e8 IM |
583 | static int |
584 | fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc) | |
862a1a5f | 585 | { |
2f18d1e8 IM |
586 | unsigned int event; |
587 | ||
f87ad35d JSR |
588 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
589 | return -1; | |
590 | ||
2f18d1e8 IM |
591 | if (unlikely(hwc->nmi)) |
592 | return -1; | |
593 | ||
594 | event = hwc->config & ARCH_PERFMON_EVENT_MASK; | |
595 | ||
5f4ec28f | 596 | if (unlikely(event == x86_pmu->event_map(PERF_COUNT_INSTRUCTIONS))) |
2f18d1e8 | 597 | return X86_PMC_IDX_FIXED_INSTRUCTIONS; |
5f4ec28f | 598 | if (unlikely(event == x86_pmu->event_map(PERF_COUNT_CPU_CYCLES))) |
2f18d1e8 | 599 | return X86_PMC_IDX_FIXED_CPU_CYCLES; |
5f4ec28f | 600 | if (unlikely(event == x86_pmu->event_map(PERF_COUNT_BUS_CYCLES))) |
2f18d1e8 IM |
601 | return X86_PMC_IDX_FIXED_BUS_CYCLES; |
602 | ||
862a1a5f IM |
603 | return -1; |
604 | } | |
605 | ||
ee06094f IM |
606 | /* |
607 | * Find a PMC slot for the freshly enabled / scheduled in counter: | |
608 | */ | |
4aeb0b42 | 609 | static int x86_pmu_enable(struct perf_counter *counter) |
241771ef IM |
610 | { |
611 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
612 | struct hw_perf_counter *hwc = &counter->hw; | |
2f18d1e8 | 613 | int idx; |
241771ef | 614 | |
2f18d1e8 IM |
615 | idx = fixed_mode_idx(counter, hwc); |
616 | if (idx >= 0) { | |
617 | /* | |
618 | * Try to get the fixed counter, if that is already taken | |
619 | * then try to get a generic counter: | |
620 | */ | |
621 | if (test_and_set_bit(idx, cpuc->used)) | |
622 | goto try_generic; | |
0dff86aa | 623 | |
2f18d1e8 IM |
624 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
625 | /* | |
626 | * We set it so that counter_base + idx in wrmsr/rdmsr maps to | |
627 | * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2: | |
628 | */ | |
629 | hwc->counter_base = | |
630 | MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED; | |
241771ef | 631 | hwc->idx = idx; |
2f18d1e8 IM |
632 | } else { |
633 | idx = hwc->idx; | |
634 | /* Try to get the previous generic counter again */ | |
635 | if (test_and_set_bit(idx, cpuc->used)) { | |
636 | try_generic: | |
637 | idx = find_first_zero_bit(cpuc->used, nr_counters_generic); | |
638 | if (idx == nr_counters_generic) | |
639 | return -EAGAIN; | |
640 | ||
641 | set_bit(idx, cpuc->used); | |
642 | hwc->idx = idx; | |
643 | } | |
5f4ec28f RR |
644 | hwc->config_base = x86_pmu->eventsel; |
645 | hwc->counter_base = x86_pmu->perfctr; | |
241771ef IM |
646 | } |
647 | ||
648 | perf_counters_lapic_init(hwc->nmi); | |
649 | ||
4aeb0b42 | 650 | __x86_pmu_disable(counter, hwc, idx); |
241771ef | 651 | |
862a1a5f | 652 | cpuc->counters[idx] = counter; |
2f18d1e8 IM |
653 | /* |
654 | * Make it visible before enabling the hw: | |
655 | */ | |
527e26af | 656 | barrier(); |
7e2ae347 | 657 | |
ee06094f | 658 | __hw_perf_counter_set_period(counter, hwc, idx); |
4aeb0b42 | 659 | __x86_pmu_enable(counter, hwc, idx); |
95cdd2e7 IM |
660 | |
661 | return 0; | |
241771ef IM |
662 | } |
663 | ||
664 | void perf_counter_print_debug(void) | |
665 | { | |
2f18d1e8 | 666 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
0dff86aa | 667 | struct cpu_hw_counters *cpuc; |
1e125676 IM |
668 | int cpu, idx; |
669 | ||
862a1a5f | 670 | if (!nr_counters_generic) |
1e125676 | 671 | return; |
241771ef IM |
672 | |
673 | local_irq_disable(); | |
674 | ||
675 | cpu = smp_processor_id(); | |
0dff86aa | 676 | cpuc = &per_cpu(cpu_hw_counters, cpu); |
241771ef | 677 | |
7bb497bd | 678 | if (intel_perfmon_version >= 2) { |
a1ef58f4 JSR |
679 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
680 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
681 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
682 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
683 | ||
684 | pr_info("\n"); | |
685 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
686 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
687 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
688 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
f87ad35d | 689 | } |
a1ef58f4 | 690 | pr_info("CPU#%d: used: %016llx\n", cpu, *(u64 *)cpuc->used); |
241771ef | 691 | |
862a1a5f | 692 | for (idx = 0; idx < nr_counters_generic; idx++) { |
5f4ec28f RR |
693 | rdmsrl(x86_pmu->eventsel + idx, pmc_ctrl); |
694 | rdmsrl(x86_pmu->perfctr + idx, pmc_count); | |
241771ef | 695 | |
ee06094f | 696 | prev_left = per_cpu(prev_left[idx], cpu); |
241771ef | 697 | |
a1ef58f4 | 698 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 699 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 700 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 701 | cpu, idx, pmc_count); |
a1ef58f4 | 702 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 703 | cpu, idx, prev_left); |
241771ef | 704 | } |
2f18d1e8 IM |
705 | for (idx = 0; idx < nr_counters_fixed; idx++) { |
706 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); | |
707 | ||
a1ef58f4 | 708 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
709 | cpu, idx, pmc_count); |
710 | } | |
241771ef IM |
711 | local_irq_enable(); |
712 | } | |
713 | ||
4aeb0b42 | 714 | static void x86_pmu_disable(struct perf_counter *counter) |
241771ef IM |
715 | { |
716 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
717 | struct hw_perf_counter *hwc = &counter->hw; | |
718 | unsigned int idx = hwc->idx; | |
719 | ||
4aeb0b42 | 720 | __x86_pmu_disable(counter, hwc, idx); |
241771ef IM |
721 | |
722 | clear_bit(idx, cpuc->used); | |
862a1a5f | 723 | cpuc->counters[idx] = NULL; |
2f18d1e8 IM |
724 | /* |
725 | * Make sure the cleared pointer becomes visible before we | |
726 | * (potentially) free the counter: | |
727 | */ | |
527e26af | 728 | barrier(); |
241771ef | 729 | |
ee06094f IM |
730 | /* |
731 | * Drain the remaining delta count out of a counter | |
732 | * that we are disabling: | |
733 | */ | |
734 | x86_perf_counter_update(counter, hwc, idx); | |
241771ef IM |
735 | } |
736 | ||
7e2ae347 | 737 | /* |
ee06094f IM |
738 | * Save and restart an expired counter. Called by NMI contexts, |
739 | * so it has to be careful about preempting normal counter ops: | |
7e2ae347 | 740 | */ |
241771ef IM |
741 | static void perf_save_and_restart(struct perf_counter *counter) |
742 | { | |
743 | struct hw_perf_counter *hwc = &counter->hw; | |
744 | int idx = hwc->idx; | |
241771ef | 745 | |
ee06094f IM |
746 | x86_perf_counter_update(counter, hwc, idx); |
747 | __hw_perf_counter_set_period(counter, hwc, idx); | |
7e2ae347 | 748 | |
2f18d1e8 | 749 | if (counter->state == PERF_COUNTER_STATE_ACTIVE) |
4aeb0b42 | 750 | __x86_pmu_enable(counter, hwc, idx); |
241771ef IM |
751 | } |
752 | ||
4b39fd96 MG |
753 | /* |
754 | * Maximum interrupt frequency of 100KHz per CPU | |
755 | */ | |
169e41eb | 756 | #define PERFMON_MAX_INTERRUPTS (100000/HZ) |
4b39fd96 | 757 | |
241771ef IM |
758 | /* |
759 | * This handler is triggered by the local APIC, so the APIC IRQ handling | |
760 | * rules apply: | |
761 | */ | |
39d81eab | 762 | static int intel_pmu_handle_irq(struct pt_regs *regs, int nmi) |
241771ef IM |
763 | { |
764 | int bit, cpu = smp_processor_id(); | |
4b39fd96 | 765 | u64 ack, status; |
1b023a96 | 766 | struct cpu_hw_counters *cpuc = &per_cpu(cpu_hw_counters, cpu); |
b0f3f28e | 767 | int ret = 0; |
43874d23 | 768 | |
b0f3f28e | 769 | cpuc->throttle_ctrl = hw_perf_save_disable(); |
241771ef | 770 | |
b7f8859a | 771 | status = intel_pmu_get_status(cpuc->throttle_ctrl); |
87b9cf46 IM |
772 | if (!status) |
773 | goto out; | |
774 | ||
b0f3f28e | 775 | ret = 1; |
241771ef | 776 | again: |
d278c484 | 777 | inc_irq_stat(apic_perf_irqs); |
241771ef | 778 | ack = status; |
2f18d1e8 | 779 | for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { |
862a1a5f | 780 | struct perf_counter *counter = cpuc->counters[bit]; |
241771ef IM |
781 | |
782 | clear_bit(bit, (unsigned long *) &status); | |
783 | if (!counter) | |
784 | continue; | |
785 | ||
786 | perf_save_and_restart(counter); | |
78f13e95 | 787 | if (perf_counter_overflow(counter, nmi, regs, 0)) |
4aeb0b42 | 788 | __x86_pmu_disable(counter, &counter->hw, bit); |
241771ef IM |
789 | } |
790 | ||
b0f3f28e | 791 | hw_perf_ack_status(ack); |
241771ef IM |
792 | |
793 | /* | |
794 | * Repeat if there is more work to be done: | |
795 | */ | |
b7f8859a | 796 | status = intel_pmu_get_status(cpuc->throttle_ctrl); |
241771ef IM |
797 | if (status) |
798 | goto again; | |
87b9cf46 | 799 | out: |
241771ef | 800 | /* |
1b023a96 | 801 | * Restore - do not reenable when global enable is off or throttled: |
241771ef | 802 | */ |
4b39fd96 | 803 | if (++cpuc->interrupts < PERFMON_MAX_INTERRUPTS) |
b0f3f28e PZ |
804 | hw_perf_restore(cpuc->throttle_ctrl); |
805 | ||
806 | return ret; | |
1b023a96 MG |
807 | } |
808 | ||
39d81eab RR |
809 | static int amd_pmu_handle_irq(struct pt_regs *regs, int nmi) { return 0; } |
810 | ||
1b023a96 MG |
811 | void perf_counter_unthrottle(void) |
812 | { | |
813 | struct cpu_hw_counters *cpuc; | |
814 | ||
815 | if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) | |
816 | return; | |
817 | ||
818 | if (unlikely(!perf_counters_initialized)) | |
819 | return; | |
820 | ||
b0f3f28e | 821 | cpuc = &__get_cpu_var(cpu_hw_counters); |
4b39fd96 | 822 | if (cpuc->interrupts >= PERFMON_MAX_INTERRUPTS) { |
1b023a96 | 823 | if (printk_ratelimit()) |
4b39fd96 | 824 | printk(KERN_WARNING "PERFMON: max interrupts exceeded!\n"); |
b0f3f28e | 825 | hw_perf_restore(cpuc->throttle_ctrl); |
1b023a96 | 826 | } |
4b39fd96 | 827 | cpuc->interrupts = 0; |
241771ef IM |
828 | } |
829 | ||
830 | void smp_perf_counter_interrupt(struct pt_regs *regs) | |
831 | { | |
832 | irq_enter(); | |
241771ef | 833 | apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR); |
b0f3f28e | 834 | ack_APIC_irq(); |
39d81eab | 835 | x86_pmu->handle_irq(regs, 0); |
241771ef IM |
836 | irq_exit(); |
837 | } | |
838 | ||
b6276f35 PZ |
839 | void smp_perf_pending_interrupt(struct pt_regs *regs) |
840 | { | |
841 | irq_enter(); | |
842 | ack_APIC_irq(); | |
843 | inc_irq_stat(apic_pending_irqs); | |
844 | perf_counter_do_pending(); | |
845 | irq_exit(); | |
846 | } | |
847 | ||
848 | void set_perf_counter_pending(void) | |
849 | { | |
850 | apic->send_IPI_self(LOCAL_PENDING_VECTOR); | |
851 | } | |
852 | ||
3415dd91 | 853 | void perf_counters_lapic_init(int nmi) |
241771ef IM |
854 | { |
855 | u32 apic_val; | |
856 | ||
857 | if (!perf_counters_initialized) | |
858 | return; | |
859 | /* | |
860 | * Enable the performance counter vector in the APIC LVT: | |
861 | */ | |
862 | apic_val = apic_read(APIC_LVTERR); | |
863 | ||
864 | apic_write(APIC_LVTERR, apic_val | APIC_LVT_MASKED); | |
865 | if (nmi) | |
866 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
867 | else | |
868 | apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR); | |
869 | apic_write(APIC_LVTERR, apic_val); | |
870 | } | |
871 | ||
872 | static int __kprobes | |
873 | perf_counter_nmi_handler(struct notifier_block *self, | |
874 | unsigned long cmd, void *__args) | |
875 | { | |
876 | struct die_args *args = __args; | |
877 | struct pt_regs *regs; | |
b0f3f28e PZ |
878 | int ret; |
879 | ||
880 | switch (cmd) { | |
881 | case DIE_NMI: | |
882 | case DIE_NMI_IPI: | |
883 | break; | |
241771ef | 884 | |
b0f3f28e | 885 | default: |
241771ef | 886 | return NOTIFY_DONE; |
b0f3f28e | 887 | } |
241771ef IM |
888 | |
889 | regs = args->regs; | |
890 | ||
891 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
39d81eab | 892 | ret = x86_pmu->handle_irq(regs, 1); |
241771ef | 893 | |
b0f3f28e | 894 | return ret ? NOTIFY_STOP : NOTIFY_OK; |
241771ef IM |
895 | } |
896 | ||
897 | static __read_mostly struct notifier_block perf_counter_nmi_notifier = { | |
5b75af0a MG |
898 | .notifier_call = perf_counter_nmi_handler, |
899 | .next = NULL, | |
900 | .priority = 1 | |
241771ef IM |
901 | }; |
902 | ||
5f4ec28f | 903 | static struct x86_pmu intel_pmu = { |
39d81eab | 904 | .handle_irq = intel_pmu_handle_irq, |
5f4ec28f RR |
905 | .save_disable_all = intel_pmu_save_disable_all, |
906 | .restore_all = intel_pmu_restore_all, | |
5f4ec28f RR |
907 | .ack_status = intel_pmu_ack_status, |
908 | .enable = intel_pmu_enable_counter, | |
909 | .disable = intel_pmu_disable_counter, | |
b56a3802 JSR |
910 | .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, |
911 | .perfctr = MSR_ARCH_PERFMON_PERFCTR0, | |
5f4ec28f RR |
912 | .event_map = intel_pmu_event_map, |
913 | .raw_event = intel_pmu_raw_event, | |
b56a3802 JSR |
914 | .max_events = ARRAY_SIZE(intel_perfmon_event_map), |
915 | }; | |
916 | ||
5f4ec28f | 917 | static struct x86_pmu amd_pmu = { |
39d81eab | 918 | .handle_irq = amd_pmu_handle_irq, |
5f4ec28f RR |
919 | .save_disable_all = amd_pmu_save_disable_all, |
920 | .restore_all = amd_pmu_restore_all, | |
5f4ec28f RR |
921 | .ack_status = amd_pmu_ack_status, |
922 | .enable = amd_pmu_enable_counter, | |
923 | .disable = amd_pmu_disable_counter, | |
f87ad35d JSR |
924 | .eventsel = MSR_K7_EVNTSEL0, |
925 | .perfctr = MSR_K7_PERFCTR0, | |
5f4ec28f RR |
926 | .event_map = amd_pmu_event_map, |
927 | .raw_event = amd_pmu_raw_event, | |
f87ad35d JSR |
928 | .max_events = ARRAY_SIZE(amd_perfmon_event_map), |
929 | }; | |
930 | ||
5f4ec28f | 931 | static struct x86_pmu *intel_pmu_init(void) |
241771ef | 932 | { |
7bb497bd | 933 | union cpuid10_edx edx; |
241771ef | 934 | union cpuid10_eax eax; |
703e937c | 935 | unsigned int unused; |
7bb497bd | 936 | unsigned int ebx; |
241771ef | 937 | |
da1a776b RR |
938 | if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) |
939 | return NULL; | |
940 | ||
241771ef IM |
941 | /* |
942 | * Check whether the Architectural PerfMon supports | |
943 | * Branch Misses Retired Event or not. | |
944 | */ | |
703e937c | 945 | cpuid(10, &eax.full, &ebx, &unused, &edx.full); |
241771ef | 946 | if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED) |
b56a3802 | 947 | return NULL; |
241771ef | 948 | |
7bb497bd IM |
949 | intel_perfmon_version = eax.split.version_id; |
950 | if (intel_perfmon_version < 2) | |
951 | return NULL; | |
952 | ||
a1ef58f4 | 953 | pr_info("Intel Performance Monitoring support detected.\n"); |
7bb497bd | 954 | pr_info("... version: %d\n", intel_perfmon_version); |
a1ef58f4 JSR |
955 | pr_info("... bit width: %d\n", eax.split.bit_width); |
956 | pr_info("... mask length: %d\n", eax.split.mask_length); | |
b56a3802 | 957 | |
862a1a5f | 958 | nr_counters_generic = eax.split.num_counters; |
b56a3802 JSR |
959 | nr_counters_fixed = edx.split.num_counters_fixed; |
960 | counter_value_mask = (1ULL << eax.split.bit_width) - 1; | |
961 | ||
5f4ec28f | 962 | return &intel_pmu; |
b56a3802 JSR |
963 | } |
964 | ||
5f4ec28f | 965 | static struct x86_pmu *amd_pmu_init(void) |
f87ad35d JSR |
966 | { |
967 | nr_counters_generic = 4; | |
968 | nr_counters_fixed = 0; | |
b5e8acf6 PZ |
969 | counter_value_mask = 0x0000FFFFFFFFFFFFULL; |
970 | counter_value_bits = 48; | |
f87ad35d | 971 | |
a1ef58f4 | 972 | pr_info("AMD Performance Monitoring support detected.\n"); |
f87ad35d | 973 | |
5f4ec28f | 974 | return &amd_pmu; |
f87ad35d JSR |
975 | } |
976 | ||
b56a3802 JSR |
977 | void __init init_hw_perf_counters(void) |
978 | { | |
b56a3802 JSR |
979 | switch (boot_cpu_data.x86_vendor) { |
980 | case X86_VENDOR_INTEL: | |
5f4ec28f | 981 | x86_pmu = intel_pmu_init(); |
b56a3802 | 982 | break; |
f87ad35d | 983 | case X86_VENDOR_AMD: |
5f4ec28f | 984 | x86_pmu = amd_pmu_init(); |
f87ad35d | 985 | break; |
4138960a RR |
986 | default: |
987 | return; | |
b56a3802 | 988 | } |
5f4ec28f | 989 | if (!x86_pmu) |
b56a3802 JSR |
990 | return; |
991 | ||
a1ef58f4 | 992 | pr_info("... num counters: %d\n", nr_counters_generic); |
862a1a5f IM |
993 | if (nr_counters_generic > X86_PMC_MAX_GENERIC) { |
994 | nr_counters_generic = X86_PMC_MAX_GENERIC; | |
241771ef | 995 | WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!", |
862a1a5f | 996 | nr_counters_generic, X86_PMC_MAX_GENERIC); |
241771ef | 997 | } |
862a1a5f IM |
998 | perf_counter_mask = (1 << nr_counters_generic) - 1; |
999 | perf_max_counters = nr_counters_generic; | |
241771ef | 1000 | |
a1ef58f4 | 1001 | pr_info("... value mask: %016Lx\n", counter_value_mask); |
2f18d1e8 | 1002 | |
862a1a5f IM |
1003 | if (nr_counters_fixed > X86_PMC_MAX_FIXED) { |
1004 | nr_counters_fixed = X86_PMC_MAX_FIXED; | |
703e937c | 1005 | WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!", |
862a1a5f | 1006 | nr_counters_fixed, X86_PMC_MAX_FIXED); |
703e937c | 1007 | } |
a1ef58f4 | 1008 | pr_info("... fixed counters: %d\n", nr_counters_fixed); |
862a1a5f IM |
1009 | |
1010 | perf_counter_mask |= ((1LL << nr_counters_fixed)-1) << X86_PMC_IDX_FIXED; | |
241771ef | 1011 | |
a1ef58f4 | 1012 | pr_info("... counter mask: %016Lx\n", perf_counter_mask); |
75f224cf IM |
1013 | perf_counters_initialized = true; |
1014 | ||
241771ef IM |
1015 | perf_counters_lapic_init(0); |
1016 | register_die_notifier(&perf_counter_nmi_notifier); | |
241771ef | 1017 | } |
621a01ea | 1018 | |
4aeb0b42 | 1019 | static void x86_pmu_read(struct perf_counter *counter) |
ee06094f IM |
1020 | { |
1021 | x86_perf_counter_update(counter, &counter->hw, counter->hw.idx); | |
1022 | } | |
1023 | ||
4aeb0b42 RR |
1024 | static const struct pmu pmu = { |
1025 | .enable = x86_pmu_enable, | |
1026 | .disable = x86_pmu_disable, | |
1027 | .read = x86_pmu_read, | |
621a01ea IM |
1028 | }; |
1029 | ||
4aeb0b42 | 1030 | const struct pmu *hw_perf_counter_init(struct perf_counter *counter) |
621a01ea IM |
1031 | { |
1032 | int err; | |
1033 | ||
1034 | err = __hw_perf_counter_init(counter); | |
1035 | if (err) | |
9ea98e19 | 1036 | return ERR_PTR(err); |
621a01ea | 1037 | |
4aeb0b42 | 1038 | return &pmu; |
621a01ea | 1039 | } |
d7d59fb3 PZ |
1040 | |
1041 | /* | |
1042 | * callchain support | |
1043 | */ | |
1044 | ||
1045 | static inline | |
1046 | void callchain_store(struct perf_callchain_entry *entry, unsigned long ip) | |
1047 | { | |
1048 | if (entry->nr < MAX_STACK_DEPTH) | |
1049 | entry->ip[entry->nr++] = ip; | |
1050 | } | |
1051 | ||
1052 | static DEFINE_PER_CPU(struct perf_callchain_entry, irq_entry); | |
1053 | static DEFINE_PER_CPU(struct perf_callchain_entry, nmi_entry); | |
1054 | ||
1055 | ||
1056 | static void | |
1057 | backtrace_warning_symbol(void *data, char *msg, unsigned long symbol) | |
1058 | { | |
1059 | /* Ignore warnings */ | |
1060 | } | |
1061 | ||
1062 | static void backtrace_warning(void *data, char *msg) | |
1063 | { | |
1064 | /* Ignore warnings */ | |
1065 | } | |
1066 | ||
1067 | static int backtrace_stack(void *data, char *name) | |
1068 | { | |
1069 | /* Don't bother with IRQ stacks for now */ | |
1070 | return -1; | |
1071 | } | |
1072 | ||
1073 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1074 | { | |
1075 | struct perf_callchain_entry *entry = data; | |
1076 | ||
1077 | if (reliable) | |
1078 | callchain_store(entry, addr); | |
1079 | } | |
1080 | ||
1081 | static const struct stacktrace_ops backtrace_ops = { | |
1082 | .warning = backtrace_warning, | |
1083 | .warning_symbol = backtrace_warning_symbol, | |
1084 | .stack = backtrace_stack, | |
1085 | .address = backtrace_address, | |
1086 | }; | |
1087 | ||
1088 | static void | |
1089 | perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1090 | { | |
1091 | unsigned long bp; | |
1092 | char *stack; | |
5872bdb8 | 1093 | int nr = entry->nr; |
d7d59fb3 PZ |
1094 | |
1095 | callchain_store(entry, instruction_pointer(regs)); | |
1096 | ||
1097 | stack = ((char *)regs + sizeof(struct pt_regs)); | |
1098 | #ifdef CONFIG_FRAME_POINTER | |
1099 | bp = frame_pointer(regs); | |
1100 | #else | |
1101 | bp = 0; | |
1102 | #endif | |
1103 | ||
1104 | dump_trace(NULL, regs, (void *)stack, bp, &backtrace_ops, entry); | |
5872bdb8 PZ |
1105 | |
1106 | entry->kernel = entry->nr - nr; | |
d7d59fb3 PZ |
1107 | } |
1108 | ||
1109 | ||
1110 | struct stack_frame { | |
1111 | const void __user *next_fp; | |
1112 | unsigned long return_address; | |
1113 | }; | |
1114 | ||
1115 | static int copy_stack_frame(const void __user *fp, struct stack_frame *frame) | |
1116 | { | |
1117 | int ret; | |
1118 | ||
1119 | if (!access_ok(VERIFY_READ, fp, sizeof(*frame))) | |
1120 | return 0; | |
1121 | ||
1122 | ret = 1; | |
1123 | pagefault_disable(); | |
1124 | if (__copy_from_user_inatomic(frame, fp, sizeof(*frame))) | |
1125 | ret = 0; | |
1126 | pagefault_enable(); | |
1127 | ||
1128 | return ret; | |
1129 | } | |
1130 | ||
1131 | static void | |
1132 | perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1133 | { | |
1134 | struct stack_frame frame; | |
1135 | const void __user *fp; | |
5872bdb8 | 1136 | int nr = entry->nr; |
d7d59fb3 PZ |
1137 | |
1138 | regs = (struct pt_regs *)current->thread.sp0 - 1; | |
1139 | fp = (void __user *)regs->bp; | |
1140 | ||
1141 | callchain_store(entry, regs->ip); | |
1142 | ||
1143 | while (entry->nr < MAX_STACK_DEPTH) { | |
1144 | frame.next_fp = NULL; | |
1145 | frame.return_address = 0; | |
1146 | ||
1147 | if (!copy_stack_frame(fp, &frame)) | |
1148 | break; | |
1149 | ||
1150 | if ((unsigned long)fp < user_stack_pointer(regs)) | |
1151 | break; | |
1152 | ||
1153 | callchain_store(entry, frame.return_address); | |
1154 | fp = frame.next_fp; | |
1155 | } | |
5872bdb8 PZ |
1156 | |
1157 | entry->user = entry->nr - nr; | |
d7d59fb3 PZ |
1158 | } |
1159 | ||
1160 | static void | |
1161 | perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1162 | { | |
1163 | int is_user; | |
1164 | ||
1165 | if (!regs) | |
1166 | return; | |
1167 | ||
1168 | is_user = user_mode(regs); | |
1169 | ||
1170 | if (!current || current->pid == 0) | |
1171 | return; | |
1172 | ||
1173 | if (is_user && current->state != TASK_RUNNING) | |
1174 | return; | |
1175 | ||
1176 | if (!is_user) | |
1177 | perf_callchain_kernel(regs, entry); | |
1178 | ||
1179 | if (current->mm) | |
1180 | perf_callchain_user(regs, entry); | |
1181 | } | |
1182 | ||
1183 | struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) | |
1184 | { | |
1185 | struct perf_callchain_entry *entry; | |
1186 | ||
1187 | if (in_nmi()) | |
1188 | entry = &__get_cpu_var(nmi_entry); | |
1189 | else | |
1190 | entry = &__get_cpu_var(irq_entry); | |
1191 | ||
1192 | entry->nr = 0; | |
5872bdb8 PZ |
1193 | entry->hv = 0; |
1194 | entry->kernel = 0; | |
1195 | entry->user = 0; | |
d7d59fb3 PZ |
1196 | |
1197 | perf_do_callchain(regs, entry); | |
1198 | ||
1199 | return entry; | |
1200 | } |