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241771ef IM |
1 | /* |
2 | * Performance counter x86 architecture code | |
3 | * | |
4 | * Copyright(C) 2008 Thomas Gleixner <tglx@linutronix.de> | |
5 | * Copyright(C) 2008 Red Hat, Inc., Ingo Molnar | |
6 | * | |
7 | * For licencing details see kernel-base/COPYING | |
8 | */ | |
9 | ||
10 | #include <linux/perf_counter.h> | |
11 | #include <linux/capability.h> | |
12 | #include <linux/notifier.h> | |
13 | #include <linux/hardirq.h> | |
14 | #include <linux/kprobes.h> | |
4ac13294 | 15 | #include <linux/module.h> |
241771ef IM |
16 | #include <linux/kdebug.h> |
17 | #include <linux/sched.h> | |
18 | ||
5c167b85 | 19 | #include <asm/perf_counter.h> |
241771ef IM |
20 | #include <asm/apic.h> |
21 | ||
22 | static bool perf_counters_initialized __read_mostly; | |
23 | ||
24 | /* | |
25 | * Number of (generic) HW counters: | |
26 | */ | |
862a1a5f IM |
27 | static int nr_counters_generic __read_mostly; |
28 | static u64 perf_counter_mask __read_mostly; | |
2f18d1e8 | 29 | static u64 counter_value_mask __read_mostly; |
241771ef | 30 | |
862a1a5f | 31 | static int nr_counters_fixed __read_mostly; |
703e937c | 32 | |
241771ef | 33 | struct cpu_hw_counters { |
862a1a5f IM |
34 | struct perf_counter *counters[X86_PMC_IDX_MAX]; |
35 | unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
4b39fd96 | 36 | unsigned long interrupts; |
1b023a96 | 37 | u64 global_enable; |
241771ef IM |
38 | }; |
39 | ||
40 | /* | |
41 | * Intel PerfMon v3. Used on Core2 and later. | |
42 | */ | |
43 | static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters); | |
44 | ||
94c46572 | 45 | static const int intel_perfmon_event_map[] = |
241771ef | 46 | { |
f650a672 | 47 | [PERF_COUNT_CPU_CYCLES] = 0x003c, |
241771ef IM |
48 | [PERF_COUNT_INSTRUCTIONS] = 0x00c0, |
49 | [PERF_COUNT_CACHE_REFERENCES] = 0x4f2e, | |
50 | [PERF_COUNT_CACHE_MISSES] = 0x412e, | |
51 | [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4, | |
52 | [PERF_COUNT_BRANCH_MISSES] = 0x00c5, | |
f650a672 | 53 | [PERF_COUNT_BUS_CYCLES] = 0x013c, |
241771ef IM |
54 | }; |
55 | ||
94c46572 | 56 | static const int max_intel_perfmon_events = ARRAY_SIZE(intel_perfmon_event_map); |
241771ef | 57 | |
ee06094f IM |
58 | /* |
59 | * Propagate counter elapsed time into the generic counter. | |
60 | * Can only be executed on the CPU where the counter is active. | |
61 | * Returns the delta events processed. | |
62 | */ | |
63 | static void | |
64 | x86_perf_counter_update(struct perf_counter *counter, | |
65 | struct hw_perf_counter *hwc, int idx) | |
66 | { | |
67 | u64 prev_raw_count, new_raw_count, delta; | |
68 | ||
ee06094f IM |
69 | /* |
70 | * Careful: an NMI might modify the previous counter value. | |
71 | * | |
72 | * Our tactic to handle this is to first atomically read and | |
73 | * exchange a new raw count - then add that new-prev delta | |
74 | * count to the generic counter atomically: | |
75 | */ | |
76 | again: | |
77 | prev_raw_count = atomic64_read(&hwc->prev_count); | |
78 | rdmsrl(hwc->counter_base + idx, new_raw_count); | |
79 | ||
80 | if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count, | |
81 | new_raw_count) != prev_raw_count) | |
82 | goto again; | |
83 | ||
84 | /* | |
85 | * Now we have the new raw value and have updated the prev | |
86 | * timestamp already. We can now calculate the elapsed delta | |
87 | * (counter-)time and add that to the generic counter. | |
88 | * | |
89 | * Careful, not all hw sign-extends above the physical width | |
90 | * of the count, so we do that by clipping the delta to 32 bits: | |
91 | */ | |
92 | delta = (u64)(u32)((s32)new_raw_count - (s32)prev_raw_count); | |
ee06094f IM |
93 | |
94 | atomic64_add(delta, &counter->count); | |
95 | atomic64_sub(delta, &hwc->period_left); | |
96 | } | |
97 | ||
241771ef IM |
98 | /* |
99 | * Setup the hardware configuration for a given hw_event_type | |
100 | */ | |
621a01ea | 101 | static int __hw_perf_counter_init(struct perf_counter *counter) |
241771ef | 102 | { |
9f66a381 | 103 | struct perf_counter_hw_event *hw_event = &counter->hw_event; |
241771ef IM |
104 | struct hw_perf_counter *hwc = &counter->hw; |
105 | ||
106 | if (unlikely(!perf_counters_initialized)) | |
107 | return -EINVAL; | |
108 | ||
109 | /* | |
110 | * Count user events, and generate PMC IRQs: | |
111 | * (keep 'enabled' bit clear for now) | |
112 | */ | |
113 | hwc->config = ARCH_PERFMON_EVENTSEL_USR | ARCH_PERFMON_EVENTSEL_INT; | |
114 | ||
115 | /* | |
116 | * If privileged enough, count OS events too, and allow | |
117 | * NMI events as well: | |
118 | */ | |
119 | hwc->nmi = 0; | |
120 | if (capable(CAP_SYS_ADMIN)) { | |
121 | hwc->config |= ARCH_PERFMON_EVENTSEL_OS; | |
9f66a381 | 122 | if (hw_event->nmi) |
241771ef IM |
123 | hwc->nmi = 1; |
124 | } | |
125 | ||
9f66a381 | 126 | hwc->irq_period = hw_event->irq_period; |
241771ef IM |
127 | /* |
128 | * Intel PMCs cannot be accessed sanely above 32 bit width, | |
129 | * so we install an artificial 1<<31 period regardless of | |
130 | * the generic counter period: | |
131 | */ | |
ee06094f | 132 | if ((s64)hwc->irq_period <= 0 || hwc->irq_period > 0x7FFFFFFF) |
241771ef IM |
133 | hwc->irq_period = 0x7FFFFFFF; |
134 | ||
ee06094f | 135 | atomic64_set(&hwc->period_left, hwc->irq_period); |
241771ef IM |
136 | |
137 | /* | |
dfa7c899 | 138 | * Raw event type provide the config in the event structure |
241771ef | 139 | */ |
9f66a381 IM |
140 | if (hw_event->raw) { |
141 | hwc->config |= hw_event->type; | |
241771ef | 142 | } else { |
9f66a381 | 143 | if (hw_event->type >= max_intel_perfmon_events) |
241771ef IM |
144 | return -EINVAL; |
145 | /* | |
146 | * The generic map: | |
147 | */ | |
9f66a381 | 148 | hwc->config |= intel_perfmon_event_map[hw_event->type]; |
241771ef | 149 | } |
241771ef IM |
150 | counter->wakeup_pending = 0; |
151 | ||
152 | return 0; | |
153 | } | |
154 | ||
01b2838c | 155 | u64 hw_perf_save_disable(void) |
4ac13294 TG |
156 | { |
157 | u64 ctrl; | |
158 | ||
2b9ff0db IM |
159 | if (unlikely(!perf_counters_initialized)) |
160 | return 0; | |
161 | ||
4ac13294 | 162 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
862a1a5f | 163 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); |
2b9ff0db | 164 | |
4ac13294 | 165 | return ctrl; |
241771ef | 166 | } |
01b2838c | 167 | EXPORT_SYMBOL_GPL(hw_perf_save_disable); |
241771ef | 168 | |
ee06094f IM |
169 | void hw_perf_restore(u64 ctrl) |
170 | { | |
2b9ff0db IM |
171 | if (unlikely(!perf_counters_initialized)) |
172 | return; | |
173 | ||
862a1a5f | 174 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
ee06094f IM |
175 | } |
176 | EXPORT_SYMBOL_GPL(hw_perf_restore); | |
177 | ||
2f18d1e8 IM |
178 | static inline void |
179 | __pmc_fixed_disable(struct perf_counter *counter, | |
180 | struct hw_perf_counter *hwc, unsigned int __idx) | |
181 | { | |
182 | int idx = __idx - X86_PMC_IDX_FIXED; | |
183 | u64 ctrl_val, mask; | |
184 | int err; | |
185 | ||
186 | mask = 0xfULL << (idx * 4); | |
187 | ||
188 | rdmsrl(hwc->config_base, ctrl_val); | |
189 | ctrl_val &= ~mask; | |
190 | err = checking_wrmsrl(hwc->config_base, ctrl_val); | |
191 | } | |
192 | ||
7e2ae347 | 193 | static inline void |
eb2b8618 | 194 | __pmc_generic_disable(struct perf_counter *counter, |
ee06094f | 195 | struct hw_perf_counter *hwc, unsigned int idx) |
7e2ae347 | 196 | { |
2f18d1e8 | 197 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) |
2b583d8b JSR |
198 | __pmc_fixed_disable(counter, hwc, idx); |
199 | else | |
200 | wrmsr_safe(hwc->config_base + idx, hwc->config, 0); | |
7e2ae347 IM |
201 | } |
202 | ||
2f18d1e8 | 203 | static DEFINE_PER_CPU(u64, prev_left[X86_PMC_IDX_MAX]); |
241771ef | 204 | |
ee06094f IM |
205 | /* |
206 | * Set the next IRQ period, based on the hwc->period_left value. | |
207 | * To be called with the counter disabled in hw: | |
208 | */ | |
209 | static void | |
210 | __hw_perf_counter_set_period(struct perf_counter *counter, | |
211 | struct hw_perf_counter *hwc, int idx) | |
241771ef | 212 | { |
2f18d1e8 | 213 | s64 left = atomic64_read(&hwc->period_left); |
ee06094f | 214 | s32 period = hwc->irq_period; |
2f18d1e8 | 215 | int err; |
ee06094f | 216 | |
ee06094f IM |
217 | /* |
218 | * If we are way outside a reasoable range then just skip forward: | |
219 | */ | |
220 | if (unlikely(left <= -period)) { | |
221 | left = period; | |
222 | atomic64_set(&hwc->period_left, left); | |
223 | } | |
224 | ||
225 | if (unlikely(left <= 0)) { | |
226 | left += period; | |
227 | atomic64_set(&hwc->period_left, left); | |
228 | } | |
241771ef | 229 | |
ee06094f IM |
230 | per_cpu(prev_left[idx], smp_processor_id()) = left; |
231 | ||
232 | /* | |
233 | * The hw counter starts counting from this counter offset, | |
234 | * mark it to be able to extra future deltas: | |
235 | */ | |
2f18d1e8 | 236 | atomic64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 237 | |
2f18d1e8 IM |
238 | err = checking_wrmsrl(hwc->counter_base + idx, |
239 | (u64)(-left) & counter_value_mask); | |
240 | } | |
241 | ||
242 | static inline void | |
243 | __pmc_fixed_enable(struct perf_counter *counter, | |
244 | struct hw_perf_counter *hwc, unsigned int __idx) | |
245 | { | |
246 | int idx = __idx - X86_PMC_IDX_FIXED; | |
247 | u64 ctrl_val, bits, mask; | |
248 | int err; | |
249 | ||
250 | /* | |
251 | * Enable IRQ generation (0x8) and ring-3 counting (0x2), | |
252 | * and enable ring-0 counting if allowed: | |
253 | */ | |
254 | bits = 0x8ULL | 0x2ULL; | |
255 | if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) | |
256 | bits |= 0x1; | |
257 | bits <<= (idx * 4); | |
258 | mask = 0xfULL << (idx * 4); | |
259 | ||
260 | rdmsrl(hwc->config_base, ctrl_val); | |
261 | ctrl_val &= ~mask; | |
262 | ctrl_val |= bits; | |
263 | err = checking_wrmsrl(hwc->config_base, ctrl_val); | |
7e2ae347 IM |
264 | } |
265 | ||
ee06094f | 266 | static void |
eb2b8618 | 267 | __pmc_generic_enable(struct perf_counter *counter, |
ee06094f | 268 | struct hw_perf_counter *hwc, int idx) |
7e2ae347 | 269 | { |
2f18d1e8 | 270 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) |
2b583d8b JSR |
271 | __pmc_fixed_enable(counter, hwc, idx); |
272 | else | |
273 | wrmsr(hwc->config_base + idx, | |
274 | hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE, 0); | |
241771ef IM |
275 | } |
276 | ||
2f18d1e8 IM |
277 | static int |
278 | fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc) | |
862a1a5f | 279 | { |
2f18d1e8 IM |
280 | unsigned int event; |
281 | ||
282 | if (unlikely(hwc->nmi)) | |
283 | return -1; | |
284 | ||
285 | event = hwc->config & ARCH_PERFMON_EVENT_MASK; | |
286 | ||
287 | if (unlikely(event == intel_perfmon_event_map[PERF_COUNT_INSTRUCTIONS])) | |
288 | return X86_PMC_IDX_FIXED_INSTRUCTIONS; | |
289 | if (unlikely(event == intel_perfmon_event_map[PERF_COUNT_CPU_CYCLES])) | |
290 | return X86_PMC_IDX_FIXED_CPU_CYCLES; | |
291 | if (unlikely(event == intel_perfmon_event_map[PERF_COUNT_BUS_CYCLES])) | |
292 | return X86_PMC_IDX_FIXED_BUS_CYCLES; | |
293 | ||
862a1a5f IM |
294 | return -1; |
295 | } | |
296 | ||
ee06094f IM |
297 | /* |
298 | * Find a PMC slot for the freshly enabled / scheduled in counter: | |
299 | */ | |
95cdd2e7 | 300 | static int pmc_generic_enable(struct perf_counter *counter) |
241771ef IM |
301 | { |
302 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
303 | struct hw_perf_counter *hwc = &counter->hw; | |
2f18d1e8 | 304 | int idx; |
241771ef | 305 | |
2f18d1e8 IM |
306 | idx = fixed_mode_idx(counter, hwc); |
307 | if (idx >= 0) { | |
308 | /* | |
309 | * Try to get the fixed counter, if that is already taken | |
310 | * then try to get a generic counter: | |
311 | */ | |
312 | if (test_and_set_bit(idx, cpuc->used)) | |
313 | goto try_generic; | |
0dff86aa | 314 | |
2f18d1e8 IM |
315 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
316 | /* | |
317 | * We set it so that counter_base + idx in wrmsr/rdmsr maps to | |
318 | * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2: | |
319 | */ | |
320 | hwc->counter_base = | |
321 | MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED; | |
241771ef | 322 | hwc->idx = idx; |
2f18d1e8 IM |
323 | } else { |
324 | idx = hwc->idx; | |
325 | /* Try to get the previous generic counter again */ | |
326 | if (test_and_set_bit(idx, cpuc->used)) { | |
327 | try_generic: | |
328 | idx = find_first_zero_bit(cpuc->used, nr_counters_generic); | |
329 | if (idx == nr_counters_generic) | |
330 | return -EAGAIN; | |
331 | ||
332 | set_bit(idx, cpuc->used); | |
333 | hwc->idx = idx; | |
334 | } | |
335 | hwc->config_base = MSR_ARCH_PERFMON_EVENTSEL0; | |
336 | hwc->counter_base = MSR_ARCH_PERFMON_PERFCTR0; | |
241771ef IM |
337 | } |
338 | ||
339 | perf_counters_lapic_init(hwc->nmi); | |
340 | ||
eb2b8618 | 341 | __pmc_generic_disable(counter, hwc, idx); |
241771ef | 342 | |
862a1a5f | 343 | cpuc->counters[idx] = counter; |
2f18d1e8 IM |
344 | /* |
345 | * Make it visible before enabling the hw: | |
346 | */ | |
347 | smp_wmb(); | |
7e2ae347 | 348 | |
ee06094f | 349 | __hw_perf_counter_set_period(counter, hwc, idx); |
eb2b8618 | 350 | __pmc_generic_enable(counter, hwc, idx); |
95cdd2e7 IM |
351 | |
352 | return 0; | |
241771ef IM |
353 | } |
354 | ||
355 | void perf_counter_print_debug(void) | |
356 | { | |
2f18d1e8 | 357 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
0dff86aa | 358 | struct cpu_hw_counters *cpuc; |
1e125676 IM |
359 | int cpu, idx; |
360 | ||
862a1a5f | 361 | if (!nr_counters_generic) |
1e125676 | 362 | return; |
241771ef IM |
363 | |
364 | local_irq_disable(); | |
365 | ||
366 | cpu = smp_processor_id(); | |
0dff86aa | 367 | cpuc = &per_cpu(cpu_hw_counters, cpu); |
241771ef | 368 | |
1e125676 IM |
369 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
370 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
371 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
2f18d1e8 | 372 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); |
241771ef IM |
373 | |
374 | printk(KERN_INFO "\n"); | |
375 | printk(KERN_INFO "CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
376 | printk(KERN_INFO "CPU#%d: status: %016llx\n", cpu, status); | |
377 | printk(KERN_INFO "CPU#%d: overflow: %016llx\n", cpu, overflow); | |
2f18d1e8 | 378 | printk(KERN_INFO "CPU#%d: fixed: %016llx\n", cpu, fixed); |
0dff86aa | 379 | printk(KERN_INFO "CPU#%d: used: %016llx\n", cpu, *(u64 *)cpuc->used); |
241771ef | 380 | |
862a1a5f | 381 | for (idx = 0; idx < nr_counters_generic; idx++) { |
1e125676 IM |
382 | rdmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + idx, pmc_ctrl); |
383 | rdmsrl(MSR_ARCH_PERFMON_PERFCTR0 + idx, pmc_count); | |
241771ef | 384 | |
ee06094f | 385 | prev_left = per_cpu(prev_left[idx], cpu); |
241771ef | 386 | |
2f18d1e8 | 387 | printk(KERN_INFO "CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 388 | cpu, idx, pmc_ctrl); |
2f18d1e8 | 389 | printk(KERN_INFO "CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 390 | cpu, idx, pmc_count); |
2f18d1e8 | 391 | printk(KERN_INFO "CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 392 | cpu, idx, prev_left); |
241771ef | 393 | } |
2f18d1e8 IM |
394 | for (idx = 0; idx < nr_counters_fixed; idx++) { |
395 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); | |
396 | ||
397 | printk(KERN_INFO "CPU#%d: fixed-PMC%d count: %016llx\n", | |
398 | cpu, idx, pmc_count); | |
399 | } | |
241771ef IM |
400 | local_irq_enable(); |
401 | } | |
402 | ||
eb2b8618 | 403 | static void pmc_generic_disable(struct perf_counter *counter) |
241771ef IM |
404 | { |
405 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
406 | struct hw_perf_counter *hwc = &counter->hw; | |
407 | unsigned int idx = hwc->idx; | |
408 | ||
eb2b8618 | 409 | __pmc_generic_disable(counter, hwc, idx); |
241771ef IM |
410 | |
411 | clear_bit(idx, cpuc->used); | |
862a1a5f | 412 | cpuc->counters[idx] = NULL; |
2f18d1e8 IM |
413 | /* |
414 | * Make sure the cleared pointer becomes visible before we | |
415 | * (potentially) free the counter: | |
416 | */ | |
417 | smp_wmb(); | |
241771ef | 418 | |
ee06094f IM |
419 | /* |
420 | * Drain the remaining delta count out of a counter | |
421 | * that we are disabling: | |
422 | */ | |
423 | x86_perf_counter_update(counter, hwc, idx); | |
241771ef IM |
424 | } |
425 | ||
426 | static void perf_store_irq_data(struct perf_counter *counter, u64 data) | |
427 | { | |
428 | struct perf_data *irqdata = counter->irqdata; | |
429 | ||
430 | if (irqdata->len > PERF_DATA_BUFLEN - sizeof(u64)) { | |
431 | irqdata->overrun++; | |
432 | } else { | |
433 | u64 *p = (u64 *) &irqdata->data[irqdata->len]; | |
434 | ||
435 | *p = data; | |
436 | irqdata->len += sizeof(u64); | |
437 | } | |
438 | } | |
439 | ||
7e2ae347 | 440 | /* |
ee06094f IM |
441 | * Save and restart an expired counter. Called by NMI contexts, |
442 | * so it has to be careful about preempting normal counter ops: | |
7e2ae347 | 443 | */ |
241771ef IM |
444 | static void perf_save_and_restart(struct perf_counter *counter) |
445 | { | |
446 | struct hw_perf_counter *hwc = &counter->hw; | |
447 | int idx = hwc->idx; | |
241771ef | 448 | |
ee06094f IM |
449 | x86_perf_counter_update(counter, hwc, idx); |
450 | __hw_perf_counter_set_period(counter, hwc, idx); | |
7e2ae347 | 451 | |
2f18d1e8 | 452 | if (counter->state == PERF_COUNTER_STATE_ACTIVE) |
eb2b8618 | 453 | __pmc_generic_enable(counter, hwc, idx); |
241771ef IM |
454 | } |
455 | ||
456 | static void | |
04289bb9 | 457 | perf_handle_group(struct perf_counter *sibling, u64 *status, u64 *overflown) |
241771ef | 458 | { |
04289bb9 | 459 | struct perf_counter *counter, *group_leader = sibling->group_leader; |
241771ef | 460 | |
04289bb9 | 461 | /* |
ee06094f | 462 | * Store sibling timestamps (if any): |
04289bb9 IM |
463 | */ |
464 | list_for_each_entry(counter, &group_leader->sibling_list, list_entry) { | |
2f18d1e8 | 465 | |
ee06094f | 466 | x86_perf_counter_update(counter, &counter->hw, counter->hw.idx); |
04289bb9 | 467 | perf_store_irq_data(sibling, counter->hw_event.type); |
ee06094f | 468 | perf_store_irq_data(sibling, atomic64_read(&counter->count)); |
241771ef IM |
469 | } |
470 | } | |
471 | ||
4b39fd96 MG |
472 | /* |
473 | * Maximum interrupt frequency of 100KHz per CPU | |
474 | */ | |
475 | #define PERFMON_MAX_INTERRUPTS 100000/HZ | |
476 | ||
241771ef IM |
477 | /* |
478 | * This handler is triggered by the local APIC, so the APIC IRQ handling | |
479 | * rules apply: | |
480 | */ | |
481 | static void __smp_perf_counter_interrupt(struct pt_regs *regs, int nmi) | |
482 | { | |
483 | int bit, cpu = smp_processor_id(); | |
4b39fd96 | 484 | u64 ack, status; |
1b023a96 | 485 | struct cpu_hw_counters *cpuc = &per_cpu(cpu_hw_counters, cpu); |
43874d23 | 486 | |
1b023a96 | 487 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, cpuc->global_enable); |
241771ef | 488 | |
241771ef | 489 | /* Disable counters globally */ |
862a1a5f | 490 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); |
241771ef IM |
491 | ack_APIC_irq(); |
492 | ||
87b9cf46 IM |
493 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); |
494 | if (!status) | |
495 | goto out; | |
496 | ||
241771ef | 497 | again: |
d278c484 | 498 | inc_irq_stat(apic_perf_irqs); |
241771ef | 499 | ack = status; |
2f18d1e8 | 500 | for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { |
862a1a5f | 501 | struct perf_counter *counter = cpuc->counters[bit]; |
241771ef IM |
502 | |
503 | clear_bit(bit, (unsigned long *) &status); | |
504 | if (!counter) | |
505 | continue; | |
506 | ||
507 | perf_save_and_restart(counter); | |
508 | ||
9f66a381 | 509 | switch (counter->hw_event.record_type) { |
241771ef IM |
510 | case PERF_RECORD_SIMPLE: |
511 | continue; | |
512 | case PERF_RECORD_IRQ: | |
513 | perf_store_irq_data(counter, instruction_pointer(regs)); | |
514 | break; | |
515 | case PERF_RECORD_GROUP: | |
241771ef IM |
516 | perf_handle_group(counter, &status, &ack); |
517 | break; | |
518 | } | |
519 | /* | |
520 | * From NMI context we cannot call into the scheduler to | |
eb2b8618 | 521 | * do a task wakeup - but we mark these generic as |
241771ef IM |
522 | * wakeup_pending and initate a wakeup callback: |
523 | */ | |
524 | if (nmi) { | |
525 | counter->wakeup_pending = 1; | |
526 | set_tsk_thread_flag(current, TIF_PERF_COUNTERS); | |
527 | } else { | |
528 | wake_up(&counter->waitq); | |
529 | } | |
530 | } | |
531 | ||
862a1a5f | 532 | wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); |
241771ef IM |
533 | |
534 | /* | |
535 | * Repeat if there is more work to be done: | |
536 | */ | |
537 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
538 | if (status) | |
539 | goto again; | |
87b9cf46 | 540 | out: |
241771ef | 541 | /* |
1b023a96 | 542 | * Restore - do not reenable when global enable is off or throttled: |
241771ef | 543 | */ |
4b39fd96 | 544 | if (++cpuc->interrupts < PERFMON_MAX_INTERRUPTS) |
1b023a96 MG |
545 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, cpuc->global_enable); |
546 | } | |
547 | ||
548 | void perf_counter_unthrottle(void) | |
549 | { | |
550 | struct cpu_hw_counters *cpuc; | |
4b39fd96 | 551 | u64 global_enable; |
1b023a96 MG |
552 | |
553 | if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) | |
554 | return; | |
555 | ||
556 | if (unlikely(!perf_counters_initialized)) | |
557 | return; | |
558 | ||
559 | cpuc = &per_cpu(cpu_hw_counters, smp_processor_id()); | |
4b39fd96 | 560 | if (cpuc->interrupts >= PERFMON_MAX_INTERRUPTS) { |
1b023a96 | 561 | if (printk_ratelimit()) |
4b39fd96 | 562 | printk(KERN_WARNING "PERFMON: max interrupts exceeded!\n"); |
1b023a96 | 563 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, cpuc->global_enable); |
1b023a96 | 564 | } |
4b39fd96 MG |
565 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, global_enable); |
566 | if (unlikely(cpuc->global_enable && !global_enable)) | |
567 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, cpuc->global_enable); | |
568 | cpuc->interrupts = 0; | |
241771ef IM |
569 | } |
570 | ||
571 | void smp_perf_counter_interrupt(struct pt_regs *regs) | |
572 | { | |
573 | irq_enter(); | |
241771ef IM |
574 | apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR); |
575 | __smp_perf_counter_interrupt(regs, 0); | |
576 | ||
577 | irq_exit(); | |
578 | } | |
579 | ||
580 | /* | |
581 | * This handler is triggered by NMI contexts: | |
582 | */ | |
583 | void perf_counter_notify(struct pt_regs *regs) | |
584 | { | |
585 | struct cpu_hw_counters *cpuc; | |
586 | unsigned long flags; | |
587 | int bit, cpu; | |
588 | ||
589 | local_irq_save(flags); | |
590 | cpu = smp_processor_id(); | |
591 | cpuc = &per_cpu(cpu_hw_counters, cpu); | |
592 | ||
862a1a5f IM |
593 | for_each_bit(bit, cpuc->used, X86_PMC_IDX_MAX) { |
594 | struct perf_counter *counter = cpuc->counters[bit]; | |
241771ef IM |
595 | |
596 | if (!counter) | |
597 | continue; | |
598 | ||
599 | if (counter->wakeup_pending) { | |
600 | counter->wakeup_pending = 0; | |
601 | wake_up(&counter->waitq); | |
602 | } | |
603 | } | |
604 | ||
605 | local_irq_restore(flags); | |
606 | } | |
607 | ||
3415dd91 | 608 | void perf_counters_lapic_init(int nmi) |
241771ef IM |
609 | { |
610 | u32 apic_val; | |
611 | ||
612 | if (!perf_counters_initialized) | |
613 | return; | |
614 | /* | |
615 | * Enable the performance counter vector in the APIC LVT: | |
616 | */ | |
617 | apic_val = apic_read(APIC_LVTERR); | |
618 | ||
619 | apic_write(APIC_LVTERR, apic_val | APIC_LVT_MASKED); | |
620 | if (nmi) | |
621 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
622 | else | |
623 | apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR); | |
624 | apic_write(APIC_LVTERR, apic_val); | |
625 | } | |
626 | ||
627 | static int __kprobes | |
628 | perf_counter_nmi_handler(struct notifier_block *self, | |
629 | unsigned long cmd, void *__args) | |
630 | { | |
631 | struct die_args *args = __args; | |
632 | struct pt_regs *regs; | |
633 | ||
634 | if (likely(cmd != DIE_NMI_IPI)) | |
635 | return NOTIFY_DONE; | |
636 | ||
637 | regs = args->regs; | |
638 | ||
639 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
640 | __smp_perf_counter_interrupt(regs, 1); | |
641 | ||
642 | return NOTIFY_STOP; | |
643 | } | |
644 | ||
645 | static __read_mostly struct notifier_block perf_counter_nmi_notifier = { | |
5b75af0a MG |
646 | .notifier_call = perf_counter_nmi_handler, |
647 | .next = NULL, | |
648 | .priority = 1 | |
241771ef IM |
649 | }; |
650 | ||
651 | void __init init_hw_perf_counters(void) | |
652 | { | |
653 | union cpuid10_eax eax; | |
241771ef | 654 | unsigned int ebx; |
703e937c IM |
655 | unsigned int unused; |
656 | union cpuid10_edx edx; | |
241771ef IM |
657 | |
658 | if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) | |
659 | return; | |
660 | ||
661 | /* | |
662 | * Check whether the Architectural PerfMon supports | |
663 | * Branch Misses Retired Event or not. | |
664 | */ | |
703e937c | 665 | cpuid(10, &eax.full, &ebx, &unused, &edx.full); |
241771ef IM |
666 | if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED) |
667 | return; | |
668 | ||
669 | printk(KERN_INFO "Intel Performance Monitoring support detected.\n"); | |
670 | ||
703e937c IM |
671 | printk(KERN_INFO "... version: %d\n", eax.split.version_id); |
672 | printk(KERN_INFO "... num counters: %d\n", eax.split.num_counters); | |
862a1a5f IM |
673 | nr_counters_generic = eax.split.num_counters; |
674 | if (nr_counters_generic > X86_PMC_MAX_GENERIC) { | |
675 | nr_counters_generic = X86_PMC_MAX_GENERIC; | |
241771ef | 676 | WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!", |
862a1a5f | 677 | nr_counters_generic, X86_PMC_MAX_GENERIC); |
241771ef | 678 | } |
862a1a5f IM |
679 | perf_counter_mask = (1 << nr_counters_generic) - 1; |
680 | perf_max_counters = nr_counters_generic; | |
241771ef | 681 | |
703e937c | 682 | printk(KERN_INFO "... bit width: %d\n", eax.split.bit_width); |
2f18d1e8 IM |
683 | counter_value_mask = (1ULL << eax.split.bit_width) - 1; |
684 | printk(KERN_INFO "... value mask: %016Lx\n", counter_value_mask); | |
685 | ||
703e937c IM |
686 | printk(KERN_INFO "... mask length: %d\n", eax.split.mask_length); |
687 | ||
862a1a5f IM |
688 | nr_counters_fixed = edx.split.num_counters_fixed; |
689 | if (nr_counters_fixed > X86_PMC_MAX_FIXED) { | |
690 | nr_counters_fixed = X86_PMC_MAX_FIXED; | |
703e937c | 691 | WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!", |
862a1a5f | 692 | nr_counters_fixed, X86_PMC_MAX_FIXED); |
703e937c | 693 | } |
862a1a5f IM |
694 | printk(KERN_INFO "... fixed counters: %d\n", nr_counters_fixed); |
695 | ||
696 | perf_counter_mask |= ((1LL << nr_counters_fixed)-1) << X86_PMC_IDX_FIXED; | |
241771ef | 697 | |
862a1a5f | 698 | printk(KERN_INFO "... counter mask: %016Lx\n", perf_counter_mask); |
75f224cf IM |
699 | perf_counters_initialized = true; |
700 | ||
241771ef IM |
701 | perf_counters_lapic_init(0); |
702 | register_die_notifier(&perf_counter_nmi_notifier); | |
241771ef | 703 | } |
621a01ea | 704 | |
eb2b8618 | 705 | static void pmc_generic_read(struct perf_counter *counter) |
ee06094f IM |
706 | { |
707 | x86_perf_counter_update(counter, &counter->hw, counter->hw.idx); | |
708 | } | |
709 | ||
5c92d124 | 710 | static const struct hw_perf_counter_ops x86_perf_counter_ops = { |
7671581f IM |
711 | .enable = pmc_generic_enable, |
712 | .disable = pmc_generic_disable, | |
713 | .read = pmc_generic_read, | |
621a01ea IM |
714 | }; |
715 | ||
5c92d124 IM |
716 | const struct hw_perf_counter_ops * |
717 | hw_perf_counter_init(struct perf_counter *counter) | |
621a01ea IM |
718 | { |
719 | int err; | |
720 | ||
721 | err = __hw_perf_counter_init(counter); | |
722 | if (err) | |
723 | return NULL; | |
724 | ||
725 | return &x86_perf_counter_ops; | |
726 | } |