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241771ef IM |
1 | /* |
2 | * Performance counter x86 architecture code | |
3 | * | |
4 | * Copyright(C) 2008 Thomas Gleixner <tglx@linutronix.de> | |
5 | * Copyright(C) 2008 Red Hat, Inc., Ingo Molnar | |
6 | * | |
7 | * For licencing details see kernel-base/COPYING | |
8 | */ | |
9 | ||
10 | #include <linux/perf_counter.h> | |
11 | #include <linux/capability.h> | |
12 | #include <linux/notifier.h> | |
13 | #include <linux/hardirq.h> | |
14 | #include <linux/kprobes.h> | |
4ac13294 | 15 | #include <linux/module.h> |
241771ef IM |
16 | #include <linux/kdebug.h> |
17 | #include <linux/sched.h> | |
18 | ||
19 | #include <asm/intel_arch_perfmon.h> | |
20 | #include <asm/apic.h> | |
21 | ||
22 | static bool perf_counters_initialized __read_mostly; | |
23 | ||
24 | /* | |
25 | * Number of (generic) HW counters: | |
26 | */ | |
27 | static int nr_hw_counters __read_mostly; | |
28 | static u32 perf_counter_mask __read_mostly; | |
29 | ||
30 | /* No support for fixed function counters yet */ | |
31 | ||
32 | #define MAX_HW_COUNTERS 8 | |
33 | ||
34 | struct cpu_hw_counters { | |
35 | struct perf_counter *counters[MAX_HW_COUNTERS]; | |
36 | unsigned long used[BITS_TO_LONGS(MAX_HW_COUNTERS)]; | |
241771ef IM |
37 | }; |
38 | ||
39 | /* | |
40 | * Intel PerfMon v3. Used on Core2 and later. | |
41 | */ | |
42 | static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters); | |
43 | ||
44 | const int intel_perfmon_event_map[] = | |
45 | { | |
46 | [PERF_COUNT_CYCLES] = 0x003c, | |
47 | [PERF_COUNT_INSTRUCTIONS] = 0x00c0, | |
48 | [PERF_COUNT_CACHE_REFERENCES] = 0x4f2e, | |
49 | [PERF_COUNT_CACHE_MISSES] = 0x412e, | |
50 | [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4, | |
51 | [PERF_COUNT_BRANCH_MISSES] = 0x00c5, | |
52 | }; | |
53 | ||
54 | const int max_intel_perfmon_events = ARRAY_SIZE(intel_perfmon_event_map); | |
55 | ||
56 | /* | |
57 | * Setup the hardware configuration for a given hw_event_type | |
58 | */ | |
dfa7c899 | 59 | int hw_perf_counter_init(struct perf_counter *counter) |
241771ef IM |
60 | { |
61 | struct hw_perf_counter *hwc = &counter->hw; | |
dfa7c899 | 62 | u32 hw_event_type = counter->event.hw_event_type; |
241771ef IM |
63 | |
64 | if (unlikely(!perf_counters_initialized)) | |
65 | return -EINVAL; | |
66 | ||
67 | /* | |
68 | * Count user events, and generate PMC IRQs: | |
69 | * (keep 'enabled' bit clear for now) | |
70 | */ | |
71 | hwc->config = ARCH_PERFMON_EVENTSEL_USR | ARCH_PERFMON_EVENTSEL_INT; | |
72 | ||
73 | /* | |
74 | * If privileged enough, count OS events too, and allow | |
75 | * NMI events as well: | |
76 | */ | |
77 | hwc->nmi = 0; | |
78 | if (capable(CAP_SYS_ADMIN)) { | |
79 | hwc->config |= ARCH_PERFMON_EVENTSEL_OS; | |
80 | if (hw_event_type & PERF_COUNT_NMI) | |
81 | hwc->nmi = 1; | |
82 | } | |
83 | ||
84 | hwc->config_base = MSR_ARCH_PERFMON_EVENTSEL0; | |
85 | hwc->counter_base = MSR_ARCH_PERFMON_PERFCTR0; | |
86 | ||
dfa7c899 | 87 | hwc->irq_period = counter->event.hw_event_period; |
241771ef IM |
88 | /* |
89 | * Intel PMCs cannot be accessed sanely above 32 bit width, | |
90 | * so we install an artificial 1<<31 period regardless of | |
91 | * the generic counter period: | |
92 | */ | |
93 | if (!hwc->irq_period) | |
94 | hwc->irq_period = 0x7FFFFFFF; | |
95 | ||
96 | hwc->next_count = -((s32) hwc->irq_period); | |
97 | ||
98 | /* | |
dfa7c899 | 99 | * Raw event type provide the config in the event structure |
241771ef | 100 | */ |
dfa7c899 TG |
101 | hw_event_type &= ~PERF_COUNT_NMI; |
102 | if (hw_event_type == PERF_COUNT_RAW) { | |
103 | hwc->config |= counter->event.hw_raw_ctrl; | |
241771ef | 104 | } else { |
241771ef IM |
105 | if (hw_event_type >= max_intel_perfmon_events) |
106 | return -EINVAL; | |
107 | /* | |
108 | * The generic map: | |
109 | */ | |
dfa7c899 | 110 | hwc->config |= intel_perfmon_event_map[hw_event_type]; |
241771ef | 111 | } |
241771ef IM |
112 | counter->wakeup_pending = 0; |
113 | ||
114 | return 0; | |
115 | } | |
116 | ||
241771ef IM |
117 | void hw_perf_enable_all(void) |
118 | { | |
43874d23 | 119 | wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, perf_counter_mask, 0); |
241771ef IM |
120 | } |
121 | ||
4ac13294 | 122 | void hw_perf_restore_ctrl(u64 ctrl) |
241771ef | 123 | { |
4ac13294 TG |
124 | wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, ctrl, 0); |
125 | } | |
126 | EXPORT_SYMBOL_GPL(hw_perf_restore_ctrl); | |
127 | ||
128 | u64 hw_perf_disable_all(void) | |
129 | { | |
130 | u64 ctrl; | |
131 | ||
132 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); | |
241771ef | 133 | wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0, 0); |
4ac13294 | 134 | return ctrl; |
241771ef | 135 | } |
4ac13294 | 136 | EXPORT_SYMBOL_GPL(hw_perf_disable_all); |
241771ef | 137 | |
7e2ae347 IM |
138 | static inline void |
139 | __hw_perf_counter_disable(struct hw_perf_counter *hwc, unsigned int idx) | |
140 | { | |
141 | wrmsr(hwc->config_base + idx, hwc->config, 0); | |
142 | } | |
143 | ||
241771ef IM |
144 | static DEFINE_PER_CPU(u64, prev_next_count[MAX_HW_COUNTERS]); |
145 | ||
7e2ae347 | 146 | static void __hw_perf_counter_set_period(struct hw_perf_counter *hwc, int idx) |
241771ef IM |
147 | { |
148 | per_cpu(prev_next_count[idx], smp_processor_id()) = hwc->next_count; | |
149 | ||
150 | wrmsr(hwc->counter_base + idx, hwc->next_count, 0); | |
7e2ae347 IM |
151 | } |
152 | ||
153 | static void __hw_perf_counter_enable(struct hw_perf_counter *hwc, int idx) | |
154 | { | |
155 | wrmsr(hwc->config_base + idx, | |
156 | hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE, 0); | |
241771ef IM |
157 | } |
158 | ||
159 | void hw_perf_counter_enable(struct perf_counter *counter) | |
160 | { | |
161 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
162 | struct hw_perf_counter *hwc = &counter->hw; | |
163 | int idx = hwc->idx; | |
164 | ||
165 | /* Try to get the previous counter again */ | |
166 | if (test_and_set_bit(idx, cpuc->used)) { | |
167 | idx = find_first_zero_bit(cpuc->used, nr_hw_counters); | |
168 | set_bit(idx, cpuc->used); | |
169 | hwc->idx = idx; | |
170 | } | |
171 | ||
172 | perf_counters_lapic_init(hwc->nmi); | |
173 | ||
7e2ae347 | 174 | __hw_perf_counter_disable(hwc, idx); |
241771ef IM |
175 | |
176 | cpuc->counters[idx] = counter; | |
7e2ae347 IM |
177 | |
178 | __hw_perf_counter_set_period(hwc, idx); | |
241771ef IM |
179 | __hw_perf_counter_enable(hwc, idx); |
180 | } | |
181 | ||
182 | #ifdef CONFIG_X86_64 | |
183 | static inline void atomic64_counter_set(struct perf_counter *counter, u64 val) | |
184 | { | |
185 | atomic64_set(&counter->count, val); | |
186 | } | |
187 | ||
188 | static inline u64 atomic64_counter_read(struct perf_counter *counter) | |
189 | { | |
190 | return atomic64_read(&counter->count); | |
191 | } | |
192 | #else | |
193 | /* | |
194 | * Todo: add proper atomic64_t support to 32-bit x86: | |
195 | */ | |
196 | static inline void atomic64_counter_set(struct perf_counter *counter, u64 val64) | |
197 | { | |
198 | u32 *val32 = (void *)&val64; | |
199 | ||
200 | atomic_set(counter->count32 + 0, *(val32 + 0)); | |
201 | atomic_set(counter->count32 + 1, *(val32 + 1)); | |
202 | } | |
203 | ||
204 | static inline u64 atomic64_counter_read(struct perf_counter *counter) | |
205 | { | |
206 | return atomic_read(counter->count32 + 0) | | |
207 | (u64) atomic_read(counter->count32 + 1) << 32; | |
208 | } | |
209 | #endif | |
210 | ||
211 | static void __hw_perf_save_counter(struct perf_counter *counter, | |
212 | struct hw_perf_counter *hwc, int idx) | |
213 | { | |
214 | s64 raw = -1; | |
215 | s64 delta; | |
241771ef IM |
216 | |
217 | /* | |
218 | * Get the raw hw counter value: | |
219 | */ | |
1e125676 | 220 | rdmsrl(hwc->counter_base + idx, raw); |
241771ef IM |
221 | |
222 | /* | |
223 | * Rebase it to zero (it started counting at -irq_period), | |
224 | * to see the delta since ->prev_count: | |
225 | */ | |
226 | delta = (s64)hwc->irq_period + (s64)(s32)raw; | |
227 | ||
228 | atomic64_counter_set(counter, hwc->prev_count + delta); | |
229 | ||
230 | /* | |
231 | * Adjust the ->prev_count offset - if we went beyond | |
232 | * irq_period of units, then we got an IRQ and the counter | |
233 | * was set back to -irq_period: | |
234 | */ | |
235 | while (delta >= (s64)hwc->irq_period) { | |
236 | hwc->prev_count += hwc->irq_period; | |
237 | delta -= (s64)hwc->irq_period; | |
238 | } | |
239 | ||
240 | /* | |
241 | * Calculate the next raw counter value we'll write into | |
242 | * the counter at the next sched-in time: | |
243 | */ | |
244 | delta -= (s64)hwc->irq_period; | |
245 | ||
246 | hwc->next_count = (s32)delta; | |
247 | } | |
248 | ||
249 | void perf_counter_print_debug(void) | |
250 | { | |
251 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, next_count; | |
1e125676 IM |
252 | int cpu, idx; |
253 | ||
254 | if (!nr_hw_counters) | |
255 | return; | |
241771ef IM |
256 | |
257 | local_irq_disable(); | |
258 | ||
259 | cpu = smp_processor_id(); | |
260 | ||
1e125676 IM |
261 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
262 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
263 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
241771ef IM |
264 | |
265 | printk(KERN_INFO "\n"); | |
266 | printk(KERN_INFO "CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
267 | printk(KERN_INFO "CPU#%d: status: %016llx\n", cpu, status); | |
268 | printk(KERN_INFO "CPU#%d: overflow: %016llx\n", cpu, overflow); | |
269 | ||
270 | for (idx = 0; idx < nr_hw_counters; idx++) { | |
1e125676 IM |
271 | rdmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + idx, pmc_ctrl); |
272 | rdmsrl(MSR_ARCH_PERFMON_PERFCTR0 + idx, pmc_count); | |
241771ef IM |
273 | |
274 | next_count = per_cpu(prev_next_count[idx], cpu); | |
275 | ||
276 | printk(KERN_INFO "CPU#%d: PMC%d ctrl: %016llx\n", | |
277 | cpu, idx, pmc_ctrl); | |
278 | printk(KERN_INFO "CPU#%d: PMC%d count: %016llx\n", | |
279 | cpu, idx, pmc_count); | |
280 | printk(KERN_INFO "CPU#%d: PMC%d next: %016llx\n", | |
281 | cpu, idx, next_count); | |
282 | } | |
283 | local_irq_enable(); | |
284 | } | |
285 | ||
286 | void hw_perf_counter_disable(struct perf_counter *counter) | |
287 | { | |
288 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
289 | struct hw_perf_counter *hwc = &counter->hw; | |
290 | unsigned int idx = hwc->idx; | |
291 | ||
7e2ae347 | 292 | __hw_perf_counter_disable(hwc, idx); |
241771ef IM |
293 | |
294 | clear_bit(idx, cpuc->used); | |
295 | cpuc->counters[idx] = NULL; | |
296 | __hw_perf_save_counter(counter, hwc, idx); | |
297 | } | |
298 | ||
299 | void hw_perf_counter_read(struct perf_counter *counter) | |
300 | { | |
301 | struct hw_perf_counter *hwc = &counter->hw; | |
302 | unsigned long addr = hwc->counter_base + hwc->idx; | |
303 | s64 offs, val = -1LL; | |
304 | s32 val32; | |
241771ef IM |
305 | |
306 | /* Careful: NMI might modify the counter offset */ | |
307 | do { | |
308 | offs = hwc->prev_count; | |
1e125676 | 309 | rdmsrl(addr, val); |
241771ef IM |
310 | } while (offs != hwc->prev_count); |
311 | ||
312 | val32 = (s32) val; | |
313 | val = (s64)hwc->irq_period + (s64)val32; | |
314 | atomic64_counter_set(counter, hwc->prev_count + val); | |
315 | } | |
316 | ||
317 | static void perf_store_irq_data(struct perf_counter *counter, u64 data) | |
318 | { | |
319 | struct perf_data *irqdata = counter->irqdata; | |
320 | ||
321 | if (irqdata->len > PERF_DATA_BUFLEN - sizeof(u64)) { | |
322 | irqdata->overrun++; | |
323 | } else { | |
324 | u64 *p = (u64 *) &irqdata->data[irqdata->len]; | |
325 | ||
326 | *p = data; | |
327 | irqdata->len += sizeof(u64); | |
328 | } | |
329 | } | |
330 | ||
7e2ae347 IM |
331 | /* |
332 | * NMI-safe enable method: | |
333 | */ | |
241771ef IM |
334 | static void perf_save_and_restart(struct perf_counter *counter) |
335 | { | |
336 | struct hw_perf_counter *hwc = &counter->hw; | |
337 | int idx = hwc->idx; | |
7e2ae347 | 338 | u64 pmc_ctrl; |
241771ef | 339 | |
1e125676 | 340 | rdmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + idx, pmc_ctrl); |
241771ef | 341 | |
7e2ae347 IM |
342 | __hw_perf_save_counter(counter, hwc, idx); |
343 | __hw_perf_counter_set_period(hwc, idx); | |
344 | ||
345 | if (pmc_ctrl & ARCH_PERFMON_EVENTSEL0_ENABLE) | |
241771ef | 346 | __hw_perf_counter_enable(hwc, idx); |
241771ef IM |
347 | } |
348 | ||
349 | static void | |
350 | perf_handle_group(struct perf_counter *leader, u64 *status, u64 *overflown) | |
351 | { | |
352 | struct perf_counter_context *ctx = leader->ctx; | |
353 | struct perf_counter *counter; | |
354 | int bit; | |
355 | ||
356 | list_for_each_entry(counter, &ctx->counters, list) { | |
357 | if (counter->record_type != PERF_RECORD_SIMPLE || | |
358 | counter == leader) | |
359 | continue; | |
360 | ||
361 | if (counter->active) { | |
362 | /* | |
363 | * When counter was not in the overflow mask, we have to | |
364 | * read it from hardware. We read it as well, when it | |
365 | * has not been read yet and clear the bit in the | |
366 | * status mask. | |
367 | */ | |
368 | bit = counter->hw.idx; | |
369 | if (!test_bit(bit, (unsigned long *) overflown) || | |
370 | test_bit(bit, (unsigned long *) status)) { | |
371 | clear_bit(bit, (unsigned long *) status); | |
372 | perf_save_and_restart(counter); | |
373 | } | |
374 | } | |
dfa7c899 | 375 | perf_store_irq_data(leader, counter->event.hw_event_type); |
241771ef IM |
376 | perf_store_irq_data(leader, atomic64_counter_read(counter)); |
377 | } | |
378 | } | |
379 | ||
380 | /* | |
381 | * This handler is triggered by the local APIC, so the APIC IRQ handling | |
382 | * rules apply: | |
383 | */ | |
384 | static void __smp_perf_counter_interrupt(struct pt_regs *regs, int nmi) | |
385 | { | |
386 | int bit, cpu = smp_processor_id(); | |
43874d23 | 387 | u64 ack, status, saved_global; |
241771ef | 388 | struct cpu_hw_counters *cpuc; |
43874d23 IM |
389 | |
390 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, saved_global); | |
241771ef | 391 | |
241771ef IM |
392 | /* Disable counters globally */ |
393 | wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0, 0); | |
394 | ack_APIC_irq(); | |
395 | ||
396 | cpuc = &per_cpu(cpu_hw_counters, cpu); | |
397 | ||
87b9cf46 IM |
398 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); |
399 | if (!status) | |
400 | goto out; | |
401 | ||
241771ef IM |
402 | again: |
403 | ack = status; | |
404 | for_each_bit(bit, (unsigned long *) &status, nr_hw_counters) { | |
405 | struct perf_counter *counter = cpuc->counters[bit]; | |
406 | ||
407 | clear_bit(bit, (unsigned long *) &status); | |
408 | if (!counter) | |
409 | continue; | |
410 | ||
411 | perf_save_and_restart(counter); | |
412 | ||
413 | switch (counter->record_type) { | |
414 | case PERF_RECORD_SIMPLE: | |
415 | continue; | |
416 | case PERF_RECORD_IRQ: | |
417 | perf_store_irq_data(counter, instruction_pointer(regs)); | |
418 | break; | |
419 | case PERF_RECORD_GROUP: | |
dfa7c899 TG |
420 | perf_store_irq_data(counter, |
421 | counter->event.hw_event_type); | |
241771ef IM |
422 | perf_store_irq_data(counter, |
423 | atomic64_counter_read(counter)); | |
424 | perf_handle_group(counter, &status, &ack); | |
425 | break; | |
426 | } | |
427 | /* | |
428 | * From NMI context we cannot call into the scheduler to | |
429 | * do a task wakeup - but we mark these counters as | |
430 | * wakeup_pending and initate a wakeup callback: | |
431 | */ | |
432 | if (nmi) { | |
433 | counter->wakeup_pending = 1; | |
434 | set_tsk_thread_flag(current, TIF_PERF_COUNTERS); | |
435 | } else { | |
436 | wake_up(&counter->waitq); | |
437 | } | |
438 | } | |
439 | ||
440 | wrmsr(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack, 0); | |
441 | ||
442 | /* | |
443 | * Repeat if there is more work to be done: | |
444 | */ | |
445 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
446 | if (status) | |
447 | goto again; | |
87b9cf46 | 448 | out: |
241771ef | 449 | /* |
43874d23 | 450 | * Restore - do not reenable when global enable is off: |
241771ef | 451 | */ |
43874d23 | 452 | wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, saved_global, 0); |
241771ef IM |
453 | } |
454 | ||
455 | void smp_perf_counter_interrupt(struct pt_regs *regs) | |
456 | { | |
457 | irq_enter(); | |
458 | #ifdef CONFIG_X86_64 | |
459 | add_pda(apic_perf_irqs, 1); | |
460 | #else | |
461 | per_cpu(irq_stat, smp_processor_id()).apic_perf_irqs++; | |
462 | #endif | |
463 | apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR); | |
464 | __smp_perf_counter_interrupt(regs, 0); | |
465 | ||
466 | irq_exit(); | |
467 | } | |
468 | ||
469 | /* | |
470 | * This handler is triggered by NMI contexts: | |
471 | */ | |
472 | void perf_counter_notify(struct pt_regs *regs) | |
473 | { | |
474 | struct cpu_hw_counters *cpuc; | |
475 | unsigned long flags; | |
476 | int bit, cpu; | |
477 | ||
478 | local_irq_save(flags); | |
479 | cpu = smp_processor_id(); | |
480 | cpuc = &per_cpu(cpu_hw_counters, cpu); | |
481 | ||
482 | for_each_bit(bit, cpuc->used, nr_hw_counters) { | |
483 | struct perf_counter *counter = cpuc->counters[bit]; | |
484 | ||
485 | if (!counter) | |
486 | continue; | |
487 | ||
488 | if (counter->wakeup_pending) { | |
489 | counter->wakeup_pending = 0; | |
490 | wake_up(&counter->waitq); | |
491 | } | |
492 | } | |
493 | ||
494 | local_irq_restore(flags); | |
495 | } | |
496 | ||
497 | void __cpuinit perf_counters_lapic_init(int nmi) | |
498 | { | |
499 | u32 apic_val; | |
500 | ||
501 | if (!perf_counters_initialized) | |
502 | return; | |
503 | /* | |
504 | * Enable the performance counter vector in the APIC LVT: | |
505 | */ | |
506 | apic_val = apic_read(APIC_LVTERR); | |
507 | ||
508 | apic_write(APIC_LVTERR, apic_val | APIC_LVT_MASKED); | |
509 | if (nmi) | |
510 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
511 | else | |
512 | apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR); | |
513 | apic_write(APIC_LVTERR, apic_val); | |
514 | } | |
515 | ||
516 | static int __kprobes | |
517 | perf_counter_nmi_handler(struct notifier_block *self, | |
518 | unsigned long cmd, void *__args) | |
519 | { | |
520 | struct die_args *args = __args; | |
521 | struct pt_regs *regs; | |
522 | ||
523 | if (likely(cmd != DIE_NMI_IPI)) | |
524 | return NOTIFY_DONE; | |
525 | ||
526 | regs = args->regs; | |
527 | ||
528 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
529 | __smp_perf_counter_interrupt(regs, 1); | |
530 | ||
531 | return NOTIFY_STOP; | |
532 | } | |
533 | ||
534 | static __read_mostly struct notifier_block perf_counter_nmi_notifier = { | |
535 | .notifier_call = perf_counter_nmi_handler | |
536 | }; | |
537 | ||
538 | void __init init_hw_perf_counters(void) | |
539 | { | |
540 | union cpuid10_eax eax; | |
541 | unsigned int unused; | |
542 | unsigned int ebx; | |
543 | ||
544 | if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) | |
545 | return; | |
546 | ||
547 | /* | |
548 | * Check whether the Architectural PerfMon supports | |
549 | * Branch Misses Retired Event or not. | |
550 | */ | |
551 | cpuid(10, &(eax.full), &ebx, &unused, &unused); | |
552 | if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED) | |
553 | return; | |
554 | ||
555 | printk(KERN_INFO "Intel Performance Monitoring support detected.\n"); | |
556 | ||
557 | printk(KERN_INFO "... version: %d\n", eax.split.version_id); | |
558 | printk(KERN_INFO "... num_counters: %d\n", eax.split.num_counters); | |
559 | nr_hw_counters = eax.split.num_counters; | |
560 | if (nr_hw_counters > MAX_HW_COUNTERS) { | |
561 | nr_hw_counters = MAX_HW_COUNTERS; | |
562 | WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!", | |
563 | nr_hw_counters, MAX_HW_COUNTERS); | |
564 | } | |
565 | perf_counter_mask = (1 << nr_hw_counters) - 1; | |
566 | perf_max_counters = nr_hw_counters; | |
567 | ||
568 | printk(KERN_INFO "... bit_width: %d\n", eax.split.bit_width); | |
569 | printk(KERN_INFO "... mask_length: %d\n", eax.split.mask_length); | |
570 | ||
571 | perf_counters_lapic_init(0); | |
572 | register_die_notifier(&perf_counter_nmi_notifier); | |
573 | ||
574 | perf_counters_initialized = true; | |
575 | } |