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241771ef IM |
1 | /* |
2 | * Performance counter x86 architecture code | |
3 | * | |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
241771ef IM |
10 | * |
11 | * For licencing details see kernel-base/COPYING | |
12 | */ | |
13 | ||
14 | #include <linux/perf_counter.h> | |
15 | #include <linux/capability.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/hardirq.h> | |
18 | #include <linux/kprobes.h> | |
4ac13294 | 19 | #include <linux/module.h> |
241771ef IM |
20 | #include <linux/kdebug.h> |
21 | #include <linux/sched.h> | |
d7d59fb3 | 22 | #include <linux/uaccess.h> |
74193ef0 | 23 | #include <linux/highmem.h> |
30dd568c | 24 | #include <linux/cpu.h> |
241771ef | 25 | |
241771ef | 26 | #include <asm/apic.h> |
d7d59fb3 | 27 | #include <asm/stacktrace.h> |
4e935e47 | 28 | #include <asm/nmi.h> |
241771ef | 29 | |
862a1a5f | 30 | static u64 perf_counter_mask __read_mostly; |
703e937c | 31 | |
30dd568c MM |
32 | /* The maximal number of PEBS counters: */ |
33 | #define MAX_PEBS_COUNTERS 4 | |
34 | ||
35 | /* The size of a BTS record in bytes: */ | |
36 | #define BTS_RECORD_SIZE 24 | |
37 | ||
38 | /* The size of a per-cpu BTS buffer in bytes: */ | |
5622f295 | 39 | #define BTS_BUFFER_SIZE (BTS_RECORD_SIZE * 2048) |
30dd568c MM |
40 | |
41 | /* The BTS overflow threshold in bytes from the end of the buffer: */ | |
5622f295 | 42 | #define BTS_OVFL_TH (BTS_RECORD_SIZE * 128) |
30dd568c MM |
43 | |
44 | ||
45 | /* | |
46 | * Bits in the debugctlmsr controlling branch tracing. | |
47 | */ | |
48 | #define X86_DEBUGCTL_TR (1 << 6) | |
49 | #define X86_DEBUGCTL_BTS (1 << 7) | |
50 | #define X86_DEBUGCTL_BTINT (1 << 8) | |
51 | #define X86_DEBUGCTL_BTS_OFF_OS (1 << 9) | |
52 | #define X86_DEBUGCTL_BTS_OFF_USR (1 << 10) | |
53 | ||
54 | /* | |
55 | * A debug store configuration. | |
56 | * | |
57 | * We only support architectures that use 64bit fields. | |
58 | */ | |
59 | struct debug_store { | |
60 | u64 bts_buffer_base; | |
61 | u64 bts_index; | |
62 | u64 bts_absolute_maximum; | |
63 | u64 bts_interrupt_threshold; | |
64 | u64 pebs_buffer_base; | |
65 | u64 pebs_index; | |
66 | u64 pebs_absolute_maximum; | |
67 | u64 pebs_interrupt_threshold; | |
68 | u64 pebs_counter_reset[MAX_PEBS_COUNTERS]; | |
69 | }; | |
70 | ||
241771ef | 71 | struct cpu_hw_counters { |
862a1a5f | 72 | struct perf_counter *counters[X86_PMC_IDX_MAX]; |
43f6201a RR |
73 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
74 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
4b39fd96 | 75 | unsigned long interrupts; |
b0f3f28e | 76 | int enabled; |
30dd568c | 77 | struct debug_store *ds; |
241771ef IM |
78 | }; |
79 | ||
80 | /* | |
5f4ec28f | 81 | * struct x86_pmu - generic x86 pmu |
241771ef | 82 | */ |
5f4ec28f | 83 | struct x86_pmu { |
faa28ae0 RR |
84 | const char *name; |
85 | int version; | |
a3288106 | 86 | int (*handle_irq)(struct pt_regs *); |
9e35ad38 PZ |
87 | void (*disable_all)(void); |
88 | void (*enable_all)(void); | |
7c90cc45 | 89 | void (*enable)(struct hw_perf_counter *, int); |
d4369891 | 90 | void (*disable)(struct hw_perf_counter *, int); |
169e41eb JSR |
91 | unsigned eventsel; |
92 | unsigned perfctr; | |
b0f3f28e PZ |
93 | u64 (*event_map)(int); |
94 | u64 (*raw_event)(u64); | |
169e41eb | 95 | int max_events; |
0933e5c6 RR |
96 | int num_counters; |
97 | int num_counters_fixed; | |
98 | int counter_bits; | |
99 | u64 counter_mask; | |
04da8a43 | 100 | int apic; |
c619b8ff | 101 | u64 max_period; |
9e35ad38 | 102 | u64 intel_ctrl; |
30dd568c MM |
103 | void (*enable_bts)(u64 config); |
104 | void (*disable_bts)(void); | |
b56a3802 JSR |
105 | }; |
106 | ||
4a06bd85 | 107 | static struct x86_pmu x86_pmu __read_mostly; |
b56a3802 | 108 | |
b0f3f28e PZ |
109 | static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = { |
110 | .enabled = 1, | |
111 | }; | |
241771ef | 112 | |
11d1578f VW |
113 | /* |
114 | * Not sure about some of these | |
115 | */ | |
116 | static const u64 p6_perfmon_event_map[] = | |
117 | { | |
118 | [PERF_COUNT_HW_CPU_CYCLES] = 0x0079, | |
119 | [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, | |
f64ccccb IM |
120 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0f2e, |
121 | [PERF_COUNT_HW_CACHE_MISSES] = 0x012e, | |
11d1578f VW |
122 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, |
123 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, | |
124 | [PERF_COUNT_HW_BUS_CYCLES] = 0x0062, | |
125 | }; | |
126 | ||
dfc65094 | 127 | static u64 p6_pmu_event_map(int hw_event) |
11d1578f | 128 | { |
dfc65094 | 129 | return p6_perfmon_event_map[hw_event]; |
11d1578f VW |
130 | } |
131 | ||
9c74fb50 PZ |
132 | /* |
133 | * Counter setting that is specified not to count anything. | |
134 | * We use this to effectively disable a counter. | |
135 | * | |
136 | * L2_RQSTS with 0 MESI unit mask. | |
137 | */ | |
138 | #define P6_NOP_COUNTER 0x0000002EULL | |
139 | ||
dfc65094 | 140 | static u64 p6_pmu_raw_event(u64 hw_event) |
11d1578f VW |
141 | { |
142 | #define P6_EVNTSEL_EVENT_MASK 0x000000FFULL | |
143 | #define P6_EVNTSEL_UNIT_MASK 0x0000FF00ULL | |
144 | #define P6_EVNTSEL_EDGE_MASK 0x00040000ULL | |
145 | #define P6_EVNTSEL_INV_MASK 0x00800000ULL | |
146 | #define P6_EVNTSEL_COUNTER_MASK 0xFF000000ULL | |
147 | ||
148 | #define P6_EVNTSEL_MASK \ | |
149 | (P6_EVNTSEL_EVENT_MASK | \ | |
150 | P6_EVNTSEL_UNIT_MASK | \ | |
151 | P6_EVNTSEL_EDGE_MASK | \ | |
152 | P6_EVNTSEL_INV_MASK | \ | |
153 | P6_EVNTSEL_COUNTER_MASK) | |
154 | ||
dfc65094 | 155 | return hw_event & P6_EVNTSEL_MASK; |
11d1578f VW |
156 | } |
157 | ||
158 | ||
b56a3802 JSR |
159 | /* |
160 | * Intel PerfMon v3. Used on Core2 and later. | |
161 | */ | |
b0f3f28e | 162 | static const u64 intel_perfmon_event_map[] = |
241771ef | 163 | { |
f4dbfa8f PZ |
164 | [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, |
165 | [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, | |
166 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, | |
167 | [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, | |
168 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, | |
169 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, | |
170 | [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, | |
241771ef IM |
171 | }; |
172 | ||
dfc65094 | 173 | static u64 intel_pmu_event_map(int hw_event) |
b56a3802 | 174 | { |
dfc65094 | 175 | return intel_perfmon_event_map[hw_event]; |
b56a3802 | 176 | } |
241771ef | 177 | |
8326f44d | 178 | /* |
dfc65094 | 179 | * Generalized hw caching related hw_event table, filled |
8326f44d | 180 | * in on a per model basis. A value of 0 means |
dfc65094 IM |
181 | * 'not supported', -1 means 'hw_event makes no sense on |
182 | * this CPU', any other value means the raw hw_event | |
8326f44d IM |
183 | * ID. |
184 | */ | |
185 | ||
186 | #define C(x) PERF_COUNT_HW_CACHE_##x | |
187 | ||
188 | static u64 __read_mostly hw_cache_event_ids | |
189 | [PERF_COUNT_HW_CACHE_MAX] | |
190 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
191 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
192 | ||
193 | static const u64 nehalem_hw_cache_event_ids | |
194 | [PERF_COUNT_HW_CACHE_MAX] | |
195 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
196 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
197 | { | |
198 | [ C(L1D) ] = { | |
199 | [ C(OP_READ) ] = { | |
200 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ | |
201 | [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ | |
202 | }, | |
203 | [ C(OP_WRITE) ] = { | |
204 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ | |
205 | [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ | |
206 | }, | |
207 | [ C(OP_PREFETCH) ] = { | |
208 | [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ | |
209 | [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ | |
210 | }, | |
211 | }, | |
212 | [ C(L1I ) ] = { | |
213 | [ C(OP_READ) ] = { | |
fecc8ac8 | 214 | [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ |
8326f44d IM |
215 | [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ |
216 | }, | |
217 | [ C(OP_WRITE) ] = { | |
218 | [ C(RESULT_ACCESS) ] = -1, | |
219 | [ C(RESULT_MISS) ] = -1, | |
220 | }, | |
221 | [ C(OP_PREFETCH) ] = { | |
222 | [ C(RESULT_ACCESS) ] = 0x0, | |
223 | [ C(RESULT_MISS) ] = 0x0, | |
224 | }, | |
225 | }, | |
8be6e8f3 | 226 | [ C(LL ) ] = { |
8326f44d IM |
227 | [ C(OP_READ) ] = { |
228 | [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS */ | |
229 | [ C(RESULT_MISS) ] = 0x0224, /* L2_RQSTS.LD_MISS */ | |
230 | }, | |
231 | [ C(OP_WRITE) ] = { | |
232 | [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS */ | |
233 | [ C(RESULT_MISS) ] = 0x0824, /* L2_RQSTS.RFO_MISS */ | |
234 | }, | |
235 | [ C(OP_PREFETCH) ] = { | |
8be6e8f3 PZ |
236 | [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference */ |
237 | [ C(RESULT_MISS) ] = 0x412e, /* LLC Misses */ | |
8326f44d IM |
238 | }, |
239 | }, | |
240 | [ C(DTLB) ] = { | |
241 | [ C(OP_READ) ] = { | |
242 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ | |
243 | [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ | |
244 | }, | |
245 | [ C(OP_WRITE) ] = { | |
246 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ | |
247 | [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ | |
248 | }, | |
249 | [ C(OP_PREFETCH) ] = { | |
250 | [ C(RESULT_ACCESS) ] = 0x0, | |
251 | [ C(RESULT_MISS) ] = 0x0, | |
252 | }, | |
253 | }, | |
254 | [ C(ITLB) ] = { | |
255 | [ C(OP_READ) ] = { | |
256 | [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ | |
fecc8ac8 | 257 | [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ |
8326f44d IM |
258 | }, |
259 | [ C(OP_WRITE) ] = { | |
260 | [ C(RESULT_ACCESS) ] = -1, | |
261 | [ C(RESULT_MISS) ] = -1, | |
262 | }, | |
263 | [ C(OP_PREFETCH) ] = { | |
264 | [ C(RESULT_ACCESS) ] = -1, | |
265 | [ C(RESULT_MISS) ] = -1, | |
266 | }, | |
267 | }, | |
268 | [ C(BPU ) ] = { | |
269 | [ C(OP_READ) ] = { | |
270 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ | |
271 | [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ | |
272 | }, | |
273 | [ C(OP_WRITE) ] = { | |
274 | [ C(RESULT_ACCESS) ] = -1, | |
275 | [ C(RESULT_MISS) ] = -1, | |
276 | }, | |
277 | [ C(OP_PREFETCH) ] = { | |
278 | [ C(RESULT_ACCESS) ] = -1, | |
279 | [ C(RESULT_MISS) ] = -1, | |
280 | }, | |
281 | }, | |
282 | }; | |
283 | ||
284 | static const u64 core2_hw_cache_event_ids | |
285 | [PERF_COUNT_HW_CACHE_MAX] | |
286 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
287 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
288 | { | |
0312af84 TG |
289 | [ C(L1D) ] = { |
290 | [ C(OP_READ) ] = { | |
291 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ | |
292 | [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ | |
293 | }, | |
294 | [ C(OP_WRITE) ] = { | |
295 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ | |
296 | [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ | |
297 | }, | |
298 | [ C(OP_PREFETCH) ] = { | |
299 | [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ | |
300 | [ C(RESULT_MISS) ] = 0, | |
301 | }, | |
302 | }, | |
303 | [ C(L1I ) ] = { | |
304 | [ C(OP_READ) ] = { | |
305 | [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ | |
306 | [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ | |
307 | }, | |
308 | [ C(OP_WRITE) ] = { | |
309 | [ C(RESULT_ACCESS) ] = -1, | |
310 | [ C(RESULT_MISS) ] = -1, | |
311 | }, | |
312 | [ C(OP_PREFETCH) ] = { | |
313 | [ C(RESULT_ACCESS) ] = 0, | |
314 | [ C(RESULT_MISS) ] = 0, | |
315 | }, | |
316 | }, | |
8be6e8f3 | 317 | [ C(LL ) ] = { |
0312af84 TG |
318 | [ C(OP_READ) ] = { |
319 | [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ | |
320 | [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ | |
321 | }, | |
322 | [ C(OP_WRITE) ] = { | |
323 | [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ | |
324 | [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ | |
325 | }, | |
326 | [ C(OP_PREFETCH) ] = { | |
327 | [ C(RESULT_ACCESS) ] = 0, | |
328 | [ C(RESULT_MISS) ] = 0, | |
329 | }, | |
330 | }, | |
331 | [ C(DTLB) ] = { | |
332 | [ C(OP_READ) ] = { | |
333 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ | |
334 | [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ | |
335 | }, | |
336 | [ C(OP_WRITE) ] = { | |
337 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ | |
338 | [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ | |
339 | }, | |
340 | [ C(OP_PREFETCH) ] = { | |
341 | [ C(RESULT_ACCESS) ] = 0, | |
342 | [ C(RESULT_MISS) ] = 0, | |
343 | }, | |
344 | }, | |
345 | [ C(ITLB) ] = { | |
346 | [ C(OP_READ) ] = { | |
347 | [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ | |
348 | [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ | |
349 | }, | |
350 | [ C(OP_WRITE) ] = { | |
351 | [ C(RESULT_ACCESS) ] = -1, | |
352 | [ C(RESULT_MISS) ] = -1, | |
353 | }, | |
354 | [ C(OP_PREFETCH) ] = { | |
355 | [ C(RESULT_ACCESS) ] = -1, | |
356 | [ C(RESULT_MISS) ] = -1, | |
357 | }, | |
358 | }, | |
359 | [ C(BPU ) ] = { | |
360 | [ C(OP_READ) ] = { | |
361 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ | |
362 | [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ | |
363 | }, | |
364 | [ C(OP_WRITE) ] = { | |
365 | [ C(RESULT_ACCESS) ] = -1, | |
366 | [ C(RESULT_MISS) ] = -1, | |
367 | }, | |
368 | [ C(OP_PREFETCH) ] = { | |
369 | [ C(RESULT_ACCESS) ] = -1, | |
370 | [ C(RESULT_MISS) ] = -1, | |
371 | }, | |
372 | }, | |
8326f44d IM |
373 | }; |
374 | ||
375 | static const u64 atom_hw_cache_event_ids | |
376 | [PERF_COUNT_HW_CACHE_MAX] | |
377 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
378 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
379 | { | |
ad689220 TG |
380 | [ C(L1D) ] = { |
381 | [ C(OP_READ) ] = { | |
382 | [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ | |
383 | [ C(RESULT_MISS) ] = 0, | |
384 | }, | |
385 | [ C(OP_WRITE) ] = { | |
fecc8ac8 | 386 | [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ |
ad689220 TG |
387 | [ C(RESULT_MISS) ] = 0, |
388 | }, | |
389 | [ C(OP_PREFETCH) ] = { | |
390 | [ C(RESULT_ACCESS) ] = 0x0, | |
391 | [ C(RESULT_MISS) ] = 0, | |
392 | }, | |
393 | }, | |
394 | [ C(L1I ) ] = { | |
395 | [ C(OP_READ) ] = { | |
fecc8ac8 YW |
396 | [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ |
397 | [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ | |
ad689220 TG |
398 | }, |
399 | [ C(OP_WRITE) ] = { | |
400 | [ C(RESULT_ACCESS) ] = -1, | |
401 | [ C(RESULT_MISS) ] = -1, | |
402 | }, | |
403 | [ C(OP_PREFETCH) ] = { | |
404 | [ C(RESULT_ACCESS) ] = 0, | |
405 | [ C(RESULT_MISS) ] = 0, | |
406 | }, | |
407 | }, | |
8be6e8f3 | 408 | [ C(LL ) ] = { |
ad689220 TG |
409 | [ C(OP_READ) ] = { |
410 | [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ | |
411 | [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ | |
412 | }, | |
413 | [ C(OP_WRITE) ] = { | |
414 | [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ | |
415 | [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ | |
416 | }, | |
417 | [ C(OP_PREFETCH) ] = { | |
418 | [ C(RESULT_ACCESS) ] = 0, | |
419 | [ C(RESULT_MISS) ] = 0, | |
420 | }, | |
421 | }, | |
422 | [ C(DTLB) ] = { | |
423 | [ C(OP_READ) ] = { | |
fecc8ac8 | 424 | [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ |
ad689220 TG |
425 | [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ |
426 | }, | |
427 | [ C(OP_WRITE) ] = { | |
fecc8ac8 | 428 | [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ |
ad689220 TG |
429 | [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ |
430 | }, | |
431 | [ C(OP_PREFETCH) ] = { | |
432 | [ C(RESULT_ACCESS) ] = 0, | |
433 | [ C(RESULT_MISS) ] = 0, | |
434 | }, | |
435 | }, | |
436 | [ C(ITLB) ] = { | |
437 | [ C(OP_READ) ] = { | |
438 | [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ | |
439 | [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ | |
440 | }, | |
441 | [ C(OP_WRITE) ] = { | |
442 | [ C(RESULT_ACCESS) ] = -1, | |
443 | [ C(RESULT_MISS) ] = -1, | |
444 | }, | |
445 | [ C(OP_PREFETCH) ] = { | |
446 | [ C(RESULT_ACCESS) ] = -1, | |
447 | [ C(RESULT_MISS) ] = -1, | |
448 | }, | |
449 | }, | |
450 | [ C(BPU ) ] = { | |
451 | [ C(OP_READ) ] = { | |
452 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ | |
453 | [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ | |
454 | }, | |
455 | [ C(OP_WRITE) ] = { | |
456 | [ C(RESULT_ACCESS) ] = -1, | |
457 | [ C(RESULT_MISS) ] = -1, | |
458 | }, | |
459 | [ C(OP_PREFETCH) ] = { | |
460 | [ C(RESULT_ACCESS) ] = -1, | |
461 | [ C(RESULT_MISS) ] = -1, | |
462 | }, | |
463 | }, | |
8326f44d IM |
464 | }; |
465 | ||
dfc65094 | 466 | static u64 intel_pmu_raw_event(u64 hw_event) |
b0f3f28e | 467 | { |
82bae4f8 PZ |
468 | #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL |
469 | #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL | |
ff99be57 PZ |
470 | #define CORE_EVNTSEL_EDGE_MASK 0x00040000ULL |
471 | #define CORE_EVNTSEL_INV_MASK 0x00800000ULL | |
82bae4f8 | 472 | #define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL |
b0f3f28e | 473 | |
128f048f | 474 | #define CORE_EVNTSEL_MASK \ |
b0f3f28e PZ |
475 | (CORE_EVNTSEL_EVENT_MASK | \ |
476 | CORE_EVNTSEL_UNIT_MASK | \ | |
ff99be57 PZ |
477 | CORE_EVNTSEL_EDGE_MASK | \ |
478 | CORE_EVNTSEL_INV_MASK | \ | |
b0f3f28e PZ |
479 | CORE_EVNTSEL_COUNTER_MASK) |
480 | ||
dfc65094 | 481 | return hw_event & CORE_EVNTSEL_MASK; |
b0f3f28e PZ |
482 | } |
483 | ||
f4db43a3 | 484 | static const u64 amd_hw_cache_event_ids |
f86748e9 TG |
485 | [PERF_COUNT_HW_CACHE_MAX] |
486 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
487 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
488 | { | |
489 | [ C(L1D) ] = { | |
490 | [ C(OP_READ) ] = { | |
f4db43a3 JSR |
491 | [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */ |
492 | [ C(RESULT_MISS) ] = 0x0041, /* Data Cache Misses */ | |
f86748e9 TG |
493 | }, |
494 | [ C(OP_WRITE) ] = { | |
d9f2a5ec | 495 | [ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */ |
f86748e9 TG |
496 | [ C(RESULT_MISS) ] = 0, |
497 | }, | |
498 | [ C(OP_PREFETCH) ] = { | |
f4db43a3 JSR |
499 | [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */ |
500 | [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */ | |
f86748e9 TG |
501 | }, |
502 | }, | |
503 | [ C(L1I ) ] = { | |
504 | [ C(OP_READ) ] = { | |
505 | [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches */ | |
506 | [ C(RESULT_MISS) ] = 0x0081, /* Instruction cache misses */ | |
507 | }, | |
508 | [ C(OP_WRITE) ] = { | |
509 | [ C(RESULT_ACCESS) ] = -1, | |
510 | [ C(RESULT_MISS) ] = -1, | |
511 | }, | |
512 | [ C(OP_PREFETCH) ] = { | |
f4db43a3 | 513 | [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */ |
f86748e9 TG |
514 | [ C(RESULT_MISS) ] = 0, |
515 | }, | |
516 | }, | |
8be6e8f3 | 517 | [ C(LL ) ] = { |
f86748e9 | 518 | [ C(OP_READ) ] = { |
f4db43a3 JSR |
519 | [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */ |
520 | [ C(RESULT_MISS) ] = 0x037E, /* L2 Cache Misses : IC+DC */ | |
f86748e9 TG |
521 | }, |
522 | [ C(OP_WRITE) ] = { | |
f4db43a3 | 523 | [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback */ |
f86748e9 TG |
524 | [ C(RESULT_MISS) ] = 0, |
525 | }, | |
526 | [ C(OP_PREFETCH) ] = { | |
527 | [ C(RESULT_ACCESS) ] = 0, | |
528 | [ C(RESULT_MISS) ] = 0, | |
529 | }, | |
530 | }, | |
531 | [ C(DTLB) ] = { | |
532 | [ C(OP_READ) ] = { | |
f4db43a3 JSR |
533 | [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */ |
534 | [ C(RESULT_MISS) ] = 0x0046, /* L1 DTLB and L2 DLTB Miss */ | |
f86748e9 TG |
535 | }, |
536 | [ C(OP_WRITE) ] = { | |
537 | [ C(RESULT_ACCESS) ] = 0, | |
538 | [ C(RESULT_MISS) ] = 0, | |
539 | }, | |
540 | [ C(OP_PREFETCH) ] = { | |
541 | [ C(RESULT_ACCESS) ] = 0, | |
542 | [ C(RESULT_MISS) ] = 0, | |
543 | }, | |
544 | }, | |
545 | [ C(ITLB) ] = { | |
546 | [ C(OP_READ) ] = { | |
547 | [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes */ | |
548 | [ C(RESULT_MISS) ] = 0x0085, /* Instr. fetch ITLB misses */ | |
549 | }, | |
550 | [ C(OP_WRITE) ] = { | |
551 | [ C(RESULT_ACCESS) ] = -1, | |
552 | [ C(RESULT_MISS) ] = -1, | |
553 | }, | |
554 | [ C(OP_PREFETCH) ] = { | |
555 | [ C(RESULT_ACCESS) ] = -1, | |
556 | [ C(RESULT_MISS) ] = -1, | |
557 | }, | |
558 | }, | |
559 | [ C(BPU ) ] = { | |
560 | [ C(OP_READ) ] = { | |
561 | [ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr. */ | |
562 | [ C(RESULT_MISS) ] = 0x00c3, /* Retired Mispredicted BI */ | |
563 | }, | |
564 | [ C(OP_WRITE) ] = { | |
565 | [ C(RESULT_ACCESS) ] = -1, | |
566 | [ C(RESULT_MISS) ] = -1, | |
567 | }, | |
568 | [ C(OP_PREFETCH) ] = { | |
569 | [ C(RESULT_ACCESS) ] = -1, | |
570 | [ C(RESULT_MISS) ] = -1, | |
571 | }, | |
572 | }, | |
573 | }; | |
574 | ||
f87ad35d JSR |
575 | /* |
576 | * AMD Performance Monitor K7 and later. | |
577 | */ | |
b0f3f28e | 578 | static const u64 amd_perfmon_event_map[] = |
f87ad35d | 579 | { |
f4dbfa8f PZ |
580 | [PERF_COUNT_HW_CPU_CYCLES] = 0x0076, |
581 | [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, | |
582 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0080, | |
583 | [PERF_COUNT_HW_CACHE_MISSES] = 0x0081, | |
584 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, | |
585 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, | |
f87ad35d JSR |
586 | }; |
587 | ||
dfc65094 | 588 | static u64 amd_pmu_event_map(int hw_event) |
f87ad35d | 589 | { |
dfc65094 | 590 | return amd_perfmon_event_map[hw_event]; |
f87ad35d JSR |
591 | } |
592 | ||
dfc65094 | 593 | static u64 amd_pmu_raw_event(u64 hw_event) |
b0f3f28e | 594 | { |
82bae4f8 PZ |
595 | #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL |
596 | #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL | |
ff99be57 PZ |
597 | #define K7_EVNTSEL_EDGE_MASK 0x000040000ULL |
598 | #define K7_EVNTSEL_INV_MASK 0x000800000ULL | |
82bae4f8 | 599 | #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL |
b0f3f28e PZ |
600 | |
601 | #define K7_EVNTSEL_MASK \ | |
602 | (K7_EVNTSEL_EVENT_MASK | \ | |
603 | K7_EVNTSEL_UNIT_MASK | \ | |
ff99be57 PZ |
604 | K7_EVNTSEL_EDGE_MASK | \ |
605 | K7_EVNTSEL_INV_MASK | \ | |
b0f3f28e PZ |
606 | K7_EVNTSEL_COUNTER_MASK) |
607 | ||
dfc65094 | 608 | return hw_event & K7_EVNTSEL_MASK; |
b0f3f28e PZ |
609 | } |
610 | ||
ee06094f IM |
611 | /* |
612 | * Propagate counter elapsed time into the generic counter. | |
613 | * Can only be executed on the CPU where the counter is active. | |
614 | * Returns the delta events processed. | |
615 | */ | |
4b7bfd0d | 616 | static u64 |
ee06094f IM |
617 | x86_perf_counter_update(struct perf_counter *counter, |
618 | struct hw_perf_counter *hwc, int idx) | |
619 | { | |
ec3232bd PZ |
620 | int shift = 64 - x86_pmu.counter_bits; |
621 | u64 prev_raw_count, new_raw_count; | |
622 | s64 delta; | |
ee06094f | 623 | |
30dd568c MM |
624 | if (idx == X86_PMC_IDX_FIXED_BTS) |
625 | return 0; | |
626 | ||
ee06094f IM |
627 | /* |
628 | * Careful: an NMI might modify the previous counter value. | |
629 | * | |
630 | * Our tactic to handle this is to first atomically read and | |
631 | * exchange a new raw count - then add that new-prev delta | |
632 | * count to the generic counter atomically: | |
633 | */ | |
634 | again: | |
635 | prev_raw_count = atomic64_read(&hwc->prev_count); | |
636 | rdmsrl(hwc->counter_base + idx, new_raw_count); | |
637 | ||
638 | if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count, | |
639 | new_raw_count) != prev_raw_count) | |
640 | goto again; | |
641 | ||
642 | /* | |
643 | * Now we have the new raw value and have updated the prev | |
644 | * timestamp already. We can now calculate the elapsed delta | |
645 | * (counter-)time and add that to the generic counter. | |
646 | * | |
647 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 648 | * of the count. |
ee06094f | 649 | */ |
ec3232bd PZ |
650 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
651 | delta >>= shift; | |
ee06094f IM |
652 | |
653 | atomic64_add(delta, &counter->count); | |
654 | atomic64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
655 | |
656 | return new_raw_count; | |
ee06094f IM |
657 | } |
658 | ||
ba77813a | 659 | static atomic_t active_counters; |
4e935e47 PZ |
660 | static DEFINE_MUTEX(pmc_reserve_mutex); |
661 | ||
662 | static bool reserve_pmc_hardware(void) | |
663 | { | |
04da8a43 | 664 | #ifdef CONFIG_X86_LOCAL_APIC |
4e935e47 PZ |
665 | int i; |
666 | ||
667 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
668 | disable_lapic_nmi_watchdog(); | |
669 | ||
0933e5c6 | 670 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 | 671 | if (!reserve_perfctr_nmi(x86_pmu.perfctr + i)) |
4e935e47 PZ |
672 | goto perfctr_fail; |
673 | } | |
674 | ||
0933e5c6 | 675 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 | 676 | if (!reserve_evntsel_nmi(x86_pmu.eventsel + i)) |
4e935e47 PZ |
677 | goto eventsel_fail; |
678 | } | |
04da8a43 | 679 | #endif |
4e935e47 PZ |
680 | |
681 | return true; | |
682 | ||
04da8a43 | 683 | #ifdef CONFIG_X86_LOCAL_APIC |
4e935e47 PZ |
684 | eventsel_fail: |
685 | for (i--; i >= 0; i--) | |
4a06bd85 | 686 | release_evntsel_nmi(x86_pmu.eventsel + i); |
4e935e47 | 687 | |
0933e5c6 | 688 | i = x86_pmu.num_counters; |
4e935e47 PZ |
689 | |
690 | perfctr_fail: | |
691 | for (i--; i >= 0; i--) | |
4a06bd85 | 692 | release_perfctr_nmi(x86_pmu.perfctr + i); |
4e935e47 PZ |
693 | |
694 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
695 | enable_lapic_nmi_watchdog(); | |
696 | ||
697 | return false; | |
04da8a43 | 698 | #endif |
4e935e47 PZ |
699 | } |
700 | ||
701 | static void release_pmc_hardware(void) | |
702 | { | |
04da8a43 | 703 | #ifdef CONFIG_X86_LOCAL_APIC |
4e935e47 PZ |
704 | int i; |
705 | ||
0933e5c6 | 706 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 RR |
707 | release_perfctr_nmi(x86_pmu.perfctr + i); |
708 | release_evntsel_nmi(x86_pmu.eventsel + i); | |
4e935e47 PZ |
709 | } |
710 | ||
711 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
712 | enable_lapic_nmi_watchdog(); | |
04da8a43 | 713 | #endif |
4e935e47 PZ |
714 | } |
715 | ||
30dd568c MM |
716 | static inline bool bts_available(void) |
717 | { | |
718 | return x86_pmu.enable_bts != NULL; | |
719 | } | |
720 | ||
721 | static inline void init_debug_store_on_cpu(int cpu) | |
722 | { | |
723 | struct debug_store *ds = per_cpu(cpu_hw_counters, cpu).ds; | |
724 | ||
725 | if (!ds) | |
726 | return; | |
727 | ||
728 | wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, | |
596da17f | 729 | (u32)((u64)(unsigned long)ds), |
730 | (u32)((u64)(unsigned long)ds >> 32)); | |
30dd568c MM |
731 | } |
732 | ||
733 | static inline void fini_debug_store_on_cpu(int cpu) | |
734 | { | |
735 | if (!per_cpu(cpu_hw_counters, cpu).ds) | |
736 | return; | |
737 | ||
738 | wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0); | |
739 | } | |
740 | ||
741 | static void release_bts_hardware(void) | |
742 | { | |
743 | int cpu; | |
744 | ||
745 | if (!bts_available()) | |
746 | return; | |
747 | ||
748 | get_online_cpus(); | |
749 | ||
750 | for_each_online_cpu(cpu) | |
751 | fini_debug_store_on_cpu(cpu); | |
752 | ||
753 | for_each_possible_cpu(cpu) { | |
754 | struct debug_store *ds = per_cpu(cpu_hw_counters, cpu).ds; | |
755 | ||
756 | if (!ds) | |
757 | continue; | |
758 | ||
759 | per_cpu(cpu_hw_counters, cpu).ds = NULL; | |
760 | ||
596da17f | 761 | kfree((void *)(unsigned long)ds->bts_buffer_base); |
30dd568c MM |
762 | kfree(ds); |
763 | } | |
764 | ||
765 | put_online_cpus(); | |
766 | } | |
767 | ||
768 | static int reserve_bts_hardware(void) | |
769 | { | |
770 | int cpu, err = 0; | |
771 | ||
772 | if (!bts_available()) | |
747b50aa | 773 | return 0; |
30dd568c MM |
774 | |
775 | get_online_cpus(); | |
776 | ||
777 | for_each_possible_cpu(cpu) { | |
778 | struct debug_store *ds; | |
779 | void *buffer; | |
780 | ||
781 | err = -ENOMEM; | |
782 | buffer = kzalloc(BTS_BUFFER_SIZE, GFP_KERNEL); | |
783 | if (unlikely(!buffer)) | |
784 | break; | |
785 | ||
786 | ds = kzalloc(sizeof(*ds), GFP_KERNEL); | |
787 | if (unlikely(!ds)) { | |
788 | kfree(buffer); | |
789 | break; | |
790 | } | |
791 | ||
596da17f | 792 | ds->bts_buffer_base = (u64)(unsigned long)buffer; |
30dd568c MM |
793 | ds->bts_index = ds->bts_buffer_base; |
794 | ds->bts_absolute_maximum = | |
795 | ds->bts_buffer_base + BTS_BUFFER_SIZE; | |
796 | ds->bts_interrupt_threshold = | |
797 | ds->bts_absolute_maximum - BTS_OVFL_TH; | |
798 | ||
799 | per_cpu(cpu_hw_counters, cpu).ds = ds; | |
800 | err = 0; | |
801 | } | |
802 | ||
803 | if (err) | |
804 | release_bts_hardware(); | |
805 | else { | |
806 | for_each_online_cpu(cpu) | |
807 | init_debug_store_on_cpu(cpu); | |
808 | } | |
809 | ||
810 | put_online_cpus(); | |
811 | ||
812 | return err; | |
813 | } | |
814 | ||
4e935e47 PZ |
815 | static void hw_perf_counter_destroy(struct perf_counter *counter) |
816 | { | |
ba77813a | 817 | if (atomic_dec_and_mutex_lock(&active_counters, &pmc_reserve_mutex)) { |
4e935e47 | 818 | release_pmc_hardware(); |
30dd568c | 819 | release_bts_hardware(); |
4e935e47 PZ |
820 | mutex_unlock(&pmc_reserve_mutex); |
821 | } | |
822 | } | |
823 | ||
85cf9dba RR |
824 | static inline int x86_pmu_initialized(void) |
825 | { | |
826 | return x86_pmu.handle_irq != NULL; | |
827 | } | |
828 | ||
8326f44d IM |
829 | static inline int |
830 | set_ext_hw_attr(struct hw_perf_counter *hwc, struct perf_counter_attr *attr) | |
831 | { | |
832 | unsigned int cache_type, cache_op, cache_result; | |
833 | u64 config, val; | |
834 | ||
835 | config = attr->config; | |
836 | ||
837 | cache_type = (config >> 0) & 0xff; | |
838 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
839 | return -EINVAL; | |
840 | ||
841 | cache_op = (config >> 8) & 0xff; | |
842 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
843 | return -EINVAL; | |
844 | ||
845 | cache_result = (config >> 16) & 0xff; | |
846 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
847 | return -EINVAL; | |
848 | ||
849 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
850 | ||
851 | if (val == 0) | |
852 | return -ENOENT; | |
853 | ||
854 | if (val == -1) | |
855 | return -EINVAL; | |
856 | ||
857 | hwc->config |= val; | |
858 | ||
859 | return 0; | |
860 | } | |
861 | ||
30dd568c MM |
862 | static void intel_pmu_enable_bts(u64 config) |
863 | { | |
864 | unsigned long debugctlmsr; | |
865 | ||
866 | debugctlmsr = get_debugctlmsr(); | |
867 | ||
868 | debugctlmsr |= X86_DEBUGCTL_TR; | |
869 | debugctlmsr |= X86_DEBUGCTL_BTS; | |
870 | debugctlmsr |= X86_DEBUGCTL_BTINT; | |
871 | ||
872 | if (!(config & ARCH_PERFMON_EVENTSEL_OS)) | |
873 | debugctlmsr |= X86_DEBUGCTL_BTS_OFF_OS; | |
874 | ||
875 | if (!(config & ARCH_PERFMON_EVENTSEL_USR)) | |
876 | debugctlmsr |= X86_DEBUGCTL_BTS_OFF_USR; | |
877 | ||
878 | update_debugctlmsr(debugctlmsr); | |
879 | } | |
880 | ||
881 | static void intel_pmu_disable_bts(void) | |
882 | { | |
883 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
884 | unsigned long debugctlmsr; | |
885 | ||
886 | if (!cpuc->ds) | |
887 | return; | |
888 | ||
889 | debugctlmsr = get_debugctlmsr(); | |
890 | ||
891 | debugctlmsr &= | |
892 | ~(X86_DEBUGCTL_TR | X86_DEBUGCTL_BTS | X86_DEBUGCTL_BTINT | | |
893 | X86_DEBUGCTL_BTS_OFF_OS | X86_DEBUGCTL_BTS_OFF_USR); | |
894 | ||
895 | update_debugctlmsr(debugctlmsr); | |
896 | } | |
897 | ||
241771ef | 898 | /* |
0d48696f | 899 | * Setup the hardware configuration for a given attr_type |
241771ef | 900 | */ |
621a01ea | 901 | static int __hw_perf_counter_init(struct perf_counter *counter) |
241771ef | 902 | { |
0d48696f | 903 | struct perf_counter_attr *attr = &counter->attr; |
241771ef | 904 | struct hw_perf_counter *hwc = &counter->hw; |
9c74fb50 | 905 | u64 config; |
4e935e47 | 906 | int err; |
241771ef | 907 | |
85cf9dba RR |
908 | if (!x86_pmu_initialized()) |
909 | return -ENODEV; | |
241771ef | 910 | |
4e935e47 | 911 | err = 0; |
ba77813a | 912 | if (!atomic_inc_not_zero(&active_counters)) { |
4e935e47 | 913 | mutex_lock(&pmc_reserve_mutex); |
30dd568c MM |
914 | if (atomic_read(&active_counters) == 0) { |
915 | if (!reserve_pmc_hardware()) | |
916 | err = -EBUSY; | |
917 | else | |
747b50aa | 918 | err = reserve_bts_hardware(); |
30dd568c MM |
919 | } |
920 | if (!err) | |
ba77813a | 921 | atomic_inc(&active_counters); |
4e935e47 PZ |
922 | mutex_unlock(&pmc_reserve_mutex); |
923 | } | |
924 | if (err) | |
925 | return err; | |
926 | ||
a1792cda PZ |
927 | counter->destroy = hw_perf_counter_destroy; |
928 | ||
241771ef | 929 | /* |
0475f9ea | 930 | * Generate PMC IRQs: |
241771ef IM |
931 | * (keep 'enabled' bit clear for now) |
932 | */ | |
0475f9ea | 933 | hwc->config = ARCH_PERFMON_EVENTSEL_INT; |
241771ef IM |
934 | |
935 | /* | |
0475f9ea | 936 | * Count user and OS events unless requested not to. |
241771ef | 937 | */ |
0d48696f | 938 | if (!attr->exclude_user) |
0475f9ea | 939 | hwc->config |= ARCH_PERFMON_EVENTSEL_USR; |
0d48696f | 940 | if (!attr->exclude_kernel) |
241771ef | 941 | hwc->config |= ARCH_PERFMON_EVENTSEL_OS; |
0475f9ea | 942 | |
bd2b5b12 | 943 | if (!hwc->sample_period) { |
b23f3325 | 944 | hwc->sample_period = x86_pmu.max_period; |
9e350de3 | 945 | hwc->last_period = hwc->sample_period; |
bd2b5b12 | 946 | atomic64_set(&hwc->period_left, hwc->sample_period); |
04da8a43 IM |
947 | } else { |
948 | /* | |
949 | * If we have a PMU initialized but no APIC | |
950 | * interrupts, we cannot sample hardware | |
951 | * counters (user-space has to fall back and | |
952 | * sample via a hrtimer based software counter): | |
953 | */ | |
954 | if (!x86_pmu.apic) | |
955 | return -EOPNOTSUPP; | |
bd2b5b12 | 956 | } |
d2517a49 | 957 | |
241771ef | 958 | /* |
dfc65094 | 959 | * Raw hw_event type provide the config in the hw_event structure |
241771ef | 960 | */ |
a21ca2ca IM |
961 | if (attr->type == PERF_TYPE_RAW) { |
962 | hwc->config |= x86_pmu.raw_event(attr->config); | |
8326f44d | 963 | return 0; |
241771ef | 964 | } |
241771ef | 965 | |
8326f44d IM |
966 | if (attr->type == PERF_TYPE_HW_CACHE) |
967 | return set_ext_hw_attr(hwc, attr); | |
968 | ||
969 | if (attr->config >= x86_pmu.max_events) | |
970 | return -EINVAL; | |
9c74fb50 | 971 | |
8326f44d IM |
972 | /* |
973 | * The generic map: | |
974 | */ | |
9c74fb50 PZ |
975 | config = x86_pmu.event_map(attr->config); |
976 | ||
977 | if (config == 0) | |
978 | return -ENOENT; | |
979 | ||
980 | if (config == -1LL) | |
981 | return -EINVAL; | |
982 | ||
747b50aa | 983 | /* |
984 | * Branch tracing: | |
985 | */ | |
986 | if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) && | |
1653192f | 987 | (hwc->sample_period == 1)) { |
988 | /* BTS is not supported by this architecture. */ | |
989 | if (!bts_available()) | |
990 | return -EOPNOTSUPP; | |
991 | ||
992 | /* BTS is currently only allowed for user-mode. */ | |
993 | if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) | |
994 | return -EOPNOTSUPP; | |
995 | } | |
747b50aa | 996 | |
9c74fb50 | 997 | hwc->config |= config; |
4e935e47 | 998 | |
241771ef IM |
999 | return 0; |
1000 | } | |
1001 | ||
11d1578f VW |
1002 | static void p6_pmu_disable_all(void) |
1003 | { | |
1004 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
9c74fb50 | 1005 | u64 val; |
11d1578f VW |
1006 | |
1007 | if (!cpuc->enabled) | |
1008 | return; | |
1009 | ||
1010 | cpuc->enabled = 0; | |
1011 | barrier(); | |
1012 | ||
1013 | /* p6 only has one enable register */ | |
1014 | rdmsrl(MSR_P6_EVNTSEL0, val); | |
1015 | val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE; | |
1016 | wrmsrl(MSR_P6_EVNTSEL0, val); | |
1017 | } | |
1018 | ||
9e35ad38 | 1019 | static void intel_pmu_disable_all(void) |
4ac13294 | 1020 | { |
30dd568c MM |
1021 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
1022 | ||
1023 | if (!cpuc->enabled) | |
1024 | return; | |
1025 | ||
1026 | cpuc->enabled = 0; | |
1027 | barrier(); | |
1028 | ||
862a1a5f | 1029 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); |
30dd568c MM |
1030 | |
1031 | if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) | |
1032 | intel_pmu_disable_bts(); | |
241771ef | 1033 | } |
b56a3802 | 1034 | |
9e35ad38 | 1035 | static void amd_pmu_disable_all(void) |
f87ad35d | 1036 | { |
b0f3f28e | 1037 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
9e35ad38 PZ |
1038 | int idx; |
1039 | ||
1040 | if (!cpuc->enabled) | |
1041 | return; | |
b0f3f28e | 1042 | |
b0f3f28e | 1043 | cpuc->enabled = 0; |
60b3df9c PZ |
1044 | /* |
1045 | * ensure we write the disable before we start disabling the | |
5f4ec28f RR |
1046 | * counters proper, so that amd_pmu_enable_counter() does the |
1047 | * right thing. | |
60b3df9c | 1048 | */ |
b0f3f28e | 1049 | barrier(); |
f87ad35d | 1050 | |
0933e5c6 | 1051 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
1052 | u64 val; |
1053 | ||
43f6201a | 1054 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 1055 | continue; |
f87ad35d | 1056 | rdmsrl(MSR_K7_EVNTSEL0 + idx, val); |
4295ee62 RR |
1057 | if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE)) |
1058 | continue; | |
1059 | val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE; | |
1060 | wrmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
f87ad35d | 1061 | } |
f87ad35d JSR |
1062 | } |
1063 | ||
9e35ad38 | 1064 | void hw_perf_disable(void) |
b56a3802 | 1065 | { |
85cf9dba | 1066 | if (!x86_pmu_initialized()) |
9e35ad38 PZ |
1067 | return; |
1068 | return x86_pmu.disable_all(); | |
b56a3802 | 1069 | } |
241771ef | 1070 | |
11d1578f VW |
1071 | static void p6_pmu_enable_all(void) |
1072 | { | |
1073 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
1074 | unsigned long val; | |
1075 | ||
1076 | if (cpuc->enabled) | |
1077 | return; | |
1078 | ||
1079 | cpuc->enabled = 1; | |
1080 | barrier(); | |
1081 | ||
1082 | /* p6 only has one enable register */ | |
1083 | rdmsrl(MSR_P6_EVNTSEL0, val); | |
1084 | val |= ARCH_PERFMON_EVENTSEL0_ENABLE; | |
1085 | wrmsrl(MSR_P6_EVNTSEL0, val); | |
1086 | } | |
1087 | ||
9e35ad38 | 1088 | static void intel_pmu_enable_all(void) |
b56a3802 | 1089 | { |
30dd568c MM |
1090 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
1091 | ||
1092 | if (cpuc->enabled) | |
1093 | return; | |
1094 | ||
1095 | cpuc->enabled = 1; | |
1096 | barrier(); | |
1097 | ||
9e35ad38 | 1098 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl); |
30dd568c MM |
1099 | |
1100 | if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { | |
1101 | struct perf_counter *counter = | |
1102 | cpuc->counters[X86_PMC_IDX_FIXED_BTS]; | |
1103 | ||
1104 | if (WARN_ON_ONCE(!counter)) | |
1105 | return; | |
1106 | ||
1107 | intel_pmu_enable_bts(counter->hw.config); | |
1108 | } | |
b56a3802 JSR |
1109 | } |
1110 | ||
9e35ad38 | 1111 | static void amd_pmu_enable_all(void) |
f87ad35d | 1112 | { |
b0f3f28e | 1113 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
f87ad35d JSR |
1114 | int idx; |
1115 | ||
9e35ad38 | 1116 | if (cpuc->enabled) |
b0f3f28e PZ |
1117 | return; |
1118 | ||
9e35ad38 PZ |
1119 | cpuc->enabled = 1; |
1120 | barrier(); | |
1121 | ||
0933e5c6 | 1122 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
984b838c | 1123 | struct perf_counter *counter = cpuc->counters[idx]; |
4295ee62 | 1124 | u64 val; |
b0f3f28e | 1125 | |
43f6201a | 1126 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 1127 | continue; |
984b838c PZ |
1128 | |
1129 | val = counter->hw.config; | |
4295ee62 RR |
1130 | val |= ARCH_PERFMON_EVENTSEL0_ENABLE; |
1131 | wrmsrl(MSR_K7_EVNTSEL0 + idx, val); | |
f87ad35d JSR |
1132 | } |
1133 | } | |
1134 | ||
9e35ad38 | 1135 | void hw_perf_enable(void) |
ee06094f | 1136 | { |
85cf9dba | 1137 | if (!x86_pmu_initialized()) |
2b9ff0db | 1138 | return; |
9e35ad38 | 1139 | x86_pmu.enable_all(); |
ee06094f | 1140 | } |
ee06094f | 1141 | |
19d84dab | 1142 | static inline u64 intel_pmu_get_status(void) |
b0f3f28e PZ |
1143 | { |
1144 | u64 status; | |
1145 | ||
b7f8859a | 1146 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); |
b0f3f28e | 1147 | |
b7f8859a | 1148 | return status; |
b0f3f28e PZ |
1149 | } |
1150 | ||
dee5d906 | 1151 | static inline void intel_pmu_ack_status(u64 ack) |
b0f3f28e PZ |
1152 | { |
1153 | wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); | |
1154 | } | |
1155 | ||
7c90cc45 | 1156 | static inline void x86_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) |
b0f3f28e | 1157 | { |
11d1578f | 1158 | (void)checking_wrmsrl(hwc->config_base + idx, |
7c90cc45 | 1159 | hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE); |
b0f3f28e PZ |
1160 | } |
1161 | ||
d4369891 | 1162 | static inline void x86_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) |
b0f3f28e | 1163 | { |
11d1578f | 1164 | (void)checking_wrmsrl(hwc->config_base + idx, hwc->config); |
b0f3f28e PZ |
1165 | } |
1166 | ||
2f18d1e8 | 1167 | static inline void |
d4369891 | 1168 | intel_pmu_disable_fixed(struct hw_perf_counter *hwc, int __idx) |
2f18d1e8 IM |
1169 | { |
1170 | int idx = __idx - X86_PMC_IDX_FIXED; | |
1171 | u64 ctrl_val, mask; | |
2f18d1e8 IM |
1172 | |
1173 | mask = 0xfULL << (idx * 4); | |
1174 | ||
1175 | rdmsrl(hwc->config_base, ctrl_val); | |
1176 | ctrl_val &= ~mask; | |
11d1578f VW |
1177 | (void)checking_wrmsrl(hwc->config_base, ctrl_val); |
1178 | } | |
1179 | ||
1180 | static inline void | |
1181 | p6_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) | |
1182 | { | |
1183 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
9c74fb50 | 1184 | u64 val = P6_NOP_COUNTER; |
11d1578f | 1185 | |
9c74fb50 PZ |
1186 | if (cpuc->enabled) |
1187 | val |= ARCH_PERFMON_EVENTSEL0_ENABLE; | |
11d1578f VW |
1188 | |
1189 | (void)checking_wrmsrl(hwc->config_base + idx, val); | |
2f18d1e8 IM |
1190 | } |
1191 | ||
7e2ae347 | 1192 | static inline void |
d4369891 | 1193 | intel_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) |
7e2ae347 | 1194 | { |
30dd568c MM |
1195 | if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) { |
1196 | intel_pmu_disable_bts(); | |
1197 | return; | |
1198 | } | |
1199 | ||
d4369891 RR |
1200 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { |
1201 | intel_pmu_disable_fixed(hwc, idx); | |
1202 | return; | |
1203 | } | |
1204 | ||
1205 | x86_pmu_disable_counter(hwc, idx); | |
1206 | } | |
1207 | ||
1208 | static inline void | |
1209 | amd_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) | |
1210 | { | |
1211 | x86_pmu_disable_counter(hwc, idx); | |
7e2ae347 IM |
1212 | } |
1213 | ||
245b2e70 | 1214 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 1215 | |
ee06094f IM |
1216 | /* |
1217 | * Set the next IRQ period, based on the hwc->period_left value. | |
1218 | * To be called with the counter disabled in hw: | |
1219 | */ | |
e4abb5d4 | 1220 | static int |
26816c28 | 1221 | x86_perf_counter_set_period(struct perf_counter *counter, |
ee06094f | 1222 | struct hw_perf_counter *hwc, int idx) |
241771ef | 1223 | { |
2f18d1e8 | 1224 | s64 left = atomic64_read(&hwc->period_left); |
e4abb5d4 PZ |
1225 | s64 period = hwc->sample_period; |
1226 | int err, ret = 0; | |
ee06094f | 1227 | |
30dd568c MM |
1228 | if (idx == X86_PMC_IDX_FIXED_BTS) |
1229 | return 0; | |
1230 | ||
ee06094f IM |
1231 | /* |
1232 | * If we are way outside a reasoable range then just skip forward: | |
1233 | */ | |
1234 | if (unlikely(left <= -period)) { | |
1235 | left = period; | |
1236 | atomic64_set(&hwc->period_left, left); | |
9e350de3 | 1237 | hwc->last_period = period; |
e4abb5d4 | 1238 | ret = 1; |
ee06094f IM |
1239 | } |
1240 | ||
1241 | if (unlikely(left <= 0)) { | |
1242 | left += period; | |
1243 | atomic64_set(&hwc->period_left, left); | |
9e350de3 | 1244 | hwc->last_period = period; |
e4abb5d4 | 1245 | ret = 1; |
ee06094f | 1246 | } |
1c80f4b5 | 1247 | /* |
dfc65094 | 1248 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
1249 | */ |
1250 | if (unlikely(left < 2)) | |
1251 | left = 2; | |
241771ef | 1252 | |
e4abb5d4 PZ |
1253 | if (left > x86_pmu.max_period) |
1254 | left = x86_pmu.max_period; | |
1255 | ||
245b2e70 | 1256 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
ee06094f IM |
1257 | |
1258 | /* | |
1259 | * The hw counter starts counting from this counter offset, | |
1260 | * mark it to be able to extra future deltas: | |
1261 | */ | |
2f18d1e8 | 1262 | atomic64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 1263 | |
2f18d1e8 | 1264 | err = checking_wrmsrl(hwc->counter_base + idx, |
0933e5c6 | 1265 | (u64)(-left) & x86_pmu.counter_mask); |
e4abb5d4 | 1266 | |
194002b2 PZ |
1267 | perf_counter_update_userpage(counter); |
1268 | ||
e4abb5d4 | 1269 | return ret; |
2f18d1e8 IM |
1270 | } |
1271 | ||
1272 | static inline void | |
7c90cc45 | 1273 | intel_pmu_enable_fixed(struct hw_perf_counter *hwc, int __idx) |
2f18d1e8 IM |
1274 | { |
1275 | int idx = __idx - X86_PMC_IDX_FIXED; | |
1276 | u64 ctrl_val, bits, mask; | |
1277 | int err; | |
1278 | ||
1279 | /* | |
0475f9ea PM |
1280 | * Enable IRQ generation (0x8), |
1281 | * and enable ring-3 counting (0x2) and ring-0 counting (0x1) | |
1282 | * if requested: | |
2f18d1e8 | 1283 | */ |
0475f9ea PM |
1284 | bits = 0x8ULL; |
1285 | if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) | |
1286 | bits |= 0x2; | |
2f18d1e8 IM |
1287 | if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) |
1288 | bits |= 0x1; | |
1289 | bits <<= (idx * 4); | |
1290 | mask = 0xfULL << (idx * 4); | |
1291 | ||
1292 | rdmsrl(hwc->config_base, ctrl_val); | |
1293 | ctrl_val &= ~mask; | |
1294 | ctrl_val |= bits; | |
1295 | err = checking_wrmsrl(hwc->config_base, ctrl_val); | |
7e2ae347 IM |
1296 | } |
1297 | ||
11d1578f VW |
1298 | static void p6_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) |
1299 | { | |
1300 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
984b838c | 1301 | u64 val; |
11d1578f | 1302 | |
984b838c | 1303 | val = hwc->config; |
11d1578f | 1304 | if (cpuc->enabled) |
984b838c PZ |
1305 | val |= ARCH_PERFMON_EVENTSEL0_ENABLE; |
1306 | ||
1307 | (void)checking_wrmsrl(hwc->config_base + idx, val); | |
11d1578f VW |
1308 | } |
1309 | ||
1310 | ||
7c90cc45 | 1311 | static void intel_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) |
7e2ae347 | 1312 | { |
30dd568c MM |
1313 | if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) { |
1314 | if (!__get_cpu_var(cpu_hw_counters).enabled) | |
1315 | return; | |
1316 | ||
1317 | intel_pmu_enable_bts(hwc->config); | |
1318 | return; | |
1319 | } | |
1320 | ||
7c90cc45 RR |
1321 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { |
1322 | intel_pmu_enable_fixed(hwc, idx); | |
1323 | return; | |
1324 | } | |
1325 | ||
1326 | x86_pmu_enable_counter(hwc, idx); | |
1327 | } | |
1328 | ||
1329 | static void amd_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) | |
1330 | { | |
1331 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
1332 | ||
1333 | if (cpuc->enabled) | |
1334 | x86_pmu_enable_counter(hwc, idx); | |
241771ef IM |
1335 | } |
1336 | ||
2f18d1e8 IM |
1337 | static int |
1338 | fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc) | |
862a1a5f | 1339 | { |
dfc65094 | 1340 | unsigned int hw_event; |
2f18d1e8 | 1341 | |
dfc65094 | 1342 | hw_event = hwc->config & ARCH_PERFMON_EVENT_MASK; |
30dd568c | 1343 | |
dfc65094 | 1344 | if (unlikely((hw_event == |
30dd568c MM |
1345 | x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS)) && |
1346 | (hwc->sample_period == 1))) | |
1347 | return X86_PMC_IDX_FIXED_BTS; | |
1348 | ||
ef7b3e09 | 1349 | if (!x86_pmu.num_counters_fixed) |
f87ad35d JSR |
1350 | return -1; |
1351 | ||
dfc65094 | 1352 | if (unlikely(hw_event == x86_pmu.event_map(PERF_COUNT_HW_INSTRUCTIONS))) |
2f18d1e8 | 1353 | return X86_PMC_IDX_FIXED_INSTRUCTIONS; |
dfc65094 | 1354 | if (unlikely(hw_event == x86_pmu.event_map(PERF_COUNT_HW_CPU_CYCLES))) |
2f18d1e8 | 1355 | return X86_PMC_IDX_FIXED_CPU_CYCLES; |
dfc65094 | 1356 | if (unlikely(hw_event == x86_pmu.event_map(PERF_COUNT_HW_BUS_CYCLES))) |
2f18d1e8 IM |
1357 | return X86_PMC_IDX_FIXED_BUS_CYCLES; |
1358 | ||
862a1a5f IM |
1359 | return -1; |
1360 | } | |
1361 | ||
ee06094f IM |
1362 | /* |
1363 | * Find a PMC slot for the freshly enabled / scheduled in counter: | |
1364 | */ | |
4aeb0b42 | 1365 | static int x86_pmu_enable(struct perf_counter *counter) |
241771ef IM |
1366 | { |
1367 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
1368 | struct hw_perf_counter *hwc = &counter->hw; | |
2f18d1e8 | 1369 | int idx; |
241771ef | 1370 | |
2f18d1e8 | 1371 | idx = fixed_mode_idx(counter, hwc); |
30dd568c | 1372 | if (idx == X86_PMC_IDX_FIXED_BTS) { |
747b50aa | 1373 | /* BTS is already occupied. */ |
30dd568c | 1374 | if (test_and_set_bit(idx, cpuc->used_mask)) |
747b50aa | 1375 | return -EAGAIN; |
30dd568c MM |
1376 | |
1377 | hwc->config_base = 0; | |
1378 | hwc->counter_base = 0; | |
1379 | hwc->idx = idx; | |
1380 | } else if (idx >= 0) { | |
2f18d1e8 IM |
1381 | /* |
1382 | * Try to get the fixed counter, if that is already taken | |
1383 | * then try to get a generic counter: | |
1384 | */ | |
43f6201a | 1385 | if (test_and_set_bit(idx, cpuc->used_mask)) |
2f18d1e8 | 1386 | goto try_generic; |
0dff86aa | 1387 | |
2f18d1e8 IM |
1388 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
1389 | /* | |
1390 | * We set it so that counter_base + idx in wrmsr/rdmsr maps to | |
1391 | * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2: | |
1392 | */ | |
1393 | hwc->counter_base = | |
1394 | MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED; | |
241771ef | 1395 | hwc->idx = idx; |
2f18d1e8 IM |
1396 | } else { |
1397 | idx = hwc->idx; | |
1398 | /* Try to get the previous generic counter again */ | |
43f6201a | 1399 | if (test_and_set_bit(idx, cpuc->used_mask)) { |
2f18d1e8 | 1400 | try_generic: |
43f6201a | 1401 | idx = find_first_zero_bit(cpuc->used_mask, |
0933e5c6 RR |
1402 | x86_pmu.num_counters); |
1403 | if (idx == x86_pmu.num_counters) | |
2f18d1e8 IM |
1404 | return -EAGAIN; |
1405 | ||
43f6201a | 1406 | set_bit(idx, cpuc->used_mask); |
2f18d1e8 IM |
1407 | hwc->idx = idx; |
1408 | } | |
4a06bd85 RR |
1409 | hwc->config_base = x86_pmu.eventsel; |
1410 | hwc->counter_base = x86_pmu.perfctr; | |
241771ef IM |
1411 | } |
1412 | ||
c323d95f | 1413 | perf_counters_lapic_init(); |
53b441a5 | 1414 | |
d4369891 | 1415 | x86_pmu.disable(hwc, idx); |
241771ef | 1416 | |
862a1a5f | 1417 | cpuc->counters[idx] = counter; |
43f6201a | 1418 | set_bit(idx, cpuc->active_mask); |
7e2ae347 | 1419 | |
26816c28 | 1420 | x86_perf_counter_set_period(counter, hwc, idx); |
7c90cc45 | 1421 | x86_pmu.enable(hwc, idx); |
95cdd2e7 | 1422 | |
194002b2 PZ |
1423 | perf_counter_update_userpage(counter); |
1424 | ||
95cdd2e7 | 1425 | return 0; |
241771ef IM |
1426 | } |
1427 | ||
a78ac325 PZ |
1428 | static void x86_pmu_unthrottle(struct perf_counter *counter) |
1429 | { | |
1430 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
1431 | struct hw_perf_counter *hwc = &counter->hw; | |
1432 | ||
1433 | if (WARN_ON_ONCE(hwc->idx >= X86_PMC_IDX_MAX || | |
1434 | cpuc->counters[hwc->idx] != counter)) | |
1435 | return; | |
1436 | ||
1437 | x86_pmu.enable(hwc, hwc->idx); | |
1438 | } | |
1439 | ||
241771ef IM |
1440 | void perf_counter_print_debug(void) |
1441 | { | |
2f18d1e8 | 1442 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
0dff86aa | 1443 | struct cpu_hw_counters *cpuc; |
5bb9efe3 | 1444 | unsigned long flags; |
1e125676 IM |
1445 | int cpu, idx; |
1446 | ||
0933e5c6 | 1447 | if (!x86_pmu.num_counters) |
1e125676 | 1448 | return; |
241771ef | 1449 | |
5bb9efe3 | 1450 | local_irq_save(flags); |
241771ef IM |
1451 | |
1452 | cpu = smp_processor_id(); | |
0dff86aa | 1453 | cpuc = &per_cpu(cpu_hw_counters, cpu); |
241771ef | 1454 | |
faa28ae0 | 1455 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1456 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1457 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1458 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1459 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
1460 | ||
1461 | pr_info("\n"); | |
1462 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1463 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1464 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1465 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
f87ad35d | 1466 | } |
43f6201a | 1467 | pr_info("CPU#%d: used: %016llx\n", cpu, *(u64 *)cpuc->used_mask); |
241771ef | 1468 | |
0933e5c6 | 1469 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
4a06bd85 RR |
1470 | rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl); |
1471 | rdmsrl(x86_pmu.perfctr + idx, pmc_count); | |
241771ef | 1472 | |
245b2e70 | 1473 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 1474 | |
a1ef58f4 | 1475 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1476 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1477 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1478 | cpu, idx, pmc_count); |
a1ef58f4 | 1479 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1480 | cpu, idx, prev_left); |
241771ef | 1481 | } |
0933e5c6 | 1482 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
1483 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1484 | ||
a1ef58f4 | 1485 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1486 | cpu, idx, pmc_count); |
1487 | } | |
5bb9efe3 | 1488 | local_irq_restore(flags); |
241771ef IM |
1489 | } |
1490 | ||
5622f295 | 1491 | static void intel_pmu_drain_bts_buffer(struct cpu_hw_counters *cpuc) |
30dd568c MM |
1492 | { |
1493 | struct debug_store *ds = cpuc->ds; | |
1494 | struct bts_record { | |
1495 | u64 from; | |
1496 | u64 to; | |
1497 | u64 flags; | |
1498 | }; | |
1499 | struct perf_counter *counter = cpuc->counters[X86_PMC_IDX_FIXED_BTS]; | |
596da17f | 1500 | struct bts_record *at, *top; |
5622f295 MM |
1501 | struct perf_output_handle handle; |
1502 | struct perf_event_header header; | |
1503 | struct perf_sample_data data; | |
1504 | struct pt_regs regs; | |
30dd568c MM |
1505 | |
1506 | if (!counter) | |
1507 | return; | |
1508 | ||
1509 | if (!ds) | |
1510 | return; | |
1511 | ||
596da17f | 1512 | at = (struct bts_record *)(unsigned long)ds->bts_buffer_base; |
1513 | top = (struct bts_record *)(unsigned long)ds->bts_index; | |
30dd568c | 1514 | |
5622f295 MM |
1515 | if (top <= at) |
1516 | return; | |
1517 | ||
596da17f | 1518 | ds->bts_index = ds->bts_buffer_base; |
1519 | ||
5622f295 MM |
1520 | |
1521 | data.period = counter->hw.last_period; | |
1522 | data.addr = 0; | |
1523 | regs.ip = 0; | |
1524 | ||
1525 | /* | |
1526 | * Prepare a generic sample, i.e. fill in the invariant fields. | |
1527 | * We will overwrite the from and to address before we output | |
1528 | * the sample. | |
1529 | */ | |
1530 | perf_prepare_sample(&header, &data, counter, ®s); | |
1531 | ||
1532 | if (perf_output_begin(&handle, counter, | |
1533 | header.size * (top - at), 1, 1)) | |
1534 | return; | |
1535 | ||
596da17f | 1536 | for (; at < top; at++) { |
5622f295 MM |
1537 | data.ip = at->from; |
1538 | data.addr = at->to; | |
30dd568c | 1539 | |
5622f295 | 1540 | perf_output_sample(&handle, &header, &data, counter); |
30dd568c MM |
1541 | } |
1542 | ||
5622f295 | 1543 | perf_output_end(&handle); |
30dd568c MM |
1544 | |
1545 | /* There's new data available. */ | |
5622f295 | 1546 | counter->hw.interrupts++; |
30dd568c MM |
1547 | counter->pending_kill = POLL_IN; |
1548 | } | |
1549 | ||
4aeb0b42 | 1550 | static void x86_pmu_disable(struct perf_counter *counter) |
241771ef IM |
1551 | { |
1552 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); | |
1553 | struct hw_perf_counter *hwc = &counter->hw; | |
6f00cada | 1554 | int idx = hwc->idx; |
241771ef | 1555 | |
09534238 RR |
1556 | /* |
1557 | * Must be done before we disable, otherwise the nmi handler | |
1558 | * could reenable again: | |
1559 | */ | |
43f6201a | 1560 | clear_bit(idx, cpuc->active_mask); |
d4369891 | 1561 | x86_pmu.disable(hwc, idx); |
241771ef | 1562 | |
2f18d1e8 IM |
1563 | /* |
1564 | * Make sure the cleared pointer becomes visible before we | |
1565 | * (potentially) free the counter: | |
1566 | */ | |
527e26af | 1567 | barrier(); |
241771ef | 1568 | |
ee06094f IM |
1569 | /* |
1570 | * Drain the remaining delta count out of a counter | |
1571 | * that we are disabling: | |
1572 | */ | |
1573 | x86_perf_counter_update(counter, hwc, idx); | |
30dd568c MM |
1574 | |
1575 | /* Drain the remaining BTS records. */ | |
5622f295 MM |
1576 | if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) |
1577 | intel_pmu_drain_bts_buffer(cpuc); | |
30dd568c | 1578 | |
09534238 | 1579 | cpuc->counters[idx] = NULL; |
43f6201a | 1580 | clear_bit(idx, cpuc->used_mask); |
194002b2 PZ |
1581 | |
1582 | perf_counter_update_userpage(counter); | |
241771ef IM |
1583 | } |
1584 | ||
7e2ae347 | 1585 | /* |
ee06094f IM |
1586 | * Save and restart an expired counter. Called by NMI contexts, |
1587 | * so it has to be careful about preempting normal counter ops: | |
7e2ae347 | 1588 | */ |
e4abb5d4 | 1589 | static int intel_pmu_save_and_restart(struct perf_counter *counter) |
241771ef IM |
1590 | { |
1591 | struct hw_perf_counter *hwc = &counter->hw; | |
1592 | int idx = hwc->idx; | |
e4abb5d4 | 1593 | int ret; |
241771ef | 1594 | |
ee06094f | 1595 | x86_perf_counter_update(counter, hwc, idx); |
e4abb5d4 | 1596 | ret = x86_perf_counter_set_period(counter, hwc, idx); |
7e2ae347 | 1597 | |
2f18d1e8 | 1598 | if (counter->state == PERF_COUNTER_STATE_ACTIVE) |
7c90cc45 | 1599 | intel_pmu_enable_counter(hwc, idx); |
e4abb5d4 PZ |
1600 | |
1601 | return ret; | |
241771ef IM |
1602 | } |
1603 | ||
aaba9801 IM |
1604 | static void intel_pmu_reset(void) |
1605 | { | |
30dd568c | 1606 | struct debug_store *ds = __get_cpu_var(cpu_hw_counters).ds; |
aaba9801 IM |
1607 | unsigned long flags; |
1608 | int idx; | |
1609 | ||
1610 | if (!x86_pmu.num_counters) | |
1611 | return; | |
1612 | ||
1613 | local_irq_save(flags); | |
1614 | ||
1615 | printk("clearing PMU state on CPU#%d\n", smp_processor_id()); | |
1616 | ||
1617 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { | |
1618 | checking_wrmsrl(x86_pmu.eventsel + idx, 0ull); | |
1619 | checking_wrmsrl(x86_pmu.perfctr + idx, 0ull); | |
1620 | } | |
1621 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { | |
1622 | checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); | |
1623 | } | |
30dd568c MM |
1624 | if (ds) |
1625 | ds->bts_index = ds->bts_buffer_base; | |
aaba9801 IM |
1626 | |
1627 | local_irq_restore(flags); | |
1628 | } | |
1629 | ||
11d1578f VW |
1630 | static int p6_pmu_handle_irq(struct pt_regs *regs) |
1631 | { | |
1632 | struct perf_sample_data data; | |
1633 | struct cpu_hw_counters *cpuc; | |
1634 | struct perf_counter *counter; | |
1635 | struct hw_perf_counter *hwc; | |
1636 | int idx, handled = 0; | |
1637 | u64 val; | |
1638 | ||
11d1578f VW |
1639 | data.addr = 0; |
1640 | ||
1641 | cpuc = &__get_cpu_var(cpu_hw_counters); | |
1642 | ||
1643 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { | |
1644 | if (!test_bit(idx, cpuc->active_mask)) | |
1645 | continue; | |
1646 | ||
1647 | counter = cpuc->counters[idx]; | |
1648 | hwc = &counter->hw; | |
1649 | ||
1650 | val = x86_perf_counter_update(counter, hwc, idx); | |
1651 | if (val & (1ULL << (x86_pmu.counter_bits - 1))) | |
1652 | continue; | |
1653 | ||
1654 | /* | |
1655 | * counter overflow | |
1656 | */ | |
1657 | handled = 1; | |
1658 | data.period = counter->hw.last_period; | |
1659 | ||
1660 | if (!x86_perf_counter_set_period(counter, hwc, idx)) | |
1661 | continue; | |
1662 | ||
5622f295 | 1663 | if (perf_counter_overflow(counter, 1, &data, regs)) |
11d1578f VW |
1664 | p6_pmu_disable_counter(hwc, idx); |
1665 | } | |
1666 | ||
1667 | if (handled) | |
1668 | inc_irq_stat(apic_perf_irqs); | |
1669 | ||
1670 | return handled; | |
1671 | } | |
aaba9801 | 1672 | |
241771ef IM |
1673 | /* |
1674 | * This handler is triggered by the local APIC, so the APIC IRQ handling | |
1675 | * rules apply: | |
1676 | */ | |
a3288106 | 1677 | static int intel_pmu_handle_irq(struct pt_regs *regs) |
241771ef | 1678 | { |
df1a132b | 1679 | struct perf_sample_data data; |
9029a5e3 | 1680 | struct cpu_hw_counters *cpuc; |
11d1578f | 1681 | int bit, loops; |
4b39fd96 | 1682 | u64 ack, status; |
9029a5e3 | 1683 | |
df1a132b PZ |
1684 | data.addr = 0; |
1685 | ||
11d1578f | 1686 | cpuc = &__get_cpu_var(cpu_hw_counters); |
241771ef | 1687 | |
9e35ad38 | 1688 | perf_disable(); |
5622f295 | 1689 | intel_pmu_drain_bts_buffer(cpuc); |
19d84dab | 1690 | status = intel_pmu_get_status(); |
9e35ad38 PZ |
1691 | if (!status) { |
1692 | perf_enable(); | |
1693 | return 0; | |
1694 | } | |
87b9cf46 | 1695 | |
9029a5e3 | 1696 | loops = 0; |
241771ef | 1697 | again: |
9029a5e3 IM |
1698 | if (++loops > 100) { |
1699 | WARN_ONCE(1, "perfcounters: irq loop stuck!\n"); | |
34adc806 | 1700 | perf_counter_print_debug(); |
aaba9801 IM |
1701 | intel_pmu_reset(); |
1702 | perf_enable(); | |
9029a5e3 IM |
1703 | return 1; |
1704 | } | |
1705 | ||
d278c484 | 1706 | inc_irq_stat(apic_perf_irqs); |
241771ef | 1707 | ack = status; |
2f18d1e8 | 1708 | for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { |
862a1a5f | 1709 | struct perf_counter *counter = cpuc->counters[bit]; |
241771ef IM |
1710 | |
1711 | clear_bit(bit, (unsigned long *) &status); | |
43f6201a | 1712 | if (!test_bit(bit, cpuc->active_mask)) |
241771ef IM |
1713 | continue; |
1714 | ||
e4abb5d4 PZ |
1715 | if (!intel_pmu_save_and_restart(counter)) |
1716 | continue; | |
1717 | ||
60f916de PZ |
1718 | data.period = counter->hw.last_period; |
1719 | ||
5622f295 | 1720 | if (perf_counter_overflow(counter, 1, &data, regs)) |
d4369891 | 1721 | intel_pmu_disable_counter(&counter->hw, bit); |
241771ef IM |
1722 | } |
1723 | ||
dee5d906 | 1724 | intel_pmu_ack_status(ack); |
241771ef IM |
1725 | |
1726 | /* | |
1727 | * Repeat if there is more work to be done: | |
1728 | */ | |
19d84dab | 1729 | status = intel_pmu_get_status(); |
241771ef IM |
1730 | if (status) |
1731 | goto again; | |
b0f3f28e | 1732 | |
48e22d56 | 1733 | perf_enable(); |
9e35ad38 PZ |
1734 | |
1735 | return 1; | |
1b023a96 MG |
1736 | } |
1737 | ||
a3288106 | 1738 | static int amd_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1739 | { |
df1a132b | 1740 | struct perf_sample_data data; |
9029a5e3 | 1741 | struct cpu_hw_counters *cpuc; |
a29aa8a7 RR |
1742 | struct perf_counter *counter; |
1743 | struct hw_perf_counter *hwc; | |
11d1578f | 1744 | int idx, handled = 0; |
9029a5e3 IM |
1745 | u64 val; |
1746 | ||
df1a132b PZ |
1747 | data.addr = 0; |
1748 | ||
11d1578f | 1749 | cpuc = &__get_cpu_var(cpu_hw_counters); |
962bf7a6 | 1750 | |
a29aa8a7 | 1751 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
43f6201a | 1752 | if (!test_bit(idx, cpuc->active_mask)) |
a29aa8a7 | 1753 | continue; |
962bf7a6 | 1754 | |
a29aa8a7 RR |
1755 | counter = cpuc->counters[idx]; |
1756 | hwc = &counter->hw; | |
a4016a79 | 1757 | |
4b7bfd0d | 1758 | val = x86_perf_counter_update(counter, hwc, idx); |
a29aa8a7 | 1759 | if (val & (1ULL << (x86_pmu.counter_bits - 1))) |
48e22d56 | 1760 | continue; |
962bf7a6 | 1761 | |
9e350de3 PZ |
1762 | /* |
1763 | * counter overflow | |
1764 | */ | |
1765 | handled = 1; | |
1766 | data.period = counter->hw.last_period; | |
1767 | ||
e4abb5d4 PZ |
1768 | if (!x86_perf_counter_set_period(counter, hwc, idx)) |
1769 | continue; | |
1770 | ||
5622f295 | 1771 | if (perf_counter_overflow(counter, 1, &data, regs)) |
a29aa8a7 | 1772 | amd_pmu_disable_counter(hwc, idx); |
a29aa8a7 | 1773 | } |
962bf7a6 | 1774 | |
9e350de3 PZ |
1775 | if (handled) |
1776 | inc_irq_stat(apic_perf_irqs); | |
1777 | ||
a29aa8a7 RR |
1778 | return handled; |
1779 | } | |
39d81eab | 1780 | |
b6276f35 PZ |
1781 | void smp_perf_pending_interrupt(struct pt_regs *regs) |
1782 | { | |
1783 | irq_enter(); | |
1784 | ack_APIC_irq(); | |
1785 | inc_irq_stat(apic_pending_irqs); | |
1786 | perf_counter_do_pending(); | |
1787 | irq_exit(); | |
1788 | } | |
1789 | ||
1790 | void set_perf_counter_pending(void) | |
1791 | { | |
04da8a43 | 1792 | #ifdef CONFIG_X86_LOCAL_APIC |
b6276f35 | 1793 | apic->send_IPI_self(LOCAL_PENDING_VECTOR); |
04da8a43 | 1794 | #endif |
b6276f35 PZ |
1795 | } |
1796 | ||
c323d95f | 1797 | void perf_counters_lapic_init(void) |
241771ef | 1798 | { |
04da8a43 IM |
1799 | #ifdef CONFIG_X86_LOCAL_APIC |
1800 | if (!x86_pmu.apic || !x86_pmu_initialized()) | |
241771ef | 1801 | return; |
85cf9dba | 1802 | |
241771ef | 1803 | /* |
c323d95f | 1804 | * Always use NMI for PMU |
241771ef | 1805 | */ |
c323d95f | 1806 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
04da8a43 | 1807 | #endif |
241771ef IM |
1808 | } |
1809 | ||
1810 | static int __kprobes | |
1811 | perf_counter_nmi_handler(struct notifier_block *self, | |
1812 | unsigned long cmd, void *__args) | |
1813 | { | |
1814 | struct die_args *args = __args; | |
1815 | struct pt_regs *regs; | |
b0f3f28e | 1816 | |
ba77813a | 1817 | if (!atomic_read(&active_counters)) |
63a809a2 PZ |
1818 | return NOTIFY_DONE; |
1819 | ||
b0f3f28e PZ |
1820 | switch (cmd) { |
1821 | case DIE_NMI: | |
1822 | case DIE_NMI_IPI: | |
1823 | break; | |
241771ef | 1824 | |
b0f3f28e | 1825 | default: |
241771ef | 1826 | return NOTIFY_DONE; |
b0f3f28e | 1827 | } |
241771ef IM |
1828 | |
1829 | regs = args->regs; | |
1830 | ||
04da8a43 | 1831 | #ifdef CONFIG_X86_LOCAL_APIC |
241771ef | 1832 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
04da8a43 | 1833 | #endif |
a4016a79 PZ |
1834 | /* |
1835 | * Can't rely on the handled return value to say it was our NMI, two | |
1836 | * counters could trigger 'simultaneously' raising two back-to-back NMIs. | |
1837 | * | |
1838 | * If the first NMI handles both, the latter will be empty and daze | |
1839 | * the CPU. | |
1840 | */ | |
a3288106 | 1841 | x86_pmu.handle_irq(regs); |
241771ef | 1842 | |
a4016a79 | 1843 | return NOTIFY_STOP; |
241771ef IM |
1844 | } |
1845 | ||
1846 | static __read_mostly struct notifier_block perf_counter_nmi_notifier = { | |
5b75af0a MG |
1847 | .notifier_call = perf_counter_nmi_handler, |
1848 | .next = NULL, | |
1849 | .priority = 1 | |
241771ef IM |
1850 | }; |
1851 | ||
11d1578f VW |
1852 | static struct x86_pmu p6_pmu = { |
1853 | .name = "p6", | |
1854 | .handle_irq = p6_pmu_handle_irq, | |
1855 | .disable_all = p6_pmu_disable_all, | |
1856 | .enable_all = p6_pmu_enable_all, | |
1857 | .enable = p6_pmu_enable_counter, | |
1858 | .disable = p6_pmu_disable_counter, | |
1859 | .eventsel = MSR_P6_EVNTSEL0, | |
1860 | .perfctr = MSR_P6_PERFCTR0, | |
1861 | .event_map = p6_pmu_event_map, | |
1862 | .raw_event = p6_pmu_raw_event, | |
1863 | .max_events = ARRAY_SIZE(p6_perfmon_event_map), | |
04da8a43 | 1864 | .apic = 1, |
11d1578f VW |
1865 | .max_period = (1ULL << 31) - 1, |
1866 | .version = 0, | |
1867 | .num_counters = 2, | |
1868 | /* | |
1869 | * Counters have 40 bits implemented. However they are designed such | |
1870 | * that bits [32-39] are sign extensions of bit 31. As such the | |
1871 | * effective width of a counter for P6-like PMU is 32 bits only. | |
1872 | * | |
1873 | * See IA-32 Intel Architecture Software developer manual Vol 3B | |
1874 | */ | |
1875 | .counter_bits = 32, | |
1876 | .counter_mask = (1ULL << 32) - 1, | |
1877 | }; | |
1878 | ||
5f4ec28f | 1879 | static struct x86_pmu intel_pmu = { |
faa28ae0 | 1880 | .name = "Intel", |
39d81eab | 1881 | .handle_irq = intel_pmu_handle_irq, |
9e35ad38 PZ |
1882 | .disable_all = intel_pmu_disable_all, |
1883 | .enable_all = intel_pmu_enable_all, | |
5f4ec28f RR |
1884 | .enable = intel_pmu_enable_counter, |
1885 | .disable = intel_pmu_disable_counter, | |
b56a3802 JSR |
1886 | .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, |
1887 | .perfctr = MSR_ARCH_PERFMON_PERFCTR0, | |
5f4ec28f RR |
1888 | .event_map = intel_pmu_event_map, |
1889 | .raw_event = intel_pmu_raw_event, | |
b56a3802 | 1890 | .max_events = ARRAY_SIZE(intel_perfmon_event_map), |
04da8a43 | 1891 | .apic = 1, |
c619b8ff RR |
1892 | /* |
1893 | * Intel PMCs cannot be accessed sanely above 32 bit width, | |
1894 | * so we install an artificial 1<<31 period regardless of | |
1895 | * the generic counter period: | |
1896 | */ | |
1897 | .max_period = (1ULL << 31) - 1, | |
30dd568c MM |
1898 | .enable_bts = intel_pmu_enable_bts, |
1899 | .disable_bts = intel_pmu_disable_bts, | |
b56a3802 JSR |
1900 | }; |
1901 | ||
5f4ec28f | 1902 | static struct x86_pmu amd_pmu = { |
faa28ae0 | 1903 | .name = "AMD", |
39d81eab | 1904 | .handle_irq = amd_pmu_handle_irq, |
9e35ad38 PZ |
1905 | .disable_all = amd_pmu_disable_all, |
1906 | .enable_all = amd_pmu_enable_all, | |
5f4ec28f RR |
1907 | .enable = amd_pmu_enable_counter, |
1908 | .disable = amd_pmu_disable_counter, | |
f87ad35d JSR |
1909 | .eventsel = MSR_K7_EVNTSEL0, |
1910 | .perfctr = MSR_K7_PERFCTR0, | |
5f4ec28f RR |
1911 | .event_map = amd_pmu_event_map, |
1912 | .raw_event = amd_pmu_raw_event, | |
f87ad35d | 1913 | .max_events = ARRAY_SIZE(amd_perfmon_event_map), |
0933e5c6 RR |
1914 | .num_counters = 4, |
1915 | .counter_bits = 48, | |
1916 | .counter_mask = (1ULL << 48) - 1, | |
04da8a43 | 1917 | .apic = 1, |
c619b8ff RR |
1918 | /* use highest bit to detect overflow */ |
1919 | .max_period = (1ULL << 47) - 1, | |
f87ad35d JSR |
1920 | }; |
1921 | ||
11d1578f VW |
1922 | static int p6_pmu_init(void) |
1923 | { | |
11d1578f VW |
1924 | switch (boot_cpu_data.x86_model) { |
1925 | case 1: | |
1926 | case 3: /* Pentium Pro */ | |
1927 | case 5: | |
1928 | case 6: /* Pentium II */ | |
1929 | case 7: | |
1930 | case 8: | |
1931 | case 11: /* Pentium III */ | |
1932 | break; | |
1933 | case 9: | |
1934 | case 13: | |
f1c6a581 DQ |
1935 | /* Pentium M */ |
1936 | break; | |
11d1578f VW |
1937 | default: |
1938 | pr_cont("unsupported p6 CPU model %d ", | |
1939 | boot_cpu_data.x86_model); | |
1940 | return -ENODEV; | |
1941 | } | |
1942 | ||
04da8a43 IM |
1943 | x86_pmu = p6_pmu; |
1944 | ||
11d1578f | 1945 | if (!cpu_has_apic) { |
3c581a7f | 1946 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); |
04da8a43 IM |
1947 | pr_info("no hardware sampling interrupt available.\n"); |
1948 | x86_pmu.apic = 0; | |
11d1578f VW |
1949 | } |
1950 | ||
11d1578f VW |
1951 | return 0; |
1952 | } | |
1953 | ||
72eae04d | 1954 | static int intel_pmu_init(void) |
241771ef | 1955 | { |
7bb497bd | 1956 | union cpuid10_edx edx; |
241771ef | 1957 | union cpuid10_eax eax; |
703e937c | 1958 | unsigned int unused; |
7bb497bd | 1959 | unsigned int ebx; |
faa28ae0 | 1960 | int version; |
241771ef | 1961 | |
11d1578f VW |
1962 | if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { |
1963 | /* check for P6 processor family */ | |
1964 | if (boot_cpu_data.x86 == 6) { | |
1965 | return p6_pmu_init(); | |
1966 | } else { | |
72eae04d | 1967 | return -ENODEV; |
11d1578f VW |
1968 | } |
1969 | } | |
da1a776b | 1970 | |
241771ef IM |
1971 | /* |
1972 | * Check whether the Architectural PerfMon supports | |
dfc65094 | 1973 | * Branch Misses Retired hw_event or not. |
241771ef | 1974 | */ |
703e937c | 1975 | cpuid(10, &eax.full, &ebx, &unused, &edx.full); |
241771ef | 1976 | if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED) |
72eae04d | 1977 | return -ENODEV; |
241771ef | 1978 | |
faa28ae0 RR |
1979 | version = eax.split.version_id; |
1980 | if (version < 2) | |
72eae04d | 1981 | return -ENODEV; |
7bb497bd | 1982 | |
1123e3ad IM |
1983 | x86_pmu = intel_pmu; |
1984 | x86_pmu.version = version; | |
1985 | x86_pmu.num_counters = eax.split.num_counters; | |
1986 | x86_pmu.counter_bits = eax.split.bit_width; | |
1987 | x86_pmu.counter_mask = (1ULL << eax.split.bit_width) - 1; | |
066d7dea IM |
1988 | |
1989 | /* | |
1990 | * Quirk: v2 perfmon does not report fixed-purpose counters, so | |
1991 | * assume at least 3 counters: | |
1992 | */ | |
1123e3ad | 1993 | x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3); |
b56a3802 | 1994 | |
8326f44d | 1995 | /* |
1123e3ad | 1996 | * Install the hw-cache-events table: |
8326f44d IM |
1997 | */ |
1998 | switch (boot_cpu_data.x86_model) { | |
dc81081b YW |
1999 | case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */ |
2000 | case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */ | |
2001 | case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */ | |
2002 | case 29: /* six-core 45 nm xeon "Dunnington" */ | |
8326f44d | 2003 | memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, |
820a6442 | 2004 | sizeof(hw_cache_event_ids)); |
8326f44d | 2005 | |
1123e3ad | 2006 | pr_cont("Core2 events, "); |
8326f44d IM |
2007 | break; |
2008 | default: | |
2009 | case 26: | |
2010 | memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, | |
820a6442 | 2011 | sizeof(hw_cache_event_ids)); |
8326f44d | 2012 | |
1123e3ad | 2013 | pr_cont("Nehalem/Corei7 events, "); |
8326f44d IM |
2014 | break; |
2015 | case 28: | |
2016 | memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, | |
820a6442 | 2017 | sizeof(hw_cache_event_ids)); |
8326f44d | 2018 | |
1123e3ad | 2019 | pr_cont("Atom events, "); |
8326f44d IM |
2020 | break; |
2021 | } | |
72eae04d | 2022 | return 0; |
b56a3802 JSR |
2023 | } |
2024 | ||
72eae04d | 2025 | static int amd_pmu_init(void) |
f87ad35d | 2026 | { |
4d2be126 JSR |
2027 | /* Performance-monitoring supported from K7 and later: */ |
2028 | if (boot_cpu_data.x86 < 6) | |
2029 | return -ENODEV; | |
2030 | ||
4a06bd85 | 2031 | x86_pmu = amd_pmu; |
f86748e9 | 2032 | |
f4db43a3 JSR |
2033 | /* Events are common for all AMDs */ |
2034 | memcpy(hw_cache_event_ids, amd_hw_cache_event_ids, | |
2035 | sizeof(hw_cache_event_ids)); | |
f86748e9 | 2036 | |
72eae04d | 2037 | return 0; |
f87ad35d JSR |
2038 | } |
2039 | ||
b56a3802 JSR |
2040 | void __init init_hw_perf_counters(void) |
2041 | { | |
72eae04d RR |
2042 | int err; |
2043 | ||
1123e3ad IM |
2044 | pr_info("Performance Counters: "); |
2045 | ||
b56a3802 JSR |
2046 | switch (boot_cpu_data.x86_vendor) { |
2047 | case X86_VENDOR_INTEL: | |
72eae04d | 2048 | err = intel_pmu_init(); |
b56a3802 | 2049 | break; |
f87ad35d | 2050 | case X86_VENDOR_AMD: |
72eae04d | 2051 | err = amd_pmu_init(); |
f87ad35d | 2052 | break; |
4138960a RR |
2053 | default: |
2054 | return; | |
b56a3802 | 2055 | } |
1123e3ad IM |
2056 | if (err != 0) { |
2057 | pr_cont("no PMU driver, software counters only.\n"); | |
b56a3802 | 2058 | return; |
1123e3ad | 2059 | } |
b56a3802 | 2060 | |
1123e3ad | 2061 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 2062 | |
0933e5c6 | 2063 | if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) { |
241771ef | 2064 | WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!", |
0933e5c6 | 2065 | x86_pmu.num_counters, X86_PMC_MAX_GENERIC); |
4078c444 | 2066 | x86_pmu.num_counters = X86_PMC_MAX_GENERIC; |
241771ef | 2067 | } |
0933e5c6 RR |
2068 | perf_counter_mask = (1 << x86_pmu.num_counters) - 1; |
2069 | perf_max_counters = x86_pmu.num_counters; | |
241771ef | 2070 | |
0933e5c6 | 2071 | if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { |
703e937c | 2072 | WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!", |
0933e5c6 | 2073 | x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED); |
4078c444 | 2074 | x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; |
703e937c | 2075 | } |
862a1a5f | 2076 | |
0933e5c6 RR |
2077 | perf_counter_mask |= |
2078 | ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED; | |
c14dab5c | 2079 | x86_pmu.intel_ctrl = perf_counter_mask; |
241771ef | 2080 | |
c323d95f | 2081 | perf_counters_lapic_init(); |
241771ef | 2082 | register_die_notifier(&perf_counter_nmi_notifier); |
1123e3ad IM |
2083 | |
2084 | pr_info("... version: %d\n", x86_pmu.version); | |
2085 | pr_info("... bit width: %d\n", x86_pmu.counter_bits); | |
2086 | pr_info("... generic counters: %d\n", x86_pmu.num_counters); | |
2087 | pr_info("... value mask: %016Lx\n", x86_pmu.counter_mask); | |
2088 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); | |
2089 | pr_info("... fixed-purpose counters: %d\n", x86_pmu.num_counters_fixed); | |
2090 | pr_info("... counter mask: %016Lx\n", perf_counter_mask); | |
241771ef | 2091 | } |
621a01ea | 2092 | |
bb775fc2 | 2093 | static inline void x86_pmu_read(struct perf_counter *counter) |
ee06094f IM |
2094 | { |
2095 | x86_perf_counter_update(counter, &counter->hw, counter->hw.idx); | |
2096 | } | |
2097 | ||
4aeb0b42 RR |
2098 | static const struct pmu pmu = { |
2099 | .enable = x86_pmu_enable, | |
2100 | .disable = x86_pmu_disable, | |
2101 | .read = x86_pmu_read, | |
a78ac325 | 2102 | .unthrottle = x86_pmu_unthrottle, |
621a01ea IM |
2103 | }; |
2104 | ||
4aeb0b42 | 2105 | const struct pmu *hw_perf_counter_init(struct perf_counter *counter) |
621a01ea IM |
2106 | { |
2107 | int err; | |
2108 | ||
2109 | err = __hw_perf_counter_init(counter); | |
a1792cda PZ |
2110 | if (err) { |
2111 | if (counter->destroy) | |
2112 | counter->destroy(counter); | |
9ea98e19 | 2113 | return ERR_PTR(err); |
a1792cda | 2114 | } |
621a01ea | 2115 | |
4aeb0b42 | 2116 | return &pmu; |
621a01ea | 2117 | } |
d7d59fb3 PZ |
2118 | |
2119 | /* | |
2120 | * callchain support | |
2121 | */ | |
2122 | ||
2123 | static inline | |
f9188e02 | 2124 | void callchain_store(struct perf_callchain_entry *entry, u64 ip) |
d7d59fb3 | 2125 | { |
f9188e02 | 2126 | if (entry->nr < PERF_MAX_STACK_DEPTH) |
d7d59fb3 PZ |
2127 | entry->ip[entry->nr++] = ip; |
2128 | } | |
2129 | ||
245b2e70 TH |
2130 | static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry); |
2131 | static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry); | |
0406ca6d | 2132 | static DEFINE_PER_CPU(int, in_nmi_frame); |
d7d59fb3 PZ |
2133 | |
2134 | ||
2135 | static void | |
2136 | backtrace_warning_symbol(void *data, char *msg, unsigned long symbol) | |
2137 | { | |
2138 | /* Ignore warnings */ | |
2139 | } | |
2140 | ||
2141 | static void backtrace_warning(void *data, char *msg) | |
2142 | { | |
2143 | /* Ignore warnings */ | |
2144 | } | |
2145 | ||
2146 | static int backtrace_stack(void *data, char *name) | |
2147 | { | |
0406ca6d FW |
2148 | per_cpu(in_nmi_frame, smp_processor_id()) = |
2149 | x86_is_stack_id(NMI_STACK, name); | |
2150 | ||
038e836e | 2151 | return 0; |
d7d59fb3 PZ |
2152 | } |
2153 | ||
2154 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
2155 | { | |
2156 | struct perf_callchain_entry *entry = data; | |
2157 | ||
0406ca6d FW |
2158 | if (per_cpu(in_nmi_frame, smp_processor_id())) |
2159 | return; | |
2160 | ||
d7d59fb3 PZ |
2161 | if (reliable) |
2162 | callchain_store(entry, addr); | |
2163 | } | |
2164 | ||
2165 | static const struct stacktrace_ops backtrace_ops = { | |
2166 | .warning = backtrace_warning, | |
2167 | .warning_symbol = backtrace_warning_symbol, | |
2168 | .stack = backtrace_stack, | |
2169 | .address = backtrace_address, | |
2170 | }; | |
2171 | ||
038e836e IM |
2172 | #include "../dumpstack.h" |
2173 | ||
d7d59fb3 PZ |
2174 | static void |
2175 | perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
2176 | { | |
f9188e02 | 2177 | callchain_store(entry, PERF_CONTEXT_KERNEL); |
038e836e | 2178 | callchain_store(entry, regs->ip); |
d7d59fb3 | 2179 | |
f9188e02 | 2180 | dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry); |
d7d59fb3 PZ |
2181 | } |
2182 | ||
74193ef0 PZ |
2183 | /* |
2184 | * best effort, GUP based copy_from_user() that assumes IRQ or NMI context | |
2185 | */ | |
2186 | static unsigned long | |
2187 | copy_from_user_nmi(void *to, const void __user *from, unsigned long n) | |
d7d59fb3 | 2188 | { |
74193ef0 PZ |
2189 | unsigned long offset, addr = (unsigned long)from; |
2190 | int type = in_nmi() ? KM_NMI : KM_IRQ0; | |
2191 | unsigned long size, len = 0; | |
2192 | struct page *page; | |
2193 | void *map; | |
d7d59fb3 PZ |
2194 | int ret; |
2195 | ||
74193ef0 PZ |
2196 | do { |
2197 | ret = __get_user_pages_fast(addr, 1, 0, &page); | |
2198 | if (!ret) | |
2199 | break; | |
d7d59fb3 | 2200 | |
74193ef0 PZ |
2201 | offset = addr & (PAGE_SIZE - 1); |
2202 | size = min(PAGE_SIZE - offset, n - len); | |
d7d59fb3 | 2203 | |
74193ef0 PZ |
2204 | map = kmap_atomic(page, type); |
2205 | memcpy(to, map+offset, size); | |
2206 | kunmap_atomic(map, type); | |
2207 | put_page(page); | |
2208 | ||
2209 | len += size; | |
2210 | to += size; | |
2211 | addr += size; | |
2212 | ||
2213 | } while (len < n); | |
2214 | ||
2215 | return len; | |
2216 | } | |
2217 | ||
2218 | static int copy_stack_frame(const void __user *fp, struct stack_frame *frame) | |
2219 | { | |
2220 | unsigned long bytes; | |
2221 | ||
2222 | bytes = copy_from_user_nmi(frame, fp, sizeof(*frame)); | |
2223 | ||
2224 | return bytes == sizeof(*frame); | |
d7d59fb3 PZ |
2225 | } |
2226 | ||
2227 | static void | |
2228 | perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
2229 | { | |
2230 | struct stack_frame frame; | |
2231 | const void __user *fp; | |
2232 | ||
5a6cec3a IM |
2233 | if (!user_mode(regs)) |
2234 | regs = task_pt_regs(current); | |
2235 | ||
74193ef0 | 2236 | fp = (void __user *)regs->bp; |
d7d59fb3 | 2237 | |
f9188e02 | 2238 | callchain_store(entry, PERF_CONTEXT_USER); |
d7d59fb3 PZ |
2239 | callchain_store(entry, regs->ip); |
2240 | ||
f9188e02 | 2241 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
038e836e | 2242 | frame.next_frame = NULL; |
d7d59fb3 PZ |
2243 | frame.return_address = 0; |
2244 | ||
2245 | if (!copy_stack_frame(fp, &frame)) | |
2246 | break; | |
2247 | ||
5a6cec3a | 2248 | if ((unsigned long)fp < regs->sp) |
d7d59fb3 PZ |
2249 | break; |
2250 | ||
2251 | callchain_store(entry, frame.return_address); | |
038e836e | 2252 | fp = frame.next_frame; |
d7d59fb3 PZ |
2253 | } |
2254 | } | |
2255 | ||
2256 | static void | |
2257 | perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
2258 | { | |
2259 | int is_user; | |
2260 | ||
2261 | if (!regs) | |
2262 | return; | |
2263 | ||
2264 | is_user = user_mode(regs); | |
2265 | ||
2266 | if (!current || current->pid == 0) | |
2267 | return; | |
2268 | ||
2269 | if (is_user && current->state != TASK_RUNNING) | |
2270 | return; | |
2271 | ||
2272 | if (!is_user) | |
2273 | perf_callchain_kernel(regs, entry); | |
2274 | ||
2275 | if (current->mm) | |
2276 | perf_callchain_user(regs, entry); | |
2277 | } | |
2278 | ||
2279 | struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) | |
2280 | { | |
2281 | struct perf_callchain_entry *entry; | |
2282 | ||
2283 | if (in_nmi()) | |
245b2e70 | 2284 | entry = &__get_cpu_var(pmc_nmi_entry); |
d7d59fb3 | 2285 | else |
245b2e70 | 2286 | entry = &__get_cpu_var(pmc_irq_entry); |
d7d59fb3 PZ |
2287 | |
2288 | entry->nr = 0; | |
2289 | ||
2290 | perf_do_callchain(regs, entry); | |
2291 | ||
2292 | return entry; | |
2293 | } | |
30dd568c MM |
2294 | |
2295 | void hw_perf_counter_setup_online(int cpu) | |
2296 | { | |
2297 | init_debug_store_on_cpu(cpu); | |
2298 | } |