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Commit | Line | Data |
---|---|---|
241771ef | 1 | /* |
cdd6c482 | 2 | * Performance events x86 architecture code |
241771ef | 3 | * |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
1da53e02 | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
241771ef IM |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
241771ef IM |
16 | #include <linux/capability.h> |
17 | #include <linux/notifier.h> | |
18 | #include <linux/hardirq.h> | |
19 | #include <linux/kprobes.h> | |
4ac13294 | 20 | #include <linux/module.h> |
241771ef IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/sched.h> | |
d7d59fb3 | 23 | #include <linux/uaccess.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
30dd568c | 25 | #include <linux/cpu.h> |
272d30be | 26 | #include <linux/bitops.h> |
0c9d42ed | 27 | #include <linux/device.h> |
241771ef | 28 | |
241771ef | 29 | #include <asm/apic.h> |
d7d59fb3 | 30 | #include <asm/stacktrace.h> |
4e935e47 | 31 | #include <asm/nmi.h> |
69092624 | 32 | #include <asm/smp.h> |
c8e5910e | 33 | #include <asm/alternative.h> |
e3f3541c | 34 | #include <asm/timer.h> |
241771ef | 35 | |
de0428a7 KW |
36 | #include "perf_event.h" |
37 | ||
7645a24c PZ |
38 | #if 0 |
39 | #undef wrmsrl | |
40 | #define wrmsrl(msr, val) \ | |
41 | do { \ | |
42 | trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\ | |
43 | (unsigned long)(val)); \ | |
44 | native_write_msr((msr), (u32)((u64)(val)), \ | |
45 | (u32)((u64)(val) >> 32)); \ | |
46 | } while (0) | |
47 | #endif | |
48 | ||
de0428a7 | 49 | struct x86_pmu x86_pmu __read_mostly; |
efc9f05d | 50 | |
de0428a7 | 51 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
b0f3f28e PZ |
52 | .enabled = 1, |
53 | }; | |
241771ef | 54 | |
de0428a7 | 55 | u64 __read_mostly hw_cache_event_ids |
8326f44d IM |
56 | [PERF_COUNT_HW_CACHE_MAX] |
57 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
58 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
de0428a7 | 59 | u64 __read_mostly hw_cache_extra_regs |
e994d7d2 AK |
60 | [PERF_COUNT_HW_CACHE_MAX] |
61 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
62 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
8326f44d | 63 | |
ee06094f | 64 | /* |
cdd6c482 IM |
65 | * Propagate event elapsed time into the generic event. |
66 | * Can only be executed on the CPU where the event is active. | |
ee06094f IM |
67 | * Returns the delta events processed. |
68 | */ | |
de0428a7 | 69 | u64 x86_perf_event_update(struct perf_event *event) |
ee06094f | 70 | { |
cc2ad4ba | 71 | struct hw_perf_event *hwc = &event->hw; |
948b1bb8 | 72 | int shift = 64 - x86_pmu.cntval_bits; |
ec3232bd | 73 | u64 prev_raw_count, new_raw_count; |
cc2ad4ba | 74 | int idx = hwc->idx; |
ec3232bd | 75 | s64 delta; |
ee06094f | 76 | |
30dd568c MM |
77 | if (idx == X86_PMC_IDX_FIXED_BTS) |
78 | return 0; | |
79 | ||
ee06094f | 80 | /* |
cdd6c482 | 81 | * Careful: an NMI might modify the previous event value. |
ee06094f IM |
82 | * |
83 | * Our tactic to handle this is to first atomically read and | |
84 | * exchange a new raw count - then add that new-prev delta | |
cdd6c482 | 85 | * count to the generic event atomically: |
ee06094f IM |
86 | */ |
87 | again: | |
e7850595 | 88 | prev_raw_count = local64_read(&hwc->prev_count); |
73d6e522 | 89 | rdmsrl(hwc->event_base, new_raw_count); |
ee06094f | 90 | |
e7850595 | 91 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
ee06094f IM |
92 | new_raw_count) != prev_raw_count) |
93 | goto again; | |
94 | ||
95 | /* | |
96 | * Now we have the new raw value and have updated the prev | |
97 | * timestamp already. We can now calculate the elapsed delta | |
cdd6c482 | 98 | * (event-)time and add that to the generic event. |
ee06094f IM |
99 | * |
100 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 101 | * of the count. |
ee06094f | 102 | */ |
ec3232bd PZ |
103 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
104 | delta >>= shift; | |
ee06094f | 105 | |
e7850595 PZ |
106 | local64_add(delta, &event->count); |
107 | local64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
108 | |
109 | return new_raw_count; | |
ee06094f IM |
110 | } |
111 | ||
a7e3ed1e AK |
112 | /* |
113 | * Find and validate any extra registers to set up. | |
114 | */ | |
115 | static int x86_pmu_extra_regs(u64 config, struct perf_event *event) | |
116 | { | |
efc9f05d | 117 | struct hw_perf_event_extra *reg; |
a7e3ed1e AK |
118 | struct extra_reg *er; |
119 | ||
efc9f05d | 120 | reg = &event->hw.extra_reg; |
a7e3ed1e AK |
121 | |
122 | if (!x86_pmu.extra_regs) | |
123 | return 0; | |
124 | ||
125 | for (er = x86_pmu.extra_regs; er->msr; er++) { | |
126 | if (er->event != (config & er->config_mask)) | |
127 | continue; | |
128 | if (event->attr.config1 & ~er->valid_mask) | |
129 | return -EINVAL; | |
efc9f05d SE |
130 | |
131 | reg->idx = er->idx; | |
132 | reg->config = event->attr.config1; | |
133 | reg->reg = er->msr; | |
a7e3ed1e AK |
134 | break; |
135 | } | |
136 | return 0; | |
137 | } | |
138 | ||
cdd6c482 | 139 | static atomic_t active_events; |
4e935e47 PZ |
140 | static DEFINE_MUTEX(pmc_reserve_mutex); |
141 | ||
b27ea29c RR |
142 | #ifdef CONFIG_X86_LOCAL_APIC |
143 | ||
4e935e47 PZ |
144 | static bool reserve_pmc_hardware(void) |
145 | { | |
146 | int i; | |
147 | ||
948b1bb8 | 148 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 149 | if (!reserve_perfctr_nmi(x86_pmu_event_addr(i))) |
4e935e47 PZ |
150 | goto perfctr_fail; |
151 | } | |
152 | ||
948b1bb8 | 153 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 154 | if (!reserve_evntsel_nmi(x86_pmu_config_addr(i))) |
4e935e47 PZ |
155 | goto eventsel_fail; |
156 | } | |
157 | ||
158 | return true; | |
159 | ||
160 | eventsel_fail: | |
161 | for (i--; i >= 0; i--) | |
41bf4989 | 162 | release_evntsel_nmi(x86_pmu_config_addr(i)); |
4e935e47 | 163 | |
948b1bb8 | 164 | i = x86_pmu.num_counters; |
4e935e47 PZ |
165 | |
166 | perfctr_fail: | |
167 | for (i--; i >= 0; i--) | |
41bf4989 | 168 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
4e935e47 | 169 | |
4e935e47 PZ |
170 | return false; |
171 | } | |
172 | ||
173 | static void release_pmc_hardware(void) | |
174 | { | |
175 | int i; | |
176 | ||
948b1bb8 | 177 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 RR |
178 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
179 | release_evntsel_nmi(x86_pmu_config_addr(i)); | |
4e935e47 | 180 | } |
4e935e47 PZ |
181 | } |
182 | ||
b27ea29c RR |
183 | #else |
184 | ||
185 | static bool reserve_pmc_hardware(void) { return true; } | |
186 | static void release_pmc_hardware(void) {} | |
187 | ||
188 | #endif | |
189 | ||
33c6d6a7 DZ |
190 | static bool check_hw_exists(void) |
191 | { | |
192 | u64 val, val_new = 0; | |
4407204c | 193 | int i, reg, ret = 0; |
33c6d6a7 | 194 | |
4407204c PZ |
195 | /* |
196 | * Check to see if the BIOS enabled any of the counters, if so | |
197 | * complain and bail. | |
198 | */ | |
199 | for (i = 0; i < x86_pmu.num_counters; i++) { | |
41bf4989 | 200 | reg = x86_pmu_config_addr(i); |
4407204c PZ |
201 | ret = rdmsrl_safe(reg, &val); |
202 | if (ret) | |
203 | goto msr_fail; | |
204 | if (val & ARCH_PERFMON_EVENTSEL_ENABLE) | |
205 | goto bios_fail; | |
206 | } | |
207 | ||
208 | if (x86_pmu.num_counters_fixed) { | |
209 | reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
210 | ret = rdmsrl_safe(reg, &val); | |
211 | if (ret) | |
212 | goto msr_fail; | |
213 | for (i = 0; i < x86_pmu.num_counters_fixed; i++) { | |
214 | if (val & (0x03 << i*4)) | |
215 | goto bios_fail; | |
216 | } | |
217 | } | |
218 | ||
219 | /* | |
220 | * Now write a value and read it back to see if it matches, | |
221 | * this is needed to detect certain hardware emulators (qemu/kvm) | |
222 | * that don't trap on the MSR access and always return 0s. | |
223 | */ | |
33c6d6a7 | 224 | val = 0xabcdUL; |
41bf4989 RR |
225 | ret = checking_wrmsrl(x86_pmu_event_addr(0), val); |
226 | ret |= rdmsrl_safe(x86_pmu_event_addr(0), &val_new); | |
33c6d6a7 | 227 | if (ret || val != val_new) |
4407204c | 228 | goto msr_fail; |
33c6d6a7 DZ |
229 | |
230 | return true; | |
4407204c PZ |
231 | |
232 | bios_fail: | |
45daae57 IM |
233 | /* |
234 | * We still allow the PMU driver to operate: | |
235 | */ | |
236 | printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n"); | |
4407204c | 237 | printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg, val); |
45daae57 IM |
238 | |
239 | return true; | |
4407204c PZ |
240 | |
241 | msr_fail: | |
242 | printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n"); | |
45daae57 | 243 | |
4407204c | 244 | return false; |
33c6d6a7 DZ |
245 | } |
246 | ||
cdd6c482 | 247 | static void hw_perf_event_destroy(struct perf_event *event) |
4e935e47 | 248 | { |
cdd6c482 | 249 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) { |
4e935e47 | 250 | release_pmc_hardware(); |
ca037701 | 251 | release_ds_buffers(); |
4e935e47 PZ |
252 | mutex_unlock(&pmc_reserve_mutex); |
253 | } | |
254 | } | |
255 | ||
85cf9dba RR |
256 | static inline int x86_pmu_initialized(void) |
257 | { | |
258 | return x86_pmu.handle_irq != NULL; | |
259 | } | |
260 | ||
8326f44d | 261 | static inline int |
e994d7d2 | 262 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) |
8326f44d | 263 | { |
e994d7d2 | 264 | struct perf_event_attr *attr = &event->attr; |
8326f44d IM |
265 | unsigned int cache_type, cache_op, cache_result; |
266 | u64 config, val; | |
267 | ||
268 | config = attr->config; | |
269 | ||
270 | cache_type = (config >> 0) & 0xff; | |
271 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
272 | return -EINVAL; | |
273 | ||
274 | cache_op = (config >> 8) & 0xff; | |
275 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
276 | return -EINVAL; | |
277 | ||
278 | cache_result = (config >> 16) & 0xff; | |
279 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
280 | return -EINVAL; | |
281 | ||
282 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
283 | ||
284 | if (val == 0) | |
285 | return -ENOENT; | |
286 | ||
287 | if (val == -1) | |
288 | return -EINVAL; | |
289 | ||
290 | hwc->config |= val; | |
e994d7d2 AK |
291 | attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result]; |
292 | return x86_pmu_extra_regs(val, event); | |
8326f44d IM |
293 | } |
294 | ||
de0428a7 | 295 | int x86_setup_perfctr(struct perf_event *event) |
c1726f34 RR |
296 | { |
297 | struct perf_event_attr *attr = &event->attr; | |
298 | struct hw_perf_event *hwc = &event->hw; | |
299 | u64 config; | |
300 | ||
6c7e550f | 301 | if (!is_sampling_event(event)) { |
c1726f34 RR |
302 | hwc->sample_period = x86_pmu.max_period; |
303 | hwc->last_period = hwc->sample_period; | |
e7850595 | 304 | local64_set(&hwc->period_left, hwc->sample_period); |
c1726f34 RR |
305 | } else { |
306 | /* | |
307 | * If we have a PMU initialized but no APIC | |
308 | * interrupts, we cannot sample hardware | |
309 | * events (user-space has to fall back and | |
310 | * sample via a hrtimer based software event): | |
311 | */ | |
312 | if (!x86_pmu.apic) | |
313 | return -EOPNOTSUPP; | |
314 | } | |
315 | ||
316 | if (attr->type == PERF_TYPE_RAW) | |
ed13ec58 | 317 | return x86_pmu_extra_regs(event->attr.config, event); |
c1726f34 RR |
318 | |
319 | if (attr->type == PERF_TYPE_HW_CACHE) | |
e994d7d2 | 320 | return set_ext_hw_attr(hwc, event); |
c1726f34 RR |
321 | |
322 | if (attr->config >= x86_pmu.max_events) | |
323 | return -EINVAL; | |
324 | ||
325 | /* | |
326 | * The generic map: | |
327 | */ | |
328 | config = x86_pmu.event_map(attr->config); | |
329 | ||
330 | if (config == 0) | |
331 | return -ENOENT; | |
332 | ||
333 | if (config == -1LL) | |
334 | return -EINVAL; | |
335 | ||
336 | /* | |
337 | * Branch tracing: | |
338 | */ | |
18a073a3 PZ |
339 | if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS && |
340 | !attr->freq && hwc->sample_period == 1) { | |
c1726f34 | 341 | /* BTS is not supported by this architecture. */ |
6809b6ea | 342 | if (!x86_pmu.bts_active) |
c1726f34 RR |
343 | return -EOPNOTSUPP; |
344 | ||
345 | /* BTS is currently only allowed for user-mode. */ | |
346 | if (!attr->exclude_kernel) | |
347 | return -EOPNOTSUPP; | |
348 | } | |
349 | ||
350 | hwc->config |= config; | |
351 | ||
352 | return 0; | |
353 | } | |
4261e0e0 | 354 | |
ff3fb511 SE |
355 | /* |
356 | * check that branch_sample_type is compatible with | |
357 | * settings needed for precise_ip > 1 which implies | |
358 | * using the LBR to capture ALL taken branches at the | |
359 | * priv levels of the measurement | |
360 | */ | |
361 | static inline int precise_br_compat(struct perf_event *event) | |
362 | { | |
363 | u64 m = event->attr.branch_sample_type; | |
364 | u64 b = 0; | |
365 | ||
366 | /* must capture all branches */ | |
367 | if (!(m & PERF_SAMPLE_BRANCH_ANY)) | |
368 | return 0; | |
369 | ||
370 | m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER; | |
371 | ||
372 | if (!event->attr.exclude_user) | |
373 | b |= PERF_SAMPLE_BRANCH_USER; | |
374 | ||
375 | if (!event->attr.exclude_kernel) | |
376 | b |= PERF_SAMPLE_BRANCH_KERNEL; | |
377 | ||
378 | /* | |
379 | * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86 | |
380 | */ | |
381 | ||
382 | return m == b; | |
383 | } | |
384 | ||
de0428a7 | 385 | int x86_pmu_hw_config(struct perf_event *event) |
a072738e | 386 | { |
ab608344 PZ |
387 | if (event->attr.precise_ip) { |
388 | int precise = 0; | |
389 | ||
390 | /* Support for constant skid */ | |
6809b6ea | 391 | if (x86_pmu.pebs_active) { |
ab608344 PZ |
392 | precise++; |
393 | ||
5553be26 PZ |
394 | /* Support for IP fixup */ |
395 | if (x86_pmu.lbr_nr) | |
396 | precise++; | |
397 | } | |
ab608344 PZ |
398 | |
399 | if (event->attr.precise_ip > precise) | |
400 | return -EOPNOTSUPP; | |
ff3fb511 SE |
401 | /* |
402 | * check that PEBS LBR correction does not conflict with | |
403 | * whatever the user is asking with attr->branch_sample_type | |
404 | */ | |
405 | if (event->attr.precise_ip > 1) { | |
406 | u64 *br_type = &event->attr.branch_sample_type; | |
407 | ||
408 | if (has_branch_stack(event)) { | |
409 | if (!precise_br_compat(event)) | |
410 | return -EOPNOTSUPP; | |
411 | ||
412 | /* branch_sample_type is compatible */ | |
413 | ||
414 | } else { | |
415 | /* | |
416 | * user did not specify branch_sample_type | |
417 | * | |
418 | * For PEBS fixups, we capture all | |
419 | * the branches at the priv level of the | |
420 | * event. | |
421 | */ | |
422 | *br_type = PERF_SAMPLE_BRANCH_ANY; | |
423 | ||
424 | if (!event->attr.exclude_user) | |
425 | *br_type |= PERF_SAMPLE_BRANCH_USER; | |
426 | ||
427 | if (!event->attr.exclude_kernel) | |
428 | *br_type |= PERF_SAMPLE_BRANCH_KERNEL; | |
429 | } | |
430 | } | |
ab608344 PZ |
431 | } |
432 | ||
a072738e CG |
433 | /* |
434 | * Generate PMC IRQs: | |
435 | * (keep 'enabled' bit clear for now) | |
436 | */ | |
b4cdc5c2 | 437 | event->hw.config = ARCH_PERFMON_EVENTSEL_INT; |
a072738e CG |
438 | |
439 | /* | |
440 | * Count user and OS events unless requested not to | |
441 | */ | |
b4cdc5c2 PZ |
442 | if (!event->attr.exclude_user) |
443 | event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; | |
444 | if (!event->attr.exclude_kernel) | |
445 | event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; | |
a072738e | 446 | |
b4cdc5c2 PZ |
447 | if (event->attr.type == PERF_TYPE_RAW) |
448 | event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; | |
a072738e | 449 | |
9d0fcba6 | 450 | return x86_setup_perfctr(event); |
a098f448 RR |
451 | } |
452 | ||
241771ef | 453 | /* |
0d48696f | 454 | * Setup the hardware configuration for a given attr_type |
241771ef | 455 | */ |
b0a873eb | 456 | static int __x86_pmu_event_init(struct perf_event *event) |
241771ef | 457 | { |
4e935e47 | 458 | int err; |
241771ef | 459 | |
85cf9dba RR |
460 | if (!x86_pmu_initialized()) |
461 | return -ENODEV; | |
241771ef | 462 | |
4e935e47 | 463 | err = 0; |
cdd6c482 | 464 | if (!atomic_inc_not_zero(&active_events)) { |
4e935e47 | 465 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 466 | if (atomic_read(&active_events) == 0) { |
30dd568c MM |
467 | if (!reserve_pmc_hardware()) |
468 | err = -EBUSY; | |
f80c9e30 PZ |
469 | else |
470 | reserve_ds_buffers(); | |
30dd568c MM |
471 | } |
472 | if (!err) | |
cdd6c482 | 473 | atomic_inc(&active_events); |
4e935e47 PZ |
474 | mutex_unlock(&pmc_reserve_mutex); |
475 | } | |
476 | if (err) | |
477 | return err; | |
478 | ||
cdd6c482 | 479 | event->destroy = hw_perf_event_destroy; |
a1792cda | 480 | |
4261e0e0 RR |
481 | event->hw.idx = -1; |
482 | event->hw.last_cpu = -1; | |
483 | event->hw.last_tag = ~0ULL; | |
b690081d | 484 | |
efc9f05d SE |
485 | /* mark unused */ |
486 | event->hw.extra_reg.idx = EXTRA_REG_NONE; | |
b36817e8 SE |
487 | event->hw.branch_reg.idx = EXTRA_REG_NONE; |
488 | ||
9d0fcba6 | 489 | return x86_pmu.hw_config(event); |
4261e0e0 RR |
490 | } |
491 | ||
de0428a7 | 492 | void x86_pmu_disable_all(void) |
f87ad35d | 493 | { |
cdd6c482 | 494 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
9e35ad38 PZ |
495 | int idx; |
496 | ||
948b1bb8 | 497 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
498 | u64 val; |
499 | ||
43f6201a | 500 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 501 | continue; |
41bf4989 | 502 | rdmsrl(x86_pmu_config_addr(idx), val); |
bb1165d6 | 503 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
4295ee62 | 504 | continue; |
bb1165d6 | 505 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
41bf4989 | 506 | wrmsrl(x86_pmu_config_addr(idx), val); |
f87ad35d | 507 | } |
f87ad35d JSR |
508 | } |
509 | ||
a4eaf7f1 | 510 | static void x86_pmu_disable(struct pmu *pmu) |
b56a3802 | 511 | { |
1da53e02 SE |
512 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
513 | ||
85cf9dba | 514 | if (!x86_pmu_initialized()) |
9e35ad38 | 515 | return; |
1da53e02 | 516 | |
1a6e21f7 PZ |
517 | if (!cpuc->enabled) |
518 | return; | |
519 | ||
520 | cpuc->n_added = 0; | |
521 | cpuc->enabled = 0; | |
522 | barrier(); | |
1da53e02 SE |
523 | |
524 | x86_pmu.disable_all(); | |
b56a3802 | 525 | } |
241771ef | 526 | |
de0428a7 | 527 | void x86_pmu_enable_all(int added) |
f87ad35d | 528 | { |
cdd6c482 | 529 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
f87ad35d JSR |
530 | int idx; |
531 | ||
948b1bb8 | 532 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
d45dd923 | 533 | struct hw_perf_event *hwc = &cpuc->events[idx]->hw; |
b0f3f28e | 534 | |
43f6201a | 535 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 536 | continue; |
984b838c | 537 | |
d45dd923 | 538 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); |
f87ad35d JSR |
539 | } |
540 | } | |
541 | ||
51b0fe39 | 542 | static struct pmu pmu; |
1da53e02 SE |
543 | |
544 | static inline int is_x86_event(struct perf_event *event) | |
545 | { | |
546 | return event->pmu == &pmu; | |
547 | } | |
548 | ||
1e2ad28f RR |
549 | /* |
550 | * Event scheduler state: | |
551 | * | |
552 | * Assign events iterating over all events and counters, beginning | |
553 | * with events with least weights first. Keep the current iterator | |
554 | * state in struct sched_state. | |
555 | */ | |
556 | struct sched_state { | |
557 | int weight; | |
558 | int event; /* event index */ | |
559 | int counter; /* counter index */ | |
560 | int unassigned; /* number of events to be assigned left */ | |
561 | unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
562 | }; | |
563 | ||
bc1738f6 RR |
564 | /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */ |
565 | #define SCHED_STATES_MAX 2 | |
566 | ||
1e2ad28f RR |
567 | struct perf_sched { |
568 | int max_weight; | |
569 | int max_events; | |
570 | struct event_constraint **constraints; | |
571 | struct sched_state state; | |
bc1738f6 RR |
572 | int saved_states; |
573 | struct sched_state saved[SCHED_STATES_MAX]; | |
1e2ad28f RR |
574 | }; |
575 | ||
576 | /* | |
577 | * Initialize interator that runs through all events and counters. | |
578 | */ | |
579 | static void perf_sched_init(struct perf_sched *sched, struct event_constraint **c, | |
580 | int num, int wmin, int wmax) | |
581 | { | |
582 | int idx; | |
583 | ||
584 | memset(sched, 0, sizeof(*sched)); | |
585 | sched->max_events = num; | |
586 | sched->max_weight = wmax; | |
587 | sched->constraints = c; | |
588 | ||
589 | for (idx = 0; idx < num; idx++) { | |
590 | if (c[idx]->weight == wmin) | |
591 | break; | |
592 | } | |
593 | ||
594 | sched->state.event = idx; /* start with min weight */ | |
595 | sched->state.weight = wmin; | |
596 | sched->state.unassigned = num; | |
597 | } | |
598 | ||
bc1738f6 RR |
599 | static void perf_sched_save_state(struct perf_sched *sched) |
600 | { | |
601 | if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX)) | |
602 | return; | |
603 | ||
604 | sched->saved[sched->saved_states] = sched->state; | |
605 | sched->saved_states++; | |
606 | } | |
607 | ||
608 | static bool perf_sched_restore_state(struct perf_sched *sched) | |
609 | { | |
610 | if (!sched->saved_states) | |
611 | return false; | |
612 | ||
613 | sched->saved_states--; | |
614 | sched->state = sched->saved[sched->saved_states]; | |
615 | ||
616 | /* continue with next counter: */ | |
617 | clear_bit(sched->state.counter++, sched->state.used); | |
618 | ||
619 | return true; | |
620 | } | |
621 | ||
1e2ad28f RR |
622 | /* |
623 | * Select a counter for the current event to schedule. Return true on | |
624 | * success. | |
625 | */ | |
bc1738f6 | 626 | static bool __perf_sched_find_counter(struct perf_sched *sched) |
1e2ad28f RR |
627 | { |
628 | struct event_constraint *c; | |
629 | int idx; | |
630 | ||
631 | if (!sched->state.unassigned) | |
632 | return false; | |
633 | ||
634 | if (sched->state.event >= sched->max_events) | |
635 | return false; | |
636 | ||
637 | c = sched->constraints[sched->state.event]; | |
638 | ||
4defea85 PZ |
639 | /* Prefer fixed purpose counters */ |
640 | if (x86_pmu.num_counters_fixed) { | |
641 | idx = X86_PMC_IDX_FIXED; | |
307b1cd7 | 642 | for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) { |
4defea85 PZ |
643 | if (!__test_and_set_bit(idx, sched->state.used)) |
644 | goto done; | |
645 | } | |
646 | } | |
1e2ad28f RR |
647 | /* Grab the first unused counter starting with idx */ |
648 | idx = sched->state.counter; | |
307b1cd7 | 649 | for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_FIXED) { |
1e2ad28f | 650 | if (!__test_and_set_bit(idx, sched->state.used)) |
4defea85 | 651 | goto done; |
1e2ad28f | 652 | } |
1e2ad28f | 653 | |
4defea85 PZ |
654 | return false; |
655 | ||
656 | done: | |
657 | sched->state.counter = idx; | |
1e2ad28f | 658 | |
bc1738f6 RR |
659 | if (c->overlap) |
660 | perf_sched_save_state(sched); | |
661 | ||
662 | return true; | |
663 | } | |
664 | ||
665 | static bool perf_sched_find_counter(struct perf_sched *sched) | |
666 | { | |
667 | while (!__perf_sched_find_counter(sched)) { | |
668 | if (!perf_sched_restore_state(sched)) | |
669 | return false; | |
670 | } | |
671 | ||
1e2ad28f RR |
672 | return true; |
673 | } | |
674 | ||
675 | /* | |
676 | * Go through all unassigned events and find the next one to schedule. | |
677 | * Take events with the least weight first. Return true on success. | |
678 | */ | |
679 | static bool perf_sched_next_event(struct perf_sched *sched) | |
680 | { | |
681 | struct event_constraint *c; | |
682 | ||
683 | if (!sched->state.unassigned || !--sched->state.unassigned) | |
684 | return false; | |
685 | ||
686 | do { | |
687 | /* next event */ | |
688 | sched->state.event++; | |
689 | if (sched->state.event >= sched->max_events) { | |
690 | /* next weight */ | |
691 | sched->state.event = 0; | |
692 | sched->state.weight++; | |
693 | if (sched->state.weight > sched->max_weight) | |
694 | return false; | |
695 | } | |
696 | c = sched->constraints[sched->state.event]; | |
697 | } while (c->weight != sched->state.weight); | |
698 | ||
699 | sched->state.counter = 0; /* start with first counter */ | |
700 | ||
701 | return true; | |
702 | } | |
703 | ||
704 | /* | |
705 | * Assign a counter for each event. | |
706 | */ | |
707 | static int perf_assign_events(struct event_constraint **constraints, int n, | |
708 | int wmin, int wmax, int *assign) | |
709 | { | |
710 | struct perf_sched sched; | |
711 | ||
712 | perf_sched_init(&sched, constraints, n, wmin, wmax); | |
713 | ||
714 | do { | |
715 | if (!perf_sched_find_counter(&sched)) | |
716 | break; /* failed */ | |
717 | if (assign) | |
718 | assign[sched.state.event] = sched.state.counter; | |
719 | } while (perf_sched_next_event(&sched)); | |
720 | ||
721 | return sched.state.unassigned; | |
722 | } | |
723 | ||
de0428a7 | 724 | int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) |
1da53e02 | 725 | { |
63b14649 | 726 | struct event_constraint *c, *constraints[X86_PMC_IDX_MAX]; |
1da53e02 | 727 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
1e2ad28f | 728 | int i, wmin, wmax, num = 0; |
1da53e02 SE |
729 | struct hw_perf_event *hwc; |
730 | ||
731 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
732 | ||
1e2ad28f | 733 | for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) { |
b622d644 PZ |
734 | c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]); |
735 | constraints[i] = c; | |
1e2ad28f RR |
736 | wmin = min(wmin, c->weight); |
737 | wmax = max(wmax, c->weight); | |
1da53e02 SE |
738 | } |
739 | ||
8113070d SE |
740 | /* |
741 | * fastpath, try to reuse previous register | |
742 | */ | |
c933c1a6 | 743 | for (i = 0; i < n; i++) { |
8113070d | 744 | hwc = &cpuc->event_list[i]->hw; |
81269a08 | 745 | c = constraints[i]; |
8113070d SE |
746 | |
747 | /* never assigned */ | |
748 | if (hwc->idx == -1) | |
749 | break; | |
750 | ||
751 | /* constraint still honored */ | |
63b14649 | 752 | if (!test_bit(hwc->idx, c->idxmsk)) |
8113070d SE |
753 | break; |
754 | ||
755 | /* not already used */ | |
756 | if (test_bit(hwc->idx, used_mask)) | |
757 | break; | |
758 | ||
34538ee7 | 759 | __set_bit(hwc->idx, used_mask); |
8113070d SE |
760 | if (assign) |
761 | assign[i] = hwc->idx; | |
762 | } | |
8113070d | 763 | |
1e2ad28f RR |
764 | /* slow path */ |
765 | if (i != n) | |
766 | num = perf_assign_events(constraints, n, wmin, wmax, assign); | |
8113070d | 767 | |
1da53e02 SE |
768 | /* |
769 | * scheduling failed or is just a simulation, | |
770 | * free resources if necessary | |
771 | */ | |
772 | if (!assign || num) { | |
773 | for (i = 0; i < n; i++) { | |
774 | if (x86_pmu.put_event_constraints) | |
775 | x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]); | |
776 | } | |
777 | } | |
aa2bc1ad | 778 | return num ? -EINVAL : 0; |
1da53e02 SE |
779 | } |
780 | ||
781 | /* | |
782 | * dogrp: true if must collect siblings events (group) | |
783 | * returns total number of events and error code | |
784 | */ | |
785 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) | |
786 | { | |
787 | struct perf_event *event; | |
788 | int n, max_count; | |
789 | ||
948b1bb8 | 790 | max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; |
1da53e02 SE |
791 | |
792 | /* current number of events already accepted */ | |
793 | n = cpuc->n_events; | |
794 | ||
795 | if (is_x86_event(leader)) { | |
796 | if (n >= max_count) | |
aa2bc1ad | 797 | return -EINVAL; |
1da53e02 SE |
798 | cpuc->event_list[n] = leader; |
799 | n++; | |
800 | } | |
801 | if (!dogrp) | |
802 | return n; | |
803 | ||
804 | list_for_each_entry(event, &leader->sibling_list, group_entry) { | |
805 | if (!is_x86_event(event) || | |
8113070d | 806 | event->state <= PERF_EVENT_STATE_OFF) |
1da53e02 SE |
807 | continue; |
808 | ||
809 | if (n >= max_count) | |
aa2bc1ad | 810 | return -EINVAL; |
1da53e02 SE |
811 | |
812 | cpuc->event_list[n] = event; | |
813 | n++; | |
814 | } | |
815 | return n; | |
816 | } | |
817 | ||
1da53e02 | 818 | static inline void x86_assign_hw_event(struct perf_event *event, |
447a194b | 819 | struct cpu_hw_events *cpuc, int i) |
1da53e02 | 820 | { |
447a194b SE |
821 | struct hw_perf_event *hwc = &event->hw; |
822 | ||
823 | hwc->idx = cpuc->assign[i]; | |
824 | hwc->last_cpu = smp_processor_id(); | |
825 | hwc->last_tag = ++cpuc->tags[i]; | |
1da53e02 SE |
826 | |
827 | if (hwc->idx == X86_PMC_IDX_FIXED_BTS) { | |
828 | hwc->config_base = 0; | |
829 | hwc->event_base = 0; | |
830 | } else if (hwc->idx >= X86_PMC_IDX_FIXED) { | |
831 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
fc66c521 | 832 | hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - X86_PMC_IDX_FIXED); |
1da53e02 | 833 | } else { |
73d6e522 RR |
834 | hwc->config_base = x86_pmu_config_addr(hwc->idx); |
835 | hwc->event_base = x86_pmu_event_addr(hwc->idx); | |
1da53e02 SE |
836 | } |
837 | } | |
838 | ||
447a194b SE |
839 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
840 | struct cpu_hw_events *cpuc, | |
841 | int i) | |
842 | { | |
843 | return hwc->idx == cpuc->assign[i] && | |
844 | hwc->last_cpu == smp_processor_id() && | |
845 | hwc->last_tag == cpuc->tags[i]; | |
846 | } | |
847 | ||
a4eaf7f1 | 848 | static void x86_pmu_start(struct perf_event *event, int flags); |
2e841873 | 849 | |
a4eaf7f1 | 850 | static void x86_pmu_enable(struct pmu *pmu) |
ee06094f | 851 | { |
1da53e02 SE |
852 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
853 | struct perf_event *event; | |
854 | struct hw_perf_event *hwc; | |
11164cd4 | 855 | int i, added = cpuc->n_added; |
1da53e02 | 856 | |
85cf9dba | 857 | if (!x86_pmu_initialized()) |
2b9ff0db | 858 | return; |
1a6e21f7 PZ |
859 | |
860 | if (cpuc->enabled) | |
861 | return; | |
862 | ||
1da53e02 | 863 | if (cpuc->n_added) { |
19925ce7 | 864 | int n_running = cpuc->n_events - cpuc->n_added; |
1da53e02 SE |
865 | /* |
866 | * apply assignment obtained either from | |
867 | * hw_perf_group_sched_in() or x86_pmu_enable() | |
868 | * | |
869 | * step1: save events moving to new counters | |
870 | * step2: reprogram moved events into new counters | |
871 | */ | |
19925ce7 | 872 | for (i = 0; i < n_running; i++) { |
1da53e02 SE |
873 | event = cpuc->event_list[i]; |
874 | hwc = &event->hw; | |
875 | ||
447a194b SE |
876 | /* |
877 | * we can avoid reprogramming counter if: | |
878 | * - assigned same counter as last time | |
879 | * - running on same CPU as last time | |
880 | * - no other event has used the counter since | |
881 | */ | |
882 | if (hwc->idx == -1 || | |
883 | match_prev_assignment(hwc, cpuc, i)) | |
1da53e02 SE |
884 | continue; |
885 | ||
a4eaf7f1 PZ |
886 | /* |
887 | * Ensure we don't accidentally enable a stopped | |
888 | * counter simply because we rescheduled. | |
889 | */ | |
890 | if (hwc->state & PERF_HES_STOPPED) | |
891 | hwc->state |= PERF_HES_ARCH; | |
892 | ||
893 | x86_pmu_stop(event, PERF_EF_UPDATE); | |
1da53e02 SE |
894 | } |
895 | ||
896 | for (i = 0; i < cpuc->n_events; i++) { | |
1da53e02 SE |
897 | event = cpuc->event_list[i]; |
898 | hwc = &event->hw; | |
899 | ||
45e16a68 | 900 | if (!match_prev_assignment(hwc, cpuc, i)) |
447a194b | 901 | x86_assign_hw_event(event, cpuc, i); |
45e16a68 PZ |
902 | else if (i < n_running) |
903 | continue; | |
1da53e02 | 904 | |
a4eaf7f1 PZ |
905 | if (hwc->state & PERF_HES_ARCH) |
906 | continue; | |
907 | ||
908 | x86_pmu_start(event, PERF_EF_RELOAD); | |
1da53e02 SE |
909 | } |
910 | cpuc->n_added = 0; | |
911 | perf_events_lapic_init(); | |
912 | } | |
1a6e21f7 PZ |
913 | |
914 | cpuc->enabled = 1; | |
915 | barrier(); | |
916 | ||
11164cd4 | 917 | x86_pmu.enable_all(added); |
ee06094f | 918 | } |
ee06094f | 919 | |
245b2e70 | 920 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 921 | |
ee06094f IM |
922 | /* |
923 | * Set the next IRQ period, based on the hwc->period_left value. | |
cdd6c482 | 924 | * To be called with the event disabled in hw: |
ee06094f | 925 | */ |
de0428a7 | 926 | int x86_perf_event_set_period(struct perf_event *event) |
241771ef | 927 | { |
07088edb | 928 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 929 | s64 left = local64_read(&hwc->period_left); |
e4abb5d4 | 930 | s64 period = hwc->sample_period; |
7645a24c | 931 | int ret = 0, idx = hwc->idx; |
ee06094f | 932 | |
30dd568c MM |
933 | if (idx == X86_PMC_IDX_FIXED_BTS) |
934 | return 0; | |
935 | ||
ee06094f | 936 | /* |
af901ca1 | 937 | * If we are way outside a reasonable range then just skip forward: |
ee06094f IM |
938 | */ |
939 | if (unlikely(left <= -period)) { | |
940 | left = period; | |
e7850595 | 941 | local64_set(&hwc->period_left, left); |
9e350de3 | 942 | hwc->last_period = period; |
e4abb5d4 | 943 | ret = 1; |
ee06094f IM |
944 | } |
945 | ||
946 | if (unlikely(left <= 0)) { | |
947 | left += period; | |
e7850595 | 948 | local64_set(&hwc->period_left, left); |
9e350de3 | 949 | hwc->last_period = period; |
e4abb5d4 | 950 | ret = 1; |
ee06094f | 951 | } |
1c80f4b5 | 952 | /* |
dfc65094 | 953 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
954 | */ |
955 | if (unlikely(left < 2)) | |
956 | left = 2; | |
241771ef | 957 | |
e4abb5d4 PZ |
958 | if (left > x86_pmu.max_period) |
959 | left = x86_pmu.max_period; | |
960 | ||
245b2e70 | 961 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
ee06094f IM |
962 | |
963 | /* | |
cdd6c482 | 964 | * The hw event starts counting from this event offset, |
ee06094f IM |
965 | * mark it to be able to extra future deltas: |
966 | */ | |
e7850595 | 967 | local64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 968 | |
73d6e522 | 969 | wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac CG |
970 | |
971 | /* | |
972 | * Due to erratum on certan cpu we need | |
973 | * a second write to be sure the register | |
974 | * is updated properly | |
975 | */ | |
976 | if (x86_pmu.perfctr_second_write) { | |
73d6e522 | 977 | wrmsrl(hwc->event_base, |
948b1bb8 | 978 | (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac | 979 | } |
e4abb5d4 | 980 | |
cdd6c482 | 981 | perf_event_update_userpage(event); |
194002b2 | 982 | |
e4abb5d4 | 983 | return ret; |
2f18d1e8 IM |
984 | } |
985 | ||
de0428a7 | 986 | void x86_pmu_enable_event(struct perf_event *event) |
7c90cc45 | 987 | { |
0a3aee0d | 988 | if (__this_cpu_read(cpu_hw_events.enabled)) |
31fa58af RR |
989 | __x86_pmu_enable_event(&event->hw, |
990 | ARCH_PERFMON_EVENTSEL_ENABLE); | |
241771ef IM |
991 | } |
992 | ||
b690081d | 993 | /* |
a4eaf7f1 | 994 | * Add a single event to the PMU. |
1da53e02 SE |
995 | * |
996 | * The event is added to the group of enabled events | |
997 | * but only if it can be scehduled with existing events. | |
fe9081cc | 998 | */ |
a4eaf7f1 | 999 | static int x86_pmu_add(struct perf_event *event, int flags) |
fe9081cc PZ |
1000 | { |
1001 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1da53e02 SE |
1002 | struct hw_perf_event *hwc; |
1003 | int assign[X86_PMC_IDX_MAX]; | |
1004 | int n, n0, ret; | |
fe9081cc | 1005 | |
1da53e02 | 1006 | hwc = &event->hw; |
fe9081cc | 1007 | |
33696fc0 | 1008 | perf_pmu_disable(event->pmu); |
1da53e02 | 1009 | n0 = cpuc->n_events; |
24cd7f54 PZ |
1010 | ret = n = collect_events(cpuc, event, false); |
1011 | if (ret < 0) | |
1012 | goto out; | |
53b441a5 | 1013 | |
a4eaf7f1 PZ |
1014 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; |
1015 | if (!(flags & PERF_EF_START)) | |
1016 | hwc->state |= PERF_HES_ARCH; | |
1017 | ||
4d1c52b0 LM |
1018 | /* |
1019 | * If group events scheduling transaction was started, | |
0d2eb44f | 1020 | * skip the schedulability test here, it will be performed |
a4eaf7f1 | 1021 | * at commit time (->commit_txn) as a whole |
4d1c52b0 | 1022 | */ |
8d2cacbb | 1023 | if (cpuc->group_flag & PERF_EVENT_TXN) |
24cd7f54 | 1024 | goto done_collect; |
4d1c52b0 | 1025 | |
a072738e | 1026 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
1da53e02 | 1027 | if (ret) |
24cd7f54 | 1028 | goto out; |
1da53e02 SE |
1029 | /* |
1030 | * copy new assignment, now we know it is possible | |
1031 | * will be used by hw_perf_enable() | |
1032 | */ | |
1033 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
7e2ae347 | 1034 | |
24cd7f54 | 1035 | done_collect: |
1da53e02 | 1036 | cpuc->n_events = n; |
356e1f2e | 1037 | cpuc->n_added += n - n0; |
90151c35 | 1038 | cpuc->n_txn += n - n0; |
95cdd2e7 | 1039 | |
24cd7f54 PZ |
1040 | ret = 0; |
1041 | out: | |
33696fc0 | 1042 | perf_pmu_enable(event->pmu); |
24cd7f54 | 1043 | return ret; |
241771ef IM |
1044 | } |
1045 | ||
a4eaf7f1 | 1046 | static void x86_pmu_start(struct perf_event *event, int flags) |
d76a0812 | 1047 | { |
c08053e6 PZ |
1048 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
1049 | int idx = event->hw.idx; | |
1050 | ||
a4eaf7f1 PZ |
1051 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) |
1052 | return; | |
1053 | ||
1054 | if (WARN_ON_ONCE(idx == -1)) | |
1055 | return; | |
1056 | ||
1057 | if (flags & PERF_EF_RELOAD) { | |
1058 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1059 | x86_perf_event_set_period(event); | |
1060 | } | |
1061 | ||
1062 | event->hw.state = 0; | |
d76a0812 | 1063 | |
c08053e6 PZ |
1064 | cpuc->events[idx] = event; |
1065 | __set_bit(idx, cpuc->active_mask); | |
63e6be6d | 1066 | __set_bit(idx, cpuc->running); |
aff3d91a | 1067 | x86_pmu.enable(event); |
c08053e6 | 1068 | perf_event_update_userpage(event); |
a78ac325 PZ |
1069 | } |
1070 | ||
cdd6c482 | 1071 | void perf_event_print_debug(void) |
241771ef | 1072 | { |
2f18d1e8 | 1073 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
ca037701 | 1074 | u64 pebs; |
cdd6c482 | 1075 | struct cpu_hw_events *cpuc; |
5bb9efe3 | 1076 | unsigned long flags; |
1e125676 IM |
1077 | int cpu, idx; |
1078 | ||
948b1bb8 | 1079 | if (!x86_pmu.num_counters) |
1e125676 | 1080 | return; |
241771ef | 1081 | |
5bb9efe3 | 1082 | local_irq_save(flags); |
241771ef IM |
1083 | |
1084 | cpu = smp_processor_id(); | |
cdd6c482 | 1085 | cpuc = &per_cpu(cpu_hw_events, cpu); |
241771ef | 1086 | |
faa28ae0 | 1087 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1088 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1089 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1090 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1091 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
ca037701 | 1092 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); |
a1ef58f4 JSR |
1093 | |
1094 | pr_info("\n"); | |
1095 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1096 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1097 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1098 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
ca037701 | 1099 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); |
f87ad35d | 1100 | } |
7645a24c | 1101 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
241771ef | 1102 | |
948b1bb8 | 1103 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
41bf4989 RR |
1104 | rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); |
1105 | rdmsrl(x86_pmu_event_addr(idx), pmc_count); | |
241771ef | 1106 | |
245b2e70 | 1107 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 1108 | |
a1ef58f4 | 1109 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1110 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1111 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1112 | cpu, idx, pmc_count); |
a1ef58f4 | 1113 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1114 | cpu, idx, prev_left); |
241771ef | 1115 | } |
948b1bb8 | 1116 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
1117 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1118 | ||
a1ef58f4 | 1119 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1120 | cpu, idx, pmc_count); |
1121 | } | |
5bb9efe3 | 1122 | local_irq_restore(flags); |
241771ef IM |
1123 | } |
1124 | ||
de0428a7 | 1125 | void x86_pmu_stop(struct perf_event *event, int flags) |
241771ef | 1126 | { |
d76a0812 | 1127 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
cdd6c482 | 1128 | struct hw_perf_event *hwc = &event->hw; |
241771ef | 1129 | |
a4eaf7f1 PZ |
1130 | if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) { |
1131 | x86_pmu.disable(event); | |
1132 | cpuc->events[hwc->idx] = NULL; | |
1133 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); | |
1134 | hwc->state |= PERF_HES_STOPPED; | |
1135 | } | |
30dd568c | 1136 | |
a4eaf7f1 PZ |
1137 | if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { |
1138 | /* | |
1139 | * Drain the remaining delta count out of a event | |
1140 | * that we are disabling: | |
1141 | */ | |
1142 | x86_perf_event_update(event); | |
1143 | hwc->state |= PERF_HES_UPTODATE; | |
1144 | } | |
2e841873 PZ |
1145 | } |
1146 | ||
a4eaf7f1 | 1147 | static void x86_pmu_del(struct perf_event *event, int flags) |
2e841873 PZ |
1148 | { |
1149 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1150 | int i; | |
1151 | ||
90151c35 SE |
1152 | /* |
1153 | * If we're called during a txn, we don't need to do anything. | |
1154 | * The events never got scheduled and ->cancel_txn will truncate | |
1155 | * the event_list. | |
1156 | */ | |
8d2cacbb | 1157 | if (cpuc->group_flag & PERF_EVENT_TXN) |
90151c35 SE |
1158 | return; |
1159 | ||
a4eaf7f1 | 1160 | x86_pmu_stop(event, PERF_EF_UPDATE); |
194002b2 | 1161 | |
1da53e02 SE |
1162 | for (i = 0; i < cpuc->n_events; i++) { |
1163 | if (event == cpuc->event_list[i]) { | |
1164 | ||
1165 | if (x86_pmu.put_event_constraints) | |
1166 | x86_pmu.put_event_constraints(cpuc, event); | |
1167 | ||
1168 | while (++i < cpuc->n_events) | |
1169 | cpuc->event_list[i-1] = cpuc->event_list[i]; | |
1170 | ||
1171 | --cpuc->n_events; | |
6c9687ab | 1172 | break; |
1da53e02 SE |
1173 | } |
1174 | } | |
cdd6c482 | 1175 | perf_event_update_userpage(event); |
241771ef IM |
1176 | } |
1177 | ||
de0428a7 | 1178 | int x86_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1179 | { |
df1a132b | 1180 | struct perf_sample_data data; |
cdd6c482 IM |
1181 | struct cpu_hw_events *cpuc; |
1182 | struct perf_event *event; | |
11d1578f | 1183 | int idx, handled = 0; |
9029a5e3 IM |
1184 | u64 val; |
1185 | ||
cdd6c482 | 1186 | cpuc = &__get_cpu_var(cpu_hw_events); |
962bf7a6 | 1187 | |
2bce5dac DZ |
1188 | /* |
1189 | * Some chipsets need to unmask the LVTPC in a particular spot | |
1190 | * inside the nmi handler. As a result, the unmasking was pushed | |
1191 | * into all the nmi handlers. | |
1192 | * | |
1193 | * This generic handler doesn't seem to have any issues where the | |
1194 | * unmasking occurs so it was left at the top. | |
1195 | */ | |
1196 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
1197 | ||
948b1bb8 | 1198 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
63e6be6d RR |
1199 | if (!test_bit(idx, cpuc->active_mask)) { |
1200 | /* | |
1201 | * Though we deactivated the counter some cpus | |
1202 | * might still deliver spurious interrupts still | |
1203 | * in flight. Catch them: | |
1204 | */ | |
1205 | if (__test_and_clear_bit(idx, cpuc->running)) | |
1206 | handled++; | |
a29aa8a7 | 1207 | continue; |
63e6be6d | 1208 | } |
962bf7a6 | 1209 | |
cdd6c482 | 1210 | event = cpuc->events[idx]; |
a4016a79 | 1211 | |
cc2ad4ba | 1212 | val = x86_perf_event_update(event); |
948b1bb8 | 1213 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
48e22d56 | 1214 | continue; |
962bf7a6 | 1215 | |
9e350de3 | 1216 | /* |
cdd6c482 | 1217 | * event overflow |
9e350de3 | 1218 | */ |
4177c42a | 1219 | handled++; |
fd0d000b | 1220 | perf_sample_data_init(&data, 0, event->hw.last_period); |
9e350de3 | 1221 | |
07088edb | 1222 | if (!x86_perf_event_set_period(event)) |
e4abb5d4 PZ |
1223 | continue; |
1224 | ||
a8b0ca17 | 1225 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1226 | x86_pmu_stop(event, 0); |
a29aa8a7 | 1227 | } |
962bf7a6 | 1228 | |
9e350de3 PZ |
1229 | if (handled) |
1230 | inc_irq_stat(apic_perf_irqs); | |
1231 | ||
a29aa8a7 RR |
1232 | return handled; |
1233 | } | |
39d81eab | 1234 | |
cdd6c482 | 1235 | void perf_events_lapic_init(void) |
241771ef | 1236 | { |
04da8a43 | 1237 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
241771ef | 1238 | return; |
85cf9dba | 1239 | |
241771ef | 1240 | /* |
c323d95f | 1241 | * Always use NMI for PMU |
241771ef | 1242 | */ |
c323d95f | 1243 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1244 | } |
1245 | ||
1246 | static int __kprobes | |
9c48f1c6 | 1247 | perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs) |
241771ef | 1248 | { |
cdd6c482 | 1249 | if (!atomic_read(&active_events)) |
9c48f1c6 | 1250 | return NMI_DONE; |
4177c42a | 1251 | |
9c48f1c6 | 1252 | return x86_pmu.handle_irq(regs); |
241771ef IM |
1253 | } |
1254 | ||
de0428a7 KW |
1255 | struct event_constraint emptyconstraint; |
1256 | struct event_constraint unconstrained; | |
f87ad35d | 1257 | |
3f6da390 PZ |
1258 | static int __cpuinit |
1259 | x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) | |
1260 | { | |
1261 | unsigned int cpu = (long)hcpu; | |
7fdba1ca | 1262 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); |
b38b24ea | 1263 | int ret = NOTIFY_OK; |
3f6da390 PZ |
1264 | |
1265 | switch (action & ~CPU_TASKS_FROZEN) { | |
1266 | case CPU_UP_PREPARE: | |
7fdba1ca | 1267 | cpuc->kfree_on_online = NULL; |
3f6da390 | 1268 | if (x86_pmu.cpu_prepare) |
b38b24ea | 1269 | ret = x86_pmu.cpu_prepare(cpu); |
3f6da390 PZ |
1270 | break; |
1271 | ||
1272 | case CPU_STARTING: | |
0c9d42ed PZ |
1273 | if (x86_pmu.attr_rdpmc) |
1274 | set_in_cr4(X86_CR4_PCE); | |
3f6da390 PZ |
1275 | if (x86_pmu.cpu_starting) |
1276 | x86_pmu.cpu_starting(cpu); | |
1277 | break; | |
1278 | ||
7fdba1ca PZ |
1279 | case CPU_ONLINE: |
1280 | kfree(cpuc->kfree_on_online); | |
1281 | break; | |
1282 | ||
3f6da390 PZ |
1283 | case CPU_DYING: |
1284 | if (x86_pmu.cpu_dying) | |
1285 | x86_pmu.cpu_dying(cpu); | |
1286 | break; | |
1287 | ||
b38b24ea | 1288 | case CPU_UP_CANCELED: |
3f6da390 PZ |
1289 | case CPU_DEAD: |
1290 | if (x86_pmu.cpu_dead) | |
1291 | x86_pmu.cpu_dead(cpu); | |
1292 | break; | |
1293 | ||
1294 | default: | |
1295 | break; | |
1296 | } | |
1297 | ||
b38b24ea | 1298 | return ret; |
3f6da390 PZ |
1299 | } |
1300 | ||
12558038 CG |
1301 | static void __init pmu_check_apic(void) |
1302 | { | |
1303 | if (cpu_has_apic) | |
1304 | return; | |
1305 | ||
1306 | x86_pmu.apic = 0; | |
1307 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); | |
1308 | pr_info("no hardware sampling interrupt available.\n"); | |
1309 | } | |
1310 | ||
641cc938 JO |
1311 | static struct attribute_group x86_pmu_format_group = { |
1312 | .name = "format", | |
1313 | .attrs = NULL, | |
1314 | }; | |
1315 | ||
dda99116 | 1316 | static int __init init_hw_perf_events(void) |
b56a3802 | 1317 | { |
c1d6f42f | 1318 | struct x86_pmu_quirk *quirk; |
b622d644 | 1319 | struct event_constraint *c; |
72eae04d RR |
1320 | int err; |
1321 | ||
cdd6c482 | 1322 | pr_info("Performance Events: "); |
1123e3ad | 1323 | |
b56a3802 JSR |
1324 | switch (boot_cpu_data.x86_vendor) { |
1325 | case X86_VENDOR_INTEL: | |
72eae04d | 1326 | err = intel_pmu_init(); |
b56a3802 | 1327 | break; |
f87ad35d | 1328 | case X86_VENDOR_AMD: |
72eae04d | 1329 | err = amd_pmu_init(); |
f87ad35d | 1330 | break; |
4138960a | 1331 | default: |
004417a6 | 1332 | return 0; |
b56a3802 | 1333 | } |
1123e3ad | 1334 | if (err != 0) { |
cdd6c482 | 1335 | pr_cont("no PMU driver, software events only.\n"); |
004417a6 | 1336 | return 0; |
1123e3ad | 1337 | } |
b56a3802 | 1338 | |
12558038 CG |
1339 | pmu_check_apic(); |
1340 | ||
33c6d6a7 | 1341 | /* sanity check that the hardware exists or is emulated */ |
4407204c | 1342 | if (!check_hw_exists()) |
004417a6 | 1343 | return 0; |
33c6d6a7 | 1344 | |
1123e3ad | 1345 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1346 | |
c1d6f42f PZ |
1347 | for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next) |
1348 | quirk->func(); | |
3c44780b | 1349 | |
948b1bb8 | 1350 | if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) { |
cdd6c482 | 1351 | WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", |
948b1bb8 RR |
1352 | x86_pmu.num_counters, X86_PMC_MAX_GENERIC); |
1353 | x86_pmu.num_counters = X86_PMC_MAX_GENERIC; | |
241771ef | 1354 | } |
948b1bb8 | 1355 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; |
241771ef | 1356 | |
948b1bb8 | 1357 | if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { |
cdd6c482 | 1358 | WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", |
948b1bb8 RR |
1359 | x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED); |
1360 | x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; | |
703e937c | 1361 | } |
862a1a5f | 1362 | |
d6dc0b4e | 1363 | x86_pmu.intel_ctrl |= |
948b1bb8 | 1364 | ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED; |
241771ef | 1365 | |
cdd6c482 | 1366 | perf_events_lapic_init(); |
9c48f1c6 | 1367 | register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI"); |
1123e3ad | 1368 | |
63b14649 | 1369 | unconstrained = (struct event_constraint) |
948b1bb8 | 1370 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
bc1738f6 | 1371 | 0, x86_pmu.num_counters, 0); |
63b14649 | 1372 | |
b622d644 | 1373 | if (x86_pmu.event_constraints) { |
cd09c0c4 SE |
1374 | /* |
1375 | * event on fixed counter2 (REF_CYCLES) only works on this | |
1376 | * counter, so do not extend mask to generic counters | |
1377 | */ | |
b622d644 | 1378 | for_each_event_constraint(c, x86_pmu.event_constraints) { |
cd09c0c4 SE |
1379 | if (c->cmask != X86_RAW_EVENT_MASK |
1380 | || c->idxmsk64 == X86_PMC_MSK_FIXED_REF_CYCLES) { | |
b622d644 | 1381 | continue; |
cd09c0c4 | 1382 | } |
b622d644 | 1383 | |
948b1bb8 RR |
1384 | c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; |
1385 | c->weight += x86_pmu.num_counters; | |
b622d644 PZ |
1386 | } |
1387 | } | |
1388 | ||
0c9d42ed | 1389 | x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */ |
641cc938 | 1390 | x86_pmu_format_group.attrs = x86_pmu.format_attrs; |
0c9d42ed | 1391 | |
57c0c15b | 1392 | pr_info("... version: %d\n", x86_pmu.version); |
948b1bb8 RR |
1393 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); |
1394 | pr_info("... generic registers: %d\n", x86_pmu.num_counters); | |
1395 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); | |
57c0c15b | 1396 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
948b1bb8 | 1397 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); |
d6dc0b4e | 1398 | pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); |
3f6da390 | 1399 | |
2e80a82a | 1400 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
3f6da390 | 1401 | perf_cpu_notifier(x86_pmu_notifier); |
004417a6 PZ |
1402 | |
1403 | return 0; | |
241771ef | 1404 | } |
004417a6 | 1405 | early_initcall(init_hw_perf_events); |
621a01ea | 1406 | |
cdd6c482 | 1407 | static inline void x86_pmu_read(struct perf_event *event) |
ee06094f | 1408 | { |
cc2ad4ba | 1409 | x86_perf_event_update(event); |
ee06094f IM |
1410 | } |
1411 | ||
4d1c52b0 LM |
1412 | /* |
1413 | * Start group events scheduling transaction | |
1414 | * Set the flag to make pmu::enable() not perform the | |
1415 | * schedulability test, it will be performed at commit time | |
1416 | */ | |
51b0fe39 | 1417 | static void x86_pmu_start_txn(struct pmu *pmu) |
4d1c52b0 | 1418 | { |
33696fc0 | 1419 | perf_pmu_disable(pmu); |
0a3aee0d TH |
1420 | __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN); |
1421 | __this_cpu_write(cpu_hw_events.n_txn, 0); | |
4d1c52b0 LM |
1422 | } |
1423 | ||
1424 | /* | |
1425 | * Stop group events scheduling transaction | |
1426 | * Clear the flag and pmu::enable() will perform the | |
1427 | * schedulability test. | |
1428 | */ | |
51b0fe39 | 1429 | static void x86_pmu_cancel_txn(struct pmu *pmu) |
4d1c52b0 | 1430 | { |
0a3aee0d | 1431 | __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN); |
90151c35 SE |
1432 | /* |
1433 | * Truncate the collected events. | |
1434 | */ | |
0a3aee0d TH |
1435 | __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn)); |
1436 | __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn)); | |
33696fc0 | 1437 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1438 | } |
1439 | ||
1440 | /* | |
1441 | * Commit group events scheduling transaction | |
1442 | * Perform the group schedulability test as a whole | |
1443 | * Return 0 if success | |
1444 | */ | |
51b0fe39 | 1445 | static int x86_pmu_commit_txn(struct pmu *pmu) |
4d1c52b0 LM |
1446 | { |
1447 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1448 | int assign[X86_PMC_IDX_MAX]; | |
1449 | int n, ret; | |
1450 | ||
1451 | n = cpuc->n_events; | |
1452 | ||
1453 | if (!x86_pmu_initialized()) | |
1454 | return -EAGAIN; | |
1455 | ||
1456 | ret = x86_pmu.schedule_events(cpuc, n, assign); | |
1457 | if (ret) | |
1458 | return ret; | |
1459 | ||
1460 | /* | |
1461 | * copy new assignment, now we know it is possible | |
1462 | * will be used by hw_perf_enable() | |
1463 | */ | |
1464 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
1465 | ||
8d2cacbb | 1466 | cpuc->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1467 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1468 | return 0; |
1469 | } | |
cd8a38d3 SE |
1470 | /* |
1471 | * a fake_cpuc is used to validate event groups. Due to | |
1472 | * the extra reg logic, we need to also allocate a fake | |
1473 | * per_core and per_cpu structure. Otherwise, group events | |
1474 | * using extra reg may conflict without the kernel being | |
1475 | * able to catch this when the last event gets added to | |
1476 | * the group. | |
1477 | */ | |
1478 | static void free_fake_cpuc(struct cpu_hw_events *cpuc) | |
1479 | { | |
1480 | kfree(cpuc->shared_regs); | |
1481 | kfree(cpuc); | |
1482 | } | |
1483 | ||
1484 | static struct cpu_hw_events *allocate_fake_cpuc(void) | |
1485 | { | |
1486 | struct cpu_hw_events *cpuc; | |
1487 | int cpu = raw_smp_processor_id(); | |
1488 | ||
1489 | cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL); | |
1490 | if (!cpuc) | |
1491 | return ERR_PTR(-ENOMEM); | |
1492 | ||
1493 | /* only needed, if we have extra_regs */ | |
1494 | if (x86_pmu.extra_regs) { | |
1495 | cpuc->shared_regs = allocate_shared_regs(cpu); | |
1496 | if (!cpuc->shared_regs) | |
1497 | goto error; | |
1498 | } | |
1499 | return cpuc; | |
1500 | error: | |
1501 | free_fake_cpuc(cpuc); | |
1502 | return ERR_PTR(-ENOMEM); | |
1503 | } | |
4d1c52b0 | 1504 | |
ca037701 PZ |
1505 | /* |
1506 | * validate that we can schedule this event | |
1507 | */ | |
1508 | static int validate_event(struct perf_event *event) | |
1509 | { | |
1510 | struct cpu_hw_events *fake_cpuc; | |
1511 | struct event_constraint *c; | |
1512 | int ret = 0; | |
1513 | ||
cd8a38d3 SE |
1514 | fake_cpuc = allocate_fake_cpuc(); |
1515 | if (IS_ERR(fake_cpuc)) | |
1516 | return PTR_ERR(fake_cpuc); | |
ca037701 PZ |
1517 | |
1518 | c = x86_pmu.get_event_constraints(fake_cpuc, event); | |
1519 | ||
1520 | if (!c || !c->weight) | |
aa2bc1ad | 1521 | ret = -EINVAL; |
ca037701 PZ |
1522 | |
1523 | if (x86_pmu.put_event_constraints) | |
1524 | x86_pmu.put_event_constraints(fake_cpuc, event); | |
1525 | ||
cd8a38d3 | 1526 | free_fake_cpuc(fake_cpuc); |
ca037701 PZ |
1527 | |
1528 | return ret; | |
1529 | } | |
1530 | ||
1da53e02 SE |
1531 | /* |
1532 | * validate a single event group | |
1533 | * | |
1534 | * validation include: | |
184f412c IM |
1535 | * - check events are compatible which each other |
1536 | * - events do not compete for the same counter | |
1537 | * - number of events <= number of counters | |
1da53e02 SE |
1538 | * |
1539 | * validation ensures the group can be loaded onto the | |
1540 | * PMU if it was the only group available. | |
1541 | */ | |
fe9081cc PZ |
1542 | static int validate_group(struct perf_event *event) |
1543 | { | |
1da53e02 | 1544 | struct perf_event *leader = event->group_leader; |
502568d5 | 1545 | struct cpu_hw_events *fake_cpuc; |
aa2bc1ad | 1546 | int ret = -EINVAL, n; |
fe9081cc | 1547 | |
cd8a38d3 SE |
1548 | fake_cpuc = allocate_fake_cpuc(); |
1549 | if (IS_ERR(fake_cpuc)) | |
1550 | return PTR_ERR(fake_cpuc); | |
1da53e02 SE |
1551 | /* |
1552 | * the event is not yet connected with its | |
1553 | * siblings therefore we must first collect | |
1554 | * existing siblings, then add the new event | |
1555 | * before we can simulate the scheduling | |
1556 | */ | |
502568d5 | 1557 | n = collect_events(fake_cpuc, leader, true); |
1da53e02 | 1558 | if (n < 0) |
cd8a38d3 | 1559 | goto out; |
fe9081cc | 1560 | |
502568d5 PZ |
1561 | fake_cpuc->n_events = n; |
1562 | n = collect_events(fake_cpuc, event, false); | |
1da53e02 | 1563 | if (n < 0) |
cd8a38d3 | 1564 | goto out; |
fe9081cc | 1565 | |
502568d5 | 1566 | fake_cpuc->n_events = n; |
1da53e02 | 1567 | |
a072738e | 1568 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
502568d5 | 1569 | |
502568d5 | 1570 | out: |
cd8a38d3 | 1571 | free_fake_cpuc(fake_cpuc); |
502568d5 | 1572 | return ret; |
fe9081cc PZ |
1573 | } |
1574 | ||
dda99116 | 1575 | static int x86_pmu_event_init(struct perf_event *event) |
621a01ea | 1576 | { |
51b0fe39 | 1577 | struct pmu *tmp; |
621a01ea IM |
1578 | int err; |
1579 | ||
b0a873eb PZ |
1580 | switch (event->attr.type) { |
1581 | case PERF_TYPE_RAW: | |
1582 | case PERF_TYPE_HARDWARE: | |
1583 | case PERF_TYPE_HW_CACHE: | |
1584 | break; | |
1585 | ||
1586 | default: | |
1587 | return -ENOENT; | |
1588 | } | |
1589 | ||
1590 | err = __x86_pmu_event_init(event); | |
fe9081cc | 1591 | if (!err) { |
8113070d SE |
1592 | /* |
1593 | * we temporarily connect event to its pmu | |
1594 | * such that validate_group() can classify | |
1595 | * it as an x86 event using is_x86_event() | |
1596 | */ | |
1597 | tmp = event->pmu; | |
1598 | event->pmu = &pmu; | |
1599 | ||
fe9081cc PZ |
1600 | if (event->group_leader != event) |
1601 | err = validate_group(event); | |
ca037701 PZ |
1602 | else |
1603 | err = validate_event(event); | |
8113070d SE |
1604 | |
1605 | event->pmu = tmp; | |
fe9081cc | 1606 | } |
a1792cda | 1607 | if (err) { |
cdd6c482 IM |
1608 | if (event->destroy) |
1609 | event->destroy(event); | |
a1792cda | 1610 | } |
621a01ea | 1611 | |
b0a873eb | 1612 | return err; |
621a01ea | 1613 | } |
d7d59fb3 | 1614 | |
fe4a3308 PZ |
1615 | static int x86_pmu_event_idx(struct perf_event *event) |
1616 | { | |
1617 | int idx = event->hw.idx; | |
1618 | ||
c7206205 PZ |
1619 | if (!x86_pmu.attr_rdpmc) |
1620 | return 0; | |
1621 | ||
fe4a3308 PZ |
1622 | if (x86_pmu.num_counters_fixed && idx >= X86_PMC_IDX_FIXED) { |
1623 | idx -= X86_PMC_IDX_FIXED; | |
1624 | idx |= 1 << 30; | |
1625 | } | |
1626 | ||
1627 | return idx + 1; | |
1628 | } | |
1629 | ||
0c9d42ed PZ |
1630 | static ssize_t get_attr_rdpmc(struct device *cdev, |
1631 | struct device_attribute *attr, | |
1632 | char *buf) | |
1633 | { | |
1634 | return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc); | |
1635 | } | |
1636 | ||
1637 | static void change_rdpmc(void *info) | |
1638 | { | |
1639 | bool enable = !!(unsigned long)info; | |
1640 | ||
1641 | if (enable) | |
1642 | set_in_cr4(X86_CR4_PCE); | |
1643 | else | |
1644 | clear_in_cr4(X86_CR4_PCE); | |
1645 | } | |
1646 | ||
1647 | static ssize_t set_attr_rdpmc(struct device *cdev, | |
1648 | struct device_attribute *attr, | |
1649 | const char *buf, size_t count) | |
1650 | { | |
1651 | unsigned long val = simple_strtoul(buf, NULL, 0); | |
1652 | ||
1653 | if (!!val != !!x86_pmu.attr_rdpmc) { | |
1654 | x86_pmu.attr_rdpmc = !!val; | |
1655 | smp_call_function(change_rdpmc, (void *)val, 1); | |
1656 | } | |
1657 | ||
1658 | return count; | |
1659 | } | |
1660 | ||
1661 | static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc); | |
1662 | ||
1663 | static struct attribute *x86_pmu_attrs[] = { | |
1664 | &dev_attr_rdpmc.attr, | |
1665 | NULL, | |
1666 | }; | |
1667 | ||
1668 | static struct attribute_group x86_pmu_attr_group = { | |
1669 | .attrs = x86_pmu_attrs, | |
1670 | }; | |
1671 | ||
1672 | static const struct attribute_group *x86_pmu_attr_groups[] = { | |
1673 | &x86_pmu_attr_group, | |
641cc938 | 1674 | &x86_pmu_format_group, |
0c9d42ed PZ |
1675 | NULL, |
1676 | }; | |
1677 | ||
d010b332 SE |
1678 | static void x86_pmu_flush_branch_stack(void) |
1679 | { | |
1680 | if (x86_pmu.flush_branch_stack) | |
1681 | x86_pmu.flush_branch_stack(); | |
1682 | } | |
1683 | ||
b0a873eb | 1684 | static struct pmu pmu = { |
d010b332 SE |
1685 | .pmu_enable = x86_pmu_enable, |
1686 | .pmu_disable = x86_pmu_disable, | |
a4eaf7f1 | 1687 | |
0c9d42ed PZ |
1688 | .attr_groups = x86_pmu_attr_groups, |
1689 | ||
b0a873eb | 1690 | .event_init = x86_pmu_event_init, |
a4eaf7f1 | 1691 | |
d010b332 SE |
1692 | .add = x86_pmu_add, |
1693 | .del = x86_pmu_del, | |
1694 | .start = x86_pmu_start, | |
1695 | .stop = x86_pmu_stop, | |
1696 | .read = x86_pmu_read, | |
a4eaf7f1 | 1697 | |
b0a873eb PZ |
1698 | .start_txn = x86_pmu_start_txn, |
1699 | .cancel_txn = x86_pmu_cancel_txn, | |
1700 | .commit_txn = x86_pmu_commit_txn, | |
fe4a3308 PZ |
1701 | |
1702 | .event_idx = x86_pmu_event_idx, | |
d010b332 | 1703 | .flush_branch_stack = x86_pmu_flush_branch_stack, |
b0a873eb PZ |
1704 | }; |
1705 | ||
c7206205 | 1706 | void arch_perf_update_userpage(struct perf_event_mmap_page *userpg, u64 now) |
e3f3541c | 1707 | { |
c7206205 PZ |
1708 | userpg->cap_usr_time = 0; |
1709 | userpg->cap_usr_rdpmc = x86_pmu.attr_rdpmc; | |
1710 | userpg->pmc_width = x86_pmu.cntval_bits; | |
1711 | ||
e3f3541c PZ |
1712 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
1713 | return; | |
1714 | ||
1715 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) | |
1716 | return; | |
1717 | ||
c7206205 | 1718 | userpg->cap_usr_time = 1; |
e3f3541c PZ |
1719 | userpg->time_mult = this_cpu_read(cyc2ns); |
1720 | userpg->time_shift = CYC2NS_SCALE_FACTOR; | |
1721 | userpg->time_offset = this_cpu_read(cyc2ns_offset) - now; | |
1722 | } | |
1723 | ||
d7d59fb3 PZ |
1724 | /* |
1725 | * callchain support | |
1726 | */ | |
1727 | ||
d7d59fb3 PZ |
1728 | static int backtrace_stack(void *data, char *name) |
1729 | { | |
038e836e | 1730 | return 0; |
d7d59fb3 PZ |
1731 | } |
1732 | ||
1733 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1734 | { | |
1735 | struct perf_callchain_entry *entry = data; | |
1736 | ||
70791ce9 | 1737 | perf_callchain_store(entry, addr); |
d7d59fb3 PZ |
1738 | } |
1739 | ||
1740 | static const struct stacktrace_ops backtrace_ops = { | |
d7d59fb3 PZ |
1741 | .stack = backtrace_stack, |
1742 | .address = backtrace_address, | |
06d65bda | 1743 | .walk_stack = print_context_stack_bp, |
d7d59fb3 PZ |
1744 | }; |
1745 | ||
56962b44 FW |
1746 | void |
1747 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 | 1748 | { |
927c7a9e FW |
1749 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1750 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1751 | return; |
927c7a9e FW |
1752 | } |
1753 | ||
70791ce9 | 1754 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1755 | |
e8e999cf | 1756 | dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry); |
d7d59fb3 PZ |
1757 | } |
1758 | ||
257ef9d2 | 1759 | #ifdef CONFIG_COMPAT |
d1a797f3 PA |
1760 | |
1761 | #include <asm/compat.h> | |
1762 | ||
257ef9d2 TE |
1763 | static inline int |
1764 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
74193ef0 | 1765 | { |
257ef9d2 TE |
1766 | /* 32-bit process in 64-bit kernel. */ |
1767 | struct stack_frame_ia32 frame; | |
1768 | const void __user *fp; | |
74193ef0 | 1769 | |
257ef9d2 TE |
1770 | if (!test_thread_flag(TIF_IA32)) |
1771 | return 0; | |
1772 | ||
1773 | fp = compat_ptr(regs->bp); | |
1774 | while (entry->nr < PERF_MAX_STACK_DEPTH) { | |
1775 | unsigned long bytes; | |
1776 | frame.next_frame = 0; | |
1777 | frame.return_address = 0; | |
1778 | ||
1779 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); | |
1780 | if (bytes != sizeof(frame)) | |
1781 | break; | |
74193ef0 | 1782 | |
257ef9d2 TE |
1783 | if (fp < compat_ptr(regs->sp)) |
1784 | break; | |
74193ef0 | 1785 | |
70791ce9 | 1786 | perf_callchain_store(entry, frame.return_address); |
257ef9d2 TE |
1787 | fp = compat_ptr(frame.next_frame); |
1788 | } | |
1789 | return 1; | |
d7d59fb3 | 1790 | } |
257ef9d2 TE |
1791 | #else |
1792 | static inline int | |
1793 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1794 | { | |
1795 | return 0; | |
1796 | } | |
1797 | #endif | |
d7d59fb3 | 1798 | |
56962b44 FW |
1799 | void |
1800 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 PZ |
1801 | { |
1802 | struct stack_frame frame; | |
1803 | const void __user *fp; | |
1804 | ||
927c7a9e FW |
1805 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1806 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1807 | return; |
927c7a9e | 1808 | } |
5a6cec3a | 1809 | |
74193ef0 | 1810 | fp = (void __user *)regs->bp; |
d7d59fb3 | 1811 | |
70791ce9 | 1812 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1813 | |
20afc60f AV |
1814 | if (!current->mm) |
1815 | return; | |
1816 | ||
257ef9d2 TE |
1817 | if (perf_callchain_user32(regs, entry)) |
1818 | return; | |
1819 | ||
f9188e02 | 1820 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
257ef9d2 | 1821 | unsigned long bytes; |
038e836e | 1822 | frame.next_frame = NULL; |
d7d59fb3 PZ |
1823 | frame.return_address = 0; |
1824 | ||
257ef9d2 TE |
1825 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); |
1826 | if (bytes != sizeof(frame)) | |
d7d59fb3 PZ |
1827 | break; |
1828 | ||
5a6cec3a | 1829 | if ((unsigned long)fp < regs->sp) |
d7d59fb3 PZ |
1830 | break; |
1831 | ||
70791ce9 | 1832 | perf_callchain_store(entry, frame.return_address); |
038e836e | 1833 | fp = frame.next_frame; |
d7d59fb3 PZ |
1834 | } |
1835 | } | |
1836 | ||
39447b38 ZY |
1837 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
1838 | { | |
1839 | unsigned long ip; | |
dcf46b94 | 1840 | |
39447b38 ZY |
1841 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) |
1842 | ip = perf_guest_cbs->get_guest_ip(); | |
1843 | else | |
1844 | ip = instruction_pointer(regs); | |
dcf46b94 | 1845 | |
39447b38 ZY |
1846 | return ip; |
1847 | } | |
1848 | ||
1849 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
1850 | { | |
1851 | int misc = 0; | |
dcf46b94 | 1852 | |
39447b38 | 1853 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
dcf46b94 ZY |
1854 | if (perf_guest_cbs->is_user_mode()) |
1855 | misc |= PERF_RECORD_MISC_GUEST_USER; | |
1856 | else | |
1857 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
1858 | } else { | |
1859 | if (user_mode(regs)) | |
1860 | misc |= PERF_RECORD_MISC_USER; | |
1861 | else | |
1862 | misc |= PERF_RECORD_MISC_KERNEL; | |
1863 | } | |
1864 | ||
39447b38 | 1865 | if (regs->flags & PERF_EFLAGS_EXACT) |
ab608344 | 1866 | misc |= PERF_RECORD_MISC_EXACT_IP; |
39447b38 ZY |
1867 | |
1868 | return misc; | |
1869 | } | |
b3d9468a GN |
1870 | |
1871 | void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) | |
1872 | { | |
1873 | cap->version = x86_pmu.version; | |
1874 | cap->num_counters_gp = x86_pmu.num_counters; | |
1875 | cap->num_counters_fixed = x86_pmu.num_counters_fixed; | |
1876 | cap->bit_width_gp = x86_pmu.cntval_bits; | |
1877 | cap->bit_width_fixed = x86_pmu.cntval_bits; | |
1878 | cap->events_mask = (unsigned int)x86_pmu.events_maskl; | |
1879 | cap->events_mask_len = x86_pmu.events_mask_len; | |
1880 | } | |
1881 | EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability); |