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Commit | Line | Data |
---|---|---|
241771ef | 1 | /* |
cdd6c482 | 2 | * Performance events x86 architecture code |
241771ef | 3 | * |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
1da53e02 | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
241771ef IM |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
241771ef IM |
16 | #include <linux/capability.h> |
17 | #include <linux/notifier.h> | |
18 | #include <linux/hardirq.h> | |
19 | #include <linux/kprobes.h> | |
4ac13294 | 20 | #include <linux/module.h> |
241771ef IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/sched.h> | |
d7d59fb3 | 23 | #include <linux/uaccess.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
74193ef0 | 25 | #include <linux/highmem.h> |
30dd568c | 26 | #include <linux/cpu.h> |
272d30be | 27 | #include <linux/bitops.h> |
241771ef | 28 | |
241771ef | 29 | #include <asm/apic.h> |
d7d59fb3 | 30 | #include <asm/stacktrace.h> |
4e935e47 | 31 | #include <asm/nmi.h> |
257ef9d2 | 32 | #include <asm/compat.h> |
241771ef | 33 | |
7645a24c PZ |
34 | #if 0 |
35 | #undef wrmsrl | |
36 | #define wrmsrl(msr, val) \ | |
37 | do { \ | |
38 | trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\ | |
39 | (unsigned long)(val)); \ | |
40 | native_write_msr((msr), (u32)((u64)(val)), \ | |
41 | (u32)((u64)(val) >> 32)); \ | |
42 | } while (0) | |
43 | #endif | |
44 | ||
ef21f683 PZ |
45 | /* |
46 | * best effort, GUP based copy_from_user() that assumes IRQ or NMI context | |
47 | */ | |
48 | static unsigned long | |
49 | copy_from_user_nmi(void *to, const void __user *from, unsigned long n) | |
50 | { | |
51 | unsigned long offset, addr = (unsigned long)from; | |
52 | int type = in_nmi() ? KM_NMI : KM_IRQ0; | |
53 | unsigned long size, len = 0; | |
54 | struct page *page; | |
55 | void *map; | |
56 | int ret; | |
57 | ||
58 | do { | |
59 | ret = __get_user_pages_fast(addr, 1, 0, &page); | |
60 | if (!ret) | |
61 | break; | |
62 | ||
63 | offset = addr & (PAGE_SIZE - 1); | |
64 | size = min(PAGE_SIZE - offset, n - len); | |
65 | ||
66 | map = kmap_atomic(page, type); | |
67 | memcpy(to, map+offset, size); | |
68 | kunmap_atomic(map, type); | |
69 | put_page(page); | |
70 | ||
71 | len += size; | |
72 | to += size; | |
73 | addr += size; | |
74 | ||
75 | } while (len < n); | |
76 | ||
77 | return len; | |
78 | } | |
79 | ||
1da53e02 | 80 | struct event_constraint { |
c91e0f5d PZ |
81 | union { |
82 | unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
b622d644 | 83 | u64 idxmsk64; |
c91e0f5d | 84 | }; |
b622d644 PZ |
85 | u64 code; |
86 | u64 cmask; | |
272d30be | 87 | int weight; |
1da53e02 SE |
88 | }; |
89 | ||
38331f62 SE |
90 | struct amd_nb { |
91 | int nb_id; /* NorthBridge id */ | |
92 | int refcnt; /* reference count */ | |
93 | struct perf_event *owners[X86_PMC_IDX_MAX]; | |
94 | struct event_constraint event_constraints[X86_PMC_IDX_MAX]; | |
95 | }; | |
96 | ||
caff2bef PZ |
97 | #define MAX_LBR_ENTRIES 16 |
98 | ||
cdd6c482 | 99 | struct cpu_hw_events { |
ca037701 PZ |
100 | /* |
101 | * Generic x86 PMC bits | |
102 | */ | |
1da53e02 | 103 | struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ |
43f6201a | 104 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
b0f3f28e | 105 | int enabled; |
241771ef | 106 | |
1da53e02 SE |
107 | int n_events; |
108 | int n_added; | |
109 | int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ | |
447a194b | 110 | u64 tags[X86_PMC_IDX_MAX]; |
1da53e02 | 111 | struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ |
ca037701 PZ |
112 | |
113 | /* | |
114 | * Intel DebugStore bits | |
115 | */ | |
116 | struct debug_store *ds; | |
117 | u64 pebs_enabled; | |
118 | ||
caff2bef PZ |
119 | /* |
120 | * Intel LBR bits | |
121 | */ | |
122 | int lbr_users; | |
123 | void *lbr_context; | |
124 | struct perf_branch_stack lbr_stack; | |
125 | struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; | |
126 | ||
ca037701 PZ |
127 | /* |
128 | * AMD specific bits | |
129 | */ | |
38331f62 | 130 | struct amd_nb *amd_nb; |
b690081d SE |
131 | }; |
132 | ||
fce877e3 | 133 | #define __EVENT_CONSTRAINT(c, n, m, w) {\ |
b622d644 | 134 | { .idxmsk64 = (n) }, \ |
c91e0f5d PZ |
135 | .code = (c), \ |
136 | .cmask = (m), \ | |
fce877e3 | 137 | .weight = (w), \ |
c91e0f5d | 138 | } |
b690081d | 139 | |
fce877e3 PZ |
140 | #define EVENT_CONSTRAINT(c, n, m) \ |
141 | __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n)) | |
142 | ||
ca037701 PZ |
143 | /* |
144 | * Constraint on the Event code. | |
145 | */ | |
ed8777fc | 146 | #define INTEL_EVENT_CONSTRAINT(c, n) \ |
a098f448 | 147 | EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT) |
8433be11 | 148 | |
ca037701 PZ |
149 | /* |
150 | * Constraint on the Event code + UMask + fixed-mask | |
a098f448 RR |
151 | * |
152 | * filter mask to validate fixed counter events. | |
153 | * the following filters disqualify for fixed counters: | |
154 | * - inv | |
155 | * - edge | |
156 | * - cnt-mask | |
157 | * The other filters are supported by fixed counters. | |
158 | * The any-thread option is supported starting with v3. | |
ca037701 | 159 | */ |
ed8777fc | 160 | #define FIXED_EVENT_CONSTRAINT(c, n) \ |
a098f448 | 161 | EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK) |
8433be11 | 162 | |
ca037701 PZ |
163 | /* |
164 | * Constraint on the Event code + UMask | |
165 | */ | |
166 | #define PEBS_EVENT_CONSTRAINT(c, n) \ | |
167 | EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) | |
168 | ||
ed8777fc PZ |
169 | #define EVENT_CONSTRAINT_END \ |
170 | EVENT_CONSTRAINT(0, 0, 0) | |
171 | ||
172 | #define for_each_event_constraint(e, c) \ | |
a1f2b70a | 173 | for ((e) = (c); (e)->weight; (e)++) |
b690081d | 174 | |
8db909a7 PZ |
175 | union perf_capabilities { |
176 | struct { | |
177 | u64 lbr_format : 6; | |
178 | u64 pebs_trap : 1; | |
179 | u64 pebs_arch_reg : 1; | |
180 | u64 pebs_format : 4; | |
181 | u64 smm_freeze : 1; | |
182 | }; | |
183 | u64 capabilities; | |
184 | }; | |
185 | ||
241771ef | 186 | /* |
5f4ec28f | 187 | * struct x86_pmu - generic x86 pmu |
241771ef | 188 | */ |
5f4ec28f | 189 | struct x86_pmu { |
ca037701 PZ |
190 | /* |
191 | * Generic x86 PMC bits | |
192 | */ | |
faa28ae0 RR |
193 | const char *name; |
194 | int version; | |
a3288106 | 195 | int (*handle_irq)(struct pt_regs *); |
9e35ad38 | 196 | void (*disable_all)(void); |
11164cd4 | 197 | void (*enable_all)(int added); |
aff3d91a PZ |
198 | void (*enable)(struct perf_event *); |
199 | void (*disable)(struct perf_event *); | |
b4cdc5c2 | 200 | int (*hw_config)(struct perf_event *event); |
a072738e | 201 | int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign); |
169e41eb JSR |
202 | unsigned eventsel; |
203 | unsigned perfctr; | |
b0f3f28e | 204 | u64 (*event_map)(int); |
169e41eb | 205 | int max_events; |
948b1bb8 RR |
206 | int num_counters; |
207 | int num_counters_fixed; | |
208 | int cntval_bits; | |
209 | u64 cntval_mask; | |
04da8a43 | 210 | int apic; |
c619b8ff | 211 | u64 max_period; |
63b14649 PZ |
212 | struct event_constraint * |
213 | (*get_event_constraints)(struct cpu_hw_events *cpuc, | |
214 | struct perf_event *event); | |
215 | ||
c91e0f5d PZ |
216 | void (*put_event_constraints)(struct cpu_hw_events *cpuc, |
217 | struct perf_event *event); | |
63b14649 | 218 | struct event_constraint *event_constraints; |
3c44780b | 219 | void (*quirks)(void); |
3f6da390 | 220 | |
b38b24ea | 221 | int (*cpu_prepare)(int cpu); |
3f6da390 PZ |
222 | void (*cpu_starting)(int cpu); |
223 | void (*cpu_dying)(int cpu); | |
224 | void (*cpu_dead)(int cpu); | |
ca037701 PZ |
225 | |
226 | /* | |
227 | * Intel Arch Perfmon v2+ | |
228 | */ | |
8db909a7 PZ |
229 | u64 intel_ctrl; |
230 | union perf_capabilities intel_cap; | |
ca037701 PZ |
231 | |
232 | /* | |
233 | * Intel DebugStore bits | |
234 | */ | |
235 | int bts, pebs; | |
236 | int pebs_record_size; | |
237 | void (*drain_pebs)(struct pt_regs *regs); | |
238 | struct event_constraint *pebs_constraints; | |
caff2bef PZ |
239 | |
240 | /* | |
241 | * Intel LBR | |
242 | */ | |
243 | unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */ | |
244 | int lbr_nr; /* hardware stack size */ | |
b56a3802 JSR |
245 | }; |
246 | ||
4a06bd85 | 247 | static struct x86_pmu x86_pmu __read_mostly; |
b56a3802 | 248 | |
cdd6c482 | 249 | static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
b0f3f28e PZ |
250 | .enabled = 1, |
251 | }; | |
241771ef | 252 | |
07088edb | 253 | static int x86_perf_event_set_period(struct perf_event *event); |
b690081d | 254 | |
8326f44d | 255 | /* |
dfc65094 | 256 | * Generalized hw caching related hw_event table, filled |
8326f44d | 257 | * in on a per model basis. A value of 0 means |
dfc65094 IM |
258 | * 'not supported', -1 means 'hw_event makes no sense on |
259 | * this CPU', any other value means the raw hw_event | |
8326f44d IM |
260 | * ID. |
261 | */ | |
262 | ||
263 | #define C(x) PERF_COUNT_HW_CACHE_##x | |
264 | ||
265 | static u64 __read_mostly hw_cache_event_ids | |
266 | [PERF_COUNT_HW_CACHE_MAX] | |
267 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
268 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
269 | ||
ee06094f | 270 | /* |
cdd6c482 IM |
271 | * Propagate event elapsed time into the generic event. |
272 | * Can only be executed on the CPU where the event is active. | |
ee06094f IM |
273 | * Returns the delta events processed. |
274 | */ | |
4b7bfd0d | 275 | static u64 |
cc2ad4ba | 276 | x86_perf_event_update(struct perf_event *event) |
ee06094f | 277 | { |
cc2ad4ba | 278 | struct hw_perf_event *hwc = &event->hw; |
948b1bb8 | 279 | int shift = 64 - x86_pmu.cntval_bits; |
ec3232bd | 280 | u64 prev_raw_count, new_raw_count; |
cc2ad4ba | 281 | int idx = hwc->idx; |
ec3232bd | 282 | s64 delta; |
ee06094f | 283 | |
30dd568c MM |
284 | if (idx == X86_PMC_IDX_FIXED_BTS) |
285 | return 0; | |
286 | ||
ee06094f | 287 | /* |
cdd6c482 | 288 | * Careful: an NMI might modify the previous event value. |
ee06094f IM |
289 | * |
290 | * Our tactic to handle this is to first atomically read and | |
291 | * exchange a new raw count - then add that new-prev delta | |
cdd6c482 | 292 | * count to the generic event atomically: |
ee06094f IM |
293 | */ |
294 | again: | |
295 | prev_raw_count = atomic64_read(&hwc->prev_count); | |
cdd6c482 | 296 | rdmsrl(hwc->event_base + idx, new_raw_count); |
ee06094f IM |
297 | |
298 | if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count, | |
299 | new_raw_count) != prev_raw_count) | |
300 | goto again; | |
301 | ||
302 | /* | |
303 | * Now we have the new raw value and have updated the prev | |
304 | * timestamp already. We can now calculate the elapsed delta | |
cdd6c482 | 305 | * (event-)time and add that to the generic event. |
ee06094f IM |
306 | * |
307 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 308 | * of the count. |
ee06094f | 309 | */ |
ec3232bd PZ |
310 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
311 | delta >>= shift; | |
ee06094f | 312 | |
cdd6c482 | 313 | atomic64_add(delta, &event->count); |
ee06094f | 314 | atomic64_sub(delta, &hwc->period_left); |
4b7bfd0d RR |
315 | |
316 | return new_raw_count; | |
ee06094f IM |
317 | } |
318 | ||
cdd6c482 | 319 | static atomic_t active_events; |
4e935e47 PZ |
320 | static DEFINE_MUTEX(pmc_reserve_mutex); |
321 | ||
b27ea29c RR |
322 | #ifdef CONFIG_X86_LOCAL_APIC |
323 | ||
4e935e47 PZ |
324 | static bool reserve_pmc_hardware(void) |
325 | { | |
326 | int i; | |
327 | ||
328 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
329 | disable_lapic_nmi_watchdog(); | |
330 | ||
948b1bb8 | 331 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 | 332 | if (!reserve_perfctr_nmi(x86_pmu.perfctr + i)) |
4e935e47 PZ |
333 | goto perfctr_fail; |
334 | } | |
335 | ||
948b1bb8 | 336 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 | 337 | if (!reserve_evntsel_nmi(x86_pmu.eventsel + i)) |
4e935e47 PZ |
338 | goto eventsel_fail; |
339 | } | |
340 | ||
341 | return true; | |
342 | ||
343 | eventsel_fail: | |
344 | for (i--; i >= 0; i--) | |
4a06bd85 | 345 | release_evntsel_nmi(x86_pmu.eventsel + i); |
4e935e47 | 346 | |
948b1bb8 | 347 | i = x86_pmu.num_counters; |
4e935e47 PZ |
348 | |
349 | perfctr_fail: | |
350 | for (i--; i >= 0; i--) | |
4a06bd85 | 351 | release_perfctr_nmi(x86_pmu.perfctr + i); |
4e935e47 PZ |
352 | |
353 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
354 | enable_lapic_nmi_watchdog(); | |
355 | ||
356 | return false; | |
357 | } | |
358 | ||
359 | static void release_pmc_hardware(void) | |
360 | { | |
361 | int i; | |
362 | ||
948b1bb8 | 363 | for (i = 0; i < x86_pmu.num_counters; i++) { |
4a06bd85 RR |
364 | release_perfctr_nmi(x86_pmu.perfctr + i); |
365 | release_evntsel_nmi(x86_pmu.eventsel + i); | |
4e935e47 PZ |
366 | } |
367 | ||
368 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
369 | enable_lapic_nmi_watchdog(); | |
370 | } | |
371 | ||
b27ea29c RR |
372 | #else |
373 | ||
374 | static bool reserve_pmc_hardware(void) { return true; } | |
375 | static void release_pmc_hardware(void) {} | |
376 | ||
377 | #endif | |
378 | ||
ca037701 PZ |
379 | static int reserve_ds_buffers(void); |
380 | static void release_ds_buffers(void); | |
30dd568c | 381 | |
cdd6c482 | 382 | static void hw_perf_event_destroy(struct perf_event *event) |
4e935e47 | 383 | { |
cdd6c482 | 384 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) { |
4e935e47 | 385 | release_pmc_hardware(); |
ca037701 | 386 | release_ds_buffers(); |
4e935e47 PZ |
387 | mutex_unlock(&pmc_reserve_mutex); |
388 | } | |
389 | } | |
390 | ||
85cf9dba RR |
391 | static inline int x86_pmu_initialized(void) |
392 | { | |
393 | return x86_pmu.handle_irq != NULL; | |
394 | } | |
395 | ||
8326f44d | 396 | static inline int |
cdd6c482 | 397 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr) |
8326f44d IM |
398 | { |
399 | unsigned int cache_type, cache_op, cache_result; | |
400 | u64 config, val; | |
401 | ||
402 | config = attr->config; | |
403 | ||
404 | cache_type = (config >> 0) & 0xff; | |
405 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
406 | return -EINVAL; | |
407 | ||
408 | cache_op = (config >> 8) & 0xff; | |
409 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
410 | return -EINVAL; | |
411 | ||
412 | cache_result = (config >> 16) & 0xff; | |
413 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
414 | return -EINVAL; | |
415 | ||
416 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
417 | ||
418 | if (val == 0) | |
419 | return -ENOENT; | |
420 | ||
421 | if (val == -1) | |
422 | return -EINVAL; | |
423 | ||
424 | hwc->config |= val; | |
425 | ||
426 | return 0; | |
427 | } | |
428 | ||
c1726f34 RR |
429 | static int x86_setup_perfctr(struct perf_event *event) |
430 | { | |
431 | struct perf_event_attr *attr = &event->attr; | |
432 | struct hw_perf_event *hwc = &event->hw; | |
433 | u64 config; | |
434 | ||
435 | if (!hwc->sample_period) { | |
436 | hwc->sample_period = x86_pmu.max_period; | |
437 | hwc->last_period = hwc->sample_period; | |
438 | atomic64_set(&hwc->period_left, hwc->sample_period); | |
439 | } else { | |
440 | /* | |
441 | * If we have a PMU initialized but no APIC | |
442 | * interrupts, we cannot sample hardware | |
443 | * events (user-space has to fall back and | |
444 | * sample via a hrtimer based software event): | |
445 | */ | |
446 | if (!x86_pmu.apic) | |
447 | return -EOPNOTSUPP; | |
448 | } | |
449 | ||
450 | if (attr->type == PERF_TYPE_RAW) | |
451 | return 0; | |
452 | ||
453 | if (attr->type == PERF_TYPE_HW_CACHE) | |
454 | return set_ext_hw_attr(hwc, attr); | |
455 | ||
456 | if (attr->config >= x86_pmu.max_events) | |
457 | return -EINVAL; | |
458 | ||
459 | /* | |
460 | * The generic map: | |
461 | */ | |
462 | config = x86_pmu.event_map(attr->config); | |
463 | ||
464 | if (config == 0) | |
465 | return -ENOENT; | |
466 | ||
467 | if (config == -1LL) | |
468 | return -EINVAL; | |
469 | ||
470 | /* | |
471 | * Branch tracing: | |
472 | */ | |
473 | if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) && | |
474 | (hwc->sample_period == 1)) { | |
475 | /* BTS is not supported by this architecture. */ | |
476 | if (!x86_pmu.bts) | |
477 | return -EOPNOTSUPP; | |
478 | ||
479 | /* BTS is currently only allowed for user-mode. */ | |
480 | if (!attr->exclude_kernel) | |
481 | return -EOPNOTSUPP; | |
482 | } | |
483 | ||
484 | hwc->config |= config; | |
485 | ||
486 | return 0; | |
487 | } | |
4261e0e0 | 488 | |
b4cdc5c2 | 489 | static int x86_pmu_hw_config(struct perf_event *event) |
a072738e | 490 | { |
ab608344 PZ |
491 | if (event->attr.precise_ip) { |
492 | int precise = 0; | |
493 | ||
494 | /* Support for constant skid */ | |
495 | if (x86_pmu.pebs) | |
496 | precise++; | |
497 | ||
498 | /* Support for IP fixup */ | |
499 | if (x86_pmu.lbr_nr) | |
500 | precise++; | |
501 | ||
502 | if (event->attr.precise_ip > precise) | |
503 | return -EOPNOTSUPP; | |
504 | } | |
505 | ||
a072738e CG |
506 | /* |
507 | * Generate PMC IRQs: | |
508 | * (keep 'enabled' bit clear for now) | |
509 | */ | |
b4cdc5c2 | 510 | event->hw.config = ARCH_PERFMON_EVENTSEL_INT; |
a072738e CG |
511 | |
512 | /* | |
513 | * Count user and OS events unless requested not to | |
514 | */ | |
b4cdc5c2 PZ |
515 | if (!event->attr.exclude_user) |
516 | event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; | |
517 | if (!event->attr.exclude_kernel) | |
518 | event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; | |
a072738e | 519 | |
b4cdc5c2 PZ |
520 | if (event->attr.type == PERF_TYPE_RAW) |
521 | event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; | |
a072738e | 522 | |
9d0fcba6 | 523 | return x86_setup_perfctr(event); |
a098f448 RR |
524 | } |
525 | ||
241771ef | 526 | /* |
0d48696f | 527 | * Setup the hardware configuration for a given attr_type |
241771ef | 528 | */ |
cdd6c482 | 529 | static int __hw_perf_event_init(struct perf_event *event) |
241771ef | 530 | { |
4e935e47 | 531 | int err; |
241771ef | 532 | |
85cf9dba RR |
533 | if (!x86_pmu_initialized()) |
534 | return -ENODEV; | |
241771ef | 535 | |
4e935e47 | 536 | err = 0; |
cdd6c482 | 537 | if (!atomic_inc_not_zero(&active_events)) { |
4e935e47 | 538 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 539 | if (atomic_read(&active_events) == 0) { |
30dd568c MM |
540 | if (!reserve_pmc_hardware()) |
541 | err = -EBUSY; | |
4b24a88b | 542 | else { |
ca037701 | 543 | err = reserve_ds_buffers(); |
4b24a88b SE |
544 | if (err) |
545 | release_pmc_hardware(); | |
546 | } | |
30dd568c MM |
547 | } |
548 | if (!err) | |
cdd6c482 | 549 | atomic_inc(&active_events); |
4e935e47 PZ |
550 | mutex_unlock(&pmc_reserve_mutex); |
551 | } | |
552 | if (err) | |
553 | return err; | |
554 | ||
cdd6c482 | 555 | event->destroy = hw_perf_event_destroy; |
a1792cda | 556 | |
4261e0e0 RR |
557 | event->hw.idx = -1; |
558 | event->hw.last_cpu = -1; | |
559 | event->hw.last_tag = ~0ULL; | |
b690081d | 560 | |
9d0fcba6 | 561 | return x86_pmu.hw_config(event); |
4261e0e0 RR |
562 | } |
563 | ||
8c48e444 | 564 | static void x86_pmu_disable_all(void) |
f87ad35d | 565 | { |
cdd6c482 | 566 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
9e35ad38 PZ |
567 | int idx; |
568 | ||
948b1bb8 | 569 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
570 | u64 val; |
571 | ||
43f6201a | 572 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 573 | continue; |
8c48e444 | 574 | rdmsrl(x86_pmu.eventsel + idx, val); |
bb1165d6 | 575 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
4295ee62 | 576 | continue; |
bb1165d6 | 577 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
8c48e444 | 578 | wrmsrl(x86_pmu.eventsel + idx, val); |
f87ad35d | 579 | } |
f87ad35d JSR |
580 | } |
581 | ||
9e35ad38 | 582 | void hw_perf_disable(void) |
b56a3802 | 583 | { |
1da53e02 SE |
584 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
585 | ||
85cf9dba | 586 | if (!x86_pmu_initialized()) |
9e35ad38 | 587 | return; |
1da53e02 | 588 | |
1a6e21f7 PZ |
589 | if (!cpuc->enabled) |
590 | return; | |
591 | ||
592 | cpuc->n_added = 0; | |
593 | cpuc->enabled = 0; | |
594 | barrier(); | |
1da53e02 SE |
595 | |
596 | x86_pmu.disable_all(); | |
b56a3802 | 597 | } |
241771ef | 598 | |
11164cd4 | 599 | static void x86_pmu_enable_all(int added) |
f87ad35d | 600 | { |
cdd6c482 | 601 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
f87ad35d JSR |
602 | int idx; |
603 | ||
948b1bb8 | 604 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
cdd6c482 | 605 | struct perf_event *event = cpuc->events[idx]; |
4295ee62 | 606 | u64 val; |
b0f3f28e | 607 | |
43f6201a | 608 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 609 | continue; |
984b838c | 610 | |
cdd6c482 | 611 | val = event->hw.config; |
bb1165d6 | 612 | val |= ARCH_PERFMON_EVENTSEL_ENABLE; |
8c48e444 | 613 | wrmsrl(x86_pmu.eventsel + idx, val); |
f87ad35d JSR |
614 | } |
615 | } | |
616 | ||
1da53e02 SE |
617 | static const struct pmu pmu; |
618 | ||
619 | static inline int is_x86_event(struct perf_event *event) | |
620 | { | |
621 | return event->pmu == &pmu; | |
622 | } | |
623 | ||
624 | static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) | |
625 | { | |
63b14649 | 626 | struct event_constraint *c, *constraints[X86_PMC_IDX_MAX]; |
1da53e02 | 627 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
c933c1a6 | 628 | int i, j, w, wmax, num = 0; |
1da53e02 SE |
629 | struct hw_perf_event *hwc; |
630 | ||
631 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
632 | ||
633 | for (i = 0; i < n; i++) { | |
b622d644 PZ |
634 | c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]); |
635 | constraints[i] = c; | |
1da53e02 SE |
636 | } |
637 | ||
8113070d SE |
638 | /* |
639 | * fastpath, try to reuse previous register | |
640 | */ | |
c933c1a6 | 641 | for (i = 0; i < n; i++) { |
8113070d | 642 | hwc = &cpuc->event_list[i]->hw; |
81269a08 | 643 | c = constraints[i]; |
8113070d SE |
644 | |
645 | /* never assigned */ | |
646 | if (hwc->idx == -1) | |
647 | break; | |
648 | ||
649 | /* constraint still honored */ | |
63b14649 | 650 | if (!test_bit(hwc->idx, c->idxmsk)) |
8113070d SE |
651 | break; |
652 | ||
653 | /* not already used */ | |
654 | if (test_bit(hwc->idx, used_mask)) | |
655 | break; | |
656 | ||
34538ee7 | 657 | __set_bit(hwc->idx, used_mask); |
8113070d SE |
658 | if (assign) |
659 | assign[i] = hwc->idx; | |
660 | } | |
c933c1a6 | 661 | if (i == n) |
8113070d SE |
662 | goto done; |
663 | ||
664 | /* | |
665 | * begin slow path | |
666 | */ | |
667 | ||
668 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
669 | ||
1da53e02 SE |
670 | /* |
671 | * weight = number of possible counters | |
672 | * | |
673 | * 1 = most constrained, only works on one counter | |
674 | * wmax = least constrained, works on any counter | |
675 | * | |
676 | * assign events to counters starting with most | |
677 | * constrained events. | |
678 | */ | |
948b1bb8 | 679 | wmax = x86_pmu.num_counters; |
1da53e02 SE |
680 | |
681 | /* | |
682 | * when fixed event counters are present, | |
683 | * wmax is incremented by 1 to account | |
684 | * for one more choice | |
685 | */ | |
948b1bb8 | 686 | if (x86_pmu.num_counters_fixed) |
1da53e02 SE |
687 | wmax++; |
688 | ||
8113070d | 689 | for (w = 1, num = n; num && w <= wmax; w++) { |
1da53e02 | 690 | /* for each event */ |
8113070d | 691 | for (i = 0; num && i < n; i++) { |
81269a08 | 692 | c = constraints[i]; |
1da53e02 SE |
693 | hwc = &cpuc->event_list[i]->hw; |
694 | ||
272d30be | 695 | if (c->weight != w) |
1da53e02 SE |
696 | continue; |
697 | ||
984b3f57 | 698 | for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) { |
1da53e02 SE |
699 | if (!test_bit(j, used_mask)) |
700 | break; | |
701 | } | |
702 | ||
703 | if (j == X86_PMC_IDX_MAX) | |
704 | break; | |
1da53e02 | 705 | |
34538ee7 | 706 | __set_bit(j, used_mask); |
8113070d | 707 | |
1da53e02 SE |
708 | if (assign) |
709 | assign[i] = j; | |
710 | num--; | |
711 | } | |
712 | } | |
8113070d | 713 | done: |
1da53e02 SE |
714 | /* |
715 | * scheduling failed or is just a simulation, | |
716 | * free resources if necessary | |
717 | */ | |
718 | if (!assign || num) { | |
719 | for (i = 0; i < n; i++) { | |
720 | if (x86_pmu.put_event_constraints) | |
721 | x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]); | |
722 | } | |
723 | } | |
724 | return num ? -ENOSPC : 0; | |
725 | } | |
726 | ||
727 | /* | |
728 | * dogrp: true if must collect siblings events (group) | |
729 | * returns total number of events and error code | |
730 | */ | |
731 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) | |
732 | { | |
733 | struct perf_event *event; | |
734 | int n, max_count; | |
735 | ||
948b1bb8 | 736 | max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; |
1da53e02 SE |
737 | |
738 | /* current number of events already accepted */ | |
739 | n = cpuc->n_events; | |
740 | ||
741 | if (is_x86_event(leader)) { | |
742 | if (n >= max_count) | |
743 | return -ENOSPC; | |
744 | cpuc->event_list[n] = leader; | |
745 | n++; | |
746 | } | |
747 | if (!dogrp) | |
748 | return n; | |
749 | ||
750 | list_for_each_entry(event, &leader->sibling_list, group_entry) { | |
751 | if (!is_x86_event(event) || | |
8113070d | 752 | event->state <= PERF_EVENT_STATE_OFF) |
1da53e02 SE |
753 | continue; |
754 | ||
755 | if (n >= max_count) | |
756 | return -ENOSPC; | |
757 | ||
758 | cpuc->event_list[n] = event; | |
759 | n++; | |
760 | } | |
761 | return n; | |
762 | } | |
763 | ||
1da53e02 | 764 | static inline void x86_assign_hw_event(struct perf_event *event, |
447a194b | 765 | struct cpu_hw_events *cpuc, int i) |
1da53e02 | 766 | { |
447a194b SE |
767 | struct hw_perf_event *hwc = &event->hw; |
768 | ||
769 | hwc->idx = cpuc->assign[i]; | |
770 | hwc->last_cpu = smp_processor_id(); | |
771 | hwc->last_tag = ++cpuc->tags[i]; | |
1da53e02 SE |
772 | |
773 | if (hwc->idx == X86_PMC_IDX_FIXED_BTS) { | |
774 | hwc->config_base = 0; | |
775 | hwc->event_base = 0; | |
776 | } else if (hwc->idx >= X86_PMC_IDX_FIXED) { | |
777 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
778 | /* | |
779 | * We set it so that event_base + idx in wrmsr/rdmsr maps to | |
780 | * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2: | |
781 | */ | |
782 | hwc->event_base = | |
783 | MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED; | |
784 | } else { | |
785 | hwc->config_base = x86_pmu.eventsel; | |
786 | hwc->event_base = x86_pmu.perfctr; | |
787 | } | |
788 | } | |
789 | ||
447a194b SE |
790 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
791 | struct cpu_hw_events *cpuc, | |
792 | int i) | |
793 | { | |
794 | return hwc->idx == cpuc->assign[i] && | |
795 | hwc->last_cpu == smp_processor_id() && | |
796 | hwc->last_tag == cpuc->tags[i]; | |
797 | } | |
798 | ||
c08053e6 | 799 | static int x86_pmu_start(struct perf_event *event); |
d76a0812 | 800 | static void x86_pmu_stop(struct perf_event *event); |
2e841873 | 801 | |
9e35ad38 | 802 | void hw_perf_enable(void) |
ee06094f | 803 | { |
1da53e02 SE |
804 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
805 | struct perf_event *event; | |
806 | struct hw_perf_event *hwc; | |
11164cd4 | 807 | int i, added = cpuc->n_added; |
1da53e02 | 808 | |
85cf9dba | 809 | if (!x86_pmu_initialized()) |
2b9ff0db | 810 | return; |
1a6e21f7 PZ |
811 | |
812 | if (cpuc->enabled) | |
813 | return; | |
814 | ||
1da53e02 | 815 | if (cpuc->n_added) { |
19925ce7 | 816 | int n_running = cpuc->n_events - cpuc->n_added; |
1da53e02 SE |
817 | /* |
818 | * apply assignment obtained either from | |
819 | * hw_perf_group_sched_in() or x86_pmu_enable() | |
820 | * | |
821 | * step1: save events moving to new counters | |
822 | * step2: reprogram moved events into new counters | |
823 | */ | |
19925ce7 | 824 | for (i = 0; i < n_running; i++) { |
1da53e02 SE |
825 | event = cpuc->event_list[i]; |
826 | hwc = &event->hw; | |
827 | ||
447a194b SE |
828 | /* |
829 | * we can avoid reprogramming counter if: | |
830 | * - assigned same counter as last time | |
831 | * - running on same CPU as last time | |
832 | * - no other event has used the counter since | |
833 | */ | |
834 | if (hwc->idx == -1 || | |
835 | match_prev_assignment(hwc, cpuc, i)) | |
1da53e02 SE |
836 | continue; |
837 | ||
d76a0812 | 838 | x86_pmu_stop(event); |
1da53e02 SE |
839 | } |
840 | ||
841 | for (i = 0; i < cpuc->n_events; i++) { | |
1da53e02 SE |
842 | event = cpuc->event_list[i]; |
843 | hwc = &event->hw; | |
844 | ||
45e16a68 | 845 | if (!match_prev_assignment(hwc, cpuc, i)) |
447a194b | 846 | x86_assign_hw_event(event, cpuc, i); |
45e16a68 PZ |
847 | else if (i < n_running) |
848 | continue; | |
1da53e02 | 849 | |
c08053e6 | 850 | x86_pmu_start(event); |
1da53e02 SE |
851 | } |
852 | cpuc->n_added = 0; | |
853 | perf_events_lapic_init(); | |
854 | } | |
1a6e21f7 PZ |
855 | |
856 | cpuc->enabled = 1; | |
857 | barrier(); | |
858 | ||
11164cd4 | 859 | x86_pmu.enable_all(added); |
ee06094f | 860 | } |
ee06094f | 861 | |
31fa58af RR |
862 | static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, |
863 | u64 enable_mask) | |
b0f3f28e | 864 | { |
31fa58af | 865 | wrmsrl(hwc->config_base + hwc->idx, hwc->config | enable_mask); |
b0f3f28e PZ |
866 | } |
867 | ||
aff3d91a | 868 | static inline void x86_pmu_disable_event(struct perf_event *event) |
b0f3f28e | 869 | { |
aff3d91a | 870 | struct hw_perf_event *hwc = &event->hw; |
7645a24c PZ |
871 | |
872 | wrmsrl(hwc->config_base + hwc->idx, hwc->config); | |
b0f3f28e PZ |
873 | } |
874 | ||
245b2e70 | 875 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 876 | |
ee06094f IM |
877 | /* |
878 | * Set the next IRQ period, based on the hwc->period_left value. | |
cdd6c482 | 879 | * To be called with the event disabled in hw: |
ee06094f | 880 | */ |
e4abb5d4 | 881 | static int |
07088edb | 882 | x86_perf_event_set_period(struct perf_event *event) |
241771ef | 883 | { |
07088edb | 884 | struct hw_perf_event *hwc = &event->hw; |
2f18d1e8 | 885 | s64 left = atomic64_read(&hwc->period_left); |
e4abb5d4 | 886 | s64 period = hwc->sample_period; |
7645a24c | 887 | int ret = 0, idx = hwc->idx; |
ee06094f | 888 | |
30dd568c MM |
889 | if (idx == X86_PMC_IDX_FIXED_BTS) |
890 | return 0; | |
891 | ||
ee06094f | 892 | /* |
af901ca1 | 893 | * If we are way outside a reasonable range then just skip forward: |
ee06094f IM |
894 | */ |
895 | if (unlikely(left <= -period)) { | |
896 | left = period; | |
897 | atomic64_set(&hwc->period_left, left); | |
9e350de3 | 898 | hwc->last_period = period; |
e4abb5d4 | 899 | ret = 1; |
ee06094f IM |
900 | } |
901 | ||
902 | if (unlikely(left <= 0)) { | |
903 | left += period; | |
904 | atomic64_set(&hwc->period_left, left); | |
9e350de3 | 905 | hwc->last_period = period; |
e4abb5d4 | 906 | ret = 1; |
ee06094f | 907 | } |
1c80f4b5 | 908 | /* |
dfc65094 | 909 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
910 | */ |
911 | if (unlikely(left < 2)) | |
912 | left = 2; | |
241771ef | 913 | |
e4abb5d4 PZ |
914 | if (left > x86_pmu.max_period) |
915 | left = x86_pmu.max_period; | |
916 | ||
245b2e70 | 917 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
ee06094f IM |
918 | |
919 | /* | |
cdd6c482 | 920 | * The hw event starts counting from this event offset, |
ee06094f IM |
921 | * mark it to be able to extra future deltas: |
922 | */ | |
2f18d1e8 | 923 | atomic64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 924 | |
7645a24c | 925 | wrmsrl(hwc->event_base + idx, |
948b1bb8 | 926 | (u64)(-left) & x86_pmu.cntval_mask); |
e4abb5d4 | 927 | |
cdd6c482 | 928 | perf_event_update_userpage(event); |
194002b2 | 929 | |
e4abb5d4 | 930 | return ret; |
2f18d1e8 IM |
931 | } |
932 | ||
aff3d91a | 933 | static void x86_pmu_enable_event(struct perf_event *event) |
7c90cc45 | 934 | { |
cdd6c482 | 935 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
7c90cc45 | 936 | if (cpuc->enabled) |
31fa58af RR |
937 | __x86_pmu_enable_event(&event->hw, |
938 | ARCH_PERFMON_EVENTSEL_ENABLE); | |
241771ef IM |
939 | } |
940 | ||
b690081d | 941 | /* |
1da53e02 SE |
942 | * activate a single event |
943 | * | |
944 | * The event is added to the group of enabled events | |
945 | * but only if it can be scehduled with existing events. | |
946 | * | |
947 | * Called with PMU disabled. If successful and return value 1, | |
948 | * then guaranteed to call perf_enable() and hw_perf_enable() | |
fe9081cc PZ |
949 | */ |
950 | static int x86_pmu_enable(struct perf_event *event) | |
951 | { | |
952 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1da53e02 SE |
953 | struct hw_perf_event *hwc; |
954 | int assign[X86_PMC_IDX_MAX]; | |
955 | int n, n0, ret; | |
fe9081cc | 956 | |
1da53e02 | 957 | hwc = &event->hw; |
fe9081cc | 958 | |
1da53e02 SE |
959 | n0 = cpuc->n_events; |
960 | n = collect_events(cpuc, event, false); | |
961 | if (n < 0) | |
962 | return n; | |
53b441a5 | 963 | |
a072738e | 964 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
1da53e02 SE |
965 | if (ret) |
966 | return ret; | |
967 | /* | |
968 | * copy new assignment, now we know it is possible | |
969 | * will be used by hw_perf_enable() | |
970 | */ | |
971 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
7e2ae347 | 972 | |
1da53e02 | 973 | cpuc->n_events = n; |
356e1f2e | 974 | cpuc->n_added += n - n0; |
95cdd2e7 IM |
975 | |
976 | return 0; | |
241771ef IM |
977 | } |
978 | ||
d76a0812 SE |
979 | static int x86_pmu_start(struct perf_event *event) |
980 | { | |
c08053e6 PZ |
981 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
982 | int idx = event->hw.idx; | |
983 | ||
984 | if (idx == -1) | |
d76a0812 SE |
985 | return -EAGAIN; |
986 | ||
07088edb | 987 | x86_perf_event_set_period(event); |
c08053e6 PZ |
988 | cpuc->events[idx] = event; |
989 | __set_bit(idx, cpuc->active_mask); | |
aff3d91a | 990 | x86_pmu.enable(event); |
c08053e6 | 991 | perf_event_update_userpage(event); |
d76a0812 SE |
992 | |
993 | return 0; | |
994 | } | |
995 | ||
cdd6c482 | 996 | static void x86_pmu_unthrottle(struct perf_event *event) |
a78ac325 | 997 | { |
71e2d282 PZ |
998 | int ret = x86_pmu_start(event); |
999 | WARN_ON_ONCE(ret); | |
a78ac325 PZ |
1000 | } |
1001 | ||
cdd6c482 | 1002 | void perf_event_print_debug(void) |
241771ef | 1003 | { |
2f18d1e8 | 1004 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
ca037701 | 1005 | u64 pebs; |
cdd6c482 | 1006 | struct cpu_hw_events *cpuc; |
5bb9efe3 | 1007 | unsigned long flags; |
1e125676 IM |
1008 | int cpu, idx; |
1009 | ||
948b1bb8 | 1010 | if (!x86_pmu.num_counters) |
1e125676 | 1011 | return; |
241771ef | 1012 | |
5bb9efe3 | 1013 | local_irq_save(flags); |
241771ef IM |
1014 | |
1015 | cpu = smp_processor_id(); | |
cdd6c482 | 1016 | cpuc = &per_cpu(cpu_hw_events, cpu); |
241771ef | 1017 | |
faa28ae0 | 1018 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1019 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1020 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1021 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1022 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
ca037701 | 1023 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); |
a1ef58f4 JSR |
1024 | |
1025 | pr_info("\n"); | |
1026 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1027 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1028 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1029 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
ca037701 | 1030 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); |
f87ad35d | 1031 | } |
7645a24c | 1032 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
241771ef | 1033 | |
948b1bb8 | 1034 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
4a06bd85 RR |
1035 | rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl); |
1036 | rdmsrl(x86_pmu.perfctr + idx, pmc_count); | |
241771ef | 1037 | |
245b2e70 | 1038 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 1039 | |
a1ef58f4 | 1040 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1041 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1042 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1043 | cpu, idx, pmc_count); |
a1ef58f4 | 1044 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1045 | cpu, idx, prev_left); |
241771ef | 1046 | } |
948b1bb8 | 1047 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
1048 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1049 | ||
a1ef58f4 | 1050 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1051 | cpu, idx, pmc_count); |
1052 | } | |
5bb9efe3 | 1053 | local_irq_restore(flags); |
241771ef IM |
1054 | } |
1055 | ||
d76a0812 | 1056 | static void x86_pmu_stop(struct perf_event *event) |
241771ef | 1057 | { |
d76a0812 | 1058 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
cdd6c482 | 1059 | struct hw_perf_event *hwc = &event->hw; |
2e841873 | 1060 | int idx = hwc->idx; |
241771ef | 1061 | |
71e2d282 PZ |
1062 | if (!__test_and_clear_bit(idx, cpuc->active_mask)) |
1063 | return; | |
1064 | ||
aff3d91a | 1065 | x86_pmu.disable(event); |
241771ef | 1066 | |
ee06094f | 1067 | /* |
cdd6c482 | 1068 | * Drain the remaining delta count out of a event |
ee06094f IM |
1069 | * that we are disabling: |
1070 | */ | |
cc2ad4ba | 1071 | x86_perf_event_update(event); |
30dd568c | 1072 | |
cdd6c482 | 1073 | cpuc->events[idx] = NULL; |
2e841873 PZ |
1074 | } |
1075 | ||
1076 | static void x86_pmu_disable(struct perf_event *event) | |
1077 | { | |
1078 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1079 | int i; | |
1080 | ||
d76a0812 | 1081 | x86_pmu_stop(event); |
194002b2 | 1082 | |
1da53e02 SE |
1083 | for (i = 0; i < cpuc->n_events; i++) { |
1084 | if (event == cpuc->event_list[i]) { | |
1085 | ||
1086 | if (x86_pmu.put_event_constraints) | |
1087 | x86_pmu.put_event_constraints(cpuc, event); | |
1088 | ||
1089 | while (++i < cpuc->n_events) | |
1090 | cpuc->event_list[i-1] = cpuc->event_list[i]; | |
1091 | ||
1092 | --cpuc->n_events; | |
6c9687ab | 1093 | break; |
1da53e02 SE |
1094 | } |
1095 | } | |
cdd6c482 | 1096 | perf_event_update_userpage(event); |
241771ef IM |
1097 | } |
1098 | ||
8c48e444 | 1099 | static int x86_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1100 | { |
df1a132b | 1101 | struct perf_sample_data data; |
cdd6c482 IM |
1102 | struct cpu_hw_events *cpuc; |
1103 | struct perf_event *event; | |
1104 | struct hw_perf_event *hwc; | |
11d1578f | 1105 | int idx, handled = 0; |
9029a5e3 IM |
1106 | u64 val; |
1107 | ||
dc1d628a | 1108 | perf_sample_data_init(&data, 0); |
df1a132b | 1109 | |
cdd6c482 | 1110 | cpuc = &__get_cpu_var(cpu_hw_events); |
962bf7a6 | 1111 | |
948b1bb8 | 1112 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
43f6201a | 1113 | if (!test_bit(idx, cpuc->active_mask)) |
a29aa8a7 | 1114 | continue; |
962bf7a6 | 1115 | |
cdd6c482 IM |
1116 | event = cpuc->events[idx]; |
1117 | hwc = &event->hw; | |
a4016a79 | 1118 | |
cc2ad4ba | 1119 | val = x86_perf_event_update(event); |
948b1bb8 | 1120 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
48e22d56 | 1121 | continue; |
962bf7a6 | 1122 | |
9e350de3 | 1123 | /* |
cdd6c482 | 1124 | * event overflow |
9e350de3 PZ |
1125 | */ |
1126 | handled = 1; | |
cdd6c482 | 1127 | data.period = event->hw.last_period; |
9e350de3 | 1128 | |
07088edb | 1129 | if (!x86_perf_event_set_period(event)) |
e4abb5d4 PZ |
1130 | continue; |
1131 | ||
cdd6c482 | 1132 | if (perf_event_overflow(event, 1, &data, regs)) |
71e2d282 | 1133 | x86_pmu_stop(event); |
a29aa8a7 | 1134 | } |
962bf7a6 | 1135 | |
9e350de3 PZ |
1136 | if (handled) |
1137 | inc_irq_stat(apic_perf_irqs); | |
1138 | ||
a29aa8a7 RR |
1139 | return handled; |
1140 | } | |
39d81eab | 1141 | |
b6276f35 PZ |
1142 | void smp_perf_pending_interrupt(struct pt_regs *regs) |
1143 | { | |
1144 | irq_enter(); | |
1145 | ack_APIC_irq(); | |
1146 | inc_irq_stat(apic_pending_irqs); | |
cdd6c482 | 1147 | perf_event_do_pending(); |
b6276f35 PZ |
1148 | irq_exit(); |
1149 | } | |
1150 | ||
cdd6c482 | 1151 | void set_perf_event_pending(void) |
b6276f35 | 1152 | { |
04da8a43 | 1153 | #ifdef CONFIG_X86_LOCAL_APIC |
7d428966 PZ |
1154 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
1155 | return; | |
1156 | ||
b6276f35 | 1157 | apic->send_IPI_self(LOCAL_PENDING_VECTOR); |
04da8a43 | 1158 | #endif |
b6276f35 PZ |
1159 | } |
1160 | ||
cdd6c482 | 1161 | void perf_events_lapic_init(void) |
241771ef | 1162 | { |
04da8a43 | 1163 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
241771ef | 1164 | return; |
85cf9dba | 1165 | |
241771ef | 1166 | /* |
c323d95f | 1167 | * Always use NMI for PMU |
241771ef | 1168 | */ |
c323d95f | 1169 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1170 | } |
1171 | ||
1172 | static int __kprobes | |
cdd6c482 | 1173 | perf_event_nmi_handler(struct notifier_block *self, |
241771ef IM |
1174 | unsigned long cmd, void *__args) |
1175 | { | |
1176 | struct die_args *args = __args; | |
1177 | struct pt_regs *regs; | |
b0f3f28e | 1178 | |
cdd6c482 | 1179 | if (!atomic_read(&active_events)) |
63a809a2 PZ |
1180 | return NOTIFY_DONE; |
1181 | ||
b0f3f28e PZ |
1182 | switch (cmd) { |
1183 | case DIE_NMI: | |
1184 | case DIE_NMI_IPI: | |
1185 | break; | |
241771ef | 1186 | |
b0f3f28e | 1187 | default: |
241771ef | 1188 | return NOTIFY_DONE; |
b0f3f28e | 1189 | } |
241771ef IM |
1190 | |
1191 | regs = args->regs; | |
1192 | ||
1193 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
a4016a79 PZ |
1194 | /* |
1195 | * Can't rely on the handled return value to say it was our NMI, two | |
cdd6c482 | 1196 | * events could trigger 'simultaneously' raising two back-to-back NMIs. |
a4016a79 PZ |
1197 | * |
1198 | * If the first NMI handles both, the latter will be empty and daze | |
1199 | * the CPU. | |
1200 | */ | |
a3288106 | 1201 | x86_pmu.handle_irq(regs); |
241771ef | 1202 | |
a4016a79 | 1203 | return NOTIFY_STOP; |
241771ef IM |
1204 | } |
1205 | ||
f22f54f4 PZ |
1206 | static __read_mostly struct notifier_block perf_event_nmi_notifier = { |
1207 | .notifier_call = perf_event_nmi_handler, | |
1208 | .next = NULL, | |
1209 | .priority = 1 | |
1210 | }; | |
1211 | ||
63b14649 | 1212 | static struct event_constraint unconstrained; |
38331f62 | 1213 | static struct event_constraint emptyconstraint; |
63b14649 | 1214 | |
63b14649 | 1215 | static struct event_constraint * |
f22f54f4 | 1216 | x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event) |
1da53e02 | 1217 | { |
63b14649 | 1218 | struct event_constraint *c; |
1da53e02 | 1219 | |
1da53e02 SE |
1220 | if (x86_pmu.event_constraints) { |
1221 | for_each_event_constraint(c, x86_pmu.event_constraints) { | |
63b14649 PZ |
1222 | if ((event->hw.config & c->cmask) == c->code) |
1223 | return c; | |
1da53e02 SE |
1224 | } |
1225 | } | |
63b14649 PZ |
1226 | |
1227 | return &unconstrained; | |
1da53e02 SE |
1228 | } |
1229 | ||
1da53e02 | 1230 | static int x86_event_sched_in(struct perf_event *event, |
6e37738a | 1231 | struct perf_cpu_context *cpuctx) |
1da53e02 SE |
1232 | { |
1233 | int ret = 0; | |
1234 | ||
1235 | event->state = PERF_EVENT_STATE_ACTIVE; | |
6e37738a | 1236 | event->oncpu = smp_processor_id(); |
1da53e02 SE |
1237 | event->tstamp_running += event->ctx->time - event->tstamp_stopped; |
1238 | ||
1239 | if (!is_x86_event(event)) | |
1240 | ret = event->pmu->enable(event); | |
1241 | ||
1242 | if (!ret && !is_software_event(event)) | |
1243 | cpuctx->active_oncpu++; | |
1244 | ||
1245 | if (!ret && event->attr.exclusive) | |
1246 | cpuctx->exclusive = 1; | |
1247 | ||
1248 | return ret; | |
1249 | } | |
1250 | ||
1251 | static void x86_event_sched_out(struct perf_event *event, | |
6e37738a | 1252 | struct perf_cpu_context *cpuctx) |
1da53e02 SE |
1253 | { |
1254 | event->state = PERF_EVENT_STATE_INACTIVE; | |
1255 | event->oncpu = -1; | |
1256 | ||
1257 | if (!is_x86_event(event)) | |
1258 | event->pmu->disable(event); | |
1259 | ||
1260 | event->tstamp_running -= event->ctx->time - event->tstamp_stopped; | |
1261 | ||
1262 | if (!is_software_event(event)) | |
1263 | cpuctx->active_oncpu--; | |
1264 | ||
1265 | if (event->attr.exclusive || !cpuctx->active_oncpu) | |
1266 | cpuctx->exclusive = 0; | |
1267 | } | |
1268 | ||
1269 | /* | |
1270 | * Called to enable a whole group of events. | |
1271 | * Returns 1 if the group was enabled, or -EAGAIN if it could not be. | |
1272 | * Assumes the caller has disabled interrupts and has | |
1273 | * frozen the PMU with hw_perf_save_disable. | |
1274 | * | |
1275 | * called with PMU disabled. If successful and return value 1, | |
1276 | * then guaranteed to call perf_enable() and hw_perf_enable() | |
1277 | */ | |
1278 | int hw_perf_group_sched_in(struct perf_event *leader, | |
1279 | struct perf_cpu_context *cpuctx, | |
6e37738a | 1280 | struct perf_event_context *ctx) |
1da53e02 | 1281 | { |
6e37738a | 1282 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
1da53e02 SE |
1283 | struct perf_event *sub; |
1284 | int assign[X86_PMC_IDX_MAX]; | |
1285 | int n0, n1, ret; | |
1286 | ||
0b861225 CG |
1287 | if (!x86_pmu_initialized()) |
1288 | return 0; | |
1289 | ||
1da53e02 SE |
1290 | /* n0 = total number of events */ |
1291 | n0 = collect_events(cpuc, leader, true); | |
1292 | if (n0 < 0) | |
1293 | return n0; | |
1294 | ||
a072738e | 1295 | ret = x86_pmu.schedule_events(cpuc, n0, assign); |
1da53e02 SE |
1296 | if (ret) |
1297 | return ret; | |
1298 | ||
6e37738a | 1299 | ret = x86_event_sched_in(leader, cpuctx); |
1da53e02 SE |
1300 | if (ret) |
1301 | return ret; | |
1302 | ||
1303 | n1 = 1; | |
1304 | list_for_each_entry(sub, &leader->sibling_list, group_entry) { | |
8113070d | 1305 | if (sub->state > PERF_EVENT_STATE_OFF) { |
6e37738a | 1306 | ret = x86_event_sched_in(sub, cpuctx); |
1da53e02 SE |
1307 | if (ret) |
1308 | goto undo; | |
1309 | ++n1; | |
1310 | } | |
1311 | } | |
1312 | /* | |
1313 | * copy new assignment, now we know it is possible | |
1314 | * will be used by hw_perf_enable() | |
1315 | */ | |
1316 | memcpy(cpuc->assign, assign, n0*sizeof(int)); | |
1317 | ||
1318 | cpuc->n_events = n0; | |
356e1f2e | 1319 | cpuc->n_added += n1; |
1da53e02 SE |
1320 | ctx->nr_active += n1; |
1321 | ||
1322 | /* | |
1323 | * 1 means successful and events are active | |
1324 | * This is not quite true because we defer | |
1325 | * actual activation until hw_perf_enable() but | |
1326 | * this way we* ensure caller won't try to enable | |
1327 | * individual events | |
1328 | */ | |
1329 | return 1; | |
1330 | undo: | |
6e37738a | 1331 | x86_event_sched_out(leader, cpuctx); |
1da53e02 SE |
1332 | n0 = 1; |
1333 | list_for_each_entry(sub, &leader->sibling_list, group_entry) { | |
1334 | if (sub->state == PERF_EVENT_STATE_ACTIVE) { | |
6e37738a | 1335 | x86_event_sched_out(sub, cpuctx); |
1da53e02 SE |
1336 | if (++n0 == n1) |
1337 | break; | |
1338 | } | |
1339 | } | |
1340 | return ret; | |
1341 | } | |
1342 | ||
f22f54f4 PZ |
1343 | #include "perf_event_amd.c" |
1344 | #include "perf_event_p6.c" | |
a072738e | 1345 | #include "perf_event_p4.c" |
caff2bef | 1346 | #include "perf_event_intel_lbr.c" |
ca037701 | 1347 | #include "perf_event_intel_ds.c" |
f22f54f4 | 1348 | #include "perf_event_intel.c" |
f87ad35d | 1349 | |
3f6da390 PZ |
1350 | static int __cpuinit |
1351 | x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) | |
1352 | { | |
1353 | unsigned int cpu = (long)hcpu; | |
b38b24ea | 1354 | int ret = NOTIFY_OK; |
3f6da390 PZ |
1355 | |
1356 | switch (action & ~CPU_TASKS_FROZEN) { | |
1357 | case CPU_UP_PREPARE: | |
1358 | if (x86_pmu.cpu_prepare) | |
b38b24ea | 1359 | ret = x86_pmu.cpu_prepare(cpu); |
3f6da390 PZ |
1360 | break; |
1361 | ||
1362 | case CPU_STARTING: | |
1363 | if (x86_pmu.cpu_starting) | |
1364 | x86_pmu.cpu_starting(cpu); | |
1365 | break; | |
1366 | ||
1367 | case CPU_DYING: | |
1368 | if (x86_pmu.cpu_dying) | |
1369 | x86_pmu.cpu_dying(cpu); | |
1370 | break; | |
1371 | ||
b38b24ea | 1372 | case CPU_UP_CANCELED: |
3f6da390 PZ |
1373 | case CPU_DEAD: |
1374 | if (x86_pmu.cpu_dead) | |
1375 | x86_pmu.cpu_dead(cpu); | |
1376 | break; | |
1377 | ||
1378 | default: | |
1379 | break; | |
1380 | } | |
1381 | ||
b38b24ea | 1382 | return ret; |
3f6da390 PZ |
1383 | } |
1384 | ||
12558038 CG |
1385 | static void __init pmu_check_apic(void) |
1386 | { | |
1387 | if (cpu_has_apic) | |
1388 | return; | |
1389 | ||
1390 | x86_pmu.apic = 0; | |
1391 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); | |
1392 | pr_info("no hardware sampling interrupt available.\n"); | |
1393 | } | |
1394 | ||
cdd6c482 | 1395 | void __init init_hw_perf_events(void) |
b56a3802 | 1396 | { |
b622d644 | 1397 | struct event_constraint *c; |
72eae04d RR |
1398 | int err; |
1399 | ||
cdd6c482 | 1400 | pr_info("Performance Events: "); |
1123e3ad | 1401 | |
b56a3802 JSR |
1402 | switch (boot_cpu_data.x86_vendor) { |
1403 | case X86_VENDOR_INTEL: | |
72eae04d | 1404 | err = intel_pmu_init(); |
b56a3802 | 1405 | break; |
f87ad35d | 1406 | case X86_VENDOR_AMD: |
72eae04d | 1407 | err = amd_pmu_init(); |
f87ad35d | 1408 | break; |
4138960a RR |
1409 | default: |
1410 | return; | |
b56a3802 | 1411 | } |
1123e3ad | 1412 | if (err != 0) { |
cdd6c482 | 1413 | pr_cont("no PMU driver, software events only.\n"); |
b56a3802 | 1414 | return; |
1123e3ad | 1415 | } |
b56a3802 | 1416 | |
12558038 CG |
1417 | pmu_check_apic(); |
1418 | ||
1123e3ad | 1419 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1420 | |
3c44780b PZ |
1421 | if (x86_pmu.quirks) |
1422 | x86_pmu.quirks(); | |
1423 | ||
948b1bb8 | 1424 | if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) { |
cdd6c482 | 1425 | WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", |
948b1bb8 RR |
1426 | x86_pmu.num_counters, X86_PMC_MAX_GENERIC); |
1427 | x86_pmu.num_counters = X86_PMC_MAX_GENERIC; | |
241771ef | 1428 | } |
948b1bb8 RR |
1429 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; |
1430 | perf_max_events = x86_pmu.num_counters; | |
241771ef | 1431 | |
948b1bb8 | 1432 | if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { |
cdd6c482 | 1433 | WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", |
948b1bb8 RR |
1434 | x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED); |
1435 | x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; | |
703e937c | 1436 | } |
862a1a5f | 1437 | |
d6dc0b4e | 1438 | x86_pmu.intel_ctrl |= |
948b1bb8 | 1439 | ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED; |
241771ef | 1440 | |
cdd6c482 IM |
1441 | perf_events_lapic_init(); |
1442 | register_die_notifier(&perf_event_nmi_notifier); | |
1123e3ad | 1443 | |
63b14649 | 1444 | unconstrained = (struct event_constraint) |
948b1bb8 RR |
1445 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
1446 | 0, x86_pmu.num_counters); | |
63b14649 | 1447 | |
b622d644 PZ |
1448 | if (x86_pmu.event_constraints) { |
1449 | for_each_event_constraint(c, x86_pmu.event_constraints) { | |
a098f448 | 1450 | if (c->cmask != X86_RAW_EVENT_MASK) |
b622d644 PZ |
1451 | continue; |
1452 | ||
948b1bb8 RR |
1453 | c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; |
1454 | c->weight += x86_pmu.num_counters; | |
b622d644 PZ |
1455 | } |
1456 | } | |
1457 | ||
57c0c15b | 1458 | pr_info("... version: %d\n", x86_pmu.version); |
948b1bb8 RR |
1459 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); |
1460 | pr_info("... generic registers: %d\n", x86_pmu.num_counters); | |
1461 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); | |
57c0c15b | 1462 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
948b1bb8 | 1463 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); |
d6dc0b4e | 1464 | pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); |
3f6da390 PZ |
1465 | |
1466 | perf_cpu_notifier(x86_pmu_notifier); | |
241771ef | 1467 | } |
621a01ea | 1468 | |
cdd6c482 | 1469 | static inline void x86_pmu_read(struct perf_event *event) |
ee06094f | 1470 | { |
cc2ad4ba | 1471 | x86_perf_event_update(event); |
ee06094f IM |
1472 | } |
1473 | ||
4aeb0b42 RR |
1474 | static const struct pmu pmu = { |
1475 | .enable = x86_pmu_enable, | |
1476 | .disable = x86_pmu_disable, | |
d76a0812 SE |
1477 | .start = x86_pmu_start, |
1478 | .stop = x86_pmu_stop, | |
4aeb0b42 | 1479 | .read = x86_pmu_read, |
a78ac325 | 1480 | .unthrottle = x86_pmu_unthrottle, |
621a01ea IM |
1481 | }; |
1482 | ||
ca037701 PZ |
1483 | /* |
1484 | * validate that we can schedule this event | |
1485 | */ | |
1486 | static int validate_event(struct perf_event *event) | |
1487 | { | |
1488 | struct cpu_hw_events *fake_cpuc; | |
1489 | struct event_constraint *c; | |
1490 | int ret = 0; | |
1491 | ||
1492 | fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO); | |
1493 | if (!fake_cpuc) | |
1494 | return -ENOMEM; | |
1495 | ||
1496 | c = x86_pmu.get_event_constraints(fake_cpuc, event); | |
1497 | ||
1498 | if (!c || !c->weight) | |
1499 | ret = -ENOSPC; | |
1500 | ||
1501 | if (x86_pmu.put_event_constraints) | |
1502 | x86_pmu.put_event_constraints(fake_cpuc, event); | |
1503 | ||
1504 | kfree(fake_cpuc); | |
1505 | ||
1506 | return ret; | |
1507 | } | |
1508 | ||
1da53e02 SE |
1509 | /* |
1510 | * validate a single event group | |
1511 | * | |
1512 | * validation include: | |
184f412c IM |
1513 | * - check events are compatible which each other |
1514 | * - events do not compete for the same counter | |
1515 | * - number of events <= number of counters | |
1da53e02 SE |
1516 | * |
1517 | * validation ensures the group can be loaded onto the | |
1518 | * PMU if it was the only group available. | |
1519 | */ | |
fe9081cc PZ |
1520 | static int validate_group(struct perf_event *event) |
1521 | { | |
1da53e02 | 1522 | struct perf_event *leader = event->group_leader; |
502568d5 PZ |
1523 | struct cpu_hw_events *fake_cpuc; |
1524 | int ret, n; | |
fe9081cc | 1525 | |
502568d5 PZ |
1526 | ret = -ENOMEM; |
1527 | fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO); | |
1528 | if (!fake_cpuc) | |
1529 | goto out; | |
fe9081cc | 1530 | |
1da53e02 SE |
1531 | /* |
1532 | * the event is not yet connected with its | |
1533 | * siblings therefore we must first collect | |
1534 | * existing siblings, then add the new event | |
1535 | * before we can simulate the scheduling | |
1536 | */ | |
502568d5 PZ |
1537 | ret = -ENOSPC; |
1538 | n = collect_events(fake_cpuc, leader, true); | |
1da53e02 | 1539 | if (n < 0) |
502568d5 | 1540 | goto out_free; |
fe9081cc | 1541 | |
502568d5 PZ |
1542 | fake_cpuc->n_events = n; |
1543 | n = collect_events(fake_cpuc, event, false); | |
1da53e02 | 1544 | if (n < 0) |
502568d5 | 1545 | goto out_free; |
fe9081cc | 1546 | |
502568d5 | 1547 | fake_cpuc->n_events = n; |
1da53e02 | 1548 | |
a072738e | 1549 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
502568d5 PZ |
1550 | |
1551 | out_free: | |
1552 | kfree(fake_cpuc); | |
1553 | out: | |
1554 | return ret; | |
fe9081cc PZ |
1555 | } |
1556 | ||
cdd6c482 | 1557 | const struct pmu *hw_perf_event_init(struct perf_event *event) |
621a01ea | 1558 | { |
8113070d | 1559 | const struct pmu *tmp; |
621a01ea IM |
1560 | int err; |
1561 | ||
cdd6c482 | 1562 | err = __hw_perf_event_init(event); |
fe9081cc | 1563 | if (!err) { |
8113070d SE |
1564 | /* |
1565 | * we temporarily connect event to its pmu | |
1566 | * such that validate_group() can classify | |
1567 | * it as an x86 event using is_x86_event() | |
1568 | */ | |
1569 | tmp = event->pmu; | |
1570 | event->pmu = &pmu; | |
1571 | ||
fe9081cc PZ |
1572 | if (event->group_leader != event) |
1573 | err = validate_group(event); | |
ca037701 PZ |
1574 | else |
1575 | err = validate_event(event); | |
8113070d SE |
1576 | |
1577 | event->pmu = tmp; | |
fe9081cc | 1578 | } |
a1792cda | 1579 | if (err) { |
cdd6c482 IM |
1580 | if (event->destroy) |
1581 | event->destroy(event); | |
9ea98e19 | 1582 | return ERR_PTR(err); |
a1792cda | 1583 | } |
621a01ea | 1584 | |
4aeb0b42 | 1585 | return &pmu; |
621a01ea | 1586 | } |
d7d59fb3 PZ |
1587 | |
1588 | /* | |
1589 | * callchain support | |
1590 | */ | |
1591 | ||
1592 | static inline | |
f9188e02 | 1593 | void callchain_store(struct perf_callchain_entry *entry, u64 ip) |
d7d59fb3 | 1594 | { |
f9188e02 | 1595 | if (entry->nr < PERF_MAX_STACK_DEPTH) |
d7d59fb3 PZ |
1596 | entry->ip[entry->nr++] = ip; |
1597 | } | |
1598 | ||
245b2e70 TH |
1599 | static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry); |
1600 | static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry); | |
d7d59fb3 PZ |
1601 | |
1602 | ||
1603 | static void | |
1604 | backtrace_warning_symbol(void *data, char *msg, unsigned long symbol) | |
1605 | { | |
1606 | /* Ignore warnings */ | |
1607 | } | |
1608 | ||
1609 | static void backtrace_warning(void *data, char *msg) | |
1610 | { | |
1611 | /* Ignore warnings */ | |
1612 | } | |
1613 | ||
1614 | static int backtrace_stack(void *data, char *name) | |
1615 | { | |
038e836e | 1616 | return 0; |
d7d59fb3 PZ |
1617 | } |
1618 | ||
1619 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1620 | { | |
1621 | struct perf_callchain_entry *entry = data; | |
1622 | ||
6f4dee06 | 1623 | callchain_store(entry, addr); |
d7d59fb3 PZ |
1624 | } |
1625 | ||
1626 | static const struct stacktrace_ops backtrace_ops = { | |
1627 | .warning = backtrace_warning, | |
1628 | .warning_symbol = backtrace_warning_symbol, | |
1629 | .stack = backtrace_stack, | |
1630 | .address = backtrace_address, | |
06d65bda | 1631 | .walk_stack = print_context_stack_bp, |
d7d59fb3 PZ |
1632 | }; |
1633 | ||
038e836e IM |
1634 | #include "../dumpstack.h" |
1635 | ||
d7d59fb3 PZ |
1636 | static void |
1637 | perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1638 | { | |
f9188e02 | 1639 | callchain_store(entry, PERF_CONTEXT_KERNEL); |
038e836e | 1640 | callchain_store(entry, regs->ip); |
d7d59fb3 | 1641 | |
48b5ba9c | 1642 | dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry); |
d7d59fb3 PZ |
1643 | } |
1644 | ||
257ef9d2 TE |
1645 | #ifdef CONFIG_COMPAT |
1646 | static inline int | |
1647 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
74193ef0 | 1648 | { |
257ef9d2 TE |
1649 | /* 32-bit process in 64-bit kernel. */ |
1650 | struct stack_frame_ia32 frame; | |
1651 | const void __user *fp; | |
74193ef0 | 1652 | |
257ef9d2 TE |
1653 | if (!test_thread_flag(TIF_IA32)) |
1654 | return 0; | |
1655 | ||
1656 | fp = compat_ptr(regs->bp); | |
1657 | while (entry->nr < PERF_MAX_STACK_DEPTH) { | |
1658 | unsigned long bytes; | |
1659 | frame.next_frame = 0; | |
1660 | frame.return_address = 0; | |
1661 | ||
1662 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); | |
1663 | if (bytes != sizeof(frame)) | |
1664 | break; | |
74193ef0 | 1665 | |
257ef9d2 TE |
1666 | if (fp < compat_ptr(regs->sp)) |
1667 | break; | |
74193ef0 | 1668 | |
257ef9d2 TE |
1669 | callchain_store(entry, frame.return_address); |
1670 | fp = compat_ptr(frame.next_frame); | |
1671 | } | |
1672 | return 1; | |
d7d59fb3 | 1673 | } |
257ef9d2 TE |
1674 | #else |
1675 | static inline int | |
1676 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1677 | { | |
1678 | return 0; | |
1679 | } | |
1680 | #endif | |
d7d59fb3 PZ |
1681 | |
1682 | static void | |
1683 | perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1684 | { | |
1685 | struct stack_frame frame; | |
1686 | const void __user *fp; | |
1687 | ||
5a6cec3a IM |
1688 | if (!user_mode(regs)) |
1689 | regs = task_pt_regs(current); | |
1690 | ||
74193ef0 | 1691 | fp = (void __user *)regs->bp; |
d7d59fb3 | 1692 | |
f9188e02 | 1693 | callchain_store(entry, PERF_CONTEXT_USER); |
d7d59fb3 PZ |
1694 | callchain_store(entry, regs->ip); |
1695 | ||
257ef9d2 TE |
1696 | if (perf_callchain_user32(regs, entry)) |
1697 | return; | |
1698 | ||
f9188e02 | 1699 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
257ef9d2 | 1700 | unsigned long bytes; |
038e836e | 1701 | frame.next_frame = NULL; |
d7d59fb3 PZ |
1702 | frame.return_address = 0; |
1703 | ||
257ef9d2 TE |
1704 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); |
1705 | if (bytes != sizeof(frame)) | |
d7d59fb3 PZ |
1706 | break; |
1707 | ||
5a6cec3a | 1708 | if ((unsigned long)fp < regs->sp) |
d7d59fb3 PZ |
1709 | break; |
1710 | ||
1711 | callchain_store(entry, frame.return_address); | |
038e836e | 1712 | fp = frame.next_frame; |
d7d59fb3 PZ |
1713 | } |
1714 | } | |
1715 | ||
1716 | static void | |
1717 | perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1718 | { | |
1719 | int is_user; | |
1720 | ||
1721 | if (!regs) | |
1722 | return; | |
1723 | ||
1724 | is_user = user_mode(regs); | |
1725 | ||
d7d59fb3 PZ |
1726 | if (is_user && current->state != TASK_RUNNING) |
1727 | return; | |
1728 | ||
1729 | if (!is_user) | |
1730 | perf_callchain_kernel(regs, entry); | |
1731 | ||
1732 | if (current->mm) | |
1733 | perf_callchain_user(regs, entry); | |
1734 | } | |
1735 | ||
1736 | struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) | |
1737 | { | |
1738 | struct perf_callchain_entry *entry; | |
1739 | ||
39447b38 ZY |
1740 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1741 | /* TODO: We don't support guest os callchain now */ | |
1742 | return NULL; | |
1743 | } | |
1744 | ||
d7d59fb3 | 1745 | if (in_nmi()) |
245b2e70 | 1746 | entry = &__get_cpu_var(pmc_nmi_entry); |
d7d59fb3 | 1747 | else |
245b2e70 | 1748 | entry = &__get_cpu_var(pmc_irq_entry); |
d7d59fb3 PZ |
1749 | |
1750 | entry->nr = 0; | |
1751 | ||
1752 | perf_do_callchain(regs, entry); | |
1753 | ||
1754 | return entry; | |
1755 | } | |
5331d7b8 FW |
1756 | |
1757 | void perf_arch_fetch_caller_regs(struct pt_regs *regs, unsigned long ip, int skip) | |
1758 | { | |
1759 | regs->ip = ip; | |
1760 | /* | |
1761 | * perf_arch_fetch_caller_regs adds another call, we need to increment | |
1762 | * the skip level | |
1763 | */ | |
1764 | regs->bp = rewind_frame_pointer(skip + 1); | |
1765 | regs->cs = __KERNEL_CS; | |
1766 | local_save_flags(regs->flags); | |
1767 | } | |
39447b38 ZY |
1768 | |
1769 | unsigned long perf_instruction_pointer(struct pt_regs *regs) | |
1770 | { | |
1771 | unsigned long ip; | |
dcf46b94 | 1772 | |
39447b38 ZY |
1773 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) |
1774 | ip = perf_guest_cbs->get_guest_ip(); | |
1775 | else | |
1776 | ip = instruction_pointer(regs); | |
dcf46b94 | 1777 | |
39447b38 ZY |
1778 | return ip; |
1779 | } | |
1780 | ||
1781 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
1782 | { | |
1783 | int misc = 0; | |
dcf46b94 | 1784 | |
39447b38 | 1785 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
dcf46b94 ZY |
1786 | if (perf_guest_cbs->is_user_mode()) |
1787 | misc |= PERF_RECORD_MISC_GUEST_USER; | |
1788 | else | |
1789 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
1790 | } else { | |
1791 | if (user_mode(regs)) | |
1792 | misc |= PERF_RECORD_MISC_USER; | |
1793 | else | |
1794 | misc |= PERF_RECORD_MISC_KERNEL; | |
1795 | } | |
1796 | ||
39447b38 | 1797 | if (regs->flags & PERF_EFLAGS_EXACT) |
ab608344 | 1798 | misc |= PERF_RECORD_MISC_EXACT_IP; |
39447b38 ZY |
1799 | |
1800 | return misc; | |
1801 | } |