]>
Commit | Line | Data |
---|---|---|
241771ef | 1 | /* |
cdd6c482 | 2 | * Performance events x86 architecture code |
241771ef | 3 | * |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
1da53e02 | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
241771ef IM |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
241771ef IM |
16 | #include <linux/capability.h> |
17 | #include <linux/notifier.h> | |
18 | #include <linux/hardirq.h> | |
19 | #include <linux/kprobes.h> | |
4ac13294 | 20 | #include <linux/module.h> |
241771ef IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/sched.h> | |
d7d59fb3 | 23 | #include <linux/uaccess.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
30dd568c | 25 | #include <linux/cpu.h> |
272d30be | 26 | #include <linux/bitops.h> |
0c9d42ed | 27 | #include <linux/device.h> |
241771ef | 28 | |
241771ef | 29 | #include <asm/apic.h> |
d7d59fb3 | 30 | #include <asm/stacktrace.h> |
4e935e47 | 31 | #include <asm/nmi.h> |
69092624 | 32 | #include <asm/smp.h> |
c8e5910e | 33 | #include <asm/alternative.h> |
e3f3541c | 34 | #include <asm/timer.h> |
241771ef | 35 | |
de0428a7 KW |
36 | #include "perf_event.h" |
37 | ||
de0428a7 | 38 | struct x86_pmu x86_pmu __read_mostly; |
efc9f05d | 39 | |
de0428a7 | 40 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
b0f3f28e PZ |
41 | .enabled = 1, |
42 | }; | |
241771ef | 43 | |
de0428a7 | 44 | u64 __read_mostly hw_cache_event_ids |
8326f44d IM |
45 | [PERF_COUNT_HW_CACHE_MAX] |
46 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
47 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
de0428a7 | 48 | u64 __read_mostly hw_cache_extra_regs |
e994d7d2 AK |
49 | [PERF_COUNT_HW_CACHE_MAX] |
50 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
51 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
8326f44d | 52 | |
ee06094f | 53 | /* |
cdd6c482 IM |
54 | * Propagate event elapsed time into the generic event. |
55 | * Can only be executed on the CPU where the event is active. | |
ee06094f IM |
56 | * Returns the delta events processed. |
57 | */ | |
de0428a7 | 58 | u64 x86_perf_event_update(struct perf_event *event) |
ee06094f | 59 | { |
cc2ad4ba | 60 | struct hw_perf_event *hwc = &event->hw; |
948b1bb8 | 61 | int shift = 64 - x86_pmu.cntval_bits; |
ec3232bd | 62 | u64 prev_raw_count, new_raw_count; |
cc2ad4ba | 63 | int idx = hwc->idx; |
ec3232bd | 64 | s64 delta; |
ee06094f | 65 | |
15c7ad51 | 66 | if (idx == INTEL_PMC_IDX_FIXED_BTS) |
30dd568c MM |
67 | return 0; |
68 | ||
ee06094f | 69 | /* |
cdd6c482 | 70 | * Careful: an NMI might modify the previous event value. |
ee06094f IM |
71 | * |
72 | * Our tactic to handle this is to first atomically read and | |
73 | * exchange a new raw count - then add that new-prev delta | |
cdd6c482 | 74 | * count to the generic event atomically: |
ee06094f IM |
75 | */ |
76 | again: | |
e7850595 | 77 | prev_raw_count = local64_read(&hwc->prev_count); |
c48b6053 | 78 | rdpmcl(hwc->event_base_rdpmc, new_raw_count); |
ee06094f | 79 | |
e7850595 | 80 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
ee06094f IM |
81 | new_raw_count) != prev_raw_count) |
82 | goto again; | |
83 | ||
84 | /* | |
85 | * Now we have the new raw value and have updated the prev | |
86 | * timestamp already. We can now calculate the elapsed delta | |
cdd6c482 | 87 | * (event-)time and add that to the generic event. |
ee06094f IM |
88 | * |
89 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 90 | * of the count. |
ee06094f | 91 | */ |
ec3232bd PZ |
92 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
93 | delta >>= shift; | |
ee06094f | 94 | |
e7850595 PZ |
95 | local64_add(delta, &event->count); |
96 | local64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
97 | |
98 | return new_raw_count; | |
ee06094f IM |
99 | } |
100 | ||
a7e3ed1e AK |
101 | /* |
102 | * Find and validate any extra registers to set up. | |
103 | */ | |
104 | static int x86_pmu_extra_regs(u64 config, struct perf_event *event) | |
105 | { | |
efc9f05d | 106 | struct hw_perf_event_extra *reg; |
a7e3ed1e AK |
107 | struct extra_reg *er; |
108 | ||
efc9f05d | 109 | reg = &event->hw.extra_reg; |
a7e3ed1e AK |
110 | |
111 | if (!x86_pmu.extra_regs) | |
112 | return 0; | |
113 | ||
114 | for (er = x86_pmu.extra_regs; er->msr; er++) { | |
115 | if (er->event != (config & er->config_mask)) | |
116 | continue; | |
117 | if (event->attr.config1 & ~er->valid_mask) | |
118 | return -EINVAL; | |
efc9f05d SE |
119 | |
120 | reg->idx = er->idx; | |
121 | reg->config = event->attr.config1; | |
122 | reg->reg = er->msr; | |
a7e3ed1e AK |
123 | break; |
124 | } | |
125 | return 0; | |
126 | } | |
127 | ||
cdd6c482 | 128 | static atomic_t active_events; |
4e935e47 PZ |
129 | static DEFINE_MUTEX(pmc_reserve_mutex); |
130 | ||
b27ea29c RR |
131 | #ifdef CONFIG_X86_LOCAL_APIC |
132 | ||
4e935e47 PZ |
133 | static bool reserve_pmc_hardware(void) |
134 | { | |
135 | int i; | |
136 | ||
948b1bb8 | 137 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 138 | if (!reserve_perfctr_nmi(x86_pmu_event_addr(i))) |
4e935e47 PZ |
139 | goto perfctr_fail; |
140 | } | |
141 | ||
948b1bb8 | 142 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 143 | if (!reserve_evntsel_nmi(x86_pmu_config_addr(i))) |
4e935e47 PZ |
144 | goto eventsel_fail; |
145 | } | |
146 | ||
147 | return true; | |
148 | ||
149 | eventsel_fail: | |
150 | for (i--; i >= 0; i--) | |
41bf4989 | 151 | release_evntsel_nmi(x86_pmu_config_addr(i)); |
4e935e47 | 152 | |
948b1bb8 | 153 | i = x86_pmu.num_counters; |
4e935e47 PZ |
154 | |
155 | perfctr_fail: | |
156 | for (i--; i >= 0; i--) | |
41bf4989 | 157 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
4e935e47 | 158 | |
4e935e47 PZ |
159 | return false; |
160 | } | |
161 | ||
162 | static void release_pmc_hardware(void) | |
163 | { | |
164 | int i; | |
165 | ||
948b1bb8 | 166 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 RR |
167 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
168 | release_evntsel_nmi(x86_pmu_config_addr(i)); | |
4e935e47 | 169 | } |
4e935e47 PZ |
170 | } |
171 | ||
b27ea29c RR |
172 | #else |
173 | ||
174 | static bool reserve_pmc_hardware(void) { return true; } | |
175 | static void release_pmc_hardware(void) {} | |
176 | ||
177 | #endif | |
178 | ||
33c6d6a7 DZ |
179 | static bool check_hw_exists(void) |
180 | { | |
f285f92f | 181 | u64 val, val_new = ~0; |
4407204c | 182 | int i, reg, ret = 0; |
33c6d6a7 | 183 | |
4407204c PZ |
184 | /* |
185 | * Check to see if the BIOS enabled any of the counters, if so | |
186 | * complain and bail. | |
187 | */ | |
188 | for (i = 0; i < x86_pmu.num_counters; i++) { | |
41bf4989 | 189 | reg = x86_pmu_config_addr(i); |
4407204c PZ |
190 | ret = rdmsrl_safe(reg, &val); |
191 | if (ret) | |
192 | goto msr_fail; | |
193 | if (val & ARCH_PERFMON_EVENTSEL_ENABLE) | |
194 | goto bios_fail; | |
195 | } | |
196 | ||
197 | if (x86_pmu.num_counters_fixed) { | |
198 | reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
199 | ret = rdmsrl_safe(reg, &val); | |
200 | if (ret) | |
201 | goto msr_fail; | |
202 | for (i = 0; i < x86_pmu.num_counters_fixed; i++) { | |
203 | if (val & (0x03 << i*4)) | |
204 | goto bios_fail; | |
205 | } | |
206 | } | |
207 | ||
208 | /* | |
209 | * Now write a value and read it back to see if it matches, | |
210 | * this is needed to detect certain hardware emulators (qemu/kvm) | |
211 | * that don't trap on the MSR access and always return 0s. | |
212 | */ | |
33c6d6a7 | 213 | val = 0xabcdUL; |
f285f92f RR |
214 | reg = x86_pmu_event_addr(0); |
215 | ret = wrmsrl_safe(reg, val); | |
216 | ret |= rdmsrl_safe(reg, &val_new); | |
33c6d6a7 | 217 | if (ret || val != val_new) |
4407204c | 218 | goto msr_fail; |
33c6d6a7 DZ |
219 | |
220 | return true; | |
4407204c PZ |
221 | |
222 | bios_fail: | |
45daae57 IM |
223 | /* |
224 | * We still allow the PMU driver to operate: | |
225 | */ | |
226 | printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n"); | |
4407204c | 227 | printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg, val); |
45daae57 IM |
228 | |
229 | return true; | |
4407204c PZ |
230 | |
231 | msr_fail: | |
232 | printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n"); | |
f285f92f | 233 | printk(KERN_ERR "Failed to access perfctr msr (MSR %x is %Lx)\n", reg, val_new); |
45daae57 | 234 | |
4407204c | 235 | return false; |
33c6d6a7 DZ |
236 | } |
237 | ||
cdd6c482 | 238 | static void hw_perf_event_destroy(struct perf_event *event) |
4e935e47 | 239 | { |
cdd6c482 | 240 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) { |
4e935e47 | 241 | release_pmc_hardware(); |
ca037701 | 242 | release_ds_buffers(); |
4e935e47 PZ |
243 | mutex_unlock(&pmc_reserve_mutex); |
244 | } | |
245 | } | |
246 | ||
85cf9dba RR |
247 | static inline int x86_pmu_initialized(void) |
248 | { | |
249 | return x86_pmu.handle_irq != NULL; | |
250 | } | |
251 | ||
8326f44d | 252 | static inline int |
e994d7d2 | 253 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) |
8326f44d | 254 | { |
e994d7d2 | 255 | struct perf_event_attr *attr = &event->attr; |
8326f44d IM |
256 | unsigned int cache_type, cache_op, cache_result; |
257 | u64 config, val; | |
258 | ||
259 | config = attr->config; | |
260 | ||
261 | cache_type = (config >> 0) & 0xff; | |
262 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
263 | return -EINVAL; | |
264 | ||
265 | cache_op = (config >> 8) & 0xff; | |
266 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
267 | return -EINVAL; | |
268 | ||
269 | cache_result = (config >> 16) & 0xff; | |
270 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
271 | return -EINVAL; | |
272 | ||
273 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
274 | ||
275 | if (val == 0) | |
276 | return -ENOENT; | |
277 | ||
278 | if (val == -1) | |
279 | return -EINVAL; | |
280 | ||
281 | hwc->config |= val; | |
e994d7d2 AK |
282 | attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result]; |
283 | return x86_pmu_extra_regs(val, event); | |
8326f44d IM |
284 | } |
285 | ||
de0428a7 | 286 | int x86_setup_perfctr(struct perf_event *event) |
c1726f34 RR |
287 | { |
288 | struct perf_event_attr *attr = &event->attr; | |
289 | struct hw_perf_event *hwc = &event->hw; | |
290 | u64 config; | |
291 | ||
6c7e550f | 292 | if (!is_sampling_event(event)) { |
c1726f34 RR |
293 | hwc->sample_period = x86_pmu.max_period; |
294 | hwc->last_period = hwc->sample_period; | |
e7850595 | 295 | local64_set(&hwc->period_left, hwc->sample_period); |
c1726f34 RR |
296 | } else { |
297 | /* | |
298 | * If we have a PMU initialized but no APIC | |
299 | * interrupts, we cannot sample hardware | |
300 | * events (user-space has to fall back and | |
301 | * sample via a hrtimer based software event): | |
302 | */ | |
303 | if (!x86_pmu.apic) | |
304 | return -EOPNOTSUPP; | |
305 | } | |
306 | ||
307 | if (attr->type == PERF_TYPE_RAW) | |
ed13ec58 | 308 | return x86_pmu_extra_regs(event->attr.config, event); |
c1726f34 RR |
309 | |
310 | if (attr->type == PERF_TYPE_HW_CACHE) | |
e994d7d2 | 311 | return set_ext_hw_attr(hwc, event); |
c1726f34 RR |
312 | |
313 | if (attr->config >= x86_pmu.max_events) | |
314 | return -EINVAL; | |
315 | ||
316 | /* | |
317 | * The generic map: | |
318 | */ | |
319 | config = x86_pmu.event_map(attr->config); | |
320 | ||
321 | if (config == 0) | |
322 | return -ENOENT; | |
323 | ||
324 | if (config == -1LL) | |
325 | return -EINVAL; | |
326 | ||
327 | /* | |
328 | * Branch tracing: | |
329 | */ | |
18a073a3 PZ |
330 | if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS && |
331 | !attr->freq && hwc->sample_period == 1) { | |
c1726f34 | 332 | /* BTS is not supported by this architecture. */ |
6809b6ea | 333 | if (!x86_pmu.bts_active) |
c1726f34 RR |
334 | return -EOPNOTSUPP; |
335 | ||
336 | /* BTS is currently only allowed for user-mode. */ | |
337 | if (!attr->exclude_kernel) | |
338 | return -EOPNOTSUPP; | |
339 | } | |
340 | ||
341 | hwc->config |= config; | |
342 | ||
343 | return 0; | |
344 | } | |
4261e0e0 | 345 | |
ff3fb511 SE |
346 | /* |
347 | * check that branch_sample_type is compatible with | |
348 | * settings needed for precise_ip > 1 which implies | |
349 | * using the LBR to capture ALL taken branches at the | |
350 | * priv levels of the measurement | |
351 | */ | |
352 | static inline int precise_br_compat(struct perf_event *event) | |
353 | { | |
354 | u64 m = event->attr.branch_sample_type; | |
355 | u64 b = 0; | |
356 | ||
357 | /* must capture all branches */ | |
358 | if (!(m & PERF_SAMPLE_BRANCH_ANY)) | |
359 | return 0; | |
360 | ||
361 | m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER; | |
362 | ||
363 | if (!event->attr.exclude_user) | |
364 | b |= PERF_SAMPLE_BRANCH_USER; | |
365 | ||
366 | if (!event->attr.exclude_kernel) | |
367 | b |= PERF_SAMPLE_BRANCH_KERNEL; | |
368 | ||
369 | /* | |
370 | * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86 | |
371 | */ | |
372 | ||
373 | return m == b; | |
374 | } | |
375 | ||
de0428a7 | 376 | int x86_pmu_hw_config(struct perf_event *event) |
a072738e | 377 | { |
ab608344 PZ |
378 | if (event->attr.precise_ip) { |
379 | int precise = 0; | |
380 | ||
381 | /* Support for constant skid */ | |
c93dc84c | 382 | if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) { |
ab608344 PZ |
383 | precise++; |
384 | ||
5553be26 PZ |
385 | /* Support for IP fixup */ |
386 | if (x86_pmu.lbr_nr) | |
387 | precise++; | |
388 | } | |
ab608344 PZ |
389 | |
390 | if (event->attr.precise_ip > precise) | |
391 | return -EOPNOTSUPP; | |
ff3fb511 SE |
392 | /* |
393 | * check that PEBS LBR correction does not conflict with | |
394 | * whatever the user is asking with attr->branch_sample_type | |
395 | */ | |
396 | if (event->attr.precise_ip > 1) { | |
397 | u64 *br_type = &event->attr.branch_sample_type; | |
398 | ||
399 | if (has_branch_stack(event)) { | |
400 | if (!precise_br_compat(event)) | |
401 | return -EOPNOTSUPP; | |
402 | ||
403 | /* branch_sample_type is compatible */ | |
404 | ||
405 | } else { | |
406 | /* | |
407 | * user did not specify branch_sample_type | |
408 | * | |
409 | * For PEBS fixups, we capture all | |
410 | * the branches at the priv level of the | |
411 | * event. | |
412 | */ | |
413 | *br_type = PERF_SAMPLE_BRANCH_ANY; | |
414 | ||
415 | if (!event->attr.exclude_user) | |
416 | *br_type |= PERF_SAMPLE_BRANCH_USER; | |
417 | ||
418 | if (!event->attr.exclude_kernel) | |
419 | *br_type |= PERF_SAMPLE_BRANCH_KERNEL; | |
420 | } | |
421 | } | |
ab608344 PZ |
422 | } |
423 | ||
a072738e CG |
424 | /* |
425 | * Generate PMC IRQs: | |
426 | * (keep 'enabled' bit clear for now) | |
427 | */ | |
b4cdc5c2 | 428 | event->hw.config = ARCH_PERFMON_EVENTSEL_INT; |
a072738e CG |
429 | |
430 | /* | |
431 | * Count user and OS events unless requested not to | |
432 | */ | |
b4cdc5c2 PZ |
433 | if (!event->attr.exclude_user) |
434 | event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; | |
435 | if (!event->attr.exclude_kernel) | |
436 | event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; | |
a072738e | 437 | |
b4cdc5c2 PZ |
438 | if (event->attr.type == PERF_TYPE_RAW) |
439 | event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; | |
a072738e | 440 | |
9d0fcba6 | 441 | return x86_setup_perfctr(event); |
a098f448 RR |
442 | } |
443 | ||
241771ef | 444 | /* |
0d48696f | 445 | * Setup the hardware configuration for a given attr_type |
241771ef | 446 | */ |
b0a873eb | 447 | static int __x86_pmu_event_init(struct perf_event *event) |
241771ef | 448 | { |
4e935e47 | 449 | int err; |
241771ef | 450 | |
85cf9dba RR |
451 | if (!x86_pmu_initialized()) |
452 | return -ENODEV; | |
241771ef | 453 | |
4e935e47 | 454 | err = 0; |
cdd6c482 | 455 | if (!atomic_inc_not_zero(&active_events)) { |
4e935e47 | 456 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 457 | if (atomic_read(&active_events) == 0) { |
30dd568c MM |
458 | if (!reserve_pmc_hardware()) |
459 | err = -EBUSY; | |
f80c9e30 PZ |
460 | else |
461 | reserve_ds_buffers(); | |
30dd568c MM |
462 | } |
463 | if (!err) | |
cdd6c482 | 464 | atomic_inc(&active_events); |
4e935e47 PZ |
465 | mutex_unlock(&pmc_reserve_mutex); |
466 | } | |
467 | if (err) | |
468 | return err; | |
469 | ||
cdd6c482 | 470 | event->destroy = hw_perf_event_destroy; |
a1792cda | 471 | |
4261e0e0 RR |
472 | event->hw.idx = -1; |
473 | event->hw.last_cpu = -1; | |
474 | event->hw.last_tag = ~0ULL; | |
b690081d | 475 | |
efc9f05d SE |
476 | /* mark unused */ |
477 | event->hw.extra_reg.idx = EXTRA_REG_NONE; | |
b36817e8 SE |
478 | event->hw.branch_reg.idx = EXTRA_REG_NONE; |
479 | ||
9d0fcba6 | 480 | return x86_pmu.hw_config(event); |
4261e0e0 RR |
481 | } |
482 | ||
de0428a7 | 483 | void x86_pmu_disable_all(void) |
f87ad35d | 484 | { |
cdd6c482 | 485 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
9e35ad38 PZ |
486 | int idx; |
487 | ||
948b1bb8 | 488 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
489 | u64 val; |
490 | ||
43f6201a | 491 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 492 | continue; |
41bf4989 | 493 | rdmsrl(x86_pmu_config_addr(idx), val); |
bb1165d6 | 494 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
4295ee62 | 495 | continue; |
bb1165d6 | 496 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
41bf4989 | 497 | wrmsrl(x86_pmu_config_addr(idx), val); |
f87ad35d | 498 | } |
f87ad35d JSR |
499 | } |
500 | ||
a4eaf7f1 | 501 | static void x86_pmu_disable(struct pmu *pmu) |
b56a3802 | 502 | { |
1da53e02 SE |
503 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
504 | ||
85cf9dba | 505 | if (!x86_pmu_initialized()) |
9e35ad38 | 506 | return; |
1da53e02 | 507 | |
1a6e21f7 PZ |
508 | if (!cpuc->enabled) |
509 | return; | |
510 | ||
511 | cpuc->n_added = 0; | |
512 | cpuc->enabled = 0; | |
513 | barrier(); | |
1da53e02 SE |
514 | |
515 | x86_pmu.disable_all(); | |
b56a3802 | 516 | } |
241771ef | 517 | |
de0428a7 | 518 | void x86_pmu_enable_all(int added) |
f87ad35d | 519 | { |
cdd6c482 | 520 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
f87ad35d JSR |
521 | int idx; |
522 | ||
948b1bb8 | 523 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
d45dd923 | 524 | struct hw_perf_event *hwc = &cpuc->events[idx]->hw; |
b0f3f28e | 525 | |
43f6201a | 526 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 527 | continue; |
984b838c | 528 | |
d45dd923 | 529 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); |
f87ad35d JSR |
530 | } |
531 | } | |
532 | ||
51b0fe39 | 533 | static struct pmu pmu; |
1da53e02 SE |
534 | |
535 | static inline int is_x86_event(struct perf_event *event) | |
536 | { | |
537 | return event->pmu == &pmu; | |
538 | } | |
539 | ||
1e2ad28f RR |
540 | /* |
541 | * Event scheduler state: | |
542 | * | |
543 | * Assign events iterating over all events and counters, beginning | |
544 | * with events with least weights first. Keep the current iterator | |
545 | * state in struct sched_state. | |
546 | */ | |
547 | struct sched_state { | |
548 | int weight; | |
549 | int event; /* event index */ | |
550 | int counter; /* counter index */ | |
551 | int unassigned; /* number of events to be assigned left */ | |
552 | unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
553 | }; | |
554 | ||
bc1738f6 RR |
555 | /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */ |
556 | #define SCHED_STATES_MAX 2 | |
557 | ||
1e2ad28f RR |
558 | struct perf_sched { |
559 | int max_weight; | |
560 | int max_events; | |
561 | struct event_constraint **constraints; | |
562 | struct sched_state state; | |
bc1738f6 RR |
563 | int saved_states; |
564 | struct sched_state saved[SCHED_STATES_MAX]; | |
1e2ad28f RR |
565 | }; |
566 | ||
567 | /* | |
568 | * Initialize interator that runs through all events and counters. | |
569 | */ | |
570 | static void perf_sched_init(struct perf_sched *sched, struct event_constraint **c, | |
571 | int num, int wmin, int wmax) | |
572 | { | |
573 | int idx; | |
574 | ||
575 | memset(sched, 0, sizeof(*sched)); | |
576 | sched->max_events = num; | |
577 | sched->max_weight = wmax; | |
578 | sched->constraints = c; | |
579 | ||
580 | for (idx = 0; idx < num; idx++) { | |
581 | if (c[idx]->weight == wmin) | |
582 | break; | |
583 | } | |
584 | ||
585 | sched->state.event = idx; /* start with min weight */ | |
586 | sched->state.weight = wmin; | |
587 | sched->state.unassigned = num; | |
588 | } | |
589 | ||
bc1738f6 RR |
590 | static void perf_sched_save_state(struct perf_sched *sched) |
591 | { | |
592 | if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX)) | |
593 | return; | |
594 | ||
595 | sched->saved[sched->saved_states] = sched->state; | |
596 | sched->saved_states++; | |
597 | } | |
598 | ||
599 | static bool perf_sched_restore_state(struct perf_sched *sched) | |
600 | { | |
601 | if (!sched->saved_states) | |
602 | return false; | |
603 | ||
604 | sched->saved_states--; | |
605 | sched->state = sched->saved[sched->saved_states]; | |
606 | ||
607 | /* continue with next counter: */ | |
608 | clear_bit(sched->state.counter++, sched->state.used); | |
609 | ||
610 | return true; | |
611 | } | |
612 | ||
1e2ad28f RR |
613 | /* |
614 | * Select a counter for the current event to schedule. Return true on | |
615 | * success. | |
616 | */ | |
bc1738f6 | 617 | static bool __perf_sched_find_counter(struct perf_sched *sched) |
1e2ad28f RR |
618 | { |
619 | struct event_constraint *c; | |
620 | int idx; | |
621 | ||
622 | if (!sched->state.unassigned) | |
623 | return false; | |
624 | ||
625 | if (sched->state.event >= sched->max_events) | |
626 | return false; | |
627 | ||
628 | c = sched->constraints[sched->state.event]; | |
629 | ||
4defea85 | 630 | /* Prefer fixed purpose counters */ |
15c7ad51 RR |
631 | if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) { |
632 | idx = INTEL_PMC_IDX_FIXED; | |
307b1cd7 | 633 | for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) { |
4defea85 PZ |
634 | if (!__test_and_set_bit(idx, sched->state.used)) |
635 | goto done; | |
636 | } | |
637 | } | |
1e2ad28f RR |
638 | /* Grab the first unused counter starting with idx */ |
639 | idx = sched->state.counter; | |
15c7ad51 | 640 | for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) { |
1e2ad28f | 641 | if (!__test_and_set_bit(idx, sched->state.used)) |
4defea85 | 642 | goto done; |
1e2ad28f | 643 | } |
1e2ad28f | 644 | |
4defea85 PZ |
645 | return false; |
646 | ||
647 | done: | |
648 | sched->state.counter = idx; | |
1e2ad28f | 649 | |
bc1738f6 RR |
650 | if (c->overlap) |
651 | perf_sched_save_state(sched); | |
652 | ||
653 | return true; | |
654 | } | |
655 | ||
656 | static bool perf_sched_find_counter(struct perf_sched *sched) | |
657 | { | |
658 | while (!__perf_sched_find_counter(sched)) { | |
659 | if (!perf_sched_restore_state(sched)) | |
660 | return false; | |
661 | } | |
662 | ||
1e2ad28f RR |
663 | return true; |
664 | } | |
665 | ||
666 | /* | |
667 | * Go through all unassigned events and find the next one to schedule. | |
668 | * Take events with the least weight first. Return true on success. | |
669 | */ | |
670 | static bool perf_sched_next_event(struct perf_sched *sched) | |
671 | { | |
672 | struct event_constraint *c; | |
673 | ||
674 | if (!sched->state.unassigned || !--sched->state.unassigned) | |
675 | return false; | |
676 | ||
677 | do { | |
678 | /* next event */ | |
679 | sched->state.event++; | |
680 | if (sched->state.event >= sched->max_events) { | |
681 | /* next weight */ | |
682 | sched->state.event = 0; | |
683 | sched->state.weight++; | |
684 | if (sched->state.weight > sched->max_weight) | |
685 | return false; | |
686 | } | |
687 | c = sched->constraints[sched->state.event]; | |
688 | } while (c->weight != sched->state.weight); | |
689 | ||
690 | sched->state.counter = 0; /* start with first counter */ | |
691 | ||
692 | return true; | |
693 | } | |
694 | ||
695 | /* | |
696 | * Assign a counter for each event. | |
697 | */ | |
4b4969b1 YZ |
698 | int perf_assign_events(struct event_constraint **constraints, int n, |
699 | int wmin, int wmax, int *assign) | |
1e2ad28f RR |
700 | { |
701 | struct perf_sched sched; | |
702 | ||
703 | perf_sched_init(&sched, constraints, n, wmin, wmax); | |
704 | ||
705 | do { | |
706 | if (!perf_sched_find_counter(&sched)) | |
707 | break; /* failed */ | |
708 | if (assign) | |
709 | assign[sched.state.event] = sched.state.counter; | |
710 | } while (perf_sched_next_event(&sched)); | |
711 | ||
712 | return sched.state.unassigned; | |
713 | } | |
714 | ||
de0428a7 | 715 | int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) |
1da53e02 | 716 | { |
63b14649 | 717 | struct event_constraint *c, *constraints[X86_PMC_IDX_MAX]; |
1da53e02 | 718 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
1e2ad28f | 719 | int i, wmin, wmax, num = 0; |
1da53e02 SE |
720 | struct hw_perf_event *hwc; |
721 | ||
722 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
723 | ||
1e2ad28f | 724 | for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) { |
b622d644 PZ |
725 | c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]); |
726 | constraints[i] = c; | |
1e2ad28f RR |
727 | wmin = min(wmin, c->weight); |
728 | wmax = max(wmax, c->weight); | |
1da53e02 SE |
729 | } |
730 | ||
8113070d SE |
731 | /* |
732 | * fastpath, try to reuse previous register | |
733 | */ | |
c933c1a6 | 734 | for (i = 0; i < n; i++) { |
8113070d | 735 | hwc = &cpuc->event_list[i]->hw; |
81269a08 | 736 | c = constraints[i]; |
8113070d SE |
737 | |
738 | /* never assigned */ | |
739 | if (hwc->idx == -1) | |
740 | break; | |
741 | ||
742 | /* constraint still honored */ | |
63b14649 | 743 | if (!test_bit(hwc->idx, c->idxmsk)) |
8113070d SE |
744 | break; |
745 | ||
746 | /* not already used */ | |
747 | if (test_bit(hwc->idx, used_mask)) | |
748 | break; | |
749 | ||
34538ee7 | 750 | __set_bit(hwc->idx, used_mask); |
8113070d SE |
751 | if (assign) |
752 | assign[i] = hwc->idx; | |
753 | } | |
8113070d | 754 | |
1e2ad28f RR |
755 | /* slow path */ |
756 | if (i != n) | |
757 | num = perf_assign_events(constraints, n, wmin, wmax, assign); | |
8113070d | 758 | |
1da53e02 SE |
759 | /* |
760 | * scheduling failed or is just a simulation, | |
761 | * free resources if necessary | |
762 | */ | |
763 | if (!assign || num) { | |
764 | for (i = 0; i < n; i++) { | |
765 | if (x86_pmu.put_event_constraints) | |
766 | x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]); | |
767 | } | |
768 | } | |
aa2bc1ad | 769 | return num ? -EINVAL : 0; |
1da53e02 SE |
770 | } |
771 | ||
772 | /* | |
773 | * dogrp: true if must collect siblings events (group) | |
774 | * returns total number of events and error code | |
775 | */ | |
776 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) | |
777 | { | |
778 | struct perf_event *event; | |
779 | int n, max_count; | |
780 | ||
948b1bb8 | 781 | max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; |
1da53e02 SE |
782 | |
783 | /* current number of events already accepted */ | |
784 | n = cpuc->n_events; | |
785 | ||
786 | if (is_x86_event(leader)) { | |
787 | if (n >= max_count) | |
aa2bc1ad | 788 | return -EINVAL; |
1da53e02 SE |
789 | cpuc->event_list[n] = leader; |
790 | n++; | |
791 | } | |
792 | if (!dogrp) | |
793 | return n; | |
794 | ||
795 | list_for_each_entry(event, &leader->sibling_list, group_entry) { | |
796 | if (!is_x86_event(event) || | |
8113070d | 797 | event->state <= PERF_EVENT_STATE_OFF) |
1da53e02 SE |
798 | continue; |
799 | ||
800 | if (n >= max_count) | |
aa2bc1ad | 801 | return -EINVAL; |
1da53e02 SE |
802 | |
803 | cpuc->event_list[n] = event; | |
804 | n++; | |
805 | } | |
806 | return n; | |
807 | } | |
808 | ||
1da53e02 | 809 | static inline void x86_assign_hw_event(struct perf_event *event, |
447a194b | 810 | struct cpu_hw_events *cpuc, int i) |
1da53e02 | 811 | { |
447a194b SE |
812 | struct hw_perf_event *hwc = &event->hw; |
813 | ||
814 | hwc->idx = cpuc->assign[i]; | |
815 | hwc->last_cpu = smp_processor_id(); | |
816 | hwc->last_tag = ++cpuc->tags[i]; | |
1da53e02 | 817 | |
15c7ad51 | 818 | if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) { |
1da53e02 SE |
819 | hwc->config_base = 0; |
820 | hwc->event_base = 0; | |
15c7ad51 | 821 | } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) { |
1da53e02 | 822 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
15c7ad51 RR |
823 | hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED); |
824 | hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30; | |
1da53e02 | 825 | } else { |
73d6e522 RR |
826 | hwc->config_base = x86_pmu_config_addr(hwc->idx); |
827 | hwc->event_base = x86_pmu_event_addr(hwc->idx); | |
76958a61 | 828 | hwc->event_base_rdpmc = hwc->idx; |
1da53e02 SE |
829 | } |
830 | } | |
831 | ||
447a194b SE |
832 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
833 | struct cpu_hw_events *cpuc, | |
834 | int i) | |
835 | { | |
836 | return hwc->idx == cpuc->assign[i] && | |
837 | hwc->last_cpu == smp_processor_id() && | |
838 | hwc->last_tag == cpuc->tags[i]; | |
839 | } | |
840 | ||
a4eaf7f1 | 841 | static void x86_pmu_start(struct perf_event *event, int flags); |
2e841873 | 842 | |
a4eaf7f1 | 843 | static void x86_pmu_enable(struct pmu *pmu) |
ee06094f | 844 | { |
1da53e02 SE |
845 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
846 | struct perf_event *event; | |
847 | struct hw_perf_event *hwc; | |
11164cd4 | 848 | int i, added = cpuc->n_added; |
1da53e02 | 849 | |
85cf9dba | 850 | if (!x86_pmu_initialized()) |
2b9ff0db | 851 | return; |
1a6e21f7 PZ |
852 | |
853 | if (cpuc->enabled) | |
854 | return; | |
855 | ||
1da53e02 | 856 | if (cpuc->n_added) { |
19925ce7 | 857 | int n_running = cpuc->n_events - cpuc->n_added; |
1da53e02 SE |
858 | /* |
859 | * apply assignment obtained either from | |
860 | * hw_perf_group_sched_in() or x86_pmu_enable() | |
861 | * | |
862 | * step1: save events moving to new counters | |
863 | * step2: reprogram moved events into new counters | |
864 | */ | |
19925ce7 | 865 | for (i = 0; i < n_running; i++) { |
1da53e02 SE |
866 | event = cpuc->event_list[i]; |
867 | hwc = &event->hw; | |
868 | ||
447a194b SE |
869 | /* |
870 | * we can avoid reprogramming counter if: | |
871 | * - assigned same counter as last time | |
872 | * - running on same CPU as last time | |
873 | * - no other event has used the counter since | |
874 | */ | |
875 | if (hwc->idx == -1 || | |
876 | match_prev_assignment(hwc, cpuc, i)) | |
1da53e02 SE |
877 | continue; |
878 | ||
a4eaf7f1 PZ |
879 | /* |
880 | * Ensure we don't accidentally enable a stopped | |
881 | * counter simply because we rescheduled. | |
882 | */ | |
883 | if (hwc->state & PERF_HES_STOPPED) | |
884 | hwc->state |= PERF_HES_ARCH; | |
885 | ||
886 | x86_pmu_stop(event, PERF_EF_UPDATE); | |
1da53e02 SE |
887 | } |
888 | ||
889 | for (i = 0; i < cpuc->n_events; i++) { | |
1da53e02 SE |
890 | event = cpuc->event_list[i]; |
891 | hwc = &event->hw; | |
892 | ||
45e16a68 | 893 | if (!match_prev_assignment(hwc, cpuc, i)) |
447a194b | 894 | x86_assign_hw_event(event, cpuc, i); |
45e16a68 PZ |
895 | else if (i < n_running) |
896 | continue; | |
1da53e02 | 897 | |
a4eaf7f1 PZ |
898 | if (hwc->state & PERF_HES_ARCH) |
899 | continue; | |
900 | ||
901 | x86_pmu_start(event, PERF_EF_RELOAD); | |
1da53e02 SE |
902 | } |
903 | cpuc->n_added = 0; | |
904 | perf_events_lapic_init(); | |
905 | } | |
1a6e21f7 PZ |
906 | |
907 | cpuc->enabled = 1; | |
908 | barrier(); | |
909 | ||
11164cd4 | 910 | x86_pmu.enable_all(added); |
ee06094f | 911 | } |
ee06094f | 912 | |
245b2e70 | 913 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 914 | |
ee06094f IM |
915 | /* |
916 | * Set the next IRQ period, based on the hwc->period_left value. | |
cdd6c482 | 917 | * To be called with the event disabled in hw: |
ee06094f | 918 | */ |
de0428a7 | 919 | int x86_perf_event_set_period(struct perf_event *event) |
241771ef | 920 | { |
07088edb | 921 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 922 | s64 left = local64_read(&hwc->period_left); |
e4abb5d4 | 923 | s64 period = hwc->sample_period; |
7645a24c | 924 | int ret = 0, idx = hwc->idx; |
ee06094f | 925 | |
15c7ad51 | 926 | if (idx == INTEL_PMC_IDX_FIXED_BTS) |
30dd568c MM |
927 | return 0; |
928 | ||
ee06094f | 929 | /* |
af901ca1 | 930 | * If we are way outside a reasonable range then just skip forward: |
ee06094f IM |
931 | */ |
932 | if (unlikely(left <= -period)) { | |
933 | left = period; | |
e7850595 | 934 | local64_set(&hwc->period_left, left); |
9e350de3 | 935 | hwc->last_period = period; |
e4abb5d4 | 936 | ret = 1; |
ee06094f IM |
937 | } |
938 | ||
939 | if (unlikely(left <= 0)) { | |
940 | left += period; | |
e7850595 | 941 | local64_set(&hwc->period_left, left); |
9e350de3 | 942 | hwc->last_period = period; |
e4abb5d4 | 943 | ret = 1; |
ee06094f | 944 | } |
1c80f4b5 | 945 | /* |
dfc65094 | 946 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
947 | */ |
948 | if (unlikely(left < 2)) | |
949 | left = 2; | |
241771ef | 950 | |
e4abb5d4 PZ |
951 | if (left > x86_pmu.max_period) |
952 | left = x86_pmu.max_period; | |
953 | ||
245b2e70 | 954 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
ee06094f IM |
955 | |
956 | /* | |
cdd6c482 | 957 | * The hw event starts counting from this event offset, |
ee06094f IM |
958 | * mark it to be able to extra future deltas: |
959 | */ | |
e7850595 | 960 | local64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 961 | |
73d6e522 | 962 | wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac CG |
963 | |
964 | /* | |
965 | * Due to erratum on certan cpu we need | |
966 | * a second write to be sure the register | |
967 | * is updated properly | |
968 | */ | |
969 | if (x86_pmu.perfctr_second_write) { | |
73d6e522 | 970 | wrmsrl(hwc->event_base, |
948b1bb8 | 971 | (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac | 972 | } |
e4abb5d4 | 973 | |
cdd6c482 | 974 | perf_event_update_userpage(event); |
194002b2 | 975 | |
e4abb5d4 | 976 | return ret; |
2f18d1e8 IM |
977 | } |
978 | ||
de0428a7 | 979 | void x86_pmu_enable_event(struct perf_event *event) |
7c90cc45 | 980 | { |
0a3aee0d | 981 | if (__this_cpu_read(cpu_hw_events.enabled)) |
31fa58af RR |
982 | __x86_pmu_enable_event(&event->hw, |
983 | ARCH_PERFMON_EVENTSEL_ENABLE); | |
241771ef IM |
984 | } |
985 | ||
b690081d | 986 | /* |
a4eaf7f1 | 987 | * Add a single event to the PMU. |
1da53e02 SE |
988 | * |
989 | * The event is added to the group of enabled events | |
990 | * but only if it can be scehduled with existing events. | |
fe9081cc | 991 | */ |
a4eaf7f1 | 992 | static int x86_pmu_add(struct perf_event *event, int flags) |
fe9081cc PZ |
993 | { |
994 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1da53e02 SE |
995 | struct hw_perf_event *hwc; |
996 | int assign[X86_PMC_IDX_MAX]; | |
997 | int n, n0, ret; | |
fe9081cc | 998 | |
1da53e02 | 999 | hwc = &event->hw; |
fe9081cc | 1000 | |
33696fc0 | 1001 | perf_pmu_disable(event->pmu); |
1da53e02 | 1002 | n0 = cpuc->n_events; |
24cd7f54 PZ |
1003 | ret = n = collect_events(cpuc, event, false); |
1004 | if (ret < 0) | |
1005 | goto out; | |
53b441a5 | 1006 | |
a4eaf7f1 PZ |
1007 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; |
1008 | if (!(flags & PERF_EF_START)) | |
1009 | hwc->state |= PERF_HES_ARCH; | |
1010 | ||
4d1c52b0 LM |
1011 | /* |
1012 | * If group events scheduling transaction was started, | |
0d2eb44f | 1013 | * skip the schedulability test here, it will be performed |
a4eaf7f1 | 1014 | * at commit time (->commit_txn) as a whole |
4d1c52b0 | 1015 | */ |
8d2cacbb | 1016 | if (cpuc->group_flag & PERF_EVENT_TXN) |
24cd7f54 | 1017 | goto done_collect; |
4d1c52b0 | 1018 | |
a072738e | 1019 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
1da53e02 | 1020 | if (ret) |
24cd7f54 | 1021 | goto out; |
1da53e02 SE |
1022 | /* |
1023 | * copy new assignment, now we know it is possible | |
1024 | * will be used by hw_perf_enable() | |
1025 | */ | |
1026 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
7e2ae347 | 1027 | |
24cd7f54 | 1028 | done_collect: |
1da53e02 | 1029 | cpuc->n_events = n; |
356e1f2e | 1030 | cpuc->n_added += n - n0; |
90151c35 | 1031 | cpuc->n_txn += n - n0; |
95cdd2e7 | 1032 | |
24cd7f54 PZ |
1033 | ret = 0; |
1034 | out: | |
33696fc0 | 1035 | perf_pmu_enable(event->pmu); |
24cd7f54 | 1036 | return ret; |
241771ef IM |
1037 | } |
1038 | ||
a4eaf7f1 | 1039 | static void x86_pmu_start(struct perf_event *event, int flags) |
d76a0812 | 1040 | { |
c08053e6 PZ |
1041 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
1042 | int idx = event->hw.idx; | |
1043 | ||
a4eaf7f1 PZ |
1044 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) |
1045 | return; | |
1046 | ||
1047 | if (WARN_ON_ONCE(idx == -1)) | |
1048 | return; | |
1049 | ||
1050 | if (flags & PERF_EF_RELOAD) { | |
1051 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1052 | x86_perf_event_set_period(event); | |
1053 | } | |
1054 | ||
1055 | event->hw.state = 0; | |
d76a0812 | 1056 | |
c08053e6 PZ |
1057 | cpuc->events[idx] = event; |
1058 | __set_bit(idx, cpuc->active_mask); | |
63e6be6d | 1059 | __set_bit(idx, cpuc->running); |
aff3d91a | 1060 | x86_pmu.enable(event); |
c08053e6 | 1061 | perf_event_update_userpage(event); |
a78ac325 PZ |
1062 | } |
1063 | ||
cdd6c482 | 1064 | void perf_event_print_debug(void) |
241771ef | 1065 | { |
2f18d1e8 | 1066 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
ca037701 | 1067 | u64 pebs; |
cdd6c482 | 1068 | struct cpu_hw_events *cpuc; |
5bb9efe3 | 1069 | unsigned long flags; |
1e125676 IM |
1070 | int cpu, idx; |
1071 | ||
948b1bb8 | 1072 | if (!x86_pmu.num_counters) |
1e125676 | 1073 | return; |
241771ef | 1074 | |
5bb9efe3 | 1075 | local_irq_save(flags); |
241771ef IM |
1076 | |
1077 | cpu = smp_processor_id(); | |
cdd6c482 | 1078 | cpuc = &per_cpu(cpu_hw_events, cpu); |
241771ef | 1079 | |
faa28ae0 | 1080 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1081 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1082 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1083 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1084 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
ca037701 | 1085 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); |
a1ef58f4 JSR |
1086 | |
1087 | pr_info("\n"); | |
1088 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1089 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1090 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1091 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
ca037701 | 1092 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); |
f87ad35d | 1093 | } |
7645a24c | 1094 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
241771ef | 1095 | |
948b1bb8 | 1096 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
41bf4989 RR |
1097 | rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); |
1098 | rdmsrl(x86_pmu_event_addr(idx), pmc_count); | |
241771ef | 1099 | |
245b2e70 | 1100 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 1101 | |
a1ef58f4 | 1102 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1103 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1104 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1105 | cpu, idx, pmc_count); |
a1ef58f4 | 1106 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1107 | cpu, idx, prev_left); |
241771ef | 1108 | } |
948b1bb8 | 1109 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
1110 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1111 | ||
a1ef58f4 | 1112 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1113 | cpu, idx, pmc_count); |
1114 | } | |
5bb9efe3 | 1115 | local_irq_restore(flags); |
241771ef IM |
1116 | } |
1117 | ||
de0428a7 | 1118 | void x86_pmu_stop(struct perf_event *event, int flags) |
241771ef | 1119 | { |
d76a0812 | 1120 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
cdd6c482 | 1121 | struct hw_perf_event *hwc = &event->hw; |
241771ef | 1122 | |
a4eaf7f1 PZ |
1123 | if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) { |
1124 | x86_pmu.disable(event); | |
1125 | cpuc->events[hwc->idx] = NULL; | |
1126 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); | |
1127 | hwc->state |= PERF_HES_STOPPED; | |
1128 | } | |
30dd568c | 1129 | |
a4eaf7f1 PZ |
1130 | if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { |
1131 | /* | |
1132 | * Drain the remaining delta count out of a event | |
1133 | * that we are disabling: | |
1134 | */ | |
1135 | x86_perf_event_update(event); | |
1136 | hwc->state |= PERF_HES_UPTODATE; | |
1137 | } | |
2e841873 PZ |
1138 | } |
1139 | ||
a4eaf7f1 | 1140 | static void x86_pmu_del(struct perf_event *event, int flags) |
2e841873 PZ |
1141 | { |
1142 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1143 | int i; | |
1144 | ||
90151c35 SE |
1145 | /* |
1146 | * If we're called during a txn, we don't need to do anything. | |
1147 | * The events never got scheduled and ->cancel_txn will truncate | |
1148 | * the event_list. | |
1149 | */ | |
8d2cacbb | 1150 | if (cpuc->group_flag & PERF_EVENT_TXN) |
90151c35 SE |
1151 | return; |
1152 | ||
a4eaf7f1 | 1153 | x86_pmu_stop(event, PERF_EF_UPDATE); |
194002b2 | 1154 | |
1da53e02 SE |
1155 | for (i = 0; i < cpuc->n_events; i++) { |
1156 | if (event == cpuc->event_list[i]) { | |
1157 | ||
1158 | if (x86_pmu.put_event_constraints) | |
1159 | x86_pmu.put_event_constraints(cpuc, event); | |
1160 | ||
1161 | while (++i < cpuc->n_events) | |
1162 | cpuc->event_list[i-1] = cpuc->event_list[i]; | |
1163 | ||
1164 | --cpuc->n_events; | |
6c9687ab | 1165 | break; |
1da53e02 SE |
1166 | } |
1167 | } | |
cdd6c482 | 1168 | perf_event_update_userpage(event); |
241771ef IM |
1169 | } |
1170 | ||
de0428a7 | 1171 | int x86_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1172 | { |
df1a132b | 1173 | struct perf_sample_data data; |
cdd6c482 IM |
1174 | struct cpu_hw_events *cpuc; |
1175 | struct perf_event *event; | |
11d1578f | 1176 | int idx, handled = 0; |
9029a5e3 IM |
1177 | u64 val; |
1178 | ||
cdd6c482 | 1179 | cpuc = &__get_cpu_var(cpu_hw_events); |
962bf7a6 | 1180 | |
2bce5dac DZ |
1181 | /* |
1182 | * Some chipsets need to unmask the LVTPC in a particular spot | |
1183 | * inside the nmi handler. As a result, the unmasking was pushed | |
1184 | * into all the nmi handlers. | |
1185 | * | |
1186 | * This generic handler doesn't seem to have any issues where the | |
1187 | * unmasking occurs so it was left at the top. | |
1188 | */ | |
1189 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
1190 | ||
948b1bb8 | 1191 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
63e6be6d RR |
1192 | if (!test_bit(idx, cpuc->active_mask)) { |
1193 | /* | |
1194 | * Though we deactivated the counter some cpus | |
1195 | * might still deliver spurious interrupts still | |
1196 | * in flight. Catch them: | |
1197 | */ | |
1198 | if (__test_and_clear_bit(idx, cpuc->running)) | |
1199 | handled++; | |
a29aa8a7 | 1200 | continue; |
63e6be6d | 1201 | } |
962bf7a6 | 1202 | |
cdd6c482 | 1203 | event = cpuc->events[idx]; |
a4016a79 | 1204 | |
cc2ad4ba | 1205 | val = x86_perf_event_update(event); |
948b1bb8 | 1206 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
48e22d56 | 1207 | continue; |
962bf7a6 | 1208 | |
9e350de3 | 1209 | /* |
cdd6c482 | 1210 | * event overflow |
9e350de3 | 1211 | */ |
4177c42a | 1212 | handled++; |
fd0d000b | 1213 | perf_sample_data_init(&data, 0, event->hw.last_period); |
9e350de3 | 1214 | |
07088edb | 1215 | if (!x86_perf_event_set_period(event)) |
e4abb5d4 PZ |
1216 | continue; |
1217 | ||
a8b0ca17 | 1218 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1219 | x86_pmu_stop(event, 0); |
a29aa8a7 | 1220 | } |
962bf7a6 | 1221 | |
9e350de3 PZ |
1222 | if (handled) |
1223 | inc_irq_stat(apic_perf_irqs); | |
1224 | ||
a29aa8a7 RR |
1225 | return handled; |
1226 | } | |
39d81eab | 1227 | |
cdd6c482 | 1228 | void perf_events_lapic_init(void) |
241771ef | 1229 | { |
04da8a43 | 1230 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
241771ef | 1231 | return; |
85cf9dba | 1232 | |
241771ef | 1233 | /* |
c323d95f | 1234 | * Always use NMI for PMU |
241771ef | 1235 | */ |
c323d95f | 1236 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1237 | } |
1238 | ||
1239 | static int __kprobes | |
9c48f1c6 | 1240 | perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs) |
241771ef | 1241 | { |
cdd6c482 | 1242 | if (!atomic_read(&active_events)) |
9c48f1c6 | 1243 | return NMI_DONE; |
4177c42a | 1244 | |
9c48f1c6 | 1245 | return x86_pmu.handle_irq(regs); |
241771ef IM |
1246 | } |
1247 | ||
de0428a7 KW |
1248 | struct event_constraint emptyconstraint; |
1249 | struct event_constraint unconstrained; | |
f87ad35d | 1250 | |
3f6da390 PZ |
1251 | static int __cpuinit |
1252 | x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) | |
1253 | { | |
1254 | unsigned int cpu = (long)hcpu; | |
7fdba1ca | 1255 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); |
b38b24ea | 1256 | int ret = NOTIFY_OK; |
3f6da390 PZ |
1257 | |
1258 | switch (action & ~CPU_TASKS_FROZEN) { | |
1259 | case CPU_UP_PREPARE: | |
7fdba1ca | 1260 | cpuc->kfree_on_online = NULL; |
3f6da390 | 1261 | if (x86_pmu.cpu_prepare) |
b38b24ea | 1262 | ret = x86_pmu.cpu_prepare(cpu); |
3f6da390 PZ |
1263 | break; |
1264 | ||
1265 | case CPU_STARTING: | |
0c9d42ed PZ |
1266 | if (x86_pmu.attr_rdpmc) |
1267 | set_in_cr4(X86_CR4_PCE); | |
3f6da390 PZ |
1268 | if (x86_pmu.cpu_starting) |
1269 | x86_pmu.cpu_starting(cpu); | |
1270 | break; | |
1271 | ||
7fdba1ca PZ |
1272 | case CPU_ONLINE: |
1273 | kfree(cpuc->kfree_on_online); | |
1274 | break; | |
1275 | ||
3f6da390 PZ |
1276 | case CPU_DYING: |
1277 | if (x86_pmu.cpu_dying) | |
1278 | x86_pmu.cpu_dying(cpu); | |
1279 | break; | |
1280 | ||
b38b24ea | 1281 | case CPU_UP_CANCELED: |
3f6da390 PZ |
1282 | case CPU_DEAD: |
1283 | if (x86_pmu.cpu_dead) | |
1284 | x86_pmu.cpu_dead(cpu); | |
1285 | break; | |
1286 | ||
1287 | default: | |
1288 | break; | |
1289 | } | |
1290 | ||
b38b24ea | 1291 | return ret; |
3f6da390 PZ |
1292 | } |
1293 | ||
12558038 CG |
1294 | static void __init pmu_check_apic(void) |
1295 | { | |
1296 | if (cpu_has_apic) | |
1297 | return; | |
1298 | ||
1299 | x86_pmu.apic = 0; | |
1300 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); | |
1301 | pr_info("no hardware sampling interrupt available.\n"); | |
1302 | } | |
1303 | ||
641cc938 JO |
1304 | static struct attribute_group x86_pmu_format_group = { |
1305 | .name = "format", | |
1306 | .attrs = NULL, | |
1307 | }; | |
1308 | ||
dda99116 | 1309 | static int __init init_hw_perf_events(void) |
b56a3802 | 1310 | { |
c1d6f42f | 1311 | struct x86_pmu_quirk *quirk; |
72eae04d RR |
1312 | int err; |
1313 | ||
cdd6c482 | 1314 | pr_info("Performance Events: "); |
1123e3ad | 1315 | |
b56a3802 JSR |
1316 | switch (boot_cpu_data.x86_vendor) { |
1317 | case X86_VENDOR_INTEL: | |
72eae04d | 1318 | err = intel_pmu_init(); |
b56a3802 | 1319 | break; |
f87ad35d | 1320 | case X86_VENDOR_AMD: |
72eae04d | 1321 | err = amd_pmu_init(); |
f87ad35d | 1322 | break; |
4138960a | 1323 | default: |
004417a6 | 1324 | return 0; |
b56a3802 | 1325 | } |
1123e3ad | 1326 | if (err != 0) { |
cdd6c482 | 1327 | pr_cont("no PMU driver, software events only.\n"); |
004417a6 | 1328 | return 0; |
1123e3ad | 1329 | } |
b56a3802 | 1330 | |
12558038 CG |
1331 | pmu_check_apic(); |
1332 | ||
33c6d6a7 | 1333 | /* sanity check that the hardware exists or is emulated */ |
4407204c | 1334 | if (!check_hw_exists()) |
004417a6 | 1335 | return 0; |
33c6d6a7 | 1336 | |
1123e3ad | 1337 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1338 | |
c1d6f42f PZ |
1339 | for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next) |
1340 | quirk->func(); | |
3c44780b | 1341 | |
a1eac7ac RR |
1342 | if (!x86_pmu.intel_ctrl) |
1343 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; | |
241771ef | 1344 | |
cdd6c482 | 1345 | perf_events_lapic_init(); |
9c48f1c6 | 1346 | register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI"); |
1123e3ad | 1347 | |
63b14649 | 1348 | unconstrained = (struct event_constraint) |
948b1bb8 | 1349 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
bc1738f6 | 1350 | 0, x86_pmu.num_counters, 0); |
63b14649 | 1351 | |
0c9d42ed | 1352 | x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */ |
641cc938 | 1353 | x86_pmu_format_group.attrs = x86_pmu.format_attrs; |
0c9d42ed | 1354 | |
57c0c15b | 1355 | pr_info("... version: %d\n", x86_pmu.version); |
948b1bb8 RR |
1356 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); |
1357 | pr_info("... generic registers: %d\n", x86_pmu.num_counters); | |
1358 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); | |
57c0c15b | 1359 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
948b1bb8 | 1360 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); |
d6dc0b4e | 1361 | pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); |
3f6da390 | 1362 | |
2e80a82a | 1363 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
3f6da390 | 1364 | perf_cpu_notifier(x86_pmu_notifier); |
004417a6 PZ |
1365 | |
1366 | return 0; | |
241771ef | 1367 | } |
004417a6 | 1368 | early_initcall(init_hw_perf_events); |
621a01ea | 1369 | |
cdd6c482 | 1370 | static inline void x86_pmu_read(struct perf_event *event) |
ee06094f | 1371 | { |
cc2ad4ba | 1372 | x86_perf_event_update(event); |
ee06094f IM |
1373 | } |
1374 | ||
4d1c52b0 LM |
1375 | /* |
1376 | * Start group events scheduling transaction | |
1377 | * Set the flag to make pmu::enable() not perform the | |
1378 | * schedulability test, it will be performed at commit time | |
1379 | */ | |
51b0fe39 | 1380 | static void x86_pmu_start_txn(struct pmu *pmu) |
4d1c52b0 | 1381 | { |
33696fc0 | 1382 | perf_pmu_disable(pmu); |
0a3aee0d TH |
1383 | __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN); |
1384 | __this_cpu_write(cpu_hw_events.n_txn, 0); | |
4d1c52b0 LM |
1385 | } |
1386 | ||
1387 | /* | |
1388 | * Stop group events scheduling transaction | |
1389 | * Clear the flag and pmu::enable() will perform the | |
1390 | * schedulability test. | |
1391 | */ | |
51b0fe39 | 1392 | static void x86_pmu_cancel_txn(struct pmu *pmu) |
4d1c52b0 | 1393 | { |
0a3aee0d | 1394 | __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN); |
90151c35 SE |
1395 | /* |
1396 | * Truncate the collected events. | |
1397 | */ | |
0a3aee0d TH |
1398 | __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn)); |
1399 | __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn)); | |
33696fc0 | 1400 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1401 | } |
1402 | ||
1403 | /* | |
1404 | * Commit group events scheduling transaction | |
1405 | * Perform the group schedulability test as a whole | |
1406 | * Return 0 if success | |
1407 | */ | |
51b0fe39 | 1408 | static int x86_pmu_commit_txn(struct pmu *pmu) |
4d1c52b0 LM |
1409 | { |
1410 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1411 | int assign[X86_PMC_IDX_MAX]; | |
1412 | int n, ret; | |
1413 | ||
1414 | n = cpuc->n_events; | |
1415 | ||
1416 | if (!x86_pmu_initialized()) | |
1417 | return -EAGAIN; | |
1418 | ||
1419 | ret = x86_pmu.schedule_events(cpuc, n, assign); | |
1420 | if (ret) | |
1421 | return ret; | |
1422 | ||
1423 | /* | |
1424 | * copy new assignment, now we know it is possible | |
1425 | * will be used by hw_perf_enable() | |
1426 | */ | |
1427 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
1428 | ||
8d2cacbb | 1429 | cpuc->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1430 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1431 | return 0; |
1432 | } | |
cd8a38d3 SE |
1433 | /* |
1434 | * a fake_cpuc is used to validate event groups. Due to | |
1435 | * the extra reg logic, we need to also allocate a fake | |
1436 | * per_core and per_cpu structure. Otherwise, group events | |
1437 | * using extra reg may conflict without the kernel being | |
1438 | * able to catch this when the last event gets added to | |
1439 | * the group. | |
1440 | */ | |
1441 | static void free_fake_cpuc(struct cpu_hw_events *cpuc) | |
1442 | { | |
1443 | kfree(cpuc->shared_regs); | |
1444 | kfree(cpuc); | |
1445 | } | |
1446 | ||
1447 | static struct cpu_hw_events *allocate_fake_cpuc(void) | |
1448 | { | |
1449 | struct cpu_hw_events *cpuc; | |
1450 | int cpu = raw_smp_processor_id(); | |
1451 | ||
1452 | cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL); | |
1453 | if (!cpuc) | |
1454 | return ERR_PTR(-ENOMEM); | |
1455 | ||
1456 | /* only needed, if we have extra_regs */ | |
1457 | if (x86_pmu.extra_regs) { | |
1458 | cpuc->shared_regs = allocate_shared_regs(cpu); | |
1459 | if (!cpuc->shared_regs) | |
1460 | goto error; | |
1461 | } | |
b430f7c4 | 1462 | cpuc->is_fake = 1; |
cd8a38d3 SE |
1463 | return cpuc; |
1464 | error: | |
1465 | free_fake_cpuc(cpuc); | |
1466 | return ERR_PTR(-ENOMEM); | |
1467 | } | |
4d1c52b0 | 1468 | |
ca037701 PZ |
1469 | /* |
1470 | * validate that we can schedule this event | |
1471 | */ | |
1472 | static int validate_event(struct perf_event *event) | |
1473 | { | |
1474 | struct cpu_hw_events *fake_cpuc; | |
1475 | struct event_constraint *c; | |
1476 | int ret = 0; | |
1477 | ||
cd8a38d3 SE |
1478 | fake_cpuc = allocate_fake_cpuc(); |
1479 | if (IS_ERR(fake_cpuc)) | |
1480 | return PTR_ERR(fake_cpuc); | |
ca037701 PZ |
1481 | |
1482 | c = x86_pmu.get_event_constraints(fake_cpuc, event); | |
1483 | ||
1484 | if (!c || !c->weight) | |
aa2bc1ad | 1485 | ret = -EINVAL; |
ca037701 PZ |
1486 | |
1487 | if (x86_pmu.put_event_constraints) | |
1488 | x86_pmu.put_event_constraints(fake_cpuc, event); | |
1489 | ||
cd8a38d3 | 1490 | free_fake_cpuc(fake_cpuc); |
ca037701 PZ |
1491 | |
1492 | return ret; | |
1493 | } | |
1494 | ||
1da53e02 SE |
1495 | /* |
1496 | * validate a single event group | |
1497 | * | |
1498 | * validation include: | |
184f412c IM |
1499 | * - check events are compatible which each other |
1500 | * - events do not compete for the same counter | |
1501 | * - number of events <= number of counters | |
1da53e02 SE |
1502 | * |
1503 | * validation ensures the group can be loaded onto the | |
1504 | * PMU if it was the only group available. | |
1505 | */ | |
fe9081cc PZ |
1506 | static int validate_group(struct perf_event *event) |
1507 | { | |
1da53e02 | 1508 | struct perf_event *leader = event->group_leader; |
502568d5 | 1509 | struct cpu_hw_events *fake_cpuc; |
aa2bc1ad | 1510 | int ret = -EINVAL, n; |
fe9081cc | 1511 | |
cd8a38d3 SE |
1512 | fake_cpuc = allocate_fake_cpuc(); |
1513 | if (IS_ERR(fake_cpuc)) | |
1514 | return PTR_ERR(fake_cpuc); | |
1da53e02 SE |
1515 | /* |
1516 | * the event is not yet connected with its | |
1517 | * siblings therefore we must first collect | |
1518 | * existing siblings, then add the new event | |
1519 | * before we can simulate the scheduling | |
1520 | */ | |
502568d5 | 1521 | n = collect_events(fake_cpuc, leader, true); |
1da53e02 | 1522 | if (n < 0) |
cd8a38d3 | 1523 | goto out; |
fe9081cc | 1524 | |
502568d5 PZ |
1525 | fake_cpuc->n_events = n; |
1526 | n = collect_events(fake_cpuc, event, false); | |
1da53e02 | 1527 | if (n < 0) |
cd8a38d3 | 1528 | goto out; |
fe9081cc | 1529 | |
502568d5 | 1530 | fake_cpuc->n_events = n; |
1da53e02 | 1531 | |
a072738e | 1532 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
502568d5 | 1533 | |
502568d5 | 1534 | out: |
cd8a38d3 | 1535 | free_fake_cpuc(fake_cpuc); |
502568d5 | 1536 | return ret; |
fe9081cc PZ |
1537 | } |
1538 | ||
dda99116 | 1539 | static int x86_pmu_event_init(struct perf_event *event) |
621a01ea | 1540 | { |
51b0fe39 | 1541 | struct pmu *tmp; |
621a01ea IM |
1542 | int err; |
1543 | ||
b0a873eb PZ |
1544 | switch (event->attr.type) { |
1545 | case PERF_TYPE_RAW: | |
1546 | case PERF_TYPE_HARDWARE: | |
1547 | case PERF_TYPE_HW_CACHE: | |
1548 | break; | |
1549 | ||
1550 | default: | |
1551 | return -ENOENT; | |
1552 | } | |
1553 | ||
1554 | err = __x86_pmu_event_init(event); | |
fe9081cc | 1555 | if (!err) { |
8113070d SE |
1556 | /* |
1557 | * we temporarily connect event to its pmu | |
1558 | * such that validate_group() can classify | |
1559 | * it as an x86 event using is_x86_event() | |
1560 | */ | |
1561 | tmp = event->pmu; | |
1562 | event->pmu = &pmu; | |
1563 | ||
fe9081cc PZ |
1564 | if (event->group_leader != event) |
1565 | err = validate_group(event); | |
ca037701 PZ |
1566 | else |
1567 | err = validate_event(event); | |
8113070d SE |
1568 | |
1569 | event->pmu = tmp; | |
fe9081cc | 1570 | } |
a1792cda | 1571 | if (err) { |
cdd6c482 IM |
1572 | if (event->destroy) |
1573 | event->destroy(event); | |
a1792cda | 1574 | } |
621a01ea | 1575 | |
b0a873eb | 1576 | return err; |
621a01ea | 1577 | } |
d7d59fb3 | 1578 | |
fe4a3308 PZ |
1579 | static int x86_pmu_event_idx(struct perf_event *event) |
1580 | { | |
1581 | int idx = event->hw.idx; | |
1582 | ||
c7206205 PZ |
1583 | if (!x86_pmu.attr_rdpmc) |
1584 | return 0; | |
1585 | ||
15c7ad51 RR |
1586 | if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) { |
1587 | idx -= INTEL_PMC_IDX_FIXED; | |
fe4a3308 PZ |
1588 | idx |= 1 << 30; |
1589 | } | |
1590 | ||
1591 | return idx + 1; | |
1592 | } | |
1593 | ||
0c9d42ed PZ |
1594 | static ssize_t get_attr_rdpmc(struct device *cdev, |
1595 | struct device_attribute *attr, | |
1596 | char *buf) | |
1597 | { | |
1598 | return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc); | |
1599 | } | |
1600 | ||
1601 | static void change_rdpmc(void *info) | |
1602 | { | |
1603 | bool enable = !!(unsigned long)info; | |
1604 | ||
1605 | if (enable) | |
1606 | set_in_cr4(X86_CR4_PCE); | |
1607 | else | |
1608 | clear_in_cr4(X86_CR4_PCE); | |
1609 | } | |
1610 | ||
1611 | static ssize_t set_attr_rdpmc(struct device *cdev, | |
1612 | struct device_attribute *attr, | |
1613 | const char *buf, size_t count) | |
1614 | { | |
e2b297fc SK |
1615 | unsigned long val; |
1616 | ssize_t ret; | |
1617 | ||
1618 | ret = kstrtoul(buf, 0, &val); | |
1619 | if (ret) | |
1620 | return ret; | |
0c9d42ed PZ |
1621 | |
1622 | if (!!val != !!x86_pmu.attr_rdpmc) { | |
1623 | x86_pmu.attr_rdpmc = !!val; | |
1624 | smp_call_function(change_rdpmc, (void *)val, 1); | |
1625 | } | |
1626 | ||
1627 | return count; | |
1628 | } | |
1629 | ||
1630 | static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc); | |
1631 | ||
1632 | static struct attribute *x86_pmu_attrs[] = { | |
1633 | &dev_attr_rdpmc.attr, | |
1634 | NULL, | |
1635 | }; | |
1636 | ||
1637 | static struct attribute_group x86_pmu_attr_group = { | |
1638 | .attrs = x86_pmu_attrs, | |
1639 | }; | |
1640 | ||
1641 | static const struct attribute_group *x86_pmu_attr_groups[] = { | |
1642 | &x86_pmu_attr_group, | |
641cc938 | 1643 | &x86_pmu_format_group, |
0c9d42ed PZ |
1644 | NULL, |
1645 | }; | |
1646 | ||
d010b332 SE |
1647 | static void x86_pmu_flush_branch_stack(void) |
1648 | { | |
1649 | if (x86_pmu.flush_branch_stack) | |
1650 | x86_pmu.flush_branch_stack(); | |
1651 | } | |
1652 | ||
c93dc84c PZ |
1653 | void perf_check_microcode(void) |
1654 | { | |
1655 | if (x86_pmu.check_microcode) | |
1656 | x86_pmu.check_microcode(); | |
1657 | } | |
1658 | EXPORT_SYMBOL_GPL(perf_check_microcode); | |
1659 | ||
b0a873eb | 1660 | static struct pmu pmu = { |
d010b332 SE |
1661 | .pmu_enable = x86_pmu_enable, |
1662 | .pmu_disable = x86_pmu_disable, | |
a4eaf7f1 | 1663 | |
c93dc84c | 1664 | .attr_groups = x86_pmu_attr_groups, |
0c9d42ed | 1665 | |
c93dc84c | 1666 | .event_init = x86_pmu_event_init, |
a4eaf7f1 | 1667 | |
d010b332 SE |
1668 | .add = x86_pmu_add, |
1669 | .del = x86_pmu_del, | |
1670 | .start = x86_pmu_start, | |
1671 | .stop = x86_pmu_stop, | |
1672 | .read = x86_pmu_read, | |
a4eaf7f1 | 1673 | |
c93dc84c PZ |
1674 | .start_txn = x86_pmu_start_txn, |
1675 | .cancel_txn = x86_pmu_cancel_txn, | |
1676 | .commit_txn = x86_pmu_commit_txn, | |
fe4a3308 | 1677 | |
c93dc84c | 1678 | .event_idx = x86_pmu_event_idx, |
d010b332 | 1679 | .flush_branch_stack = x86_pmu_flush_branch_stack, |
b0a873eb PZ |
1680 | }; |
1681 | ||
c7206205 | 1682 | void arch_perf_update_userpage(struct perf_event_mmap_page *userpg, u64 now) |
e3f3541c | 1683 | { |
c7206205 PZ |
1684 | userpg->cap_usr_time = 0; |
1685 | userpg->cap_usr_rdpmc = x86_pmu.attr_rdpmc; | |
1686 | userpg->pmc_width = x86_pmu.cntval_bits; | |
1687 | ||
e3f3541c PZ |
1688 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
1689 | return; | |
1690 | ||
1691 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) | |
1692 | return; | |
1693 | ||
c7206205 | 1694 | userpg->cap_usr_time = 1; |
e3f3541c PZ |
1695 | userpg->time_mult = this_cpu_read(cyc2ns); |
1696 | userpg->time_shift = CYC2NS_SCALE_FACTOR; | |
1697 | userpg->time_offset = this_cpu_read(cyc2ns_offset) - now; | |
1698 | } | |
1699 | ||
d7d59fb3 PZ |
1700 | /* |
1701 | * callchain support | |
1702 | */ | |
1703 | ||
d7d59fb3 PZ |
1704 | static int backtrace_stack(void *data, char *name) |
1705 | { | |
038e836e | 1706 | return 0; |
d7d59fb3 PZ |
1707 | } |
1708 | ||
1709 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1710 | { | |
1711 | struct perf_callchain_entry *entry = data; | |
1712 | ||
70791ce9 | 1713 | perf_callchain_store(entry, addr); |
d7d59fb3 PZ |
1714 | } |
1715 | ||
1716 | static const struct stacktrace_ops backtrace_ops = { | |
d7d59fb3 PZ |
1717 | .stack = backtrace_stack, |
1718 | .address = backtrace_address, | |
06d65bda | 1719 | .walk_stack = print_context_stack_bp, |
d7d59fb3 PZ |
1720 | }; |
1721 | ||
56962b44 FW |
1722 | void |
1723 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 | 1724 | { |
927c7a9e FW |
1725 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1726 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1727 | return; |
927c7a9e FW |
1728 | } |
1729 | ||
70791ce9 | 1730 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1731 | |
e8e999cf | 1732 | dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry); |
d7d59fb3 PZ |
1733 | } |
1734 | ||
bc6ca7b3 AS |
1735 | static inline int |
1736 | valid_user_frame(const void __user *fp, unsigned long size) | |
1737 | { | |
1738 | return (__range_not_ok(fp, size, TASK_SIZE) == 0); | |
1739 | } | |
1740 | ||
257ef9d2 | 1741 | #ifdef CONFIG_COMPAT |
d1a797f3 PA |
1742 | |
1743 | #include <asm/compat.h> | |
1744 | ||
257ef9d2 TE |
1745 | static inline int |
1746 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
74193ef0 | 1747 | { |
257ef9d2 TE |
1748 | /* 32-bit process in 64-bit kernel. */ |
1749 | struct stack_frame_ia32 frame; | |
1750 | const void __user *fp; | |
74193ef0 | 1751 | |
257ef9d2 TE |
1752 | if (!test_thread_flag(TIF_IA32)) |
1753 | return 0; | |
1754 | ||
1755 | fp = compat_ptr(regs->bp); | |
1756 | while (entry->nr < PERF_MAX_STACK_DEPTH) { | |
1757 | unsigned long bytes; | |
1758 | frame.next_frame = 0; | |
1759 | frame.return_address = 0; | |
1760 | ||
1761 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); | |
1762 | if (bytes != sizeof(frame)) | |
1763 | break; | |
74193ef0 | 1764 | |
bc6ca7b3 AS |
1765 | if (!valid_user_frame(fp, sizeof(frame))) |
1766 | break; | |
1767 | ||
70791ce9 | 1768 | perf_callchain_store(entry, frame.return_address); |
257ef9d2 TE |
1769 | fp = compat_ptr(frame.next_frame); |
1770 | } | |
1771 | return 1; | |
d7d59fb3 | 1772 | } |
257ef9d2 TE |
1773 | #else |
1774 | static inline int | |
1775 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1776 | { | |
1777 | return 0; | |
1778 | } | |
1779 | #endif | |
d7d59fb3 | 1780 | |
56962b44 FW |
1781 | void |
1782 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 PZ |
1783 | { |
1784 | struct stack_frame frame; | |
1785 | const void __user *fp; | |
1786 | ||
927c7a9e FW |
1787 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1788 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1789 | return; |
927c7a9e | 1790 | } |
5a6cec3a | 1791 | |
74193ef0 | 1792 | fp = (void __user *)regs->bp; |
d7d59fb3 | 1793 | |
70791ce9 | 1794 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1795 | |
20afc60f AV |
1796 | if (!current->mm) |
1797 | return; | |
1798 | ||
257ef9d2 TE |
1799 | if (perf_callchain_user32(regs, entry)) |
1800 | return; | |
1801 | ||
f9188e02 | 1802 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
257ef9d2 | 1803 | unsigned long bytes; |
038e836e | 1804 | frame.next_frame = NULL; |
d7d59fb3 PZ |
1805 | frame.return_address = 0; |
1806 | ||
257ef9d2 TE |
1807 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); |
1808 | if (bytes != sizeof(frame)) | |
d7d59fb3 PZ |
1809 | break; |
1810 | ||
bc6ca7b3 AS |
1811 | if (!valid_user_frame(fp, sizeof(frame))) |
1812 | break; | |
1813 | ||
70791ce9 | 1814 | perf_callchain_store(entry, frame.return_address); |
038e836e | 1815 | fp = frame.next_frame; |
d7d59fb3 PZ |
1816 | } |
1817 | } | |
1818 | ||
39447b38 ZY |
1819 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
1820 | { | |
1821 | unsigned long ip; | |
dcf46b94 | 1822 | |
39447b38 ZY |
1823 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) |
1824 | ip = perf_guest_cbs->get_guest_ip(); | |
1825 | else | |
1826 | ip = instruction_pointer(regs); | |
dcf46b94 | 1827 | |
39447b38 ZY |
1828 | return ip; |
1829 | } | |
1830 | ||
1831 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
1832 | { | |
1833 | int misc = 0; | |
dcf46b94 | 1834 | |
39447b38 | 1835 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
dcf46b94 ZY |
1836 | if (perf_guest_cbs->is_user_mode()) |
1837 | misc |= PERF_RECORD_MISC_GUEST_USER; | |
1838 | else | |
1839 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
1840 | } else { | |
ce5c1fe9 | 1841 | if (!kernel_ip(regs->ip)) |
dcf46b94 ZY |
1842 | misc |= PERF_RECORD_MISC_USER; |
1843 | else | |
1844 | misc |= PERF_RECORD_MISC_KERNEL; | |
1845 | } | |
1846 | ||
39447b38 | 1847 | if (regs->flags & PERF_EFLAGS_EXACT) |
ab608344 | 1848 | misc |= PERF_RECORD_MISC_EXACT_IP; |
39447b38 ZY |
1849 | |
1850 | return misc; | |
1851 | } | |
b3d9468a GN |
1852 | |
1853 | void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) | |
1854 | { | |
1855 | cap->version = x86_pmu.version; | |
1856 | cap->num_counters_gp = x86_pmu.num_counters; | |
1857 | cap->num_counters_fixed = x86_pmu.num_counters_fixed; | |
1858 | cap->bit_width_gp = x86_pmu.cntval_bits; | |
1859 | cap->bit_width_fixed = x86_pmu.cntval_bits; | |
1860 | cap->events_mask = (unsigned int)x86_pmu.events_maskl; | |
1861 | cap->events_mask_len = x86_pmu.events_mask_len; | |
1862 | } | |
1863 | EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability); |