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Commit | Line | Data |
---|---|---|
241771ef | 1 | /* |
cdd6c482 | 2 | * Performance events x86 architecture code |
241771ef | 3 | * |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
1da53e02 | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
241771ef IM |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
241771ef IM |
16 | #include <linux/capability.h> |
17 | #include <linux/notifier.h> | |
18 | #include <linux/hardirq.h> | |
19 | #include <linux/kprobes.h> | |
4ac13294 | 20 | #include <linux/module.h> |
241771ef IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/sched.h> | |
d7d59fb3 | 23 | #include <linux/uaccess.h> |
74193ef0 | 24 | #include <linux/highmem.h> |
30dd568c | 25 | #include <linux/cpu.h> |
272d30be | 26 | #include <linux/bitops.h> |
241771ef | 27 | |
241771ef | 28 | #include <asm/apic.h> |
d7d59fb3 | 29 | #include <asm/stacktrace.h> |
4e935e47 | 30 | #include <asm/nmi.h> |
241771ef | 31 | |
ef21f683 PZ |
32 | /* |
33 | * best effort, GUP based copy_from_user() that assumes IRQ or NMI context | |
34 | */ | |
35 | static unsigned long | |
36 | copy_from_user_nmi(void *to, const void __user *from, unsigned long n) | |
37 | { | |
38 | unsigned long offset, addr = (unsigned long)from; | |
39 | int type = in_nmi() ? KM_NMI : KM_IRQ0; | |
40 | unsigned long size, len = 0; | |
41 | struct page *page; | |
42 | void *map; | |
43 | int ret; | |
44 | ||
45 | do { | |
46 | ret = __get_user_pages_fast(addr, 1, 0, &page); | |
47 | if (!ret) | |
48 | break; | |
49 | ||
50 | offset = addr & (PAGE_SIZE - 1); | |
51 | size = min(PAGE_SIZE - offset, n - len); | |
52 | ||
53 | map = kmap_atomic(page, type); | |
54 | memcpy(to, map+offset, size); | |
55 | kunmap_atomic(map, type); | |
56 | put_page(page); | |
57 | ||
58 | len += size; | |
59 | to += size; | |
60 | addr += size; | |
61 | ||
62 | } while (len < n); | |
63 | ||
64 | return len; | |
65 | } | |
66 | ||
cdd6c482 | 67 | static u64 perf_event_mask __read_mostly; |
703e937c | 68 | |
1da53e02 | 69 | struct event_constraint { |
c91e0f5d PZ |
70 | union { |
71 | unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
b622d644 | 72 | u64 idxmsk64; |
c91e0f5d | 73 | }; |
b622d644 PZ |
74 | u64 code; |
75 | u64 cmask; | |
272d30be | 76 | int weight; |
1da53e02 SE |
77 | }; |
78 | ||
38331f62 SE |
79 | struct amd_nb { |
80 | int nb_id; /* NorthBridge id */ | |
81 | int refcnt; /* reference count */ | |
82 | struct perf_event *owners[X86_PMC_IDX_MAX]; | |
83 | struct event_constraint event_constraints[X86_PMC_IDX_MAX]; | |
84 | }; | |
85 | ||
caff2bef PZ |
86 | #define MAX_LBR_ENTRIES 16 |
87 | ||
cdd6c482 | 88 | struct cpu_hw_events { |
ca037701 PZ |
89 | /* |
90 | * Generic x86 PMC bits | |
91 | */ | |
1da53e02 | 92 | struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ |
43f6201a | 93 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
4b39fd96 | 94 | unsigned long interrupts; |
b0f3f28e | 95 | int enabled; |
241771ef | 96 | |
1da53e02 SE |
97 | int n_events; |
98 | int n_added; | |
99 | int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ | |
447a194b | 100 | u64 tags[X86_PMC_IDX_MAX]; |
1da53e02 | 101 | struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ |
ca037701 PZ |
102 | |
103 | /* | |
104 | * Intel DebugStore bits | |
105 | */ | |
106 | struct debug_store *ds; | |
107 | u64 pebs_enabled; | |
108 | ||
caff2bef PZ |
109 | /* |
110 | * Intel LBR bits | |
111 | */ | |
112 | int lbr_users; | |
113 | void *lbr_context; | |
114 | struct perf_branch_stack lbr_stack; | |
115 | struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; | |
116 | ||
ca037701 PZ |
117 | /* |
118 | * AMD specific bits | |
119 | */ | |
38331f62 | 120 | struct amd_nb *amd_nb; |
b690081d SE |
121 | }; |
122 | ||
fce877e3 | 123 | #define __EVENT_CONSTRAINT(c, n, m, w) {\ |
b622d644 | 124 | { .idxmsk64 = (n) }, \ |
c91e0f5d PZ |
125 | .code = (c), \ |
126 | .cmask = (m), \ | |
fce877e3 | 127 | .weight = (w), \ |
c91e0f5d | 128 | } |
b690081d | 129 | |
fce877e3 PZ |
130 | #define EVENT_CONSTRAINT(c, n, m) \ |
131 | __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n)) | |
132 | ||
ca037701 PZ |
133 | /* |
134 | * Constraint on the Event code. | |
135 | */ | |
ed8777fc PZ |
136 | #define INTEL_EVENT_CONSTRAINT(c, n) \ |
137 | EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVTSEL_MASK) | |
8433be11 | 138 | |
ca037701 PZ |
139 | /* |
140 | * Constraint on the Event code + UMask + fixed-mask | |
141 | */ | |
ed8777fc | 142 | #define FIXED_EVENT_CONSTRAINT(c, n) \ |
b622d644 | 143 | EVENT_CONSTRAINT(c, (1ULL << (32+n)), INTEL_ARCH_FIXED_MASK) |
8433be11 | 144 | |
ca037701 PZ |
145 | /* |
146 | * Constraint on the Event code + UMask | |
147 | */ | |
148 | #define PEBS_EVENT_CONSTRAINT(c, n) \ | |
149 | EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) | |
150 | ||
ed8777fc PZ |
151 | #define EVENT_CONSTRAINT_END \ |
152 | EVENT_CONSTRAINT(0, 0, 0) | |
153 | ||
154 | #define for_each_event_constraint(e, c) \ | |
155 | for ((e) = (c); (e)->cmask; (e)++) | |
b690081d | 156 | |
8db909a7 PZ |
157 | union perf_capabilities { |
158 | struct { | |
159 | u64 lbr_format : 6; | |
160 | u64 pebs_trap : 1; | |
161 | u64 pebs_arch_reg : 1; | |
162 | u64 pebs_format : 4; | |
163 | u64 smm_freeze : 1; | |
164 | }; | |
165 | u64 capabilities; | |
166 | }; | |
167 | ||
241771ef | 168 | /* |
5f4ec28f | 169 | * struct x86_pmu - generic x86 pmu |
241771ef | 170 | */ |
5f4ec28f | 171 | struct x86_pmu { |
ca037701 PZ |
172 | /* |
173 | * Generic x86 PMC bits | |
174 | */ | |
faa28ae0 RR |
175 | const char *name; |
176 | int version; | |
a3288106 | 177 | int (*handle_irq)(struct pt_regs *); |
9e35ad38 PZ |
178 | void (*disable_all)(void); |
179 | void (*enable_all)(void); | |
aff3d91a PZ |
180 | void (*enable)(struct perf_event *); |
181 | void (*disable)(struct perf_event *); | |
169e41eb JSR |
182 | unsigned eventsel; |
183 | unsigned perfctr; | |
b0f3f28e PZ |
184 | u64 (*event_map)(int); |
185 | u64 (*raw_event)(u64); | |
169e41eb | 186 | int max_events; |
cdd6c482 IM |
187 | int num_events; |
188 | int num_events_fixed; | |
189 | int event_bits; | |
190 | u64 event_mask; | |
04da8a43 | 191 | int apic; |
c619b8ff | 192 | u64 max_period; |
63b14649 PZ |
193 | struct event_constraint * |
194 | (*get_event_constraints)(struct cpu_hw_events *cpuc, | |
195 | struct perf_event *event); | |
196 | ||
c91e0f5d PZ |
197 | void (*put_event_constraints)(struct cpu_hw_events *cpuc, |
198 | struct perf_event *event); | |
63b14649 | 199 | struct event_constraint *event_constraints; |
3c44780b | 200 | void (*quirks)(void); |
3f6da390 PZ |
201 | |
202 | void (*cpu_prepare)(int cpu); | |
203 | void (*cpu_starting)(int cpu); | |
204 | void (*cpu_dying)(int cpu); | |
205 | void (*cpu_dead)(int cpu); | |
ca037701 PZ |
206 | |
207 | /* | |
208 | * Intel Arch Perfmon v2+ | |
209 | */ | |
8db909a7 PZ |
210 | u64 intel_ctrl; |
211 | union perf_capabilities intel_cap; | |
ca037701 PZ |
212 | |
213 | /* | |
214 | * Intel DebugStore bits | |
215 | */ | |
216 | int bts, pebs; | |
217 | int pebs_record_size; | |
218 | void (*drain_pebs)(struct pt_regs *regs); | |
219 | struct event_constraint *pebs_constraints; | |
caff2bef PZ |
220 | |
221 | /* | |
222 | * Intel LBR | |
223 | */ | |
224 | unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */ | |
225 | int lbr_nr; /* hardware stack size */ | |
b56a3802 JSR |
226 | }; |
227 | ||
4a06bd85 | 228 | static struct x86_pmu x86_pmu __read_mostly; |
b56a3802 | 229 | |
cdd6c482 | 230 | static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
b0f3f28e PZ |
231 | .enabled = 1, |
232 | }; | |
241771ef | 233 | |
07088edb | 234 | static int x86_perf_event_set_period(struct perf_event *event); |
b690081d | 235 | |
8326f44d | 236 | /* |
dfc65094 | 237 | * Generalized hw caching related hw_event table, filled |
8326f44d | 238 | * in on a per model basis. A value of 0 means |
dfc65094 IM |
239 | * 'not supported', -1 means 'hw_event makes no sense on |
240 | * this CPU', any other value means the raw hw_event | |
8326f44d IM |
241 | * ID. |
242 | */ | |
243 | ||
244 | #define C(x) PERF_COUNT_HW_CACHE_##x | |
245 | ||
246 | static u64 __read_mostly hw_cache_event_ids | |
247 | [PERF_COUNT_HW_CACHE_MAX] | |
248 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
249 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
250 | ||
ee06094f | 251 | /* |
cdd6c482 IM |
252 | * Propagate event elapsed time into the generic event. |
253 | * Can only be executed on the CPU where the event is active. | |
ee06094f IM |
254 | * Returns the delta events processed. |
255 | */ | |
4b7bfd0d | 256 | static u64 |
cc2ad4ba | 257 | x86_perf_event_update(struct perf_event *event) |
ee06094f | 258 | { |
cc2ad4ba | 259 | struct hw_perf_event *hwc = &event->hw; |
cdd6c482 | 260 | int shift = 64 - x86_pmu.event_bits; |
ec3232bd | 261 | u64 prev_raw_count, new_raw_count; |
cc2ad4ba | 262 | int idx = hwc->idx; |
ec3232bd | 263 | s64 delta; |
ee06094f | 264 | |
30dd568c MM |
265 | if (idx == X86_PMC_IDX_FIXED_BTS) |
266 | return 0; | |
267 | ||
ee06094f | 268 | /* |
cdd6c482 | 269 | * Careful: an NMI might modify the previous event value. |
ee06094f IM |
270 | * |
271 | * Our tactic to handle this is to first atomically read and | |
272 | * exchange a new raw count - then add that new-prev delta | |
cdd6c482 | 273 | * count to the generic event atomically: |
ee06094f IM |
274 | */ |
275 | again: | |
276 | prev_raw_count = atomic64_read(&hwc->prev_count); | |
cdd6c482 | 277 | rdmsrl(hwc->event_base + idx, new_raw_count); |
ee06094f IM |
278 | |
279 | if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count, | |
280 | new_raw_count) != prev_raw_count) | |
281 | goto again; | |
282 | ||
283 | /* | |
284 | * Now we have the new raw value and have updated the prev | |
285 | * timestamp already. We can now calculate the elapsed delta | |
cdd6c482 | 286 | * (event-)time and add that to the generic event. |
ee06094f IM |
287 | * |
288 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 289 | * of the count. |
ee06094f | 290 | */ |
ec3232bd PZ |
291 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
292 | delta >>= shift; | |
ee06094f | 293 | |
cdd6c482 | 294 | atomic64_add(delta, &event->count); |
ee06094f | 295 | atomic64_sub(delta, &hwc->period_left); |
4b7bfd0d RR |
296 | |
297 | return new_raw_count; | |
ee06094f IM |
298 | } |
299 | ||
cdd6c482 | 300 | static atomic_t active_events; |
4e935e47 PZ |
301 | static DEFINE_MUTEX(pmc_reserve_mutex); |
302 | ||
303 | static bool reserve_pmc_hardware(void) | |
304 | { | |
04da8a43 | 305 | #ifdef CONFIG_X86_LOCAL_APIC |
4e935e47 PZ |
306 | int i; |
307 | ||
308 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
309 | disable_lapic_nmi_watchdog(); | |
310 | ||
cdd6c482 | 311 | for (i = 0; i < x86_pmu.num_events; i++) { |
4a06bd85 | 312 | if (!reserve_perfctr_nmi(x86_pmu.perfctr + i)) |
4e935e47 PZ |
313 | goto perfctr_fail; |
314 | } | |
315 | ||
cdd6c482 | 316 | for (i = 0; i < x86_pmu.num_events; i++) { |
4a06bd85 | 317 | if (!reserve_evntsel_nmi(x86_pmu.eventsel + i)) |
4e935e47 PZ |
318 | goto eventsel_fail; |
319 | } | |
04da8a43 | 320 | #endif |
4e935e47 PZ |
321 | |
322 | return true; | |
323 | ||
04da8a43 | 324 | #ifdef CONFIG_X86_LOCAL_APIC |
4e935e47 PZ |
325 | eventsel_fail: |
326 | for (i--; i >= 0; i--) | |
4a06bd85 | 327 | release_evntsel_nmi(x86_pmu.eventsel + i); |
4e935e47 | 328 | |
cdd6c482 | 329 | i = x86_pmu.num_events; |
4e935e47 PZ |
330 | |
331 | perfctr_fail: | |
332 | for (i--; i >= 0; i--) | |
4a06bd85 | 333 | release_perfctr_nmi(x86_pmu.perfctr + i); |
4e935e47 PZ |
334 | |
335 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
336 | enable_lapic_nmi_watchdog(); | |
337 | ||
338 | return false; | |
04da8a43 | 339 | #endif |
4e935e47 PZ |
340 | } |
341 | ||
342 | static void release_pmc_hardware(void) | |
343 | { | |
04da8a43 | 344 | #ifdef CONFIG_X86_LOCAL_APIC |
4e935e47 PZ |
345 | int i; |
346 | ||
cdd6c482 | 347 | for (i = 0; i < x86_pmu.num_events; i++) { |
4a06bd85 RR |
348 | release_perfctr_nmi(x86_pmu.perfctr + i); |
349 | release_evntsel_nmi(x86_pmu.eventsel + i); | |
4e935e47 PZ |
350 | } |
351 | ||
352 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
353 | enable_lapic_nmi_watchdog(); | |
04da8a43 | 354 | #endif |
4e935e47 PZ |
355 | } |
356 | ||
ca037701 PZ |
357 | static int reserve_ds_buffers(void); |
358 | static void release_ds_buffers(void); | |
30dd568c | 359 | |
cdd6c482 | 360 | static void hw_perf_event_destroy(struct perf_event *event) |
4e935e47 | 361 | { |
cdd6c482 | 362 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) { |
4e935e47 | 363 | release_pmc_hardware(); |
ca037701 | 364 | release_ds_buffers(); |
4e935e47 PZ |
365 | mutex_unlock(&pmc_reserve_mutex); |
366 | } | |
367 | } | |
368 | ||
85cf9dba RR |
369 | static inline int x86_pmu_initialized(void) |
370 | { | |
371 | return x86_pmu.handle_irq != NULL; | |
372 | } | |
373 | ||
8326f44d | 374 | static inline int |
cdd6c482 | 375 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr) |
8326f44d IM |
376 | { |
377 | unsigned int cache_type, cache_op, cache_result; | |
378 | u64 config, val; | |
379 | ||
380 | config = attr->config; | |
381 | ||
382 | cache_type = (config >> 0) & 0xff; | |
383 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
384 | return -EINVAL; | |
385 | ||
386 | cache_op = (config >> 8) & 0xff; | |
387 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
388 | return -EINVAL; | |
389 | ||
390 | cache_result = (config >> 16) & 0xff; | |
391 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
392 | return -EINVAL; | |
393 | ||
394 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
395 | ||
396 | if (val == 0) | |
397 | return -ENOENT; | |
398 | ||
399 | if (val == -1) | |
400 | return -EINVAL; | |
401 | ||
402 | hwc->config |= val; | |
403 | ||
404 | return 0; | |
405 | } | |
406 | ||
241771ef | 407 | /* |
0d48696f | 408 | * Setup the hardware configuration for a given attr_type |
241771ef | 409 | */ |
cdd6c482 | 410 | static int __hw_perf_event_init(struct perf_event *event) |
241771ef | 411 | { |
cdd6c482 IM |
412 | struct perf_event_attr *attr = &event->attr; |
413 | struct hw_perf_event *hwc = &event->hw; | |
9c74fb50 | 414 | u64 config; |
4e935e47 | 415 | int err; |
241771ef | 416 | |
85cf9dba RR |
417 | if (!x86_pmu_initialized()) |
418 | return -ENODEV; | |
241771ef | 419 | |
4e935e47 | 420 | err = 0; |
cdd6c482 | 421 | if (!atomic_inc_not_zero(&active_events)) { |
4e935e47 | 422 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 423 | if (atomic_read(&active_events) == 0) { |
30dd568c MM |
424 | if (!reserve_pmc_hardware()) |
425 | err = -EBUSY; | |
426 | else | |
ca037701 | 427 | err = reserve_ds_buffers(); |
30dd568c MM |
428 | } |
429 | if (!err) | |
cdd6c482 | 430 | atomic_inc(&active_events); |
4e935e47 PZ |
431 | mutex_unlock(&pmc_reserve_mutex); |
432 | } | |
433 | if (err) | |
434 | return err; | |
435 | ||
cdd6c482 | 436 | event->destroy = hw_perf_event_destroy; |
a1792cda | 437 | |
241771ef | 438 | /* |
0475f9ea | 439 | * Generate PMC IRQs: |
241771ef IM |
440 | * (keep 'enabled' bit clear for now) |
441 | */ | |
0475f9ea | 442 | hwc->config = ARCH_PERFMON_EVENTSEL_INT; |
241771ef | 443 | |
b690081d | 444 | hwc->idx = -1; |
447a194b SE |
445 | hwc->last_cpu = -1; |
446 | hwc->last_tag = ~0ULL; | |
b690081d | 447 | |
241771ef | 448 | /* |
0475f9ea | 449 | * Count user and OS events unless requested not to. |
241771ef | 450 | */ |
0d48696f | 451 | if (!attr->exclude_user) |
0475f9ea | 452 | hwc->config |= ARCH_PERFMON_EVENTSEL_USR; |
0d48696f | 453 | if (!attr->exclude_kernel) |
241771ef | 454 | hwc->config |= ARCH_PERFMON_EVENTSEL_OS; |
0475f9ea | 455 | |
bd2b5b12 | 456 | if (!hwc->sample_period) { |
b23f3325 | 457 | hwc->sample_period = x86_pmu.max_period; |
9e350de3 | 458 | hwc->last_period = hwc->sample_period; |
bd2b5b12 | 459 | atomic64_set(&hwc->period_left, hwc->sample_period); |
04da8a43 IM |
460 | } else { |
461 | /* | |
462 | * If we have a PMU initialized but no APIC | |
463 | * interrupts, we cannot sample hardware | |
cdd6c482 IM |
464 | * events (user-space has to fall back and |
465 | * sample via a hrtimer based software event): | |
04da8a43 IM |
466 | */ |
467 | if (!x86_pmu.apic) | |
468 | return -EOPNOTSUPP; | |
bd2b5b12 | 469 | } |
d2517a49 | 470 | |
241771ef | 471 | /* |
dfc65094 | 472 | * Raw hw_event type provide the config in the hw_event structure |
241771ef | 473 | */ |
a21ca2ca IM |
474 | if (attr->type == PERF_TYPE_RAW) { |
475 | hwc->config |= x86_pmu.raw_event(attr->config); | |
320ebf09 PZ |
476 | if ((hwc->config & ARCH_PERFMON_EVENTSEL_ANY) && |
477 | perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN)) | |
478 | return -EACCES; | |
8326f44d | 479 | return 0; |
241771ef | 480 | } |
241771ef | 481 | |
8326f44d IM |
482 | if (attr->type == PERF_TYPE_HW_CACHE) |
483 | return set_ext_hw_attr(hwc, attr); | |
484 | ||
485 | if (attr->config >= x86_pmu.max_events) | |
486 | return -EINVAL; | |
9c74fb50 | 487 | |
8326f44d IM |
488 | /* |
489 | * The generic map: | |
490 | */ | |
9c74fb50 PZ |
491 | config = x86_pmu.event_map(attr->config); |
492 | ||
493 | if (config == 0) | |
494 | return -ENOENT; | |
495 | ||
496 | if (config == -1LL) | |
497 | return -EINVAL; | |
498 | ||
747b50aa | 499 | /* |
500 | * Branch tracing: | |
501 | */ | |
502 | if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) && | |
1653192f | 503 | (hwc->sample_period == 1)) { |
504 | /* BTS is not supported by this architecture. */ | |
ca037701 | 505 | if (!x86_pmu.bts) |
1653192f | 506 | return -EOPNOTSUPP; |
507 | ||
508 | /* BTS is currently only allowed for user-mode. */ | |
509 | if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) | |
510 | return -EOPNOTSUPP; | |
511 | } | |
747b50aa | 512 | |
9c74fb50 | 513 | hwc->config |= config; |
4e935e47 | 514 | |
241771ef IM |
515 | return 0; |
516 | } | |
517 | ||
8c48e444 | 518 | static void x86_pmu_disable_all(void) |
f87ad35d | 519 | { |
cdd6c482 | 520 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
9e35ad38 PZ |
521 | int idx; |
522 | ||
cdd6c482 | 523 | for (idx = 0; idx < x86_pmu.num_events; idx++) { |
b0f3f28e PZ |
524 | u64 val; |
525 | ||
43f6201a | 526 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 527 | continue; |
8c48e444 | 528 | rdmsrl(x86_pmu.eventsel + idx, val); |
bb1165d6 | 529 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
4295ee62 | 530 | continue; |
bb1165d6 | 531 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
8c48e444 | 532 | wrmsrl(x86_pmu.eventsel + idx, val); |
f87ad35d | 533 | } |
f87ad35d JSR |
534 | } |
535 | ||
9e35ad38 | 536 | void hw_perf_disable(void) |
b56a3802 | 537 | { |
1da53e02 SE |
538 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
539 | ||
85cf9dba | 540 | if (!x86_pmu_initialized()) |
9e35ad38 | 541 | return; |
1da53e02 | 542 | |
1a6e21f7 PZ |
543 | if (!cpuc->enabled) |
544 | return; | |
545 | ||
546 | cpuc->n_added = 0; | |
547 | cpuc->enabled = 0; | |
548 | barrier(); | |
1da53e02 SE |
549 | |
550 | x86_pmu.disable_all(); | |
b56a3802 | 551 | } |
241771ef | 552 | |
8c48e444 | 553 | static void x86_pmu_enable_all(void) |
f87ad35d | 554 | { |
cdd6c482 | 555 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
f87ad35d JSR |
556 | int idx; |
557 | ||
cdd6c482 IM |
558 | for (idx = 0; idx < x86_pmu.num_events; idx++) { |
559 | struct perf_event *event = cpuc->events[idx]; | |
4295ee62 | 560 | u64 val; |
b0f3f28e | 561 | |
43f6201a | 562 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 563 | continue; |
984b838c | 564 | |
cdd6c482 | 565 | val = event->hw.config; |
bb1165d6 | 566 | val |= ARCH_PERFMON_EVENTSEL_ENABLE; |
8c48e444 | 567 | wrmsrl(x86_pmu.eventsel + idx, val); |
f87ad35d JSR |
568 | } |
569 | } | |
570 | ||
1da53e02 SE |
571 | static const struct pmu pmu; |
572 | ||
573 | static inline int is_x86_event(struct perf_event *event) | |
574 | { | |
575 | return event->pmu == &pmu; | |
576 | } | |
577 | ||
578 | static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) | |
579 | { | |
63b14649 | 580 | struct event_constraint *c, *constraints[X86_PMC_IDX_MAX]; |
1da53e02 | 581 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
c933c1a6 | 582 | int i, j, w, wmax, num = 0; |
1da53e02 SE |
583 | struct hw_perf_event *hwc; |
584 | ||
585 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
586 | ||
587 | for (i = 0; i < n; i++) { | |
b622d644 PZ |
588 | c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]); |
589 | constraints[i] = c; | |
1da53e02 SE |
590 | } |
591 | ||
8113070d SE |
592 | /* |
593 | * fastpath, try to reuse previous register | |
594 | */ | |
c933c1a6 | 595 | for (i = 0; i < n; i++) { |
8113070d | 596 | hwc = &cpuc->event_list[i]->hw; |
81269a08 | 597 | c = constraints[i]; |
8113070d SE |
598 | |
599 | /* never assigned */ | |
600 | if (hwc->idx == -1) | |
601 | break; | |
602 | ||
603 | /* constraint still honored */ | |
63b14649 | 604 | if (!test_bit(hwc->idx, c->idxmsk)) |
8113070d SE |
605 | break; |
606 | ||
607 | /* not already used */ | |
608 | if (test_bit(hwc->idx, used_mask)) | |
609 | break; | |
610 | ||
34538ee7 | 611 | __set_bit(hwc->idx, used_mask); |
8113070d SE |
612 | if (assign) |
613 | assign[i] = hwc->idx; | |
614 | } | |
c933c1a6 | 615 | if (i == n) |
8113070d SE |
616 | goto done; |
617 | ||
618 | /* | |
619 | * begin slow path | |
620 | */ | |
621 | ||
622 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
623 | ||
1da53e02 SE |
624 | /* |
625 | * weight = number of possible counters | |
626 | * | |
627 | * 1 = most constrained, only works on one counter | |
628 | * wmax = least constrained, works on any counter | |
629 | * | |
630 | * assign events to counters starting with most | |
631 | * constrained events. | |
632 | */ | |
633 | wmax = x86_pmu.num_events; | |
634 | ||
635 | /* | |
636 | * when fixed event counters are present, | |
637 | * wmax is incremented by 1 to account | |
638 | * for one more choice | |
639 | */ | |
640 | if (x86_pmu.num_events_fixed) | |
641 | wmax++; | |
642 | ||
8113070d | 643 | for (w = 1, num = n; num && w <= wmax; w++) { |
1da53e02 | 644 | /* for each event */ |
8113070d | 645 | for (i = 0; num && i < n; i++) { |
81269a08 | 646 | c = constraints[i]; |
1da53e02 SE |
647 | hwc = &cpuc->event_list[i]->hw; |
648 | ||
272d30be | 649 | if (c->weight != w) |
1da53e02 SE |
650 | continue; |
651 | ||
984b3f57 | 652 | for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) { |
1da53e02 SE |
653 | if (!test_bit(j, used_mask)) |
654 | break; | |
655 | } | |
656 | ||
657 | if (j == X86_PMC_IDX_MAX) | |
658 | break; | |
1da53e02 | 659 | |
34538ee7 | 660 | __set_bit(j, used_mask); |
8113070d | 661 | |
1da53e02 SE |
662 | if (assign) |
663 | assign[i] = j; | |
664 | num--; | |
665 | } | |
666 | } | |
8113070d | 667 | done: |
1da53e02 SE |
668 | /* |
669 | * scheduling failed or is just a simulation, | |
670 | * free resources if necessary | |
671 | */ | |
672 | if (!assign || num) { | |
673 | for (i = 0; i < n; i++) { | |
674 | if (x86_pmu.put_event_constraints) | |
675 | x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]); | |
676 | } | |
677 | } | |
678 | return num ? -ENOSPC : 0; | |
679 | } | |
680 | ||
681 | /* | |
682 | * dogrp: true if must collect siblings events (group) | |
683 | * returns total number of events and error code | |
684 | */ | |
685 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) | |
686 | { | |
687 | struct perf_event *event; | |
688 | int n, max_count; | |
689 | ||
690 | max_count = x86_pmu.num_events + x86_pmu.num_events_fixed; | |
691 | ||
692 | /* current number of events already accepted */ | |
693 | n = cpuc->n_events; | |
694 | ||
695 | if (is_x86_event(leader)) { | |
696 | if (n >= max_count) | |
697 | return -ENOSPC; | |
698 | cpuc->event_list[n] = leader; | |
699 | n++; | |
700 | } | |
701 | if (!dogrp) | |
702 | return n; | |
703 | ||
704 | list_for_each_entry(event, &leader->sibling_list, group_entry) { | |
705 | if (!is_x86_event(event) || | |
8113070d | 706 | event->state <= PERF_EVENT_STATE_OFF) |
1da53e02 SE |
707 | continue; |
708 | ||
709 | if (n >= max_count) | |
710 | return -ENOSPC; | |
711 | ||
712 | cpuc->event_list[n] = event; | |
713 | n++; | |
714 | } | |
715 | return n; | |
716 | } | |
717 | ||
1da53e02 | 718 | static inline void x86_assign_hw_event(struct perf_event *event, |
447a194b | 719 | struct cpu_hw_events *cpuc, int i) |
1da53e02 | 720 | { |
447a194b SE |
721 | struct hw_perf_event *hwc = &event->hw; |
722 | ||
723 | hwc->idx = cpuc->assign[i]; | |
724 | hwc->last_cpu = smp_processor_id(); | |
725 | hwc->last_tag = ++cpuc->tags[i]; | |
1da53e02 SE |
726 | |
727 | if (hwc->idx == X86_PMC_IDX_FIXED_BTS) { | |
728 | hwc->config_base = 0; | |
729 | hwc->event_base = 0; | |
730 | } else if (hwc->idx >= X86_PMC_IDX_FIXED) { | |
731 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
732 | /* | |
733 | * We set it so that event_base + idx in wrmsr/rdmsr maps to | |
734 | * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2: | |
735 | */ | |
736 | hwc->event_base = | |
737 | MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED; | |
738 | } else { | |
739 | hwc->config_base = x86_pmu.eventsel; | |
740 | hwc->event_base = x86_pmu.perfctr; | |
741 | } | |
742 | } | |
743 | ||
447a194b SE |
744 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
745 | struct cpu_hw_events *cpuc, | |
746 | int i) | |
747 | { | |
748 | return hwc->idx == cpuc->assign[i] && | |
749 | hwc->last_cpu == smp_processor_id() && | |
750 | hwc->last_tag == cpuc->tags[i]; | |
751 | } | |
752 | ||
c08053e6 | 753 | static int x86_pmu_start(struct perf_event *event); |
d76a0812 | 754 | static void x86_pmu_stop(struct perf_event *event); |
2e841873 | 755 | |
9e35ad38 | 756 | void hw_perf_enable(void) |
ee06094f | 757 | { |
1da53e02 SE |
758 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
759 | struct perf_event *event; | |
760 | struct hw_perf_event *hwc; | |
761 | int i; | |
762 | ||
85cf9dba | 763 | if (!x86_pmu_initialized()) |
2b9ff0db | 764 | return; |
1a6e21f7 PZ |
765 | |
766 | if (cpuc->enabled) | |
767 | return; | |
768 | ||
1da53e02 | 769 | if (cpuc->n_added) { |
19925ce7 | 770 | int n_running = cpuc->n_events - cpuc->n_added; |
1da53e02 SE |
771 | /* |
772 | * apply assignment obtained either from | |
773 | * hw_perf_group_sched_in() or x86_pmu_enable() | |
774 | * | |
775 | * step1: save events moving to new counters | |
776 | * step2: reprogram moved events into new counters | |
777 | */ | |
19925ce7 | 778 | for (i = 0; i < n_running; i++) { |
1da53e02 SE |
779 | |
780 | event = cpuc->event_list[i]; | |
781 | hwc = &event->hw; | |
782 | ||
447a194b SE |
783 | /* |
784 | * we can avoid reprogramming counter if: | |
785 | * - assigned same counter as last time | |
786 | * - running on same CPU as last time | |
787 | * - no other event has used the counter since | |
788 | */ | |
789 | if (hwc->idx == -1 || | |
790 | match_prev_assignment(hwc, cpuc, i)) | |
1da53e02 SE |
791 | continue; |
792 | ||
d76a0812 | 793 | x86_pmu_stop(event); |
1da53e02 SE |
794 | |
795 | hwc->idx = -1; | |
796 | } | |
797 | ||
798 | for (i = 0; i < cpuc->n_events; i++) { | |
799 | ||
800 | event = cpuc->event_list[i]; | |
801 | hwc = &event->hw; | |
802 | ||
f3d46b2e PZ |
803 | if (i < n_running && |
804 | match_prev_assignment(hwc, cpuc, i)) | |
805 | continue; | |
806 | ||
c08053e6 | 807 | if (hwc->idx == -1) |
447a194b | 808 | x86_assign_hw_event(event, cpuc, i); |
1da53e02 | 809 | |
c08053e6 | 810 | x86_pmu_start(event); |
1da53e02 SE |
811 | } |
812 | cpuc->n_added = 0; | |
813 | perf_events_lapic_init(); | |
814 | } | |
1a6e21f7 PZ |
815 | |
816 | cpuc->enabled = 1; | |
817 | barrier(); | |
818 | ||
9e35ad38 | 819 | x86_pmu.enable_all(); |
ee06094f | 820 | } |
ee06094f | 821 | |
aff3d91a | 822 | static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc) |
b0f3f28e | 823 | { |
aff3d91a | 824 | (void)checking_wrmsrl(hwc->config_base + hwc->idx, |
bb1165d6 | 825 | hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE); |
b0f3f28e PZ |
826 | } |
827 | ||
aff3d91a | 828 | static inline void x86_pmu_disable_event(struct perf_event *event) |
b0f3f28e | 829 | { |
aff3d91a PZ |
830 | struct hw_perf_event *hwc = &event->hw; |
831 | (void)checking_wrmsrl(hwc->config_base + hwc->idx, hwc->config); | |
b0f3f28e PZ |
832 | } |
833 | ||
245b2e70 | 834 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 835 | |
ee06094f IM |
836 | /* |
837 | * Set the next IRQ period, based on the hwc->period_left value. | |
cdd6c482 | 838 | * To be called with the event disabled in hw: |
ee06094f | 839 | */ |
e4abb5d4 | 840 | static int |
07088edb | 841 | x86_perf_event_set_period(struct perf_event *event) |
241771ef | 842 | { |
07088edb | 843 | struct hw_perf_event *hwc = &event->hw; |
2f18d1e8 | 844 | s64 left = atomic64_read(&hwc->period_left); |
e4abb5d4 | 845 | s64 period = hwc->sample_period; |
07088edb | 846 | int err, ret = 0, idx = hwc->idx; |
ee06094f | 847 | |
30dd568c MM |
848 | if (idx == X86_PMC_IDX_FIXED_BTS) |
849 | return 0; | |
850 | ||
ee06094f | 851 | /* |
af901ca1 | 852 | * If we are way outside a reasonable range then just skip forward: |
ee06094f IM |
853 | */ |
854 | if (unlikely(left <= -period)) { | |
855 | left = period; | |
856 | atomic64_set(&hwc->period_left, left); | |
9e350de3 | 857 | hwc->last_period = period; |
e4abb5d4 | 858 | ret = 1; |
ee06094f IM |
859 | } |
860 | ||
861 | if (unlikely(left <= 0)) { | |
862 | left += period; | |
863 | atomic64_set(&hwc->period_left, left); | |
9e350de3 | 864 | hwc->last_period = period; |
e4abb5d4 | 865 | ret = 1; |
ee06094f | 866 | } |
1c80f4b5 | 867 | /* |
dfc65094 | 868 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
869 | */ |
870 | if (unlikely(left < 2)) | |
871 | left = 2; | |
241771ef | 872 | |
e4abb5d4 PZ |
873 | if (left > x86_pmu.max_period) |
874 | left = x86_pmu.max_period; | |
875 | ||
245b2e70 | 876 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
ee06094f IM |
877 | |
878 | /* | |
cdd6c482 | 879 | * The hw event starts counting from this event offset, |
ee06094f IM |
880 | * mark it to be able to extra future deltas: |
881 | */ | |
2f18d1e8 | 882 | atomic64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 883 | |
cdd6c482 IM |
884 | err = checking_wrmsrl(hwc->event_base + idx, |
885 | (u64)(-left) & x86_pmu.event_mask); | |
e4abb5d4 | 886 | |
cdd6c482 | 887 | perf_event_update_userpage(event); |
194002b2 | 888 | |
e4abb5d4 | 889 | return ret; |
2f18d1e8 IM |
890 | } |
891 | ||
aff3d91a | 892 | static void x86_pmu_enable_event(struct perf_event *event) |
7c90cc45 | 893 | { |
cdd6c482 | 894 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
7c90cc45 | 895 | if (cpuc->enabled) |
aff3d91a | 896 | __x86_pmu_enable_event(&event->hw); |
241771ef IM |
897 | } |
898 | ||
b690081d | 899 | /* |
1da53e02 SE |
900 | * activate a single event |
901 | * | |
902 | * The event is added to the group of enabled events | |
903 | * but only if it can be scehduled with existing events. | |
904 | * | |
905 | * Called with PMU disabled. If successful and return value 1, | |
906 | * then guaranteed to call perf_enable() and hw_perf_enable() | |
fe9081cc PZ |
907 | */ |
908 | static int x86_pmu_enable(struct perf_event *event) | |
909 | { | |
910 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1da53e02 SE |
911 | struct hw_perf_event *hwc; |
912 | int assign[X86_PMC_IDX_MAX]; | |
913 | int n, n0, ret; | |
fe9081cc | 914 | |
1da53e02 | 915 | hwc = &event->hw; |
fe9081cc | 916 | |
1da53e02 SE |
917 | n0 = cpuc->n_events; |
918 | n = collect_events(cpuc, event, false); | |
919 | if (n < 0) | |
920 | return n; | |
53b441a5 | 921 | |
1da53e02 SE |
922 | ret = x86_schedule_events(cpuc, n, assign); |
923 | if (ret) | |
924 | return ret; | |
925 | /* | |
926 | * copy new assignment, now we know it is possible | |
927 | * will be used by hw_perf_enable() | |
928 | */ | |
929 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
7e2ae347 | 930 | |
1da53e02 | 931 | cpuc->n_events = n; |
356e1f2e | 932 | cpuc->n_added += n - n0; |
95cdd2e7 IM |
933 | |
934 | return 0; | |
241771ef IM |
935 | } |
936 | ||
d76a0812 SE |
937 | static int x86_pmu_start(struct perf_event *event) |
938 | { | |
c08053e6 PZ |
939 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
940 | int idx = event->hw.idx; | |
941 | ||
942 | if (idx == -1) | |
d76a0812 SE |
943 | return -EAGAIN; |
944 | ||
07088edb | 945 | x86_perf_event_set_period(event); |
c08053e6 PZ |
946 | cpuc->events[idx] = event; |
947 | __set_bit(idx, cpuc->active_mask); | |
aff3d91a | 948 | x86_pmu.enable(event); |
c08053e6 | 949 | perf_event_update_userpage(event); |
d76a0812 SE |
950 | |
951 | return 0; | |
952 | } | |
953 | ||
cdd6c482 | 954 | static void x86_pmu_unthrottle(struct perf_event *event) |
a78ac325 | 955 | { |
71e2d282 PZ |
956 | int ret = x86_pmu_start(event); |
957 | WARN_ON_ONCE(ret); | |
a78ac325 PZ |
958 | } |
959 | ||
cdd6c482 | 960 | void perf_event_print_debug(void) |
241771ef | 961 | { |
2f18d1e8 | 962 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
ca037701 | 963 | u64 pebs; |
cdd6c482 | 964 | struct cpu_hw_events *cpuc; |
5bb9efe3 | 965 | unsigned long flags; |
1e125676 IM |
966 | int cpu, idx; |
967 | ||
cdd6c482 | 968 | if (!x86_pmu.num_events) |
1e125676 | 969 | return; |
241771ef | 970 | |
5bb9efe3 | 971 | local_irq_save(flags); |
241771ef IM |
972 | |
973 | cpu = smp_processor_id(); | |
cdd6c482 | 974 | cpuc = &per_cpu(cpu_hw_events, cpu); |
241771ef | 975 | |
faa28ae0 | 976 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
977 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
978 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
979 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
980 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
ca037701 | 981 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); |
a1ef58f4 JSR |
982 | |
983 | pr_info("\n"); | |
984 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
985 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
986 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
987 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
ca037701 | 988 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); |
f87ad35d | 989 | } |
1da53e02 | 990 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
241771ef | 991 | |
cdd6c482 | 992 | for (idx = 0; idx < x86_pmu.num_events; idx++) { |
4a06bd85 RR |
993 | rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl); |
994 | rdmsrl(x86_pmu.perfctr + idx, pmc_count); | |
241771ef | 995 | |
245b2e70 | 996 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 997 | |
a1ef58f4 | 998 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 999 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1000 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1001 | cpu, idx, pmc_count); |
a1ef58f4 | 1002 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1003 | cpu, idx, prev_left); |
241771ef | 1004 | } |
cdd6c482 | 1005 | for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) { |
2f18d1e8 IM |
1006 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1007 | ||
a1ef58f4 | 1008 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1009 | cpu, idx, pmc_count); |
1010 | } | |
5bb9efe3 | 1011 | local_irq_restore(flags); |
241771ef IM |
1012 | } |
1013 | ||
d76a0812 | 1014 | static void x86_pmu_stop(struct perf_event *event) |
241771ef | 1015 | { |
d76a0812 | 1016 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
cdd6c482 | 1017 | struct hw_perf_event *hwc = &event->hw; |
2e841873 | 1018 | int idx = hwc->idx; |
241771ef | 1019 | |
71e2d282 PZ |
1020 | if (!__test_and_clear_bit(idx, cpuc->active_mask)) |
1021 | return; | |
1022 | ||
aff3d91a | 1023 | x86_pmu.disable(event); |
241771ef | 1024 | |
ee06094f | 1025 | /* |
cdd6c482 | 1026 | * Drain the remaining delta count out of a event |
ee06094f IM |
1027 | * that we are disabling: |
1028 | */ | |
cc2ad4ba | 1029 | x86_perf_event_update(event); |
30dd568c | 1030 | |
cdd6c482 | 1031 | cpuc->events[idx] = NULL; |
2e841873 PZ |
1032 | } |
1033 | ||
1034 | static void x86_pmu_disable(struct perf_event *event) | |
1035 | { | |
1036 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1037 | int i; | |
1038 | ||
d76a0812 | 1039 | x86_pmu_stop(event); |
194002b2 | 1040 | |
1da53e02 SE |
1041 | for (i = 0; i < cpuc->n_events; i++) { |
1042 | if (event == cpuc->event_list[i]) { | |
1043 | ||
1044 | if (x86_pmu.put_event_constraints) | |
1045 | x86_pmu.put_event_constraints(cpuc, event); | |
1046 | ||
1047 | while (++i < cpuc->n_events) | |
1048 | cpuc->event_list[i-1] = cpuc->event_list[i]; | |
1049 | ||
1050 | --cpuc->n_events; | |
6c9687ab | 1051 | break; |
1da53e02 SE |
1052 | } |
1053 | } | |
cdd6c482 | 1054 | perf_event_update_userpage(event); |
241771ef IM |
1055 | } |
1056 | ||
8c48e444 | 1057 | static int x86_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1058 | { |
df1a132b | 1059 | struct perf_sample_data data; |
cdd6c482 IM |
1060 | struct cpu_hw_events *cpuc; |
1061 | struct perf_event *event; | |
1062 | struct hw_perf_event *hwc; | |
11d1578f | 1063 | int idx, handled = 0; |
9029a5e3 IM |
1064 | u64 val; |
1065 | ||
dc1d628a | 1066 | perf_sample_data_init(&data, 0); |
df1a132b | 1067 | |
cdd6c482 | 1068 | cpuc = &__get_cpu_var(cpu_hw_events); |
962bf7a6 | 1069 | |
cdd6c482 | 1070 | for (idx = 0; idx < x86_pmu.num_events; idx++) { |
43f6201a | 1071 | if (!test_bit(idx, cpuc->active_mask)) |
a29aa8a7 | 1072 | continue; |
962bf7a6 | 1073 | |
cdd6c482 IM |
1074 | event = cpuc->events[idx]; |
1075 | hwc = &event->hw; | |
a4016a79 | 1076 | |
cc2ad4ba | 1077 | val = x86_perf_event_update(event); |
cdd6c482 | 1078 | if (val & (1ULL << (x86_pmu.event_bits - 1))) |
48e22d56 | 1079 | continue; |
962bf7a6 | 1080 | |
9e350de3 | 1081 | /* |
cdd6c482 | 1082 | * event overflow |
9e350de3 PZ |
1083 | */ |
1084 | handled = 1; | |
cdd6c482 | 1085 | data.period = event->hw.last_period; |
9e350de3 | 1086 | |
07088edb | 1087 | if (!x86_perf_event_set_period(event)) |
e4abb5d4 PZ |
1088 | continue; |
1089 | ||
cdd6c482 | 1090 | if (perf_event_overflow(event, 1, &data, regs)) |
71e2d282 | 1091 | x86_pmu_stop(event); |
a29aa8a7 | 1092 | } |
962bf7a6 | 1093 | |
9e350de3 PZ |
1094 | if (handled) |
1095 | inc_irq_stat(apic_perf_irqs); | |
1096 | ||
a29aa8a7 RR |
1097 | return handled; |
1098 | } | |
39d81eab | 1099 | |
b6276f35 PZ |
1100 | void smp_perf_pending_interrupt(struct pt_regs *regs) |
1101 | { | |
1102 | irq_enter(); | |
1103 | ack_APIC_irq(); | |
1104 | inc_irq_stat(apic_pending_irqs); | |
cdd6c482 | 1105 | perf_event_do_pending(); |
b6276f35 PZ |
1106 | irq_exit(); |
1107 | } | |
1108 | ||
cdd6c482 | 1109 | void set_perf_event_pending(void) |
b6276f35 | 1110 | { |
04da8a43 | 1111 | #ifdef CONFIG_X86_LOCAL_APIC |
7d428966 PZ |
1112 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
1113 | return; | |
1114 | ||
b6276f35 | 1115 | apic->send_IPI_self(LOCAL_PENDING_VECTOR); |
04da8a43 | 1116 | #endif |
b6276f35 PZ |
1117 | } |
1118 | ||
cdd6c482 | 1119 | void perf_events_lapic_init(void) |
241771ef | 1120 | { |
04da8a43 IM |
1121 | #ifdef CONFIG_X86_LOCAL_APIC |
1122 | if (!x86_pmu.apic || !x86_pmu_initialized()) | |
241771ef | 1123 | return; |
85cf9dba | 1124 | |
241771ef | 1125 | /* |
c323d95f | 1126 | * Always use NMI for PMU |
241771ef | 1127 | */ |
c323d95f | 1128 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
04da8a43 | 1129 | #endif |
241771ef IM |
1130 | } |
1131 | ||
1132 | static int __kprobes | |
cdd6c482 | 1133 | perf_event_nmi_handler(struct notifier_block *self, |
241771ef IM |
1134 | unsigned long cmd, void *__args) |
1135 | { | |
1136 | struct die_args *args = __args; | |
1137 | struct pt_regs *regs; | |
b0f3f28e | 1138 | |
cdd6c482 | 1139 | if (!atomic_read(&active_events)) |
63a809a2 PZ |
1140 | return NOTIFY_DONE; |
1141 | ||
b0f3f28e PZ |
1142 | switch (cmd) { |
1143 | case DIE_NMI: | |
1144 | case DIE_NMI_IPI: | |
1145 | break; | |
241771ef | 1146 | |
b0f3f28e | 1147 | default: |
241771ef | 1148 | return NOTIFY_DONE; |
b0f3f28e | 1149 | } |
241771ef IM |
1150 | |
1151 | regs = args->regs; | |
1152 | ||
04da8a43 | 1153 | #ifdef CONFIG_X86_LOCAL_APIC |
241771ef | 1154 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
04da8a43 | 1155 | #endif |
a4016a79 PZ |
1156 | /* |
1157 | * Can't rely on the handled return value to say it was our NMI, two | |
cdd6c482 | 1158 | * events could trigger 'simultaneously' raising two back-to-back NMIs. |
a4016a79 PZ |
1159 | * |
1160 | * If the first NMI handles both, the latter will be empty and daze | |
1161 | * the CPU. | |
1162 | */ | |
a3288106 | 1163 | x86_pmu.handle_irq(regs); |
241771ef | 1164 | |
a4016a79 | 1165 | return NOTIFY_STOP; |
241771ef IM |
1166 | } |
1167 | ||
f22f54f4 PZ |
1168 | static __read_mostly struct notifier_block perf_event_nmi_notifier = { |
1169 | .notifier_call = perf_event_nmi_handler, | |
1170 | .next = NULL, | |
1171 | .priority = 1 | |
1172 | }; | |
1173 | ||
63b14649 | 1174 | static struct event_constraint unconstrained; |
38331f62 | 1175 | static struct event_constraint emptyconstraint; |
63b14649 | 1176 | |
63b14649 | 1177 | static struct event_constraint * |
f22f54f4 | 1178 | x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event) |
1da53e02 | 1179 | { |
63b14649 | 1180 | struct event_constraint *c; |
1da53e02 | 1181 | |
1da53e02 SE |
1182 | if (x86_pmu.event_constraints) { |
1183 | for_each_event_constraint(c, x86_pmu.event_constraints) { | |
63b14649 PZ |
1184 | if ((event->hw.config & c->cmask) == c->code) |
1185 | return c; | |
1da53e02 SE |
1186 | } |
1187 | } | |
63b14649 PZ |
1188 | |
1189 | return &unconstrained; | |
1da53e02 SE |
1190 | } |
1191 | ||
1da53e02 | 1192 | static int x86_event_sched_in(struct perf_event *event, |
6e37738a | 1193 | struct perf_cpu_context *cpuctx) |
1da53e02 SE |
1194 | { |
1195 | int ret = 0; | |
1196 | ||
1197 | event->state = PERF_EVENT_STATE_ACTIVE; | |
6e37738a | 1198 | event->oncpu = smp_processor_id(); |
1da53e02 SE |
1199 | event->tstamp_running += event->ctx->time - event->tstamp_stopped; |
1200 | ||
1201 | if (!is_x86_event(event)) | |
1202 | ret = event->pmu->enable(event); | |
1203 | ||
1204 | if (!ret && !is_software_event(event)) | |
1205 | cpuctx->active_oncpu++; | |
1206 | ||
1207 | if (!ret && event->attr.exclusive) | |
1208 | cpuctx->exclusive = 1; | |
1209 | ||
1210 | return ret; | |
1211 | } | |
1212 | ||
1213 | static void x86_event_sched_out(struct perf_event *event, | |
6e37738a | 1214 | struct perf_cpu_context *cpuctx) |
1da53e02 SE |
1215 | { |
1216 | event->state = PERF_EVENT_STATE_INACTIVE; | |
1217 | event->oncpu = -1; | |
1218 | ||
1219 | if (!is_x86_event(event)) | |
1220 | event->pmu->disable(event); | |
1221 | ||
1222 | event->tstamp_running -= event->ctx->time - event->tstamp_stopped; | |
1223 | ||
1224 | if (!is_software_event(event)) | |
1225 | cpuctx->active_oncpu--; | |
1226 | ||
1227 | if (event->attr.exclusive || !cpuctx->active_oncpu) | |
1228 | cpuctx->exclusive = 0; | |
1229 | } | |
1230 | ||
1231 | /* | |
1232 | * Called to enable a whole group of events. | |
1233 | * Returns 1 if the group was enabled, or -EAGAIN if it could not be. | |
1234 | * Assumes the caller has disabled interrupts and has | |
1235 | * frozen the PMU with hw_perf_save_disable. | |
1236 | * | |
1237 | * called with PMU disabled. If successful and return value 1, | |
1238 | * then guaranteed to call perf_enable() and hw_perf_enable() | |
1239 | */ | |
1240 | int hw_perf_group_sched_in(struct perf_event *leader, | |
1241 | struct perf_cpu_context *cpuctx, | |
6e37738a | 1242 | struct perf_event_context *ctx) |
1da53e02 | 1243 | { |
6e37738a | 1244 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
1da53e02 SE |
1245 | struct perf_event *sub; |
1246 | int assign[X86_PMC_IDX_MAX]; | |
1247 | int n0, n1, ret; | |
1248 | ||
1249 | /* n0 = total number of events */ | |
1250 | n0 = collect_events(cpuc, leader, true); | |
1251 | if (n0 < 0) | |
1252 | return n0; | |
1253 | ||
1254 | ret = x86_schedule_events(cpuc, n0, assign); | |
1255 | if (ret) | |
1256 | return ret; | |
1257 | ||
6e37738a | 1258 | ret = x86_event_sched_in(leader, cpuctx); |
1da53e02 SE |
1259 | if (ret) |
1260 | return ret; | |
1261 | ||
1262 | n1 = 1; | |
1263 | list_for_each_entry(sub, &leader->sibling_list, group_entry) { | |
8113070d | 1264 | if (sub->state > PERF_EVENT_STATE_OFF) { |
6e37738a | 1265 | ret = x86_event_sched_in(sub, cpuctx); |
1da53e02 SE |
1266 | if (ret) |
1267 | goto undo; | |
1268 | ++n1; | |
1269 | } | |
1270 | } | |
1271 | /* | |
1272 | * copy new assignment, now we know it is possible | |
1273 | * will be used by hw_perf_enable() | |
1274 | */ | |
1275 | memcpy(cpuc->assign, assign, n0*sizeof(int)); | |
1276 | ||
1277 | cpuc->n_events = n0; | |
356e1f2e | 1278 | cpuc->n_added += n1; |
1da53e02 SE |
1279 | ctx->nr_active += n1; |
1280 | ||
1281 | /* | |
1282 | * 1 means successful and events are active | |
1283 | * This is not quite true because we defer | |
1284 | * actual activation until hw_perf_enable() but | |
1285 | * this way we* ensure caller won't try to enable | |
1286 | * individual events | |
1287 | */ | |
1288 | return 1; | |
1289 | undo: | |
6e37738a | 1290 | x86_event_sched_out(leader, cpuctx); |
1da53e02 SE |
1291 | n0 = 1; |
1292 | list_for_each_entry(sub, &leader->sibling_list, group_entry) { | |
1293 | if (sub->state == PERF_EVENT_STATE_ACTIVE) { | |
6e37738a | 1294 | x86_event_sched_out(sub, cpuctx); |
1da53e02 SE |
1295 | if (++n0 == n1) |
1296 | break; | |
1297 | } | |
1298 | } | |
1299 | return ret; | |
1300 | } | |
1301 | ||
f22f54f4 PZ |
1302 | #include "perf_event_amd.c" |
1303 | #include "perf_event_p6.c" | |
caff2bef | 1304 | #include "perf_event_intel_lbr.c" |
ca037701 | 1305 | #include "perf_event_intel_ds.c" |
f22f54f4 | 1306 | #include "perf_event_intel.c" |
f87ad35d | 1307 | |
3f6da390 PZ |
1308 | static int __cpuinit |
1309 | x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) | |
1310 | { | |
1311 | unsigned int cpu = (long)hcpu; | |
1312 | ||
1313 | switch (action & ~CPU_TASKS_FROZEN) { | |
1314 | case CPU_UP_PREPARE: | |
1315 | if (x86_pmu.cpu_prepare) | |
1316 | x86_pmu.cpu_prepare(cpu); | |
1317 | break; | |
1318 | ||
1319 | case CPU_STARTING: | |
1320 | if (x86_pmu.cpu_starting) | |
1321 | x86_pmu.cpu_starting(cpu); | |
1322 | break; | |
1323 | ||
1324 | case CPU_DYING: | |
1325 | if (x86_pmu.cpu_dying) | |
1326 | x86_pmu.cpu_dying(cpu); | |
1327 | break; | |
1328 | ||
1329 | case CPU_DEAD: | |
1330 | if (x86_pmu.cpu_dead) | |
1331 | x86_pmu.cpu_dead(cpu); | |
1332 | break; | |
1333 | ||
1334 | default: | |
1335 | break; | |
1336 | } | |
1337 | ||
1338 | return NOTIFY_OK; | |
1339 | } | |
1340 | ||
12558038 CG |
1341 | static void __init pmu_check_apic(void) |
1342 | { | |
1343 | if (cpu_has_apic) | |
1344 | return; | |
1345 | ||
1346 | x86_pmu.apic = 0; | |
1347 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); | |
1348 | pr_info("no hardware sampling interrupt available.\n"); | |
1349 | } | |
1350 | ||
cdd6c482 | 1351 | void __init init_hw_perf_events(void) |
b56a3802 | 1352 | { |
b622d644 | 1353 | struct event_constraint *c; |
72eae04d RR |
1354 | int err; |
1355 | ||
cdd6c482 | 1356 | pr_info("Performance Events: "); |
1123e3ad | 1357 | |
b56a3802 JSR |
1358 | switch (boot_cpu_data.x86_vendor) { |
1359 | case X86_VENDOR_INTEL: | |
72eae04d | 1360 | err = intel_pmu_init(); |
b56a3802 | 1361 | break; |
f87ad35d | 1362 | case X86_VENDOR_AMD: |
72eae04d | 1363 | err = amd_pmu_init(); |
f87ad35d | 1364 | break; |
4138960a RR |
1365 | default: |
1366 | return; | |
b56a3802 | 1367 | } |
1123e3ad | 1368 | if (err != 0) { |
cdd6c482 | 1369 | pr_cont("no PMU driver, software events only.\n"); |
b56a3802 | 1370 | return; |
1123e3ad | 1371 | } |
b56a3802 | 1372 | |
12558038 CG |
1373 | pmu_check_apic(); |
1374 | ||
1123e3ad | 1375 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1376 | |
3c44780b PZ |
1377 | if (x86_pmu.quirks) |
1378 | x86_pmu.quirks(); | |
1379 | ||
cdd6c482 IM |
1380 | if (x86_pmu.num_events > X86_PMC_MAX_GENERIC) { |
1381 | WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", | |
1382 | x86_pmu.num_events, X86_PMC_MAX_GENERIC); | |
1383 | x86_pmu.num_events = X86_PMC_MAX_GENERIC; | |
241771ef | 1384 | } |
cdd6c482 IM |
1385 | perf_event_mask = (1 << x86_pmu.num_events) - 1; |
1386 | perf_max_events = x86_pmu.num_events; | |
241771ef | 1387 | |
cdd6c482 IM |
1388 | if (x86_pmu.num_events_fixed > X86_PMC_MAX_FIXED) { |
1389 | WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", | |
1390 | x86_pmu.num_events_fixed, X86_PMC_MAX_FIXED); | |
1391 | x86_pmu.num_events_fixed = X86_PMC_MAX_FIXED; | |
703e937c | 1392 | } |
862a1a5f | 1393 | |
cdd6c482 IM |
1394 | perf_event_mask |= |
1395 | ((1LL << x86_pmu.num_events_fixed)-1) << X86_PMC_IDX_FIXED; | |
1396 | x86_pmu.intel_ctrl = perf_event_mask; | |
241771ef | 1397 | |
cdd6c482 IM |
1398 | perf_events_lapic_init(); |
1399 | register_die_notifier(&perf_event_nmi_notifier); | |
1123e3ad | 1400 | |
63b14649 | 1401 | unconstrained = (struct event_constraint) |
fce877e3 PZ |
1402 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_events) - 1, |
1403 | 0, x86_pmu.num_events); | |
63b14649 | 1404 | |
b622d644 PZ |
1405 | if (x86_pmu.event_constraints) { |
1406 | for_each_event_constraint(c, x86_pmu.event_constraints) { | |
1407 | if (c->cmask != INTEL_ARCH_FIXED_MASK) | |
1408 | continue; | |
1409 | ||
1410 | c->idxmsk64 |= (1ULL << x86_pmu.num_events) - 1; | |
1411 | c->weight += x86_pmu.num_events; | |
1412 | } | |
1413 | } | |
1414 | ||
57c0c15b IM |
1415 | pr_info("... version: %d\n", x86_pmu.version); |
1416 | pr_info("... bit width: %d\n", x86_pmu.event_bits); | |
1417 | pr_info("... generic registers: %d\n", x86_pmu.num_events); | |
1418 | pr_info("... value mask: %016Lx\n", x86_pmu.event_mask); | |
1419 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); | |
1420 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_events_fixed); | |
1421 | pr_info("... event mask: %016Lx\n", perf_event_mask); | |
3f6da390 PZ |
1422 | |
1423 | perf_cpu_notifier(x86_pmu_notifier); | |
241771ef | 1424 | } |
621a01ea | 1425 | |
cdd6c482 | 1426 | static inline void x86_pmu_read(struct perf_event *event) |
ee06094f | 1427 | { |
cc2ad4ba | 1428 | x86_perf_event_update(event); |
ee06094f IM |
1429 | } |
1430 | ||
4aeb0b42 RR |
1431 | static const struct pmu pmu = { |
1432 | .enable = x86_pmu_enable, | |
1433 | .disable = x86_pmu_disable, | |
d76a0812 SE |
1434 | .start = x86_pmu_start, |
1435 | .stop = x86_pmu_stop, | |
4aeb0b42 | 1436 | .read = x86_pmu_read, |
a78ac325 | 1437 | .unthrottle = x86_pmu_unthrottle, |
621a01ea IM |
1438 | }; |
1439 | ||
ca037701 PZ |
1440 | /* |
1441 | * validate that we can schedule this event | |
1442 | */ | |
1443 | static int validate_event(struct perf_event *event) | |
1444 | { | |
1445 | struct cpu_hw_events *fake_cpuc; | |
1446 | struct event_constraint *c; | |
1447 | int ret = 0; | |
1448 | ||
1449 | fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO); | |
1450 | if (!fake_cpuc) | |
1451 | return -ENOMEM; | |
1452 | ||
1453 | c = x86_pmu.get_event_constraints(fake_cpuc, event); | |
1454 | ||
1455 | if (!c || !c->weight) | |
1456 | ret = -ENOSPC; | |
1457 | ||
1458 | if (x86_pmu.put_event_constraints) | |
1459 | x86_pmu.put_event_constraints(fake_cpuc, event); | |
1460 | ||
1461 | kfree(fake_cpuc); | |
1462 | ||
1463 | return ret; | |
1464 | } | |
1465 | ||
1da53e02 SE |
1466 | /* |
1467 | * validate a single event group | |
1468 | * | |
1469 | * validation include: | |
184f412c IM |
1470 | * - check events are compatible which each other |
1471 | * - events do not compete for the same counter | |
1472 | * - number of events <= number of counters | |
1da53e02 SE |
1473 | * |
1474 | * validation ensures the group can be loaded onto the | |
1475 | * PMU if it was the only group available. | |
1476 | */ | |
fe9081cc PZ |
1477 | static int validate_group(struct perf_event *event) |
1478 | { | |
1da53e02 | 1479 | struct perf_event *leader = event->group_leader; |
502568d5 PZ |
1480 | struct cpu_hw_events *fake_cpuc; |
1481 | int ret, n; | |
fe9081cc | 1482 | |
502568d5 PZ |
1483 | ret = -ENOMEM; |
1484 | fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO); | |
1485 | if (!fake_cpuc) | |
1486 | goto out; | |
fe9081cc | 1487 | |
1da53e02 SE |
1488 | /* |
1489 | * the event is not yet connected with its | |
1490 | * siblings therefore we must first collect | |
1491 | * existing siblings, then add the new event | |
1492 | * before we can simulate the scheduling | |
1493 | */ | |
502568d5 PZ |
1494 | ret = -ENOSPC; |
1495 | n = collect_events(fake_cpuc, leader, true); | |
1da53e02 | 1496 | if (n < 0) |
502568d5 | 1497 | goto out_free; |
fe9081cc | 1498 | |
502568d5 PZ |
1499 | fake_cpuc->n_events = n; |
1500 | n = collect_events(fake_cpuc, event, false); | |
1da53e02 | 1501 | if (n < 0) |
502568d5 | 1502 | goto out_free; |
fe9081cc | 1503 | |
502568d5 | 1504 | fake_cpuc->n_events = n; |
1da53e02 | 1505 | |
502568d5 PZ |
1506 | ret = x86_schedule_events(fake_cpuc, n, NULL); |
1507 | ||
1508 | out_free: | |
1509 | kfree(fake_cpuc); | |
1510 | out: | |
1511 | return ret; | |
fe9081cc PZ |
1512 | } |
1513 | ||
cdd6c482 | 1514 | const struct pmu *hw_perf_event_init(struct perf_event *event) |
621a01ea | 1515 | { |
8113070d | 1516 | const struct pmu *tmp; |
621a01ea IM |
1517 | int err; |
1518 | ||
cdd6c482 | 1519 | err = __hw_perf_event_init(event); |
fe9081cc | 1520 | if (!err) { |
8113070d SE |
1521 | /* |
1522 | * we temporarily connect event to its pmu | |
1523 | * such that validate_group() can classify | |
1524 | * it as an x86 event using is_x86_event() | |
1525 | */ | |
1526 | tmp = event->pmu; | |
1527 | event->pmu = &pmu; | |
1528 | ||
fe9081cc PZ |
1529 | if (event->group_leader != event) |
1530 | err = validate_group(event); | |
ca037701 PZ |
1531 | else |
1532 | err = validate_event(event); | |
8113070d SE |
1533 | |
1534 | event->pmu = tmp; | |
fe9081cc | 1535 | } |
a1792cda | 1536 | if (err) { |
cdd6c482 IM |
1537 | if (event->destroy) |
1538 | event->destroy(event); | |
9ea98e19 | 1539 | return ERR_PTR(err); |
a1792cda | 1540 | } |
621a01ea | 1541 | |
4aeb0b42 | 1542 | return &pmu; |
621a01ea | 1543 | } |
d7d59fb3 PZ |
1544 | |
1545 | /* | |
1546 | * callchain support | |
1547 | */ | |
1548 | ||
1549 | static inline | |
f9188e02 | 1550 | void callchain_store(struct perf_callchain_entry *entry, u64 ip) |
d7d59fb3 | 1551 | { |
f9188e02 | 1552 | if (entry->nr < PERF_MAX_STACK_DEPTH) |
d7d59fb3 PZ |
1553 | entry->ip[entry->nr++] = ip; |
1554 | } | |
1555 | ||
245b2e70 TH |
1556 | static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry); |
1557 | static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry); | |
d7d59fb3 PZ |
1558 | |
1559 | ||
1560 | static void | |
1561 | backtrace_warning_symbol(void *data, char *msg, unsigned long symbol) | |
1562 | { | |
1563 | /* Ignore warnings */ | |
1564 | } | |
1565 | ||
1566 | static void backtrace_warning(void *data, char *msg) | |
1567 | { | |
1568 | /* Ignore warnings */ | |
1569 | } | |
1570 | ||
1571 | static int backtrace_stack(void *data, char *name) | |
1572 | { | |
038e836e | 1573 | return 0; |
d7d59fb3 PZ |
1574 | } |
1575 | ||
1576 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1577 | { | |
1578 | struct perf_callchain_entry *entry = data; | |
1579 | ||
1580 | if (reliable) | |
1581 | callchain_store(entry, addr); | |
1582 | } | |
1583 | ||
1584 | static const struct stacktrace_ops backtrace_ops = { | |
1585 | .warning = backtrace_warning, | |
1586 | .warning_symbol = backtrace_warning_symbol, | |
1587 | .stack = backtrace_stack, | |
1588 | .address = backtrace_address, | |
06d65bda | 1589 | .walk_stack = print_context_stack_bp, |
d7d59fb3 PZ |
1590 | }; |
1591 | ||
038e836e IM |
1592 | #include "../dumpstack.h" |
1593 | ||
d7d59fb3 PZ |
1594 | static void |
1595 | perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1596 | { | |
f9188e02 | 1597 | callchain_store(entry, PERF_CONTEXT_KERNEL); |
038e836e | 1598 | callchain_store(entry, regs->ip); |
d7d59fb3 | 1599 | |
48b5ba9c | 1600 | dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry); |
d7d59fb3 PZ |
1601 | } |
1602 | ||
74193ef0 PZ |
1603 | static int copy_stack_frame(const void __user *fp, struct stack_frame *frame) |
1604 | { | |
1605 | unsigned long bytes; | |
1606 | ||
1607 | bytes = copy_from_user_nmi(frame, fp, sizeof(*frame)); | |
1608 | ||
1609 | return bytes == sizeof(*frame); | |
d7d59fb3 PZ |
1610 | } |
1611 | ||
1612 | static void | |
1613 | perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1614 | { | |
1615 | struct stack_frame frame; | |
1616 | const void __user *fp; | |
1617 | ||
5a6cec3a IM |
1618 | if (!user_mode(regs)) |
1619 | regs = task_pt_regs(current); | |
1620 | ||
74193ef0 | 1621 | fp = (void __user *)regs->bp; |
d7d59fb3 | 1622 | |
f9188e02 | 1623 | callchain_store(entry, PERF_CONTEXT_USER); |
d7d59fb3 PZ |
1624 | callchain_store(entry, regs->ip); |
1625 | ||
f9188e02 | 1626 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
038e836e | 1627 | frame.next_frame = NULL; |
d7d59fb3 PZ |
1628 | frame.return_address = 0; |
1629 | ||
1630 | if (!copy_stack_frame(fp, &frame)) | |
1631 | break; | |
1632 | ||
5a6cec3a | 1633 | if ((unsigned long)fp < regs->sp) |
d7d59fb3 PZ |
1634 | break; |
1635 | ||
1636 | callchain_store(entry, frame.return_address); | |
038e836e | 1637 | fp = frame.next_frame; |
d7d59fb3 PZ |
1638 | } |
1639 | } | |
1640 | ||
1641 | static void | |
1642 | perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1643 | { | |
1644 | int is_user; | |
1645 | ||
1646 | if (!regs) | |
1647 | return; | |
1648 | ||
1649 | is_user = user_mode(regs); | |
1650 | ||
d7d59fb3 PZ |
1651 | if (is_user && current->state != TASK_RUNNING) |
1652 | return; | |
1653 | ||
1654 | if (!is_user) | |
1655 | perf_callchain_kernel(regs, entry); | |
1656 | ||
1657 | if (current->mm) | |
1658 | perf_callchain_user(regs, entry); | |
1659 | } | |
1660 | ||
1661 | struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) | |
1662 | { | |
1663 | struct perf_callchain_entry *entry; | |
1664 | ||
1665 | if (in_nmi()) | |
245b2e70 | 1666 | entry = &__get_cpu_var(pmc_nmi_entry); |
d7d59fb3 | 1667 | else |
245b2e70 | 1668 | entry = &__get_cpu_var(pmc_irq_entry); |
d7d59fb3 PZ |
1669 | |
1670 | entry->nr = 0; | |
1671 | ||
1672 | perf_do_callchain(regs, entry); | |
1673 | ||
1674 | return entry; | |
1675 | } |