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Commit | Line | Data |
---|---|---|
241771ef | 1 | /* |
cdd6c482 | 2 | * Performance events x86 architecture code |
241771ef | 3 | * |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
1da53e02 | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
241771ef IM |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
241771ef IM |
16 | #include <linux/capability.h> |
17 | #include <linux/notifier.h> | |
18 | #include <linux/hardirq.h> | |
19 | #include <linux/kprobes.h> | |
4ac13294 | 20 | #include <linux/module.h> |
241771ef IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/sched.h> | |
d7d59fb3 | 23 | #include <linux/uaccess.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
30dd568c | 25 | #include <linux/cpu.h> |
272d30be | 26 | #include <linux/bitops.h> |
241771ef | 27 | |
241771ef | 28 | #include <asm/apic.h> |
d7d59fb3 | 29 | #include <asm/stacktrace.h> |
4e935e47 | 30 | #include <asm/nmi.h> |
257ef9d2 | 31 | #include <asm/compat.h> |
69092624 | 32 | #include <asm/smp.h> |
c8e5910e | 33 | #include <asm/alternative.h> |
241771ef | 34 | |
7645a24c PZ |
35 | #if 0 |
36 | #undef wrmsrl | |
37 | #define wrmsrl(msr, val) \ | |
38 | do { \ | |
39 | trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\ | |
40 | (unsigned long)(val)); \ | |
41 | native_write_msr((msr), (u32)((u64)(val)), \ | |
42 | (u32)((u64)(val) >> 32)); \ | |
43 | } while (0) | |
44 | #endif | |
45 | ||
efc9f05d SE |
46 | /* |
47 | * | NHM/WSM | SNB | | |
48 | * register ------------------------------- | |
49 | * | HT | no HT | HT | no HT | | |
50 | *----------------------------------------- | |
51 | * offcore | core | core | cpu | core | | |
52 | * lbr_sel | core | core | cpu | core | | |
53 | * ld_lat | cpu | core | cpu | core | | |
54 | *----------------------------------------- | |
55 | * | |
56 | * Given that there is a small number of shared regs, | |
57 | * we can pre-allocate their slot in the per-cpu | |
58 | * per-core reg tables. | |
59 | */ | |
60 | enum extra_reg_type { | |
61 | EXTRA_REG_NONE = -1, /* not used */ | |
62 | ||
63 | EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */ | |
64 | EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */ | |
65 | ||
66 | EXTRA_REG_MAX /* number of entries needed */ | |
67 | }; | |
68 | ||
1da53e02 | 69 | struct event_constraint { |
c91e0f5d PZ |
70 | union { |
71 | unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
b622d644 | 72 | u64 idxmsk64; |
c91e0f5d | 73 | }; |
b622d644 PZ |
74 | u64 code; |
75 | u64 cmask; | |
272d30be | 76 | int weight; |
1da53e02 SE |
77 | }; |
78 | ||
38331f62 SE |
79 | struct amd_nb { |
80 | int nb_id; /* NorthBridge id */ | |
81 | int refcnt; /* reference count */ | |
82 | struct perf_event *owners[X86_PMC_IDX_MAX]; | |
83 | struct event_constraint event_constraints[X86_PMC_IDX_MAX]; | |
84 | }; | |
85 | ||
a7e3ed1e AK |
86 | struct intel_percore; |
87 | ||
caff2bef PZ |
88 | #define MAX_LBR_ENTRIES 16 |
89 | ||
cdd6c482 | 90 | struct cpu_hw_events { |
ca037701 PZ |
91 | /* |
92 | * Generic x86 PMC bits | |
93 | */ | |
1da53e02 | 94 | struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ |
43f6201a | 95 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
63e6be6d | 96 | unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
b0f3f28e | 97 | int enabled; |
241771ef | 98 | |
1da53e02 SE |
99 | int n_events; |
100 | int n_added; | |
90151c35 | 101 | int n_txn; |
1da53e02 | 102 | int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ |
447a194b | 103 | u64 tags[X86_PMC_IDX_MAX]; |
1da53e02 | 104 | struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ |
ca037701 | 105 | |
4d1c52b0 LM |
106 | unsigned int group_flag; |
107 | ||
ca037701 PZ |
108 | /* |
109 | * Intel DebugStore bits | |
110 | */ | |
111 | struct debug_store *ds; | |
112 | u64 pebs_enabled; | |
113 | ||
caff2bef PZ |
114 | /* |
115 | * Intel LBR bits | |
116 | */ | |
117 | int lbr_users; | |
118 | void *lbr_context; | |
119 | struct perf_branch_stack lbr_stack; | |
120 | struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; | |
121 | ||
a7e3ed1e | 122 | /* |
efc9f05d SE |
123 | * manage shared (per-core, per-cpu) registers |
124 | * used on Intel NHM/WSM/SNB | |
a7e3ed1e | 125 | */ |
efc9f05d | 126 | struct intel_shared_regs *shared_regs; |
a7e3ed1e | 127 | |
ca037701 PZ |
128 | /* |
129 | * AMD specific bits | |
130 | */ | |
38331f62 | 131 | struct amd_nb *amd_nb; |
b690081d SE |
132 | }; |
133 | ||
fce877e3 | 134 | #define __EVENT_CONSTRAINT(c, n, m, w) {\ |
b622d644 | 135 | { .idxmsk64 = (n) }, \ |
c91e0f5d PZ |
136 | .code = (c), \ |
137 | .cmask = (m), \ | |
fce877e3 | 138 | .weight = (w), \ |
c91e0f5d | 139 | } |
b690081d | 140 | |
fce877e3 PZ |
141 | #define EVENT_CONSTRAINT(c, n, m) \ |
142 | __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n)) | |
143 | ||
ca037701 PZ |
144 | /* |
145 | * Constraint on the Event code. | |
146 | */ | |
ed8777fc | 147 | #define INTEL_EVENT_CONSTRAINT(c, n) \ |
a098f448 | 148 | EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT) |
8433be11 | 149 | |
ca037701 PZ |
150 | /* |
151 | * Constraint on the Event code + UMask + fixed-mask | |
a098f448 RR |
152 | * |
153 | * filter mask to validate fixed counter events. | |
154 | * the following filters disqualify for fixed counters: | |
155 | * - inv | |
156 | * - edge | |
157 | * - cnt-mask | |
158 | * The other filters are supported by fixed counters. | |
159 | * The any-thread option is supported starting with v3. | |
ca037701 | 160 | */ |
ed8777fc | 161 | #define FIXED_EVENT_CONSTRAINT(c, n) \ |
a098f448 | 162 | EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK) |
8433be11 | 163 | |
ca037701 PZ |
164 | /* |
165 | * Constraint on the Event code + UMask | |
166 | */ | |
b06b3d49 | 167 | #define INTEL_UEVENT_CONSTRAINT(c, n) \ |
ca037701 PZ |
168 | EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) |
169 | ||
ed8777fc PZ |
170 | #define EVENT_CONSTRAINT_END \ |
171 | EVENT_CONSTRAINT(0, 0, 0) | |
172 | ||
173 | #define for_each_event_constraint(e, c) \ | |
a1f2b70a | 174 | for ((e) = (c); (e)->weight; (e)++) |
b690081d | 175 | |
efc9f05d SE |
176 | /* |
177 | * Per register state. | |
178 | */ | |
179 | struct er_account { | |
180 | raw_spinlock_t lock; /* per-core: protect structure */ | |
181 | u64 config; /* extra MSR config */ | |
182 | u64 reg; /* extra MSR number */ | |
183 | atomic_t ref; /* reference count */ | |
184 | }; | |
185 | ||
a7e3ed1e AK |
186 | /* |
187 | * Extra registers for specific events. | |
efc9f05d | 188 | * |
a7e3ed1e | 189 | * Some events need large masks and require external MSRs. |
efc9f05d SE |
190 | * Those extra MSRs end up being shared for all events on |
191 | * a PMU and sometimes between PMU of sibling HT threads. | |
192 | * In either case, the kernel needs to handle conflicting | |
193 | * accesses to those extra, shared, regs. The data structure | |
194 | * to manage those registers is stored in cpu_hw_event. | |
a7e3ed1e AK |
195 | */ |
196 | struct extra_reg { | |
197 | unsigned int event; | |
198 | unsigned int msr; | |
199 | u64 config_mask; | |
200 | u64 valid_mask; | |
efc9f05d | 201 | int idx; /* per_xxx->regs[] reg index */ |
a7e3ed1e AK |
202 | }; |
203 | ||
efc9f05d | 204 | #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \ |
a7e3ed1e AK |
205 | .event = (e), \ |
206 | .msr = (ms), \ | |
207 | .config_mask = (m), \ | |
208 | .valid_mask = (vm), \ | |
efc9f05d | 209 | .idx = EXTRA_REG_##i \ |
a7e3ed1e | 210 | } |
efc9f05d SE |
211 | |
212 | #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \ | |
213 | EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx) | |
214 | ||
215 | #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0) | |
a7e3ed1e | 216 | |
8db909a7 PZ |
217 | union perf_capabilities { |
218 | struct { | |
219 | u64 lbr_format : 6; | |
220 | u64 pebs_trap : 1; | |
221 | u64 pebs_arch_reg : 1; | |
222 | u64 pebs_format : 4; | |
223 | u64 smm_freeze : 1; | |
224 | }; | |
225 | u64 capabilities; | |
226 | }; | |
227 | ||
241771ef | 228 | /* |
5f4ec28f | 229 | * struct x86_pmu - generic x86 pmu |
241771ef | 230 | */ |
5f4ec28f | 231 | struct x86_pmu { |
ca037701 PZ |
232 | /* |
233 | * Generic x86 PMC bits | |
234 | */ | |
faa28ae0 RR |
235 | const char *name; |
236 | int version; | |
a3288106 | 237 | int (*handle_irq)(struct pt_regs *); |
9e35ad38 | 238 | void (*disable_all)(void); |
11164cd4 | 239 | void (*enable_all)(int added); |
aff3d91a PZ |
240 | void (*enable)(struct perf_event *); |
241 | void (*disable)(struct perf_event *); | |
b4cdc5c2 | 242 | int (*hw_config)(struct perf_event *event); |
a072738e | 243 | int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign); |
169e41eb JSR |
244 | unsigned eventsel; |
245 | unsigned perfctr; | |
b0f3f28e | 246 | u64 (*event_map)(int); |
169e41eb | 247 | int max_events; |
948b1bb8 RR |
248 | int num_counters; |
249 | int num_counters_fixed; | |
250 | int cntval_bits; | |
251 | u64 cntval_mask; | |
04da8a43 | 252 | int apic; |
c619b8ff | 253 | u64 max_period; |
63b14649 PZ |
254 | struct event_constraint * |
255 | (*get_event_constraints)(struct cpu_hw_events *cpuc, | |
256 | struct perf_event *event); | |
257 | ||
c91e0f5d PZ |
258 | void (*put_event_constraints)(struct cpu_hw_events *cpuc, |
259 | struct perf_event *event); | |
63b14649 | 260 | struct event_constraint *event_constraints; |
3c44780b | 261 | void (*quirks)(void); |
68aa00ac | 262 | int perfctr_second_write; |
3f6da390 | 263 | |
b38b24ea | 264 | int (*cpu_prepare)(int cpu); |
3f6da390 PZ |
265 | void (*cpu_starting)(int cpu); |
266 | void (*cpu_dying)(int cpu); | |
267 | void (*cpu_dead)(int cpu); | |
ca037701 PZ |
268 | |
269 | /* | |
270 | * Intel Arch Perfmon v2+ | |
271 | */ | |
8db909a7 PZ |
272 | u64 intel_ctrl; |
273 | union perf_capabilities intel_cap; | |
ca037701 PZ |
274 | |
275 | /* | |
276 | * Intel DebugStore bits | |
277 | */ | |
278 | int bts, pebs; | |
6809b6ea | 279 | int bts_active, pebs_active; |
ca037701 PZ |
280 | int pebs_record_size; |
281 | void (*drain_pebs)(struct pt_regs *regs); | |
282 | struct event_constraint *pebs_constraints; | |
caff2bef PZ |
283 | |
284 | /* | |
285 | * Intel LBR | |
286 | */ | |
287 | unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */ | |
288 | int lbr_nr; /* hardware stack size */ | |
a7e3ed1e AK |
289 | |
290 | /* | |
291 | * Extra registers for events | |
292 | */ | |
293 | struct extra_reg *extra_regs; | |
b79e8941 | 294 | unsigned int er_flags; |
b56a3802 JSR |
295 | }; |
296 | ||
b79e8941 PZ |
297 | #define ERF_NO_HT_SHARING 1 |
298 | #define ERF_HAS_RSP_1 2 | |
299 | ||
4a06bd85 | 300 | static struct x86_pmu x86_pmu __read_mostly; |
b56a3802 | 301 | |
cdd6c482 | 302 | static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
b0f3f28e PZ |
303 | .enabled = 1, |
304 | }; | |
241771ef | 305 | |
07088edb | 306 | static int x86_perf_event_set_period(struct perf_event *event); |
b690081d | 307 | |
8326f44d | 308 | /* |
dfc65094 | 309 | * Generalized hw caching related hw_event table, filled |
8326f44d | 310 | * in on a per model basis. A value of 0 means |
dfc65094 IM |
311 | * 'not supported', -1 means 'hw_event makes no sense on |
312 | * this CPU', any other value means the raw hw_event | |
8326f44d IM |
313 | * ID. |
314 | */ | |
315 | ||
316 | #define C(x) PERF_COUNT_HW_CACHE_##x | |
317 | ||
318 | static u64 __read_mostly hw_cache_event_ids | |
319 | [PERF_COUNT_HW_CACHE_MAX] | |
320 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
321 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
e994d7d2 AK |
322 | static u64 __read_mostly hw_cache_extra_regs |
323 | [PERF_COUNT_HW_CACHE_MAX] | |
324 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
325 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
8326f44d | 326 | |
ee06094f | 327 | /* |
cdd6c482 IM |
328 | * Propagate event elapsed time into the generic event. |
329 | * Can only be executed on the CPU where the event is active. | |
ee06094f IM |
330 | * Returns the delta events processed. |
331 | */ | |
4b7bfd0d | 332 | static u64 |
cc2ad4ba | 333 | x86_perf_event_update(struct perf_event *event) |
ee06094f | 334 | { |
cc2ad4ba | 335 | struct hw_perf_event *hwc = &event->hw; |
948b1bb8 | 336 | int shift = 64 - x86_pmu.cntval_bits; |
ec3232bd | 337 | u64 prev_raw_count, new_raw_count; |
cc2ad4ba | 338 | int idx = hwc->idx; |
ec3232bd | 339 | s64 delta; |
ee06094f | 340 | |
30dd568c MM |
341 | if (idx == X86_PMC_IDX_FIXED_BTS) |
342 | return 0; | |
343 | ||
ee06094f | 344 | /* |
cdd6c482 | 345 | * Careful: an NMI might modify the previous event value. |
ee06094f IM |
346 | * |
347 | * Our tactic to handle this is to first atomically read and | |
348 | * exchange a new raw count - then add that new-prev delta | |
cdd6c482 | 349 | * count to the generic event atomically: |
ee06094f IM |
350 | */ |
351 | again: | |
e7850595 | 352 | prev_raw_count = local64_read(&hwc->prev_count); |
73d6e522 | 353 | rdmsrl(hwc->event_base, new_raw_count); |
ee06094f | 354 | |
e7850595 | 355 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
ee06094f IM |
356 | new_raw_count) != prev_raw_count) |
357 | goto again; | |
358 | ||
359 | /* | |
360 | * Now we have the new raw value and have updated the prev | |
361 | * timestamp already. We can now calculate the elapsed delta | |
cdd6c482 | 362 | * (event-)time and add that to the generic event. |
ee06094f IM |
363 | * |
364 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 365 | * of the count. |
ee06094f | 366 | */ |
ec3232bd PZ |
367 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
368 | delta >>= shift; | |
ee06094f | 369 | |
e7850595 PZ |
370 | local64_add(delta, &event->count); |
371 | local64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
372 | |
373 | return new_raw_count; | |
ee06094f IM |
374 | } |
375 | ||
4979d272 RR |
376 | static inline int x86_pmu_addr_offset(int index) |
377 | { | |
c8e5910e RR |
378 | int offset; |
379 | ||
380 | /* offset = X86_FEATURE_PERFCTR_CORE ? index << 1 : index */ | |
381 | alternative_io(ASM_NOP2, | |
382 | "shll $1, %%eax", | |
383 | X86_FEATURE_PERFCTR_CORE, | |
384 | "=a" (offset), | |
385 | "a" (index)); | |
386 | ||
387 | return offset; | |
4979d272 RR |
388 | } |
389 | ||
41bf4989 RR |
390 | static inline unsigned int x86_pmu_config_addr(int index) |
391 | { | |
4979d272 | 392 | return x86_pmu.eventsel + x86_pmu_addr_offset(index); |
41bf4989 RR |
393 | } |
394 | ||
395 | static inline unsigned int x86_pmu_event_addr(int index) | |
396 | { | |
4979d272 | 397 | return x86_pmu.perfctr + x86_pmu_addr_offset(index); |
41bf4989 RR |
398 | } |
399 | ||
a7e3ed1e AK |
400 | /* |
401 | * Find and validate any extra registers to set up. | |
402 | */ | |
403 | static int x86_pmu_extra_regs(u64 config, struct perf_event *event) | |
404 | { | |
efc9f05d | 405 | struct hw_perf_event_extra *reg; |
a7e3ed1e AK |
406 | struct extra_reg *er; |
407 | ||
efc9f05d | 408 | reg = &event->hw.extra_reg; |
a7e3ed1e AK |
409 | |
410 | if (!x86_pmu.extra_regs) | |
411 | return 0; | |
412 | ||
413 | for (er = x86_pmu.extra_regs; er->msr; er++) { | |
414 | if (er->event != (config & er->config_mask)) | |
415 | continue; | |
416 | if (event->attr.config1 & ~er->valid_mask) | |
417 | return -EINVAL; | |
efc9f05d SE |
418 | |
419 | reg->idx = er->idx; | |
420 | reg->config = event->attr.config1; | |
421 | reg->reg = er->msr; | |
a7e3ed1e AK |
422 | break; |
423 | } | |
424 | return 0; | |
425 | } | |
426 | ||
cdd6c482 | 427 | static atomic_t active_events; |
4e935e47 PZ |
428 | static DEFINE_MUTEX(pmc_reserve_mutex); |
429 | ||
b27ea29c RR |
430 | #ifdef CONFIG_X86_LOCAL_APIC |
431 | ||
4e935e47 PZ |
432 | static bool reserve_pmc_hardware(void) |
433 | { | |
434 | int i; | |
435 | ||
948b1bb8 | 436 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 437 | if (!reserve_perfctr_nmi(x86_pmu_event_addr(i))) |
4e935e47 PZ |
438 | goto perfctr_fail; |
439 | } | |
440 | ||
948b1bb8 | 441 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 442 | if (!reserve_evntsel_nmi(x86_pmu_config_addr(i))) |
4e935e47 PZ |
443 | goto eventsel_fail; |
444 | } | |
445 | ||
446 | return true; | |
447 | ||
448 | eventsel_fail: | |
449 | for (i--; i >= 0; i--) | |
41bf4989 | 450 | release_evntsel_nmi(x86_pmu_config_addr(i)); |
4e935e47 | 451 | |
948b1bb8 | 452 | i = x86_pmu.num_counters; |
4e935e47 PZ |
453 | |
454 | perfctr_fail: | |
455 | for (i--; i >= 0; i--) | |
41bf4989 | 456 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
4e935e47 | 457 | |
4e935e47 PZ |
458 | return false; |
459 | } | |
460 | ||
461 | static void release_pmc_hardware(void) | |
462 | { | |
463 | int i; | |
464 | ||
948b1bb8 | 465 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 RR |
466 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
467 | release_evntsel_nmi(x86_pmu_config_addr(i)); | |
4e935e47 | 468 | } |
4e935e47 PZ |
469 | } |
470 | ||
b27ea29c RR |
471 | #else |
472 | ||
473 | static bool reserve_pmc_hardware(void) { return true; } | |
474 | static void release_pmc_hardware(void) {} | |
475 | ||
476 | #endif | |
477 | ||
33c6d6a7 DZ |
478 | static bool check_hw_exists(void) |
479 | { | |
480 | u64 val, val_new = 0; | |
4407204c | 481 | int i, reg, ret = 0; |
33c6d6a7 | 482 | |
4407204c PZ |
483 | /* |
484 | * Check to see if the BIOS enabled any of the counters, if so | |
485 | * complain and bail. | |
486 | */ | |
487 | for (i = 0; i < x86_pmu.num_counters; i++) { | |
41bf4989 | 488 | reg = x86_pmu_config_addr(i); |
4407204c PZ |
489 | ret = rdmsrl_safe(reg, &val); |
490 | if (ret) | |
491 | goto msr_fail; | |
492 | if (val & ARCH_PERFMON_EVENTSEL_ENABLE) | |
493 | goto bios_fail; | |
494 | } | |
495 | ||
496 | if (x86_pmu.num_counters_fixed) { | |
497 | reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
498 | ret = rdmsrl_safe(reg, &val); | |
499 | if (ret) | |
500 | goto msr_fail; | |
501 | for (i = 0; i < x86_pmu.num_counters_fixed; i++) { | |
502 | if (val & (0x03 << i*4)) | |
503 | goto bios_fail; | |
504 | } | |
505 | } | |
506 | ||
507 | /* | |
508 | * Now write a value and read it back to see if it matches, | |
509 | * this is needed to detect certain hardware emulators (qemu/kvm) | |
510 | * that don't trap on the MSR access and always return 0s. | |
511 | */ | |
33c6d6a7 | 512 | val = 0xabcdUL; |
41bf4989 RR |
513 | ret = checking_wrmsrl(x86_pmu_event_addr(0), val); |
514 | ret |= rdmsrl_safe(x86_pmu_event_addr(0), &val_new); | |
33c6d6a7 | 515 | if (ret || val != val_new) |
4407204c | 516 | goto msr_fail; |
33c6d6a7 DZ |
517 | |
518 | return true; | |
4407204c PZ |
519 | |
520 | bios_fail: | |
45daae57 IM |
521 | /* |
522 | * We still allow the PMU driver to operate: | |
523 | */ | |
524 | printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n"); | |
4407204c | 525 | printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg, val); |
45daae57 IM |
526 | |
527 | return true; | |
4407204c PZ |
528 | |
529 | msr_fail: | |
530 | printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n"); | |
45daae57 | 531 | |
4407204c | 532 | return false; |
33c6d6a7 DZ |
533 | } |
534 | ||
f80c9e30 | 535 | static void reserve_ds_buffers(void); |
ca037701 | 536 | static void release_ds_buffers(void); |
30dd568c | 537 | |
cdd6c482 | 538 | static void hw_perf_event_destroy(struct perf_event *event) |
4e935e47 | 539 | { |
cdd6c482 | 540 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) { |
4e935e47 | 541 | release_pmc_hardware(); |
ca037701 | 542 | release_ds_buffers(); |
4e935e47 PZ |
543 | mutex_unlock(&pmc_reserve_mutex); |
544 | } | |
545 | } | |
546 | ||
85cf9dba RR |
547 | static inline int x86_pmu_initialized(void) |
548 | { | |
549 | return x86_pmu.handle_irq != NULL; | |
550 | } | |
551 | ||
8326f44d | 552 | static inline int |
e994d7d2 | 553 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) |
8326f44d | 554 | { |
e994d7d2 | 555 | struct perf_event_attr *attr = &event->attr; |
8326f44d IM |
556 | unsigned int cache_type, cache_op, cache_result; |
557 | u64 config, val; | |
558 | ||
559 | config = attr->config; | |
560 | ||
561 | cache_type = (config >> 0) & 0xff; | |
562 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
563 | return -EINVAL; | |
564 | ||
565 | cache_op = (config >> 8) & 0xff; | |
566 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
567 | return -EINVAL; | |
568 | ||
569 | cache_result = (config >> 16) & 0xff; | |
570 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
571 | return -EINVAL; | |
572 | ||
573 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
574 | ||
575 | if (val == 0) | |
576 | return -ENOENT; | |
577 | ||
578 | if (val == -1) | |
579 | return -EINVAL; | |
580 | ||
581 | hwc->config |= val; | |
e994d7d2 AK |
582 | attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result]; |
583 | return x86_pmu_extra_regs(val, event); | |
8326f44d IM |
584 | } |
585 | ||
c1726f34 RR |
586 | static int x86_setup_perfctr(struct perf_event *event) |
587 | { | |
588 | struct perf_event_attr *attr = &event->attr; | |
589 | struct hw_perf_event *hwc = &event->hw; | |
590 | u64 config; | |
591 | ||
6c7e550f | 592 | if (!is_sampling_event(event)) { |
c1726f34 RR |
593 | hwc->sample_period = x86_pmu.max_period; |
594 | hwc->last_period = hwc->sample_period; | |
e7850595 | 595 | local64_set(&hwc->period_left, hwc->sample_period); |
c1726f34 RR |
596 | } else { |
597 | /* | |
598 | * If we have a PMU initialized but no APIC | |
599 | * interrupts, we cannot sample hardware | |
600 | * events (user-space has to fall back and | |
601 | * sample via a hrtimer based software event): | |
602 | */ | |
603 | if (!x86_pmu.apic) | |
604 | return -EOPNOTSUPP; | |
605 | } | |
606 | ||
b52c55c6 IM |
607 | /* |
608 | * Do not allow config1 (extended registers) to propagate, | |
609 | * there's no sane user-space generalization yet: | |
610 | */ | |
c1726f34 | 611 | if (attr->type == PERF_TYPE_RAW) |
b52c55c6 | 612 | return 0; |
c1726f34 RR |
613 | |
614 | if (attr->type == PERF_TYPE_HW_CACHE) | |
e994d7d2 | 615 | return set_ext_hw_attr(hwc, event); |
c1726f34 RR |
616 | |
617 | if (attr->config >= x86_pmu.max_events) | |
618 | return -EINVAL; | |
619 | ||
620 | /* | |
621 | * The generic map: | |
622 | */ | |
623 | config = x86_pmu.event_map(attr->config); | |
624 | ||
625 | if (config == 0) | |
626 | return -ENOENT; | |
627 | ||
628 | if (config == -1LL) | |
629 | return -EINVAL; | |
630 | ||
631 | /* | |
632 | * Branch tracing: | |
633 | */ | |
18a073a3 PZ |
634 | if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS && |
635 | !attr->freq && hwc->sample_period == 1) { | |
c1726f34 | 636 | /* BTS is not supported by this architecture. */ |
6809b6ea | 637 | if (!x86_pmu.bts_active) |
c1726f34 RR |
638 | return -EOPNOTSUPP; |
639 | ||
640 | /* BTS is currently only allowed for user-mode. */ | |
641 | if (!attr->exclude_kernel) | |
642 | return -EOPNOTSUPP; | |
643 | } | |
644 | ||
645 | hwc->config |= config; | |
646 | ||
647 | return 0; | |
648 | } | |
4261e0e0 | 649 | |
b4cdc5c2 | 650 | static int x86_pmu_hw_config(struct perf_event *event) |
a072738e | 651 | { |
ab608344 PZ |
652 | if (event->attr.precise_ip) { |
653 | int precise = 0; | |
654 | ||
655 | /* Support for constant skid */ | |
6809b6ea | 656 | if (x86_pmu.pebs_active) { |
ab608344 PZ |
657 | precise++; |
658 | ||
5553be26 PZ |
659 | /* Support for IP fixup */ |
660 | if (x86_pmu.lbr_nr) | |
661 | precise++; | |
662 | } | |
ab608344 PZ |
663 | |
664 | if (event->attr.precise_ip > precise) | |
665 | return -EOPNOTSUPP; | |
666 | } | |
667 | ||
a072738e CG |
668 | /* |
669 | * Generate PMC IRQs: | |
670 | * (keep 'enabled' bit clear for now) | |
671 | */ | |
b4cdc5c2 | 672 | event->hw.config = ARCH_PERFMON_EVENTSEL_INT; |
a072738e CG |
673 | |
674 | /* | |
675 | * Count user and OS events unless requested not to | |
676 | */ | |
b4cdc5c2 PZ |
677 | if (!event->attr.exclude_user) |
678 | event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; | |
679 | if (!event->attr.exclude_kernel) | |
680 | event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; | |
a072738e | 681 | |
b4cdc5c2 PZ |
682 | if (event->attr.type == PERF_TYPE_RAW) |
683 | event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; | |
a072738e | 684 | |
9d0fcba6 | 685 | return x86_setup_perfctr(event); |
a098f448 RR |
686 | } |
687 | ||
241771ef | 688 | /* |
0d48696f | 689 | * Setup the hardware configuration for a given attr_type |
241771ef | 690 | */ |
b0a873eb | 691 | static int __x86_pmu_event_init(struct perf_event *event) |
241771ef | 692 | { |
4e935e47 | 693 | int err; |
241771ef | 694 | |
85cf9dba RR |
695 | if (!x86_pmu_initialized()) |
696 | return -ENODEV; | |
241771ef | 697 | |
4e935e47 | 698 | err = 0; |
cdd6c482 | 699 | if (!atomic_inc_not_zero(&active_events)) { |
4e935e47 | 700 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 701 | if (atomic_read(&active_events) == 0) { |
30dd568c MM |
702 | if (!reserve_pmc_hardware()) |
703 | err = -EBUSY; | |
f80c9e30 PZ |
704 | else |
705 | reserve_ds_buffers(); | |
30dd568c MM |
706 | } |
707 | if (!err) | |
cdd6c482 | 708 | atomic_inc(&active_events); |
4e935e47 PZ |
709 | mutex_unlock(&pmc_reserve_mutex); |
710 | } | |
711 | if (err) | |
712 | return err; | |
713 | ||
cdd6c482 | 714 | event->destroy = hw_perf_event_destroy; |
a1792cda | 715 | |
4261e0e0 RR |
716 | event->hw.idx = -1; |
717 | event->hw.last_cpu = -1; | |
718 | event->hw.last_tag = ~0ULL; | |
b690081d | 719 | |
efc9f05d SE |
720 | /* mark unused */ |
721 | event->hw.extra_reg.idx = EXTRA_REG_NONE; | |
722 | ||
9d0fcba6 | 723 | return x86_pmu.hw_config(event); |
4261e0e0 RR |
724 | } |
725 | ||
8c48e444 | 726 | static void x86_pmu_disable_all(void) |
f87ad35d | 727 | { |
cdd6c482 | 728 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
9e35ad38 PZ |
729 | int idx; |
730 | ||
948b1bb8 | 731 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
732 | u64 val; |
733 | ||
43f6201a | 734 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 735 | continue; |
41bf4989 | 736 | rdmsrl(x86_pmu_config_addr(idx), val); |
bb1165d6 | 737 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
4295ee62 | 738 | continue; |
bb1165d6 | 739 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
41bf4989 | 740 | wrmsrl(x86_pmu_config_addr(idx), val); |
f87ad35d | 741 | } |
f87ad35d JSR |
742 | } |
743 | ||
a4eaf7f1 | 744 | static void x86_pmu_disable(struct pmu *pmu) |
b56a3802 | 745 | { |
1da53e02 SE |
746 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
747 | ||
85cf9dba | 748 | if (!x86_pmu_initialized()) |
9e35ad38 | 749 | return; |
1da53e02 | 750 | |
1a6e21f7 PZ |
751 | if (!cpuc->enabled) |
752 | return; | |
753 | ||
754 | cpuc->n_added = 0; | |
755 | cpuc->enabled = 0; | |
756 | barrier(); | |
1da53e02 SE |
757 | |
758 | x86_pmu.disable_all(); | |
b56a3802 | 759 | } |
241771ef | 760 | |
d45dd923 RR |
761 | static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, |
762 | u64 enable_mask) | |
763 | { | |
efc9f05d SE |
764 | if (hwc->extra_reg.reg) |
765 | wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config); | |
73d6e522 | 766 | wrmsrl(hwc->config_base, hwc->config | enable_mask); |
d45dd923 RR |
767 | } |
768 | ||
11164cd4 | 769 | static void x86_pmu_enable_all(int added) |
f87ad35d | 770 | { |
cdd6c482 | 771 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
f87ad35d JSR |
772 | int idx; |
773 | ||
948b1bb8 | 774 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
d45dd923 | 775 | struct hw_perf_event *hwc = &cpuc->events[idx]->hw; |
b0f3f28e | 776 | |
43f6201a | 777 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 778 | continue; |
984b838c | 779 | |
d45dd923 | 780 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); |
f87ad35d JSR |
781 | } |
782 | } | |
783 | ||
51b0fe39 | 784 | static struct pmu pmu; |
1da53e02 SE |
785 | |
786 | static inline int is_x86_event(struct perf_event *event) | |
787 | { | |
788 | return event->pmu == &pmu; | |
789 | } | |
790 | ||
791 | static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) | |
792 | { | |
63b14649 | 793 | struct event_constraint *c, *constraints[X86_PMC_IDX_MAX]; |
1da53e02 | 794 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
c933c1a6 | 795 | int i, j, w, wmax, num = 0; |
1da53e02 SE |
796 | struct hw_perf_event *hwc; |
797 | ||
798 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
799 | ||
800 | for (i = 0; i < n; i++) { | |
b622d644 PZ |
801 | c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]); |
802 | constraints[i] = c; | |
1da53e02 SE |
803 | } |
804 | ||
8113070d SE |
805 | /* |
806 | * fastpath, try to reuse previous register | |
807 | */ | |
c933c1a6 | 808 | for (i = 0; i < n; i++) { |
8113070d | 809 | hwc = &cpuc->event_list[i]->hw; |
81269a08 | 810 | c = constraints[i]; |
8113070d SE |
811 | |
812 | /* never assigned */ | |
813 | if (hwc->idx == -1) | |
814 | break; | |
815 | ||
816 | /* constraint still honored */ | |
63b14649 | 817 | if (!test_bit(hwc->idx, c->idxmsk)) |
8113070d SE |
818 | break; |
819 | ||
820 | /* not already used */ | |
821 | if (test_bit(hwc->idx, used_mask)) | |
822 | break; | |
823 | ||
34538ee7 | 824 | __set_bit(hwc->idx, used_mask); |
8113070d SE |
825 | if (assign) |
826 | assign[i] = hwc->idx; | |
827 | } | |
c933c1a6 | 828 | if (i == n) |
8113070d SE |
829 | goto done; |
830 | ||
831 | /* | |
832 | * begin slow path | |
833 | */ | |
834 | ||
835 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
836 | ||
1da53e02 SE |
837 | /* |
838 | * weight = number of possible counters | |
839 | * | |
840 | * 1 = most constrained, only works on one counter | |
841 | * wmax = least constrained, works on any counter | |
842 | * | |
843 | * assign events to counters starting with most | |
844 | * constrained events. | |
845 | */ | |
948b1bb8 | 846 | wmax = x86_pmu.num_counters; |
1da53e02 SE |
847 | |
848 | /* | |
849 | * when fixed event counters are present, | |
850 | * wmax is incremented by 1 to account | |
851 | * for one more choice | |
852 | */ | |
948b1bb8 | 853 | if (x86_pmu.num_counters_fixed) |
1da53e02 SE |
854 | wmax++; |
855 | ||
8113070d | 856 | for (w = 1, num = n; num && w <= wmax; w++) { |
1da53e02 | 857 | /* for each event */ |
8113070d | 858 | for (i = 0; num && i < n; i++) { |
81269a08 | 859 | c = constraints[i]; |
1da53e02 SE |
860 | hwc = &cpuc->event_list[i]->hw; |
861 | ||
272d30be | 862 | if (c->weight != w) |
1da53e02 SE |
863 | continue; |
864 | ||
984b3f57 | 865 | for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) { |
1da53e02 SE |
866 | if (!test_bit(j, used_mask)) |
867 | break; | |
868 | } | |
869 | ||
870 | if (j == X86_PMC_IDX_MAX) | |
871 | break; | |
1da53e02 | 872 | |
34538ee7 | 873 | __set_bit(j, used_mask); |
8113070d | 874 | |
1da53e02 SE |
875 | if (assign) |
876 | assign[i] = j; | |
877 | num--; | |
878 | } | |
879 | } | |
8113070d | 880 | done: |
1da53e02 SE |
881 | /* |
882 | * scheduling failed or is just a simulation, | |
883 | * free resources if necessary | |
884 | */ | |
885 | if (!assign || num) { | |
886 | for (i = 0; i < n; i++) { | |
887 | if (x86_pmu.put_event_constraints) | |
888 | x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]); | |
889 | } | |
890 | } | |
891 | return num ? -ENOSPC : 0; | |
892 | } | |
893 | ||
894 | /* | |
895 | * dogrp: true if must collect siblings events (group) | |
896 | * returns total number of events and error code | |
897 | */ | |
898 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) | |
899 | { | |
900 | struct perf_event *event; | |
901 | int n, max_count; | |
902 | ||
948b1bb8 | 903 | max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; |
1da53e02 SE |
904 | |
905 | /* current number of events already accepted */ | |
906 | n = cpuc->n_events; | |
907 | ||
908 | if (is_x86_event(leader)) { | |
909 | if (n >= max_count) | |
910 | return -ENOSPC; | |
911 | cpuc->event_list[n] = leader; | |
912 | n++; | |
913 | } | |
914 | if (!dogrp) | |
915 | return n; | |
916 | ||
917 | list_for_each_entry(event, &leader->sibling_list, group_entry) { | |
918 | if (!is_x86_event(event) || | |
8113070d | 919 | event->state <= PERF_EVENT_STATE_OFF) |
1da53e02 SE |
920 | continue; |
921 | ||
922 | if (n >= max_count) | |
923 | return -ENOSPC; | |
924 | ||
925 | cpuc->event_list[n] = event; | |
926 | n++; | |
927 | } | |
928 | return n; | |
929 | } | |
930 | ||
1da53e02 | 931 | static inline void x86_assign_hw_event(struct perf_event *event, |
447a194b | 932 | struct cpu_hw_events *cpuc, int i) |
1da53e02 | 933 | { |
447a194b SE |
934 | struct hw_perf_event *hwc = &event->hw; |
935 | ||
936 | hwc->idx = cpuc->assign[i]; | |
937 | hwc->last_cpu = smp_processor_id(); | |
938 | hwc->last_tag = ++cpuc->tags[i]; | |
1da53e02 SE |
939 | |
940 | if (hwc->idx == X86_PMC_IDX_FIXED_BTS) { | |
941 | hwc->config_base = 0; | |
942 | hwc->event_base = 0; | |
943 | } else if (hwc->idx >= X86_PMC_IDX_FIXED) { | |
944 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
fc66c521 | 945 | hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - X86_PMC_IDX_FIXED); |
1da53e02 | 946 | } else { |
73d6e522 RR |
947 | hwc->config_base = x86_pmu_config_addr(hwc->idx); |
948 | hwc->event_base = x86_pmu_event_addr(hwc->idx); | |
1da53e02 SE |
949 | } |
950 | } | |
951 | ||
447a194b SE |
952 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
953 | struct cpu_hw_events *cpuc, | |
954 | int i) | |
955 | { | |
956 | return hwc->idx == cpuc->assign[i] && | |
957 | hwc->last_cpu == smp_processor_id() && | |
958 | hwc->last_tag == cpuc->tags[i]; | |
959 | } | |
960 | ||
a4eaf7f1 PZ |
961 | static void x86_pmu_start(struct perf_event *event, int flags); |
962 | static void x86_pmu_stop(struct perf_event *event, int flags); | |
2e841873 | 963 | |
a4eaf7f1 | 964 | static void x86_pmu_enable(struct pmu *pmu) |
ee06094f | 965 | { |
1da53e02 SE |
966 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
967 | struct perf_event *event; | |
968 | struct hw_perf_event *hwc; | |
11164cd4 | 969 | int i, added = cpuc->n_added; |
1da53e02 | 970 | |
85cf9dba | 971 | if (!x86_pmu_initialized()) |
2b9ff0db | 972 | return; |
1a6e21f7 PZ |
973 | |
974 | if (cpuc->enabled) | |
975 | return; | |
976 | ||
1da53e02 | 977 | if (cpuc->n_added) { |
19925ce7 | 978 | int n_running = cpuc->n_events - cpuc->n_added; |
1da53e02 SE |
979 | /* |
980 | * apply assignment obtained either from | |
981 | * hw_perf_group_sched_in() or x86_pmu_enable() | |
982 | * | |
983 | * step1: save events moving to new counters | |
984 | * step2: reprogram moved events into new counters | |
985 | */ | |
19925ce7 | 986 | for (i = 0; i < n_running; i++) { |
1da53e02 SE |
987 | event = cpuc->event_list[i]; |
988 | hwc = &event->hw; | |
989 | ||
447a194b SE |
990 | /* |
991 | * we can avoid reprogramming counter if: | |
992 | * - assigned same counter as last time | |
993 | * - running on same CPU as last time | |
994 | * - no other event has used the counter since | |
995 | */ | |
996 | if (hwc->idx == -1 || | |
997 | match_prev_assignment(hwc, cpuc, i)) | |
1da53e02 SE |
998 | continue; |
999 | ||
a4eaf7f1 PZ |
1000 | /* |
1001 | * Ensure we don't accidentally enable a stopped | |
1002 | * counter simply because we rescheduled. | |
1003 | */ | |
1004 | if (hwc->state & PERF_HES_STOPPED) | |
1005 | hwc->state |= PERF_HES_ARCH; | |
1006 | ||
1007 | x86_pmu_stop(event, PERF_EF_UPDATE); | |
1da53e02 SE |
1008 | } |
1009 | ||
1010 | for (i = 0; i < cpuc->n_events; i++) { | |
1da53e02 SE |
1011 | event = cpuc->event_list[i]; |
1012 | hwc = &event->hw; | |
1013 | ||
45e16a68 | 1014 | if (!match_prev_assignment(hwc, cpuc, i)) |
447a194b | 1015 | x86_assign_hw_event(event, cpuc, i); |
45e16a68 PZ |
1016 | else if (i < n_running) |
1017 | continue; | |
1da53e02 | 1018 | |
a4eaf7f1 PZ |
1019 | if (hwc->state & PERF_HES_ARCH) |
1020 | continue; | |
1021 | ||
1022 | x86_pmu_start(event, PERF_EF_RELOAD); | |
1da53e02 SE |
1023 | } |
1024 | cpuc->n_added = 0; | |
1025 | perf_events_lapic_init(); | |
1026 | } | |
1a6e21f7 PZ |
1027 | |
1028 | cpuc->enabled = 1; | |
1029 | barrier(); | |
1030 | ||
11164cd4 | 1031 | x86_pmu.enable_all(added); |
ee06094f | 1032 | } |
ee06094f | 1033 | |
aff3d91a | 1034 | static inline void x86_pmu_disable_event(struct perf_event *event) |
b0f3f28e | 1035 | { |
aff3d91a | 1036 | struct hw_perf_event *hwc = &event->hw; |
7645a24c | 1037 | |
73d6e522 | 1038 | wrmsrl(hwc->config_base, hwc->config); |
b0f3f28e PZ |
1039 | } |
1040 | ||
245b2e70 | 1041 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 1042 | |
ee06094f IM |
1043 | /* |
1044 | * Set the next IRQ period, based on the hwc->period_left value. | |
cdd6c482 | 1045 | * To be called with the event disabled in hw: |
ee06094f | 1046 | */ |
e4abb5d4 | 1047 | static int |
07088edb | 1048 | x86_perf_event_set_period(struct perf_event *event) |
241771ef | 1049 | { |
07088edb | 1050 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 1051 | s64 left = local64_read(&hwc->period_left); |
e4abb5d4 | 1052 | s64 period = hwc->sample_period; |
7645a24c | 1053 | int ret = 0, idx = hwc->idx; |
ee06094f | 1054 | |
30dd568c MM |
1055 | if (idx == X86_PMC_IDX_FIXED_BTS) |
1056 | return 0; | |
1057 | ||
ee06094f | 1058 | /* |
af901ca1 | 1059 | * If we are way outside a reasonable range then just skip forward: |
ee06094f IM |
1060 | */ |
1061 | if (unlikely(left <= -period)) { | |
1062 | left = period; | |
e7850595 | 1063 | local64_set(&hwc->period_left, left); |
9e350de3 | 1064 | hwc->last_period = period; |
e4abb5d4 | 1065 | ret = 1; |
ee06094f IM |
1066 | } |
1067 | ||
1068 | if (unlikely(left <= 0)) { | |
1069 | left += period; | |
e7850595 | 1070 | local64_set(&hwc->period_left, left); |
9e350de3 | 1071 | hwc->last_period = period; |
e4abb5d4 | 1072 | ret = 1; |
ee06094f | 1073 | } |
1c80f4b5 | 1074 | /* |
dfc65094 | 1075 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
1076 | */ |
1077 | if (unlikely(left < 2)) | |
1078 | left = 2; | |
241771ef | 1079 | |
e4abb5d4 PZ |
1080 | if (left > x86_pmu.max_period) |
1081 | left = x86_pmu.max_period; | |
1082 | ||
245b2e70 | 1083 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
ee06094f IM |
1084 | |
1085 | /* | |
cdd6c482 | 1086 | * The hw event starts counting from this event offset, |
ee06094f IM |
1087 | * mark it to be able to extra future deltas: |
1088 | */ | |
e7850595 | 1089 | local64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 1090 | |
73d6e522 | 1091 | wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac CG |
1092 | |
1093 | /* | |
1094 | * Due to erratum on certan cpu we need | |
1095 | * a second write to be sure the register | |
1096 | * is updated properly | |
1097 | */ | |
1098 | if (x86_pmu.perfctr_second_write) { | |
73d6e522 | 1099 | wrmsrl(hwc->event_base, |
948b1bb8 | 1100 | (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac | 1101 | } |
e4abb5d4 | 1102 | |
cdd6c482 | 1103 | perf_event_update_userpage(event); |
194002b2 | 1104 | |
e4abb5d4 | 1105 | return ret; |
2f18d1e8 IM |
1106 | } |
1107 | ||
aff3d91a | 1108 | static void x86_pmu_enable_event(struct perf_event *event) |
7c90cc45 | 1109 | { |
0a3aee0d | 1110 | if (__this_cpu_read(cpu_hw_events.enabled)) |
31fa58af RR |
1111 | __x86_pmu_enable_event(&event->hw, |
1112 | ARCH_PERFMON_EVENTSEL_ENABLE); | |
241771ef IM |
1113 | } |
1114 | ||
b690081d | 1115 | /* |
a4eaf7f1 | 1116 | * Add a single event to the PMU. |
1da53e02 SE |
1117 | * |
1118 | * The event is added to the group of enabled events | |
1119 | * but only if it can be scehduled with existing events. | |
fe9081cc | 1120 | */ |
a4eaf7f1 | 1121 | static int x86_pmu_add(struct perf_event *event, int flags) |
fe9081cc PZ |
1122 | { |
1123 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1da53e02 SE |
1124 | struct hw_perf_event *hwc; |
1125 | int assign[X86_PMC_IDX_MAX]; | |
1126 | int n, n0, ret; | |
fe9081cc | 1127 | |
1da53e02 | 1128 | hwc = &event->hw; |
fe9081cc | 1129 | |
33696fc0 | 1130 | perf_pmu_disable(event->pmu); |
1da53e02 | 1131 | n0 = cpuc->n_events; |
24cd7f54 PZ |
1132 | ret = n = collect_events(cpuc, event, false); |
1133 | if (ret < 0) | |
1134 | goto out; | |
53b441a5 | 1135 | |
a4eaf7f1 PZ |
1136 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; |
1137 | if (!(flags & PERF_EF_START)) | |
1138 | hwc->state |= PERF_HES_ARCH; | |
1139 | ||
4d1c52b0 LM |
1140 | /* |
1141 | * If group events scheduling transaction was started, | |
0d2eb44f | 1142 | * skip the schedulability test here, it will be performed |
a4eaf7f1 | 1143 | * at commit time (->commit_txn) as a whole |
4d1c52b0 | 1144 | */ |
8d2cacbb | 1145 | if (cpuc->group_flag & PERF_EVENT_TXN) |
24cd7f54 | 1146 | goto done_collect; |
4d1c52b0 | 1147 | |
a072738e | 1148 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
1da53e02 | 1149 | if (ret) |
24cd7f54 | 1150 | goto out; |
1da53e02 SE |
1151 | /* |
1152 | * copy new assignment, now we know it is possible | |
1153 | * will be used by hw_perf_enable() | |
1154 | */ | |
1155 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
7e2ae347 | 1156 | |
24cd7f54 | 1157 | done_collect: |
1da53e02 | 1158 | cpuc->n_events = n; |
356e1f2e | 1159 | cpuc->n_added += n - n0; |
90151c35 | 1160 | cpuc->n_txn += n - n0; |
95cdd2e7 | 1161 | |
24cd7f54 PZ |
1162 | ret = 0; |
1163 | out: | |
33696fc0 | 1164 | perf_pmu_enable(event->pmu); |
24cd7f54 | 1165 | return ret; |
241771ef IM |
1166 | } |
1167 | ||
a4eaf7f1 | 1168 | static void x86_pmu_start(struct perf_event *event, int flags) |
d76a0812 | 1169 | { |
c08053e6 PZ |
1170 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
1171 | int idx = event->hw.idx; | |
1172 | ||
a4eaf7f1 PZ |
1173 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) |
1174 | return; | |
1175 | ||
1176 | if (WARN_ON_ONCE(idx == -1)) | |
1177 | return; | |
1178 | ||
1179 | if (flags & PERF_EF_RELOAD) { | |
1180 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1181 | x86_perf_event_set_period(event); | |
1182 | } | |
1183 | ||
1184 | event->hw.state = 0; | |
d76a0812 | 1185 | |
c08053e6 PZ |
1186 | cpuc->events[idx] = event; |
1187 | __set_bit(idx, cpuc->active_mask); | |
63e6be6d | 1188 | __set_bit(idx, cpuc->running); |
aff3d91a | 1189 | x86_pmu.enable(event); |
c08053e6 | 1190 | perf_event_update_userpage(event); |
a78ac325 PZ |
1191 | } |
1192 | ||
cdd6c482 | 1193 | void perf_event_print_debug(void) |
241771ef | 1194 | { |
2f18d1e8 | 1195 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
ca037701 | 1196 | u64 pebs; |
cdd6c482 | 1197 | struct cpu_hw_events *cpuc; |
5bb9efe3 | 1198 | unsigned long flags; |
1e125676 IM |
1199 | int cpu, idx; |
1200 | ||
948b1bb8 | 1201 | if (!x86_pmu.num_counters) |
1e125676 | 1202 | return; |
241771ef | 1203 | |
5bb9efe3 | 1204 | local_irq_save(flags); |
241771ef IM |
1205 | |
1206 | cpu = smp_processor_id(); | |
cdd6c482 | 1207 | cpuc = &per_cpu(cpu_hw_events, cpu); |
241771ef | 1208 | |
faa28ae0 | 1209 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1210 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1211 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1212 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1213 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
ca037701 | 1214 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); |
a1ef58f4 JSR |
1215 | |
1216 | pr_info("\n"); | |
1217 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1218 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1219 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1220 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
ca037701 | 1221 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); |
f87ad35d | 1222 | } |
7645a24c | 1223 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
241771ef | 1224 | |
948b1bb8 | 1225 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
41bf4989 RR |
1226 | rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); |
1227 | rdmsrl(x86_pmu_event_addr(idx), pmc_count); | |
241771ef | 1228 | |
245b2e70 | 1229 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 1230 | |
a1ef58f4 | 1231 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1232 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1233 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1234 | cpu, idx, pmc_count); |
a1ef58f4 | 1235 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1236 | cpu, idx, prev_left); |
241771ef | 1237 | } |
948b1bb8 | 1238 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
1239 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1240 | ||
a1ef58f4 | 1241 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1242 | cpu, idx, pmc_count); |
1243 | } | |
5bb9efe3 | 1244 | local_irq_restore(flags); |
241771ef IM |
1245 | } |
1246 | ||
a4eaf7f1 | 1247 | static void x86_pmu_stop(struct perf_event *event, int flags) |
241771ef | 1248 | { |
d76a0812 | 1249 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
cdd6c482 | 1250 | struct hw_perf_event *hwc = &event->hw; |
241771ef | 1251 | |
a4eaf7f1 PZ |
1252 | if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) { |
1253 | x86_pmu.disable(event); | |
1254 | cpuc->events[hwc->idx] = NULL; | |
1255 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); | |
1256 | hwc->state |= PERF_HES_STOPPED; | |
1257 | } | |
30dd568c | 1258 | |
a4eaf7f1 PZ |
1259 | if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { |
1260 | /* | |
1261 | * Drain the remaining delta count out of a event | |
1262 | * that we are disabling: | |
1263 | */ | |
1264 | x86_perf_event_update(event); | |
1265 | hwc->state |= PERF_HES_UPTODATE; | |
1266 | } | |
2e841873 PZ |
1267 | } |
1268 | ||
a4eaf7f1 | 1269 | static void x86_pmu_del(struct perf_event *event, int flags) |
2e841873 PZ |
1270 | { |
1271 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1272 | int i; | |
1273 | ||
90151c35 SE |
1274 | /* |
1275 | * If we're called during a txn, we don't need to do anything. | |
1276 | * The events never got scheduled and ->cancel_txn will truncate | |
1277 | * the event_list. | |
1278 | */ | |
8d2cacbb | 1279 | if (cpuc->group_flag & PERF_EVENT_TXN) |
90151c35 SE |
1280 | return; |
1281 | ||
a4eaf7f1 | 1282 | x86_pmu_stop(event, PERF_EF_UPDATE); |
194002b2 | 1283 | |
1da53e02 SE |
1284 | for (i = 0; i < cpuc->n_events; i++) { |
1285 | if (event == cpuc->event_list[i]) { | |
1286 | ||
1287 | if (x86_pmu.put_event_constraints) | |
1288 | x86_pmu.put_event_constraints(cpuc, event); | |
1289 | ||
1290 | while (++i < cpuc->n_events) | |
1291 | cpuc->event_list[i-1] = cpuc->event_list[i]; | |
1292 | ||
1293 | --cpuc->n_events; | |
6c9687ab | 1294 | break; |
1da53e02 SE |
1295 | } |
1296 | } | |
cdd6c482 | 1297 | perf_event_update_userpage(event); |
241771ef IM |
1298 | } |
1299 | ||
8c48e444 | 1300 | static int x86_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1301 | { |
df1a132b | 1302 | struct perf_sample_data data; |
cdd6c482 IM |
1303 | struct cpu_hw_events *cpuc; |
1304 | struct perf_event *event; | |
11d1578f | 1305 | int idx, handled = 0; |
9029a5e3 IM |
1306 | u64 val; |
1307 | ||
dc1d628a | 1308 | perf_sample_data_init(&data, 0); |
df1a132b | 1309 | |
cdd6c482 | 1310 | cpuc = &__get_cpu_var(cpu_hw_events); |
962bf7a6 | 1311 | |
2bce5dac DZ |
1312 | /* |
1313 | * Some chipsets need to unmask the LVTPC in a particular spot | |
1314 | * inside the nmi handler. As a result, the unmasking was pushed | |
1315 | * into all the nmi handlers. | |
1316 | * | |
1317 | * This generic handler doesn't seem to have any issues where the | |
1318 | * unmasking occurs so it was left at the top. | |
1319 | */ | |
1320 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
1321 | ||
948b1bb8 | 1322 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
63e6be6d RR |
1323 | if (!test_bit(idx, cpuc->active_mask)) { |
1324 | /* | |
1325 | * Though we deactivated the counter some cpus | |
1326 | * might still deliver spurious interrupts still | |
1327 | * in flight. Catch them: | |
1328 | */ | |
1329 | if (__test_and_clear_bit(idx, cpuc->running)) | |
1330 | handled++; | |
a29aa8a7 | 1331 | continue; |
63e6be6d | 1332 | } |
962bf7a6 | 1333 | |
cdd6c482 | 1334 | event = cpuc->events[idx]; |
a4016a79 | 1335 | |
cc2ad4ba | 1336 | val = x86_perf_event_update(event); |
948b1bb8 | 1337 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
48e22d56 | 1338 | continue; |
962bf7a6 | 1339 | |
9e350de3 | 1340 | /* |
cdd6c482 | 1341 | * event overflow |
9e350de3 | 1342 | */ |
4177c42a | 1343 | handled++; |
cdd6c482 | 1344 | data.period = event->hw.last_period; |
9e350de3 | 1345 | |
07088edb | 1346 | if (!x86_perf_event_set_period(event)) |
e4abb5d4 PZ |
1347 | continue; |
1348 | ||
a8b0ca17 | 1349 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1350 | x86_pmu_stop(event, 0); |
a29aa8a7 | 1351 | } |
962bf7a6 | 1352 | |
9e350de3 PZ |
1353 | if (handled) |
1354 | inc_irq_stat(apic_perf_irqs); | |
1355 | ||
a29aa8a7 RR |
1356 | return handled; |
1357 | } | |
39d81eab | 1358 | |
cdd6c482 | 1359 | void perf_events_lapic_init(void) |
241771ef | 1360 | { |
04da8a43 | 1361 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
241771ef | 1362 | return; |
85cf9dba | 1363 | |
241771ef | 1364 | /* |
c323d95f | 1365 | * Always use NMI for PMU |
241771ef | 1366 | */ |
c323d95f | 1367 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1368 | } |
1369 | ||
4177c42a RR |
1370 | struct pmu_nmi_state { |
1371 | unsigned int marked; | |
1372 | int handled; | |
1373 | }; | |
1374 | ||
1375 | static DEFINE_PER_CPU(struct pmu_nmi_state, pmu_nmi); | |
1376 | ||
241771ef | 1377 | static int __kprobes |
cdd6c482 | 1378 | perf_event_nmi_handler(struct notifier_block *self, |
241771ef IM |
1379 | unsigned long cmd, void *__args) |
1380 | { | |
1381 | struct die_args *args = __args; | |
4177c42a RR |
1382 | unsigned int this_nmi; |
1383 | int handled; | |
b0f3f28e | 1384 | |
cdd6c482 | 1385 | if (!atomic_read(&active_events)) |
63a809a2 PZ |
1386 | return NOTIFY_DONE; |
1387 | ||
b0f3f28e PZ |
1388 | switch (cmd) { |
1389 | case DIE_NMI: | |
b0f3f28e | 1390 | break; |
4177c42a RR |
1391 | case DIE_NMIUNKNOWN: |
1392 | this_nmi = percpu_read(irq_stat.__nmi_count); | |
0a3aee0d | 1393 | if (this_nmi != __this_cpu_read(pmu_nmi.marked)) |
4177c42a RR |
1394 | /* let the kernel handle the unknown nmi */ |
1395 | return NOTIFY_DONE; | |
1396 | /* | |
1397 | * This one is a PMU back-to-back nmi. Two events | |
1398 | * trigger 'simultaneously' raising two back-to-back | |
1399 | * NMIs. If the first NMI handles both, the latter | |
1400 | * will be empty and daze the CPU. So, we drop it to | |
1401 | * avoid false-positive 'unknown nmi' messages. | |
1402 | */ | |
1403 | return NOTIFY_STOP; | |
b0f3f28e | 1404 | default: |
241771ef | 1405 | return NOTIFY_DONE; |
b0f3f28e | 1406 | } |
241771ef | 1407 | |
4177c42a RR |
1408 | handled = x86_pmu.handle_irq(args->regs); |
1409 | if (!handled) | |
1410 | return NOTIFY_DONE; | |
1411 | ||
1412 | this_nmi = percpu_read(irq_stat.__nmi_count); | |
1413 | if ((handled > 1) || | |
1414 | /* the next nmi could be a back-to-back nmi */ | |
0a3aee0d TH |
1415 | ((__this_cpu_read(pmu_nmi.marked) == this_nmi) && |
1416 | (__this_cpu_read(pmu_nmi.handled) > 1))) { | |
4177c42a RR |
1417 | /* |
1418 | * We could have two subsequent back-to-back nmis: The | |
1419 | * first handles more than one counter, the 2nd | |
1420 | * handles only one counter and the 3rd handles no | |
1421 | * counter. | |
1422 | * | |
1423 | * This is the 2nd nmi because the previous was | |
1424 | * handling more than one counter. We will mark the | |
1425 | * next (3rd) and then drop it if unhandled. | |
1426 | */ | |
0a3aee0d TH |
1427 | __this_cpu_write(pmu_nmi.marked, this_nmi + 1); |
1428 | __this_cpu_write(pmu_nmi.handled, handled); | |
4177c42a | 1429 | } |
241771ef | 1430 | |
a4016a79 | 1431 | return NOTIFY_STOP; |
241771ef IM |
1432 | } |
1433 | ||
f22f54f4 PZ |
1434 | static __read_mostly struct notifier_block perf_event_nmi_notifier = { |
1435 | .notifier_call = perf_event_nmi_handler, | |
1436 | .next = NULL, | |
166d7514 | 1437 | .priority = NMI_LOCAL_LOW_PRIOR, |
f22f54f4 PZ |
1438 | }; |
1439 | ||
63b14649 | 1440 | static struct event_constraint unconstrained; |
38331f62 | 1441 | static struct event_constraint emptyconstraint; |
63b14649 | 1442 | |
63b14649 | 1443 | static struct event_constraint * |
f22f54f4 | 1444 | x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event) |
1da53e02 | 1445 | { |
63b14649 | 1446 | struct event_constraint *c; |
1da53e02 | 1447 | |
1da53e02 SE |
1448 | if (x86_pmu.event_constraints) { |
1449 | for_each_event_constraint(c, x86_pmu.event_constraints) { | |
63b14649 PZ |
1450 | if ((event->hw.config & c->cmask) == c->code) |
1451 | return c; | |
1da53e02 SE |
1452 | } |
1453 | } | |
63b14649 PZ |
1454 | |
1455 | return &unconstrained; | |
1da53e02 SE |
1456 | } |
1457 | ||
f22f54f4 PZ |
1458 | #include "perf_event_amd.c" |
1459 | #include "perf_event_p6.c" | |
a072738e | 1460 | #include "perf_event_p4.c" |
caff2bef | 1461 | #include "perf_event_intel_lbr.c" |
ca037701 | 1462 | #include "perf_event_intel_ds.c" |
f22f54f4 | 1463 | #include "perf_event_intel.c" |
f87ad35d | 1464 | |
3f6da390 PZ |
1465 | static int __cpuinit |
1466 | x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) | |
1467 | { | |
1468 | unsigned int cpu = (long)hcpu; | |
b38b24ea | 1469 | int ret = NOTIFY_OK; |
3f6da390 PZ |
1470 | |
1471 | switch (action & ~CPU_TASKS_FROZEN) { | |
1472 | case CPU_UP_PREPARE: | |
1473 | if (x86_pmu.cpu_prepare) | |
b38b24ea | 1474 | ret = x86_pmu.cpu_prepare(cpu); |
3f6da390 PZ |
1475 | break; |
1476 | ||
1477 | case CPU_STARTING: | |
1478 | if (x86_pmu.cpu_starting) | |
1479 | x86_pmu.cpu_starting(cpu); | |
1480 | break; | |
1481 | ||
1482 | case CPU_DYING: | |
1483 | if (x86_pmu.cpu_dying) | |
1484 | x86_pmu.cpu_dying(cpu); | |
1485 | break; | |
1486 | ||
b38b24ea | 1487 | case CPU_UP_CANCELED: |
3f6da390 PZ |
1488 | case CPU_DEAD: |
1489 | if (x86_pmu.cpu_dead) | |
1490 | x86_pmu.cpu_dead(cpu); | |
1491 | break; | |
1492 | ||
1493 | default: | |
1494 | break; | |
1495 | } | |
1496 | ||
b38b24ea | 1497 | return ret; |
3f6da390 PZ |
1498 | } |
1499 | ||
12558038 CG |
1500 | static void __init pmu_check_apic(void) |
1501 | { | |
1502 | if (cpu_has_apic) | |
1503 | return; | |
1504 | ||
1505 | x86_pmu.apic = 0; | |
1506 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); | |
1507 | pr_info("no hardware sampling interrupt available.\n"); | |
1508 | } | |
1509 | ||
dda99116 | 1510 | static int __init init_hw_perf_events(void) |
b56a3802 | 1511 | { |
b622d644 | 1512 | struct event_constraint *c; |
72eae04d RR |
1513 | int err; |
1514 | ||
cdd6c482 | 1515 | pr_info("Performance Events: "); |
1123e3ad | 1516 | |
b56a3802 JSR |
1517 | switch (boot_cpu_data.x86_vendor) { |
1518 | case X86_VENDOR_INTEL: | |
72eae04d | 1519 | err = intel_pmu_init(); |
b56a3802 | 1520 | break; |
f87ad35d | 1521 | case X86_VENDOR_AMD: |
72eae04d | 1522 | err = amd_pmu_init(); |
f87ad35d | 1523 | break; |
4138960a | 1524 | default: |
004417a6 | 1525 | return 0; |
b56a3802 | 1526 | } |
1123e3ad | 1527 | if (err != 0) { |
cdd6c482 | 1528 | pr_cont("no PMU driver, software events only.\n"); |
004417a6 | 1529 | return 0; |
1123e3ad | 1530 | } |
b56a3802 | 1531 | |
12558038 CG |
1532 | pmu_check_apic(); |
1533 | ||
33c6d6a7 | 1534 | /* sanity check that the hardware exists or is emulated */ |
4407204c | 1535 | if (!check_hw_exists()) |
004417a6 | 1536 | return 0; |
33c6d6a7 | 1537 | |
1123e3ad | 1538 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1539 | |
3c44780b PZ |
1540 | if (x86_pmu.quirks) |
1541 | x86_pmu.quirks(); | |
1542 | ||
948b1bb8 | 1543 | if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) { |
cdd6c482 | 1544 | WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", |
948b1bb8 RR |
1545 | x86_pmu.num_counters, X86_PMC_MAX_GENERIC); |
1546 | x86_pmu.num_counters = X86_PMC_MAX_GENERIC; | |
241771ef | 1547 | } |
948b1bb8 | 1548 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; |
241771ef | 1549 | |
948b1bb8 | 1550 | if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { |
cdd6c482 | 1551 | WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", |
948b1bb8 RR |
1552 | x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED); |
1553 | x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; | |
703e937c | 1554 | } |
862a1a5f | 1555 | |
d6dc0b4e | 1556 | x86_pmu.intel_ctrl |= |
948b1bb8 | 1557 | ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED; |
241771ef | 1558 | |
cdd6c482 IM |
1559 | perf_events_lapic_init(); |
1560 | register_die_notifier(&perf_event_nmi_notifier); | |
1123e3ad | 1561 | |
63b14649 | 1562 | unconstrained = (struct event_constraint) |
948b1bb8 RR |
1563 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
1564 | 0, x86_pmu.num_counters); | |
63b14649 | 1565 | |
b622d644 PZ |
1566 | if (x86_pmu.event_constraints) { |
1567 | for_each_event_constraint(c, x86_pmu.event_constraints) { | |
a098f448 | 1568 | if (c->cmask != X86_RAW_EVENT_MASK) |
b622d644 PZ |
1569 | continue; |
1570 | ||
948b1bb8 RR |
1571 | c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; |
1572 | c->weight += x86_pmu.num_counters; | |
b622d644 PZ |
1573 | } |
1574 | } | |
1575 | ||
57c0c15b | 1576 | pr_info("... version: %d\n", x86_pmu.version); |
948b1bb8 RR |
1577 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); |
1578 | pr_info("... generic registers: %d\n", x86_pmu.num_counters); | |
1579 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); | |
57c0c15b | 1580 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
948b1bb8 | 1581 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); |
d6dc0b4e | 1582 | pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); |
3f6da390 | 1583 | |
2e80a82a | 1584 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
3f6da390 | 1585 | perf_cpu_notifier(x86_pmu_notifier); |
004417a6 PZ |
1586 | |
1587 | return 0; | |
241771ef | 1588 | } |
004417a6 | 1589 | early_initcall(init_hw_perf_events); |
621a01ea | 1590 | |
cdd6c482 | 1591 | static inline void x86_pmu_read(struct perf_event *event) |
ee06094f | 1592 | { |
cc2ad4ba | 1593 | x86_perf_event_update(event); |
ee06094f IM |
1594 | } |
1595 | ||
4d1c52b0 LM |
1596 | /* |
1597 | * Start group events scheduling transaction | |
1598 | * Set the flag to make pmu::enable() not perform the | |
1599 | * schedulability test, it will be performed at commit time | |
1600 | */ | |
51b0fe39 | 1601 | static void x86_pmu_start_txn(struct pmu *pmu) |
4d1c52b0 | 1602 | { |
33696fc0 | 1603 | perf_pmu_disable(pmu); |
0a3aee0d TH |
1604 | __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN); |
1605 | __this_cpu_write(cpu_hw_events.n_txn, 0); | |
4d1c52b0 LM |
1606 | } |
1607 | ||
1608 | /* | |
1609 | * Stop group events scheduling transaction | |
1610 | * Clear the flag and pmu::enable() will perform the | |
1611 | * schedulability test. | |
1612 | */ | |
51b0fe39 | 1613 | static void x86_pmu_cancel_txn(struct pmu *pmu) |
4d1c52b0 | 1614 | { |
0a3aee0d | 1615 | __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN); |
90151c35 SE |
1616 | /* |
1617 | * Truncate the collected events. | |
1618 | */ | |
0a3aee0d TH |
1619 | __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn)); |
1620 | __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn)); | |
33696fc0 | 1621 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1622 | } |
1623 | ||
1624 | /* | |
1625 | * Commit group events scheduling transaction | |
1626 | * Perform the group schedulability test as a whole | |
1627 | * Return 0 if success | |
1628 | */ | |
51b0fe39 | 1629 | static int x86_pmu_commit_txn(struct pmu *pmu) |
4d1c52b0 LM |
1630 | { |
1631 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1632 | int assign[X86_PMC_IDX_MAX]; | |
1633 | int n, ret; | |
1634 | ||
1635 | n = cpuc->n_events; | |
1636 | ||
1637 | if (!x86_pmu_initialized()) | |
1638 | return -EAGAIN; | |
1639 | ||
1640 | ret = x86_pmu.schedule_events(cpuc, n, assign); | |
1641 | if (ret) | |
1642 | return ret; | |
1643 | ||
1644 | /* | |
1645 | * copy new assignment, now we know it is possible | |
1646 | * will be used by hw_perf_enable() | |
1647 | */ | |
1648 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
1649 | ||
8d2cacbb | 1650 | cpuc->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1651 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1652 | return 0; |
1653 | } | |
cd8a38d3 SE |
1654 | /* |
1655 | * a fake_cpuc is used to validate event groups. Due to | |
1656 | * the extra reg logic, we need to also allocate a fake | |
1657 | * per_core and per_cpu structure. Otherwise, group events | |
1658 | * using extra reg may conflict without the kernel being | |
1659 | * able to catch this when the last event gets added to | |
1660 | * the group. | |
1661 | */ | |
1662 | static void free_fake_cpuc(struct cpu_hw_events *cpuc) | |
1663 | { | |
1664 | kfree(cpuc->shared_regs); | |
1665 | kfree(cpuc); | |
1666 | } | |
1667 | ||
1668 | static struct cpu_hw_events *allocate_fake_cpuc(void) | |
1669 | { | |
1670 | struct cpu_hw_events *cpuc; | |
1671 | int cpu = raw_smp_processor_id(); | |
1672 | ||
1673 | cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL); | |
1674 | if (!cpuc) | |
1675 | return ERR_PTR(-ENOMEM); | |
1676 | ||
1677 | /* only needed, if we have extra_regs */ | |
1678 | if (x86_pmu.extra_regs) { | |
1679 | cpuc->shared_regs = allocate_shared_regs(cpu); | |
1680 | if (!cpuc->shared_regs) | |
1681 | goto error; | |
1682 | } | |
1683 | return cpuc; | |
1684 | error: | |
1685 | free_fake_cpuc(cpuc); | |
1686 | return ERR_PTR(-ENOMEM); | |
1687 | } | |
4d1c52b0 | 1688 | |
ca037701 PZ |
1689 | /* |
1690 | * validate that we can schedule this event | |
1691 | */ | |
1692 | static int validate_event(struct perf_event *event) | |
1693 | { | |
1694 | struct cpu_hw_events *fake_cpuc; | |
1695 | struct event_constraint *c; | |
1696 | int ret = 0; | |
1697 | ||
cd8a38d3 SE |
1698 | fake_cpuc = allocate_fake_cpuc(); |
1699 | if (IS_ERR(fake_cpuc)) | |
1700 | return PTR_ERR(fake_cpuc); | |
ca037701 PZ |
1701 | |
1702 | c = x86_pmu.get_event_constraints(fake_cpuc, event); | |
1703 | ||
1704 | if (!c || !c->weight) | |
1705 | ret = -ENOSPC; | |
1706 | ||
1707 | if (x86_pmu.put_event_constraints) | |
1708 | x86_pmu.put_event_constraints(fake_cpuc, event); | |
1709 | ||
cd8a38d3 | 1710 | free_fake_cpuc(fake_cpuc); |
ca037701 PZ |
1711 | |
1712 | return ret; | |
1713 | } | |
1714 | ||
1da53e02 SE |
1715 | /* |
1716 | * validate a single event group | |
1717 | * | |
1718 | * validation include: | |
184f412c IM |
1719 | * - check events are compatible which each other |
1720 | * - events do not compete for the same counter | |
1721 | * - number of events <= number of counters | |
1da53e02 SE |
1722 | * |
1723 | * validation ensures the group can be loaded onto the | |
1724 | * PMU if it was the only group available. | |
1725 | */ | |
fe9081cc PZ |
1726 | static int validate_group(struct perf_event *event) |
1727 | { | |
1da53e02 | 1728 | struct perf_event *leader = event->group_leader; |
502568d5 | 1729 | struct cpu_hw_events *fake_cpuc; |
cd8a38d3 | 1730 | int ret = -ENOSPC, n; |
fe9081cc | 1731 | |
cd8a38d3 SE |
1732 | fake_cpuc = allocate_fake_cpuc(); |
1733 | if (IS_ERR(fake_cpuc)) | |
1734 | return PTR_ERR(fake_cpuc); | |
1da53e02 SE |
1735 | /* |
1736 | * the event is not yet connected with its | |
1737 | * siblings therefore we must first collect | |
1738 | * existing siblings, then add the new event | |
1739 | * before we can simulate the scheduling | |
1740 | */ | |
502568d5 | 1741 | n = collect_events(fake_cpuc, leader, true); |
1da53e02 | 1742 | if (n < 0) |
cd8a38d3 | 1743 | goto out; |
fe9081cc | 1744 | |
502568d5 PZ |
1745 | fake_cpuc->n_events = n; |
1746 | n = collect_events(fake_cpuc, event, false); | |
1da53e02 | 1747 | if (n < 0) |
cd8a38d3 | 1748 | goto out; |
fe9081cc | 1749 | |
502568d5 | 1750 | fake_cpuc->n_events = n; |
1da53e02 | 1751 | |
a072738e | 1752 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
502568d5 | 1753 | |
502568d5 | 1754 | out: |
cd8a38d3 | 1755 | free_fake_cpuc(fake_cpuc); |
502568d5 | 1756 | return ret; |
fe9081cc PZ |
1757 | } |
1758 | ||
dda99116 | 1759 | static int x86_pmu_event_init(struct perf_event *event) |
621a01ea | 1760 | { |
51b0fe39 | 1761 | struct pmu *tmp; |
621a01ea IM |
1762 | int err; |
1763 | ||
b0a873eb PZ |
1764 | switch (event->attr.type) { |
1765 | case PERF_TYPE_RAW: | |
1766 | case PERF_TYPE_HARDWARE: | |
1767 | case PERF_TYPE_HW_CACHE: | |
1768 | break; | |
1769 | ||
1770 | default: | |
1771 | return -ENOENT; | |
1772 | } | |
1773 | ||
1774 | err = __x86_pmu_event_init(event); | |
fe9081cc | 1775 | if (!err) { |
8113070d SE |
1776 | /* |
1777 | * we temporarily connect event to its pmu | |
1778 | * such that validate_group() can classify | |
1779 | * it as an x86 event using is_x86_event() | |
1780 | */ | |
1781 | tmp = event->pmu; | |
1782 | event->pmu = &pmu; | |
1783 | ||
fe9081cc PZ |
1784 | if (event->group_leader != event) |
1785 | err = validate_group(event); | |
ca037701 PZ |
1786 | else |
1787 | err = validate_event(event); | |
8113070d SE |
1788 | |
1789 | event->pmu = tmp; | |
fe9081cc | 1790 | } |
a1792cda | 1791 | if (err) { |
cdd6c482 IM |
1792 | if (event->destroy) |
1793 | event->destroy(event); | |
a1792cda | 1794 | } |
621a01ea | 1795 | |
b0a873eb | 1796 | return err; |
621a01ea | 1797 | } |
d7d59fb3 | 1798 | |
b0a873eb | 1799 | static struct pmu pmu = { |
a4eaf7f1 PZ |
1800 | .pmu_enable = x86_pmu_enable, |
1801 | .pmu_disable = x86_pmu_disable, | |
1802 | ||
b0a873eb | 1803 | .event_init = x86_pmu_event_init, |
a4eaf7f1 PZ |
1804 | |
1805 | .add = x86_pmu_add, | |
1806 | .del = x86_pmu_del, | |
b0a873eb PZ |
1807 | .start = x86_pmu_start, |
1808 | .stop = x86_pmu_stop, | |
1809 | .read = x86_pmu_read, | |
a4eaf7f1 | 1810 | |
b0a873eb PZ |
1811 | .start_txn = x86_pmu_start_txn, |
1812 | .cancel_txn = x86_pmu_cancel_txn, | |
1813 | .commit_txn = x86_pmu_commit_txn, | |
1814 | }; | |
1815 | ||
d7d59fb3 PZ |
1816 | /* |
1817 | * callchain support | |
1818 | */ | |
1819 | ||
d7d59fb3 PZ |
1820 | static int backtrace_stack(void *data, char *name) |
1821 | { | |
038e836e | 1822 | return 0; |
d7d59fb3 PZ |
1823 | } |
1824 | ||
1825 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1826 | { | |
1827 | struct perf_callchain_entry *entry = data; | |
1828 | ||
70791ce9 | 1829 | perf_callchain_store(entry, addr); |
d7d59fb3 PZ |
1830 | } |
1831 | ||
1832 | static const struct stacktrace_ops backtrace_ops = { | |
d7d59fb3 PZ |
1833 | .stack = backtrace_stack, |
1834 | .address = backtrace_address, | |
06d65bda | 1835 | .walk_stack = print_context_stack_bp, |
d7d59fb3 PZ |
1836 | }; |
1837 | ||
56962b44 FW |
1838 | void |
1839 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 | 1840 | { |
927c7a9e FW |
1841 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1842 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1843 | return; |
927c7a9e FW |
1844 | } |
1845 | ||
70791ce9 | 1846 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1847 | |
e8e999cf | 1848 | dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry); |
d7d59fb3 PZ |
1849 | } |
1850 | ||
257ef9d2 TE |
1851 | #ifdef CONFIG_COMPAT |
1852 | static inline int | |
1853 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
74193ef0 | 1854 | { |
257ef9d2 TE |
1855 | /* 32-bit process in 64-bit kernel. */ |
1856 | struct stack_frame_ia32 frame; | |
1857 | const void __user *fp; | |
74193ef0 | 1858 | |
257ef9d2 TE |
1859 | if (!test_thread_flag(TIF_IA32)) |
1860 | return 0; | |
1861 | ||
1862 | fp = compat_ptr(regs->bp); | |
1863 | while (entry->nr < PERF_MAX_STACK_DEPTH) { | |
1864 | unsigned long bytes; | |
1865 | frame.next_frame = 0; | |
1866 | frame.return_address = 0; | |
1867 | ||
1868 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); | |
1869 | if (bytes != sizeof(frame)) | |
1870 | break; | |
74193ef0 | 1871 | |
257ef9d2 TE |
1872 | if (fp < compat_ptr(regs->sp)) |
1873 | break; | |
74193ef0 | 1874 | |
70791ce9 | 1875 | perf_callchain_store(entry, frame.return_address); |
257ef9d2 TE |
1876 | fp = compat_ptr(frame.next_frame); |
1877 | } | |
1878 | return 1; | |
d7d59fb3 | 1879 | } |
257ef9d2 TE |
1880 | #else |
1881 | static inline int | |
1882 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1883 | { | |
1884 | return 0; | |
1885 | } | |
1886 | #endif | |
d7d59fb3 | 1887 | |
56962b44 FW |
1888 | void |
1889 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 PZ |
1890 | { |
1891 | struct stack_frame frame; | |
1892 | const void __user *fp; | |
1893 | ||
927c7a9e FW |
1894 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1895 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1896 | return; |
927c7a9e | 1897 | } |
5a6cec3a | 1898 | |
74193ef0 | 1899 | fp = (void __user *)regs->bp; |
d7d59fb3 | 1900 | |
70791ce9 | 1901 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1902 | |
257ef9d2 TE |
1903 | if (perf_callchain_user32(regs, entry)) |
1904 | return; | |
1905 | ||
f9188e02 | 1906 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
257ef9d2 | 1907 | unsigned long bytes; |
038e836e | 1908 | frame.next_frame = NULL; |
d7d59fb3 PZ |
1909 | frame.return_address = 0; |
1910 | ||
257ef9d2 TE |
1911 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); |
1912 | if (bytes != sizeof(frame)) | |
d7d59fb3 PZ |
1913 | break; |
1914 | ||
5a6cec3a | 1915 | if ((unsigned long)fp < regs->sp) |
d7d59fb3 PZ |
1916 | break; |
1917 | ||
70791ce9 | 1918 | perf_callchain_store(entry, frame.return_address); |
038e836e | 1919 | fp = frame.next_frame; |
d7d59fb3 PZ |
1920 | } |
1921 | } | |
1922 | ||
39447b38 ZY |
1923 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
1924 | { | |
1925 | unsigned long ip; | |
dcf46b94 | 1926 | |
39447b38 ZY |
1927 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) |
1928 | ip = perf_guest_cbs->get_guest_ip(); | |
1929 | else | |
1930 | ip = instruction_pointer(regs); | |
dcf46b94 | 1931 | |
39447b38 ZY |
1932 | return ip; |
1933 | } | |
1934 | ||
1935 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
1936 | { | |
1937 | int misc = 0; | |
dcf46b94 | 1938 | |
39447b38 | 1939 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
dcf46b94 ZY |
1940 | if (perf_guest_cbs->is_user_mode()) |
1941 | misc |= PERF_RECORD_MISC_GUEST_USER; | |
1942 | else | |
1943 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
1944 | } else { | |
1945 | if (user_mode(regs)) | |
1946 | misc |= PERF_RECORD_MISC_USER; | |
1947 | else | |
1948 | misc |= PERF_RECORD_MISC_KERNEL; | |
1949 | } | |
1950 | ||
39447b38 | 1951 | if (regs->flags & PERF_EFLAGS_EXACT) |
ab608344 | 1952 | misc |= PERF_RECORD_MISC_EXACT_IP; |
39447b38 ZY |
1953 | |
1954 | return misc; | |
1955 | } |