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Commit | Line | Data |
---|---|---|
241771ef | 1 | /* |
cdd6c482 | 2 | * Performance events x86 architecture code |
241771ef | 3 | * |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
1da53e02 | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
241771ef IM |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
241771ef IM |
16 | #include <linux/capability.h> |
17 | #include <linux/notifier.h> | |
18 | #include <linux/hardirq.h> | |
19 | #include <linux/kprobes.h> | |
4ac13294 | 20 | #include <linux/module.h> |
241771ef IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/sched.h> | |
d7d59fb3 | 23 | #include <linux/uaccess.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
74193ef0 | 25 | #include <linux/highmem.h> |
30dd568c | 26 | #include <linux/cpu.h> |
272d30be | 27 | #include <linux/bitops.h> |
241771ef | 28 | |
241771ef | 29 | #include <asm/apic.h> |
d7d59fb3 | 30 | #include <asm/stacktrace.h> |
4e935e47 | 31 | #include <asm/nmi.h> |
257ef9d2 | 32 | #include <asm/compat.h> |
69092624 | 33 | #include <asm/smp.h> |
241771ef | 34 | |
7645a24c PZ |
35 | #if 0 |
36 | #undef wrmsrl | |
37 | #define wrmsrl(msr, val) \ | |
38 | do { \ | |
39 | trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\ | |
40 | (unsigned long)(val)); \ | |
41 | native_write_msr((msr), (u32)((u64)(val)), \ | |
42 | (u32)((u64)(val) >> 32)); \ | |
43 | } while (0) | |
44 | #endif | |
45 | ||
ef21f683 PZ |
46 | /* |
47 | * best effort, GUP based copy_from_user() that assumes IRQ or NMI context | |
48 | */ | |
49 | static unsigned long | |
50 | copy_from_user_nmi(void *to, const void __user *from, unsigned long n) | |
51 | { | |
52 | unsigned long offset, addr = (unsigned long)from; | |
ef21f683 PZ |
53 | unsigned long size, len = 0; |
54 | struct page *page; | |
55 | void *map; | |
56 | int ret; | |
57 | ||
58 | do { | |
59 | ret = __get_user_pages_fast(addr, 1, 0, &page); | |
60 | if (!ret) | |
61 | break; | |
62 | ||
63 | offset = addr & (PAGE_SIZE - 1); | |
64 | size = min(PAGE_SIZE - offset, n - len); | |
65 | ||
7a837d1b | 66 | map = kmap_atomic(page); |
ef21f683 | 67 | memcpy(to, map+offset, size); |
7a837d1b | 68 | kunmap_atomic(map); |
ef21f683 PZ |
69 | put_page(page); |
70 | ||
71 | len += size; | |
72 | to += size; | |
73 | addr += size; | |
74 | ||
75 | } while (len < n); | |
76 | ||
77 | return len; | |
78 | } | |
79 | ||
1da53e02 | 80 | struct event_constraint { |
c91e0f5d PZ |
81 | union { |
82 | unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
b622d644 | 83 | u64 idxmsk64; |
c91e0f5d | 84 | }; |
b622d644 PZ |
85 | u64 code; |
86 | u64 cmask; | |
272d30be | 87 | int weight; |
1da53e02 SE |
88 | }; |
89 | ||
38331f62 SE |
90 | struct amd_nb { |
91 | int nb_id; /* NorthBridge id */ | |
92 | int refcnt; /* reference count */ | |
93 | struct perf_event *owners[X86_PMC_IDX_MAX]; | |
94 | struct event_constraint event_constraints[X86_PMC_IDX_MAX]; | |
95 | }; | |
96 | ||
a7e3ed1e AK |
97 | struct intel_percore; |
98 | ||
caff2bef PZ |
99 | #define MAX_LBR_ENTRIES 16 |
100 | ||
cdd6c482 | 101 | struct cpu_hw_events { |
ca037701 PZ |
102 | /* |
103 | * Generic x86 PMC bits | |
104 | */ | |
1da53e02 | 105 | struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ |
43f6201a | 106 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
63e6be6d | 107 | unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
b0f3f28e | 108 | int enabled; |
241771ef | 109 | |
1da53e02 SE |
110 | int n_events; |
111 | int n_added; | |
90151c35 | 112 | int n_txn; |
1da53e02 | 113 | int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ |
447a194b | 114 | u64 tags[X86_PMC_IDX_MAX]; |
1da53e02 | 115 | struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ |
ca037701 | 116 | |
4d1c52b0 LM |
117 | unsigned int group_flag; |
118 | ||
ca037701 PZ |
119 | /* |
120 | * Intel DebugStore bits | |
121 | */ | |
122 | struct debug_store *ds; | |
123 | u64 pebs_enabled; | |
124 | ||
caff2bef PZ |
125 | /* |
126 | * Intel LBR bits | |
127 | */ | |
128 | int lbr_users; | |
129 | void *lbr_context; | |
130 | struct perf_branch_stack lbr_stack; | |
131 | struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; | |
132 | ||
a7e3ed1e AK |
133 | /* |
134 | * Intel percore register state. | |
135 | * Coordinate shared resources between HT threads. | |
136 | */ | |
137 | int percore_used; /* Used by this CPU? */ | |
138 | struct intel_percore *per_core; | |
139 | ||
ca037701 PZ |
140 | /* |
141 | * AMD specific bits | |
142 | */ | |
38331f62 | 143 | struct amd_nb *amd_nb; |
b690081d SE |
144 | }; |
145 | ||
fce877e3 | 146 | #define __EVENT_CONSTRAINT(c, n, m, w) {\ |
b622d644 | 147 | { .idxmsk64 = (n) }, \ |
c91e0f5d PZ |
148 | .code = (c), \ |
149 | .cmask = (m), \ | |
fce877e3 | 150 | .weight = (w), \ |
c91e0f5d | 151 | } |
b690081d | 152 | |
fce877e3 PZ |
153 | #define EVENT_CONSTRAINT(c, n, m) \ |
154 | __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n)) | |
155 | ||
ca037701 PZ |
156 | /* |
157 | * Constraint on the Event code. | |
158 | */ | |
ed8777fc | 159 | #define INTEL_EVENT_CONSTRAINT(c, n) \ |
a098f448 | 160 | EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT) |
8433be11 | 161 | |
ca037701 PZ |
162 | /* |
163 | * Constraint on the Event code + UMask + fixed-mask | |
a098f448 RR |
164 | * |
165 | * filter mask to validate fixed counter events. | |
166 | * the following filters disqualify for fixed counters: | |
167 | * - inv | |
168 | * - edge | |
169 | * - cnt-mask | |
170 | * The other filters are supported by fixed counters. | |
171 | * The any-thread option is supported starting with v3. | |
ca037701 | 172 | */ |
ed8777fc | 173 | #define FIXED_EVENT_CONSTRAINT(c, n) \ |
a098f448 | 174 | EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK) |
8433be11 | 175 | |
ca037701 PZ |
176 | /* |
177 | * Constraint on the Event code + UMask | |
178 | */ | |
b06b3d49 | 179 | #define INTEL_UEVENT_CONSTRAINT(c, n) \ |
ca037701 PZ |
180 | EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK) |
181 | ||
ed8777fc PZ |
182 | #define EVENT_CONSTRAINT_END \ |
183 | EVENT_CONSTRAINT(0, 0, 0) | |
184 | ||
185 | #define for_each_event_constraint(e, c) \ | |
a1f2b70a | 186 | for ((e) = (c); (e)->weight; (e)++) |
b690081d | 187 | |
a7e3ed1e AK |
188 | /* |
189 | * Extra registers for specific events. | |
190 | * Some events need large masks and require external MSRs. | |
191 | * Define a mapping to these extra registers. | |
192 | */ | |
193 | struct extra_reg { | |
194 | unsigned int event; | |
195 | unsigned int msr; | |
196 | u64 config_mask; | |
197 | u64 valid_mask; | |
198 | }; | |
199 | ||
200 | #define EVENT_EXTRA_REG(e, ms, m, vm) { \ | |
201 | .event = (e), \ | |
202 | .msr = (ms), \ | |
203 | .config_mask = (m), \ | |
204 | .valid_mask = (vm), \ | |
205 | } | |
206 | #define INTEL_EVENT_EXTRA_REG(event, msr, vm) \ | |
207 | EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm) | |
208 | #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0) | |
209 | ||
8db909a7 PZ |
210 | union perf_capabilities { |
211 | struct { | |
212 | u64 lbr_format : 6; | |
213 | u64 pebs_trap : 1; | |
214 | u64 pebs_arch_reg : 1; | |
215 | u64 pebs_format : 4; | |
216 | u64 smm_freeze : 1; | |
217 | }; | |
218 | u64 capabilities; | |
219 | }; | |
220 | ||
241771ef | 221 | /* |
5f4ec28f | 222 | * struct x86_pmu - generic x86 pmu |
241771ef | 223 | */ |
5f4ec28f | 224 | struct x86_pmu { |
ca037701 PZ |
225 | /* |
226 | * Generic x86 PMC bits | |
227 | */ | |
faa28ae0 RR |
228 | const char *name; |
229 | int version; | |
a3288106 | 230 | int (*handle_irq)(struct pt_regs *); |
9e35ad38 | 231 | void (*disable_all)(void); |
11164cd4 | 232 | void (*enable_all)(int added); |
aff3d91a PZ |
233 | void (*enable)(struct perf_event *); |
234 | void (*disable)(struct perf_event *); | |
b4cdc5c2 | 235 | int (*hw_config)(struct perf_event *event); |
a072738e | 236 | int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign); |
169e41eb JSR |
237 | unsigned eventsel; |
238 | unsigned perfctr; | |
b0f3f28e | 239 | u64 (*event_map)(int); |
169e41eb | 240 | int max_events; |
948b1bb8 RR |
241 | int num_counters; |
242 | int num_counters_fixed; | |
243 | int cntval_bits; | |
244 | u64 cntval_mask; | |
04da8a43 | 245 | int apic; |
c619b8ff | 246 | u64 max_period; |
63b14649 PZ |
247 | struct event_constraint * |
248 | (*get_event_constraints)(struct cpu_hw_events *cpuc, | |
249 | struct perf_event *event); | |
250 | ||
c91e0f5d PZ |
251 | void (*put_event_constraints)(struct cpu_hw_events *cpuc, |
252 | struct perf_event *event); | |
63b14649 | 253 | struct event_constraint *event_constraints; |
a7e3ed1e | 254 | struct event_constraint *percore_constraints; |
3c44780b | 255 | void (*quirks)(void); |
68aa00ac | 256 | int perfctr_second_write; |
3f6da390 | 257 | |
b38b24ea | 258 | int (*cpu_prepare)(int cpu); |
3f6da390 PZ |
259 | void (*cpu_starting)(int cpu); |
260 | void (*cpu_dying)(int cpu); | |
261 | void (*cpu_dead)(int cpu); | |
ca037701 PZ |
262 | |
263 | /* | |
264 | * Intel Arch Perfmon v2+ | |
265 | */ | |
8db909a7 PZ |
266 | u64 intel_ctrl; |
267 | union perf_capabilities intel_cap; | |
ca037701 PZ |
268 | |
269 | /* | |
270 | * Intel DebugStore bits | |
271 | */ | |
272 | int bts, pebs; | |
6809b6ea | 273 | int bts_active, pebs_active; |
ca037701 PZ |
274 | int pebs_record_size; |
275 | void (*drain_pebs)(struct pt_regs *regs); | |
276 | struct event_constraint *pebs_constraints; | |
caff2bef PZ |
277 | |
278 | /* | |
279 | * Intel LBR | |
280 | */ | |
281 | unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */ | |
282 | int lbr_nr; /* hardware stack size */ | |
a7e3ed1e AK |
283 | |
284 | /* | |
285 | * Extra registers for events | |
286 | */ | |
287 | struct extra_reg *extra_regs; | |
b56a3802 JSR |
288 | }; |
289 | ||
4a06bd85 | 290 | static struct x86_pmu x86_pmu __read_mostly; |
b56a3802 | 291 | |
cdd6c482 | 292 | static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
b0f3f28e PZ |
293 | .enabled = 1, |
294 | }; | |
241771ef | 295 | |
07088edb | 296 | static int x86_perf_event_set_period(struct perf_event *event); |
b690081d | 297 | |
8326f44d | 298 | /* |
dfc65094 | 299 | * Generalized hw caching related hw_event table, filled |
8326f44d | 300 | * in on a per model basis. A value of 0 means |
dfc65094 IM |
301 | * 'not supported', -1 means 'hw_event makes no sense on |
302 | * this CPU', any other value means the raw hw_event | |
8326f44d IM |
303 | * ID. |
304 | */ | |
305 | ||
306 | #define C(x) PERF_COUNT_HW_CACHE_##x | |
307 | ||
308 | static u64 __read_mostly hw_cache_event_ids | |
309 | [PERF_COUNT_HW_CACHE_MAX] | |
310 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
311 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
e994d7d2 AK |
312 | static u64 __read_mostly hw_cache_extra_regs |
313 | [PERF_COUNT_HW_CACHE_MAX] | |
314 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
315 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
8326f44d | 316 | |
ee06094f | 317 | /* |
cdd6c482 IM |
318 | * Propagate event elapsed time into the generic event. |
319 | * Can only be executed on the CPU where the event is active. | |
ee06094f IM |
320 | * Returns the delta events processed. |
321 | */ | |
4b7bfd0d | 322 | static u64 |
cc2ad4ba | 323 | x86_perf_event_update(struct perf_event *event) |
ee06094f | 324 | { |
cc2ad4ba | 325 | struct hw_perf_event *hwc = &event->hw; |
948b1bb8 | 326 | int shift = 64 - x86_pmu.cntval_bits; |
ec3232bd | 327 | u64 prev_raw_count, new_raw_count; |
cc2ad4ba | 328 | int idx = hwc->idx; |
ec3232bd | 329 | s64 delta; |
ee06094f | 330 | |
30dd568c MM |
331 | if (idx == X86_PMC_IDX_FIXED_BTS) |
332 | return 0; | |
333 | ||
ee06094f | 334 | /* |
cdd6c482 | 335 | * Careful: an NMI might modify the previous event value. |
ee06094f IM |
336 | * |
337 | * Our tactic to handle this is to first atomically read and | |
338 | * exchange a new raw count - then add that new-prev delta | |
cdd6c482 | 339 | * count to the generic event atomically: |
ee06094f IM |
340 | */ |
341 | again: | |
e7850595 | 342 | prev_raw_count = local64_read(&hwc->prev_count); |
73d6e522 | 343 | rdmsrl(hwc->event_base, new_raw_count); |
ee06094f | 344 | |
e7850595 | 345 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
ee06094f IM |
346 | new_raw_count) != prev_raw_count) |
347 | goto again; | |
348 | ||
349 | /* | |
350 | * Now we have the new raw value and have updated the prev | |
351 | * timestamp already. We can now calculate the elapsed delta | |
cdd6c482 | 352 | * (event-)time and add that to the generic event. |
ee06094f IM |
353 | * |
354 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 355 | * of the count. |
ee06094f | 356 | */ |
ec3232bd PZ |
357 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
358 | delta >>= shift; | |
ee06094f | 359 | |
e7850595 PZ |
360 | local64_add(delta, &event->count); |
361 | local64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
362 | |
363 | return new_raw_count; | |
ee06094f IM |
364 | } |
365 | ||
4979d272 RR |
366 | /* using X86_FEATURE_PERFCTR_CORE to later implement ALTERNATIVE() here */ |
367 | static inline int x86_pmu_addr_offset(int index) | |
368 | { | |
369 | if (boot_cpu_has(X86_FEATURE_PERFCTR_CORE)) | |
370 | return index << 1; | |
371 | return index; | |
372 | } | |
373 | ||
41bf4989 RR |
374 | static inline unsigned int x86_pmu_config_addr(int index) |
375 | { | |
4979d272 | 376 | return x86_pmu.eventsel + x86_pmu_addr_offset(index); |
41bf4989 RR |
377 | } |
378 | ||
379 | static inline unsigned int x86_pmu_event_addr(int index) | |
380 | { | |
4979d272 | 381 | return x86_pmu.perfctr + x86_pmu_addr_offset(index); |
41bf4989 RR |
382 | } |
383 | ||
a7e3ed1e AK |
384 | /* |
385 | * Find and validate any extra registers to set up. | |
386 | */ | |
387 | static int x86_pmu_extra_regs(u64 config, struct perf_event *event) | |
388 | { | |
389 | struct extra_reg *er; | |
390 | ||
391 | event->hw.extra_reg = 0; | |
392 | event->hw.extra_config = 0; | |
393 | ||
394 | if (!x86_pmu.extra_regs) | |
395 | return 0; | |
396 | ||
397 | for (er = x86_pmu.extra_regs; er->msr; er++) { | |
398 | if (er->event != (config & er->config_mask)) | |
399 | continue; | |
400 | if (event->attr.config1 & ~er->valid_mask) | |
401 | return -EINVAL; | |
402 | event->hw.extra_reg = er->msr; | |
403 | event->hw.extra_config = event->attr.config1; | |
404 | break; | |
405 | } | |
406 | return 0; | |
407 | } | |
408 | ||
cdd6c482 | 409 | static atomic_t active_events; |
4e935e47 PZ |
410 | static DEFINE_MUTEX(pmc_reserve_mutex); |
411 | ||
b27ea29c RR |
412 | #ifdef CONFIG_X86_LOCAL_APIC |
413 | ||
4e935e47 PZ |
414 | static bool reserve_pmc_hardware(void) |
415 | { | |
416 | int i; | |
417 | ||
948b1bb8 | 418 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 419 | if (!reserve_perfctr_nmi(x86_pmu_event_addr(i))) |
4e935e47 PZ |
420 | goto perfctr_fail; |
421 | } | |
422 | ||
948b1bb8 | 423 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 424 | if (!reserve_evntsel_nmi(x86_pmu_config_addr(i))) |
4e935e47 PZ |
425 | goto eventsel_fail; |
426 | } | |
427 | ||
428 | return true; | |
429 | ||
430 | eventsel_fail: | |
431 | for (i--; i >= 0; i--) | |
41bf4989 | 432 | release_evntsel_nmi(x86_pmu_config_addr(i)); |
4e935e47 | 433 | |
948b1bb8 | 434 | i = x86_pmu.num_counters; |
4e935e47 PZ |
435 | |
436 | perfctr_fail: | |
437 | for (i--; i >= 0; i--) | |
41bf4989 | 438 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
4e935e47 | 439 | |
4e935e47 PZ |
440 | return false; |
441 | } | |
442 | ||
443 | static void release_pmc_hardware(void) | |
444 | { | |
445 | int i; | |
446 | ||
948b1bb8 | 447 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 RR |
448 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
449 | release_evntsel_nmi(x86_pmu_config_addr(i)); | |
4e935e47 | 450 | } |
4e935e47 PZ |
451 | } |
452 | ||
b27ea29c RR |
453 | #else |
454 | ||
455 | static bool reserve_pmc_hardware(void) { return true; } | |
456 | static void release_pmc_hardware(void) {} | |
457 | ||
458 | #endif | |
459 | ||
33c6d6a7 DZ |
460 | static bool check_hw_exists(void) |
461 | { | |
462 | u64 val, val_new = 0; | |
4407204c | 463 | int i, reg, ret = 0; |
33c6d6a7 | 464 | |
4407204c PZ |
465 | /* |
466 | * Check to see if the BIOS enabled any of the counters, if so | |
467 | * complain and bail. | |
468 | */ | |
469 | for (i = 0; i < x86_pmu.num_counters; i++) { | |
41bf4989 | 470 | reg = x86_pmu_config_addr(i); |
4407204c PZ |
471 | ret = rdmsrl_safe(reg, &val); |
472 | if (ret) | |
473 | goto msr_fail; | |
474 | if (val & ARCH_PERFMON_EVENTSEL_ENABLE) | |
475 | goto bios_fail; | |
476 | } | |
477 | ||
478 | if (x86_pmu.num_counters_fixed) { | |
479 | reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
480 | ret = rdmsrl_safe(reg, &val); | |
481 | if (ret) | |
482 | goto msr_fail; | |
483 | for (i = 0; i < x86_pmu.num_counters_fixed; i++) { | |
484 | if (val & (0x03 << i*4)) | |
485 | goto bios_fail; | |
486 | } | |
487 | } | |
488 | ||
489 | /* | |
490 | * Now write a value and read it back to see if it matches, | |
491 | * this is needed to detect certain hardware emulators (qemu/kvm) | |
492 | * that don't trap on the MSR access and always return 0s. | |
493 | */ | |
33c6d6a7 | 494 | val = 0xabcdUL; |
41bf4989 RR |
495 | ret = checking_wrmsrl(x86_pmu_event_addr(0), val); |
496 | ret |= rdmsrl_safe(x86_pmu_event_addr(0), &val_new); | |
33c6d6a7 | 497 | if (ret || val != val_new) |
4407204c | 498 | goto msr_fail; |
33c6d6a7 DZ |
499 | |
500 | return true; | |
4407204c PZ |
501 | |
502 | bios_fail: | |
45daae57 IM |
503 | /* |
504 | * We still allow the PMU driver to operate: | |
505 | */ | |
506 | printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n"); | |
4407204c | 507 | printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg, val); |
45daae57 IM |
508 | |
509 | return true; | |
4407204c PZ |
510 | |
511 | msr_fail: | |
512 | printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n"); | |
45daae57 | 513 | |
4407204c | 514 | return false; |
33c6d6a7 DZ |
515 | } |
516 | ||
f80c9e30 | 517 | static void reserve_ds_buffers(void); |
ca037701 | 518 | static void release_ds_buffers(void); |
30dd568c | 519 | |
cdd6c482 | 520 | static void hw_perf_event_destroy(struct perf_event *event) |
4e935e47 | 521 | { |
cdd6c482 | 522 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) { |
4e935e47 | 523 | release_pmc_hardware(); |
ca037701 | 524 | release_ds_buffers(); |
4e935e47 PZ |
525 | mutex_unlock(&pmc_reserve_mutex); |
526 | } | |
527 | } | |
528 | ||
85cf9dba RR |
529 | static inline int x86_pmu_initialized(void) |
530 | { | |
531 | return x86_pmu.handle_irq != NULL; | |
532 | } | |
533 | ||
8326f44d | 534 | static inline int |
e994d7d2 | 535 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) |
8326f44d | 536 | { |
e994d7d2 | 537 | struct perf_event_attr *attr = &event->attr; |
8326f44d IM |
538 | unsigned int cache_type, cache_op, cache_result; |
539 | u64 config, val; | |
540 | ||
541 | config = attr->config; | |
542 | ||
543 | cache_type = (config >> 0) & 0xff; | |
544 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
545 | return -EINVAL; | |
546 | ||
547 | cache_op = (config >> 8) & 0xff; | |
548 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
549 | return -EINVAL; | |
550 | ||
551 | cache_result = (config >> 16) & 0xff; | |
552 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
553 | return -EINVAL; | |
554 | ||
555 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
556 | ||
557 | if (val == 0) | |
558 | return -ENOENT; | |
559 | ||
560 | if (val == -1) | |
561 | return -EINVAL; | |
562 | ||
563 | hwc->config |= val; | |
e994d7d2 AK |
564 | attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result]; |
565 | return x86_pmu_extra_regs(val, event); | |
8326f44d IM |
566 | } |
567 | ||
c1726f34 RR |
568 | static int x86_setup_perfctr(struct perf_event *event) |
569 | { | |
570 | struct perf_event_attr *attr = &event->attr; | |
571 | struct hw_perf_event *hwc = &event->hw; | |
572 | u64 config; | |
573 | ||
6c7e550f | 574 | if (!is_sampling_event(event)) { |
c1726f34 RR |
575 | hwc->sample_period = x86_pmu.max_period; |
576 | hwc->last_period = hwc->sample_period; | |
e7850595 | 577 | local64_set(&hwc->period_left, hwc->sample_period); |
c1726f34 RR |
578 | } else { |
579 | /* | |
580 | * If we have a PMU initialized but no APIC | |
581 | * interrupts, we cannot sample hardware | |
582 | * events (user-space has to fall back and | |
583 | * sample via a hrtimer based software event): | |
584 | */ | |
585 | if (!x86_pmu.apic) | |
586 | return -EOPNOTSUPP; | |
587 | } | |
588 | ||
b52c55c6 IM |
589 | /* |
590 | * Do not allow config1 (extended registers) to propagate, | |
591 | * there's no sane user-space generalization yet: | |
592 | */ | |
c1726f34 | 593 | if (attr->type == PERF_TYPE_RAW) |
b52c55c6 | 594 | return 0; |
c1726f34 RR |
595 | |
596 | if (attr->type == PERF_TYPE_HW_CACHE) | |
e994d7d2 | 597 | return set_ext_hw_attr(hwc, event); |
c1726f34 RR |
598 | |
599 | if (attr->config >= x86_pmu.max_events) | |
600 | return -EINVAL; | |
601 | ||
602 | /* | |
603 | * The generic map: | |
604 | */ | |
605 | config = x86_pmu.event_map(attr->config); | |
606 | ||
607 | if (config == 0) | |
608 | return -ENOENT; | |
609 | ||
610 | if (config == -1LL) | |
611 | return -EINVAL; | |
612 | ||
613 | /* | |
614 | * Branch tracing: | |
615 | */ | |
616 | if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) && | |
617 | (hwc->sample_period == 1)) { | |
618 | /* BTS is not supported by this architecture. */ | |
6809b6ea | 619 | if (!x86_pmu.bts_active) |
c1726f34 RR |
620 | return -EOPNOTSUPP; |
621 | ||
622 | /* BTS is currently only allowed for user-mode. */ | |
623 | if (!attr->exclude_kernel) | |
624 | return -EOPNOTSUPP; | |
625 | } | |
626 | ||
627 | hwc->config |= config; | |
628 | ||
629 | return 0; | |
630 | } | |
4261e0e0 | 631 | |
b4cdc5c2 | 632 | static int x86_pmu_hw_config(struct perf_event *event) |
a072738e | 633 | { |
ab608344 PZ |
634 | if (event->attr.precise_ip) { |
635 | int precise = 0; | |
636 | ||
637 | /* Support for constant skid */ | |
6809b6ea | 638 | if (x86_pmu.pebs_active) { |
ab608344 PZ |
639 | precise++; |
640 | ||
5553be26 PZ |
641 | /* Support for IP fixup */ |
642 | if (x86_pmu.lbr_nr) | |
643 | precise++; | |
644 | } | |
ab608344 PZ |
645 | |
646 | if (event->attr.precise_ip > precise) | |
647 | return -EOPNOTSUPP; | |
648 | } | |
649 | ||
a072738e CG |
650 | /* |
651 | * Generate PMC IRQs: | |
652 | * (keep 'enabled' bit clear for now) | |
653 | */ | |
b4cdc5c2 | 654 | event->hw.config = ARCH_PERFMON_EVENTSEL_INT; |
a072738e CG |
655 | |
656 | /* | |
657 | * Count user and OS events unless requested not to | |
658 | */ | |
b4cdc5c2 PZ |
659 | if (!event->attr.exclude_user) |
660 | event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; | |
661 | if (!event->attr.exclude_kernel) | |
662 | event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; | |
a072738e | 663 | |
b4cdc5c2 PZ |
664 | if (event->attr.type == PERF_TYPE_RAW) |
665 | event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; | |
a072738e | 666 | |
9d0fcba6 | 667 | return x86_setup_perfctr(event); |
a098f448 RR |
668 | } |
669 | ||
241771ef | 670 | /* |
0d48696f | 671 | * Setup the hardware configuration for a given attr_type |
241771ef | 672 | */ |
b0a873eb | 673 | static int __x86_pmu_event_init(struct perf_event *event) |
241771ef | 674 | { |
4e935e47 | 675 | int err; |
241771ef | 676 | |
85cf9dba RR |
677 | if (!x86_pmu_initialized()) |
678 | return -ENODEV; | |
241771ef | 679 | |
4e935e47 | 680 | err = 0; |
cdd6c482 | 681 | if (!atomic_inc_not_zero(&active_events)) { |
4e935e47 | 682 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 683 | if (atomic_read(&active_events) == 0) { |
30dd568c MM |
684 | if (!reserve_pmc_hardware()) |
685 | err = -EBUSY; | |
f80c9e30 PZ |
686 | else |
687 | reserve_ds_buffers(); | |
30dd568c MM |
688 | } |
689 | if (!err) | |
cdd6c482 | 690 | atomic_inc(&active_events); |
4e935e47 PZ |
691 | mutex_unlock(&pmc_reserve_mutex); |
692 | } | |
693 | if (err) | |
694 | return err; | |
695 | ||
cdd6c482 | 696 | event->destroy = hw_perf_event_destroy; |
a1792cda | 697 | |
4261e0e0 RR |
698 | event->hw.idx = -1; |
699 | event->hw.last_cpu = -1; | |
700 | event->hw.last_tag = ~0ULL; | |
b690081d | 701 | |
9d0fcba6 | 702 | return x86_pmu.hw_config(event); |
4261e0e0 RR |
703 | } |
704 | ||
8c48e444 | 705 | static void x86_pmu_disable_all(void) |
f87ad35d | 706 | { |
cdd6c482 | 707 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
9e35ad38 PZ |
708 | int idx; |
709 | ||
948b1bb8 | 710 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
711 | u64 val; |
712 | ||
43f6201a | 713 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 714 | continue; |
41bf4989 | 715 | rdmsrl(x86_pmu_config_addr(idx), val); |
bb1165d6 | 716 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
4295ee62 | 717 | continue; |
bb1165d6 | 718 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
41bf4989 | 719 | wrmsrl(x86_pmu_config_addr(idx), val); |
f87ad35d | 720 | } |
f87ad35d JSR |
721 | } |
722 | ||
a4eaf7f1 | 723 | static void x86_pmu_disable(struct pmu *pmu) |
b56a3802 | 724 | { |
1da53e02 SE |
725 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
726 | ||
85cf9dba | 727 | if (!x86_pmu_initialized()) |
9e35ad38 | 728 | return; |
1da53e02 | 729 | |
1a6e21f7 PZ |
730 | if (!cpuc->enabled) |
731 | return; | |
732 | ||
733 | cpuc->n_added = 0; | |
734 | cpuc->enabled = 0; | |
735 | barrier(); | |
1da53e02 SE |
736 | |
737 | x86_pmu.disable_all(); | |
b56a3802 | 738 | } |
241771ef | 739 | |
d45dd923 RR |
740 | static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, |
741 | u64 enable_mask) | |
742 | { | |
a7e3ed1e AK |
743 | if (hwc->extra_reg) |
744 | wrmsrl(hwc->extra_reg, hwc->extra_config); | |
73d6e522 | 745 | wrmsrl(hwc->config_base, hwc->config | enable_mask); |
d45dd923 RR |
746 | } |
747 | ||
11164cd4 | 748 | static void x86_pmu_enable_all(int added) |
f87ad35d | 749 | { |
cdd6c482 | 750 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
f87ad35d JSR |
751 | int idx; |
752 | ||
948b1bb8 | 753 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
d45dd923 | 754 | struct hw_perf_event *hwc = &cpuc->events[idx]->hw; |
b0f3f28e | 755 | |
43f6201a | 756 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 757 | continue; |
984b838c | 758 | |
d45dd923 | 759 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); |
f87ad35d JSR |
760 | } |
761 | } | |
762 | ||
51b0fe39 | 763 | static struct pmu pmu; |
1da53e02 SE |
764 | |
765 | static inline int is_x86_event(struct perf_event *event) | |
766 | { | |
767 | return event->pmu == &pmu; | |
768 | } | |
769 | ||
770 | static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) | |
771 | { | |
63b14649 | 772 | struct event_constraint *c, *constraints[X86_PMC_IDX_MAX]; |
1da53e02 | 773 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
c933c1a6 | 774 | int i, j, w, wmax, num = 0; |
1da53e02 SE |
775 | struct hw_perf_event *hwc; |
776 | ||
777 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
778 | ||
779 | for (i = 0; i < n; i++) { | |
b622d644 PZ |
780 | c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]); |
781 | constraints[i] = c; | |
1da53e02 SE |
782 | } |
783 | ||
8113070d SE |
784 | /* |
785 | * fastpath, try to reuse previous register | |
786 | */ | |
c933c1a6 | 787 | for (i = 0; i < n; i++) { |
8113070d | 788 | hwc = &cpuc->event_list[i]->hw; |
81269a08 | 789 | c = constraints[i]; |
8113070d SE |
790 | |
791 | /* never assigned */ | |
792 | if (hwc->idx == -1) | |
793 | break; | |
794 | ||
795 | /* constraint still honored */ | |
63b14649 | 796 | if (!test_bit(hwc->idx, c->idxmsk)) |
8113070d SE |
797 | break; |
798 | ||
799 | /* not already used */ | |
800 | if (test_bit(hwc->idx, used_mask)) | |
801 | break; | |
802 | ||
34538ee7 | 803 | __set_bit(hwc->idx, used_mask); |
8113070d SE |
804 | if (assign) |
805 | assign[i] = hwc->idx; | |
806 | } | |
c933c1a6 | 807 | if (i == n) |
8113070d SE |
808 | goto done; |
809 | ||
810 | /* | |
811 | * begin slow path | |
812 | */ | |
813 | ||
814 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
815 | ||
1da53e02 SE |
816 | /* |
817 | * weight = number of possible counters | |
818 | * | |
819 | * 1 = most constrained, only works on one counter | |
820 | * wmax = least constrained, works on any counter | |
821 | * | |
822 | * assign events to counters starting with most | |
823 | * constrained events. | |
824 | */ | |
948b1bb8 | 825 | wmax = x86_pmu.num_counters; |
1da53e02 SE |
826 | |
827 | /* | |
828 | * when fixed event counters are present, | |
829 | * wmax is incremented by 1 to account | |
830 | * for one more choice | |
831 | */ | |
948b1bb8 | 832 | if (x86_pmu.num_counters_fixed) |
1da53e02 SE |
833 | wmax++; |
834 | ||
8113070d | 835 | for (w = 1, num = n; num && w <= wmax; w++) { |
1da53e02 | 836 | /* for each event */ |
8113070d | 837 | for (i = 0; num && i < n; i++) { |
81269a08 | 838 | c = constraints[i]; |
1da53e02 SE |
839 | hwc = &cpuc->event_list[i]->hw; |
840 | ||
272d30be | 841 | if (c->weight != w) |
1da53e02 SE |
842 | continue; |
843 | ||
984b3f57 | 844 | for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) { |
1da53e02 SE |
845 | if (!test_bit(j, used_mask)) |
846 | break; | |
847 | } | |
848 | ||
849 | if (j == X86_PMC_IDX_MAX) | |
850 | break; | |
1da53e02 | 851 | |
34538ee7 | 852 | __set_bit(j, used_mask); |
8113070d | 853 | |
1da53e02 SE |
854 | if (assign) |
855 | assign[i] = j; | |
856 | num--; | |
857 | } | |
858 | } | |
8113070d | 859 | done: |
1da53e02 SE |
860 | /* |
861 | * scheduling failed or is just a simulation, | |
862 | * free resources if necessary | |
863 | */ | |
864 | if (!assign || num) { | |
865 | for (i = 0; i < n; i++) { | |
866 | if (x86_pmu.put_event_constraints) | |
867 | x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]); | |
868 | } | |
869 | } | |
870 | return num ? -ENOSPC : 0; | |
871 | } | |
872 | ||
873 | /* | |
874 | * dogrp: true if must collect siblings events (group) | |
875 | * returns total number of events and error code | |
876 | */ | |
877 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) | |
878 | { | |
879 | struct perf_event *event; | |
880 | int n, max_count; | |
881 | ||
948b1bb8 | 882 | max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; |
1da53e02 SE |
883 | |
884 | /* current number of events already accepted */ | |
885 | n = cpuc->n_events; | |
886 | ||
887 | if (is_x86_event(leader)) { | |
888 | if (n >= max_count) | |
889 | return -ENOSPC; | |
890 | cpuc->event_list[n] = leader; | |
891 | n++; | |
892 | } | |
893 | if (!dogrp) | |
894 | return n; | |
895 | ||
896 | list_for_each_entry(event, &leader->sibling_list, group_entry) { | |
897 | if (!is_x86_event(event) || | |
8113070d | 898 | event->state <= PERF_EVENT_STATE_OFF) |
1da53e02 SE |
899 | continue; |
900 | ||
901 | if (n >= max_count) | |
902 | return -ENOSPC; | |
903 | ||
904 | cpuc->event_list[n] = event; | |
905 | n++; | |
906 | } | |
907 | return n; | |
908 | } | |
909 | ||
1da53e02 | 910 | static inline void x86_assign_hw_event(struct perf_event *event, |
447a194b | 911 | struct cpu_hw_events *cpuc, int i) |
1da53e02 | 912 | { |
447a194b SE |
913 | struct hw_perf_event *hwc = &event->hw; |
914 | ||
915 | hwc->idx = cpuc->assign[i]; | |
916 | hwc->last_cpu = smp_processor_id(); | |
917 | hwc->last_tag = ++cpuc->tags[i]; | |
1da53e02 SE |
918 | |
919 | if (hwc->idx == X86_PMC_IDX_FIXED_BTS) { | |
920 | hwc->config_base = 0; | |
921 | hwc->event_base = 0; | |
922 | } else if (hwc->idx >= X86_PMC_IDX_FIXED) { | |
923 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
fc66c521 | 924 | hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - X86_PMC_IDX_FIXED); |
1da53e02 | 925 | } else { |
73d6e522 RR |
926 | hwc->config_base = x86_pmu_config_addr(hwc->idx); |
927 | hwc->event_base = x86_pmu_event_addr(hwc->idx); | |
1da53e02 SE |
928 | } |
929 | } | |
930 | ||
447a194b SE |
931 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
932 | struct cpu_hw_events *cpuc, | |
933 | int i) | |
934 | { | |
935 | return hwc->idx == cpuc->assign[i] && | |
936 | hwc->last_cpu == smp_processor_id() && | |
937 | hwc->last_tag == cpuc->tags[i]; | |
938 | } | |
939 | ||
a4eaf7f1 PZ |
940 | static void x86_pmu_start(struct perf_event *event, int flags); |
941 | static void x86_pmu_stop(struct perf_event *event, int flags); | |
2e841873 | 942 | |
a4eaf7f1 | 943 | static void x86_pmu_enable(struct pmu *pmu) |
ee06094f | 944 | { |
1da53e02 SE |
945 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
946 | struct perf_event *event; | |
947 | struct hw_perf_event *hwc; | |
11164cd4 | 948 | int i, added = cpuc->n_added; |
1da53e02 | 949 | |
85cf9dba | 950 | if (!x86_pmu_initialized()) |
2b9ff0db | 951 | return; |
1a6e21f7 PZ |
952 | |
953 | if (cpuc->enabled) | |
954 | return; | |
955 | ||
1da53e02 | 956 | if (cpuc->n_added) { |
19925ce7 | 957 | int n_running = cpuc->n_events - cpuc->n_added; |
1da53e02 SE |
958 | /* |
959 | * apply assignment obtained either from | |
960 | * hw_perf_group_sched_in() or x86_pmu_enable() | |
961 | * | |
962 | * step1: save events moving to new counters | |
963 | * step2: reprogram moved events into new counters | |
964 | */ | |
19925ce7 | 965 | for (i = 0; i < n_running; i++) { |
1da53e02 SE |
966 | event = cpuc->event_list[i]; |
967 | hwc = &event->hw; | |
968 | ||
447a194b SE |
969 | /* |
970 | * we can avoid reprogramming counter if: | |
971 | * - assigned same counter as last time | |
972 | * - running on same CPU as last time | |
973 | * - no other event has used the counter since | |
974 | */ | |
975 | if (hwc->idx == -1 || | |
976 | match_prev_assignment(hwc, cpuc, i)) | |
1da53e02 SE |
977 | continue; |
978 | ||
a4eaf7f1 PZ |
979 | /* |
980 | * Ensure we don't accidentally enable a stopped | |
981 | * counter simply because we rescheduled. | |
982 | */ | |
983 | if (hwc->state & PERF_HES_STOPPED) | |
984 | hwc->state |= PERF_HES_ARCH; | |
985 | ||
986 | x86_pmu_stop(event, PERF_EF_UPDATE); | |
1da53e02 SE |
987 | } |
988 | ||
989 | for (i = 0; i < cpuc->n_events; i++) { | |
1da53e02 SE |
990 | event = cpuc->event_list[i]; |
991 | hwc = &event->hw; | |
992 | ||
45e16a68 | 993 | if (!match_prev_assignment(hwc, cpuc, i)) |
447a194b | 994 | x86_assign_hw_event(event, cpuc, i); |
45e16a68 PZ |
995 | else if (i < n_running) |
996 | continue; | |
1da53e02 | 997 | |
a4eaf7f1 PZ |
998 | if (hwc->state & PERF_HES_ARCH) |
999 | continue; | |
1000 | ||
1001 | x86_pmu_start(event, PERF_EF_RELOAD); | |
1da53e02 SE |
1002 | } |
1003 | cpuc->n_added = 0; | |
1004 | perf_events_lapic_init(); | |
1005 | } | |
1a6e21f7 PZ |
1006 | |
1007 | cpuc->enabled = 1; | |
1008 | barrier(); | |
1009 | ||
11164cd4 | 1010 | x86_pmu.enable_all(added); |
ee06094f | 1011 | } |
ee06094f | 1012 | |
aff3d91a | 1013 | static inline void x86_pmu_disable_event(struct perf_event *event) |
b0f3f28e | 1014 | { |
aff3d91a | 1015 | struct hw_perf_event *hwc = &event->hw; |
7645a24c | 1016 | |
73d6e522 | 1017 | wrmsrl(hwc->config_base, hwc->config); |
b0f3f28e PZ |
1018 | } |
1019 | ||
245b2e70 | 1020 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 1021 | |
ee06094f IM |
1022 | /* |
1023 | * Set the next IRQ period, based on the hwc->period_left value. | |
cdd6c482 | 1024 | * To be called with the event disabled in hw: |
ee06094f | 1025 | */ |
e4abb5d4 | 1026 | static int |
07088edb | 1027 | x86_perf_event_set_period(struct perf_event *event) |
241771ef | 1028 | { |
07088edb | 1029 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 1030 | s64 left = local64_read(&hwc->period_left); |
e4abb5d4 | 1031 | s64 period = hwc->sample_period; |
7645a24c | 1032 | int ret = 0, idx = hwc->idx; |
ee06094f | 1033 | |
30dd568c MM |
1034 | if (idx == X86_PMC_IDX_FIXED_BTS) |
1035 | return 0; | |
1036 | ||
ee06094f | 1037 | /* |
af901ca1 | 1038 | * If we are way outside a reasonable range then just skip forward: |
ee06094f IM |
1039 | */ |
1040 | if (unlikely(left <= -period)) { | |
1041 | left = period; | |
e7850595 | 1042 | local64_set(&hwc->period_left, left); |
9e350de3 | 1043 | hwc->last_period = period; |
e4abb5d4 | 1044 | ret = 1; |
ee06094f IM |
1045 | } |
1046 | ||
1047 | if (unlikely(left <= 0)) { | |
1048 | left += period; | |
e7850595 | 1049 | local64_set(&hwc->period_left, left); |
9e350de3 | 1050 | hwc->last_period = period; |
e4abb5d4 | 1051 | ret = 1; |
ee06094f | 1052 | } |
1c80f4b5 | 1053 | /* |
dfc65094 | 1054 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
1055 | */ |
1056 | if (unlikely(left < 2)) | |
1057 | left = 2; | |
241771ef | 1058 | |
e4abb5d4 PZ |
1059 | if (left > x86_pmu.max_period) |
1060 | left = x86_pmu.max_period; | |
1061 | ||
245b2e70 | 1062 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
ee06094f IM |
1063 | |
1064 | /* | |
cdd6c482 | 1065 | * The hw event starts counting from this event offset, |
ee06094f IM |
1066 | * mark it to be able to extra future deltas: |
1067 | */ | |
e7850595 | 1068 | local64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 1069 | |
73d6e522 | 1070 | wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac CG |
1071 | |
1072 | /* | |
1073 | * Due to erratum on certan cpu we need | |
1074 | * a second write to be sure the register | |
1075 | * is updated properly | |
1076 | */ | |
1077 | if (x86_pmu.perfctr_second_write) { | |
73d6e522 | 1078 | wrmsrl(hwc->event_base, |
948b1bb8 | 1079 | (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac | 1080 | } |
e4abb5d4 | 1081 | |
cdd6c482 | 1082 | perf_event_update_userpage(event); |
194002b2 | 1083 | |
e4abb5d4 | 1084 | return ret; |
2f18d1e8 IM |
1085 | } |
1086 | ||
aff3d91a | 1087 | static void x86_pmu_enable_event(struct perf_event *event) |
7c90cc45 | 1088 | { |
0a3aee0d | 1089 | if (__this_cpu_read(cpu_hw_events.enabled)) |
31fa58af RR |
1090 | __x86_pmu_enable_event(&event->hw, |
1091 | ARCH_PERFMON_EVENTSEL_ENABLE); | |
241771ef IM |
1092 | } |
1093 | ||
b690081d | 1094 | /* |
a4eaf7f1 | 1095 | * Add a single event to the PMU. |
1da53e02 SE |
1096 | * |
1097 | * The event is added to the group of enabled events | |
1098 | * but only if it can be scehduled with existing events. | |
fe9081cc | 1099 | */ |
a4eaf7f1 | 1100 | static int x86_pmu_add(struct perf_event *event, int flags) |
fe9081cc PZ |
1101 | { |
1102 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1da53e02 SE |
1103 | struct hw_perf_event *hwc; |
1104 | int assign[X86_PMC_IDX_MAX]; | |
1105 | int n, n0, ret; | |
fe9081cc | 1106 | |
1da53e02 | 1107 | hwc = &event->hw; |
fe9081cc | 1108 | |
33696fc0 | 1109 | perf_pmu_disable(event->pmu); |
1da53e02 | 1110 | n0 = cpuc->n_events; |
24cd7f54 PZ |
1111 | ret = n = collect_events(cpuc, event, false); |
1112 | if (ret < 0) | |
1113 | goto out; | |
53b441a5 | 1114 | |
a4eaf7f1 PZ |
1115 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; |
1116 | if (!(flags & PERF_EF_START)) | |
1117 | hwc->state |= PERF_HES_ARCH; | |
1118 | ||
4d1c52b0 LM |
1119 | /* |
1120 | * If group events scheduling transaction was started, | |
0d2eb44f | 1121 | * skip the schedulability test here, it will be performed |
a4eaf7f1 | 1122 | * at commit time (->commit_txn) as a whole |
4d1c52b0 | 1123 | */ |
8d2cacbb | 1124 | if (cpuc->group_flag & PERF_EVENT_TXN) |
24cd7f54 | 1125 | goto done_collect; |
4d1c52b0 | 1126 | |
a072738e | 1127 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
1da53e02 | 1128 | if (ret) |
24cd7f54 | 1129 | goto out; |
1da53e02 SE |
1130 | /* |
1131 | * copy new assignment, now we know it is possible | |
1132 | * will be used by hw_perf_enable() | |
1133 | */ | |
1134 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
7e2ae347 | 1135 | |
24cd7f54 | 1136 | done_collect: |
1da53e02 | 1137 | cpuc->n_events = n; |
356e1f2e | 1138 | cpuc->n_added += n - n0; |
90151c35 | 1139 | cpuc->n_txn += n - n0; |
95cdd2e7 | 1140 | |
24cd7f54 PZ |
1141 | ret = 0; |
1142 | out: | |
33696fc0 | 1143 | perf_pmu_enable(event->pmu); |
24cd7f54 | 1144 | return ret; |
241771ef IM |
1145 | } |
1146 | ||
a4eaf7f1 | 1147 | static void x86_pmu_start(struct perf_event *event, int flags) |
d76a0812 | 1148 | { |
c08053e6 PZ |
1149 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
1150 | int idx = event->hw.idx; | |
1151 | ||
a4eaf7f1 PZ |
1152 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) |
1153 | return; | |
1154 | ||
1155 | if (WARN_ON_ONCE(idx == -1)) | |
1156 | return; | |
1157 | ||
1158 | if (flags & PERF_EF_RELOAD) { | |
1159 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1160 | x86_perf_event_set_period(event); | |
1161 | } | |
1162 | ||
1163 | event->hw.state = 0; | |
d76a0812 | 1164 | |
c08053e6 PZ |
1165 | cpuc->events[idx] = event; |
1166 | __set_bit(idx, cpuc->active_mask); | |
63e6be6d | 1167 | __set_bit(idx, cpuc->running); |
aff3d91a | 1168 | x86_pmu.enable(event); |
c08053e6 | 1169 | perf_event_update_userpage(event); |
a78ac325 PZ |
1170 | } |
1171 | ||
cdd6c482 | 1172 | void perf_event_print_debug(void) |
241771ef | 1173 | { |
2f18d1e8 | 1174 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
ca037701 | 1175 | u64 pebs; |
cdd6c482 | 1176 | struct cpu_hw_events *cpuc; |
5bb9efe3 | 1177 | unsigned long flags; |
1e125676 IM |
1178 | int cpu, idx; |
1179 | ||
948b1bb8 | 1180 | if (!x86_pmu.num_counters) |
1e125676 | 1181 | return; |
241771ef | 1182 | |
5bb9efe3 | 1183 | local_irq_save(flags); |
241771ef IM |
1184 | |
1185 | cpu = smp_processor_id(); | |
cdd6c482 | 1186 | cpuc = &per_cpu(cpu_hw_events, cpu); |
241771ef | 1187 | |
faa28ae0 | 1188 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1189 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1190 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1191 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1192 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
ca037701 | 1193 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); |
a1ef58f4 JSR |
1194 | |
1195 | pr_info("\n"); | |
1196 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1197 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1198 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1199 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
ca037701 | 1200 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); |
f87ad35d | 1201 | } |
7645a24c | 1202 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
241771ef | 1203 | |
948b1bb8 | 1204 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
41bf4989 RR |
1205 | rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); |
1206 | rdmsrl(x86_pmu_event_addr(idx), pmc_count); | |
241771ef | 1207 | |
245b2e70 | 1208 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 1209 | |
a1ef58f4 | 1210 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1211 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1212 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1213 | cpu, idx, pmc_count); |
a1ef58f4 | 1214 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1215 | cpu, idx, prev_left); |
241771ef | 1216 | } |
948b1bb8 | 1217 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
1218 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1219 | ||
a1ef58f4 | 1220 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1221 | cpu, idx, pmc_count); |
1222 | } | |
5bb9efe3 | 1223 | local_irq_restore(flags); |
241771ef IM |
1224 | } |
1225 | ||
a4eaf7f1 | 1226 | static void x86_pmu_stop(struct perf_event *event, int flags) |
241771ef | 1227 | { |
d76a0812 | 1228 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
cdd6c482 | 1229 | struct hw_perf_event *hwc = &event->hw; |
241771ef | 1230 | |
a4eaf7f1 PZ |
1231 | if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) { |
1232 | x86_pmu.disable(event); | |
1233 | cpuc->events[hwc->idx] = NULL; | |
1234 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); | |
1235 | hwc->state |= PERF_HES_STOPPED; | |
1236 | } | |
30dd568c | 1237 | |
a4eaf7f1 PZ |
1238 | if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { |
1239 | /* | |
1240 | * Drain the remaining delta count out of a event | |
1241 | * that we are disabling: | |
1242 | */ | |
1243 | x86_perf_event_update(event); | |
1244 | hwc->state |= PERF_HES_UPTODATE; | |
1245 | } | |
2e841873 PZ |
1246 | } |
1247 | ||
a4eaf7f1 | 1248 | static void x86_pmu_del(struct perf_event *event, int flags) |
2e841873 PZ |
1249 | { |
1250 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1251 | int i; | |
1252 | ||
90151c35 SE |
1253 | /* |
1254 | * If we're called during a txn, we don't need to do anything. | |
1255 | * The events never got scheduled and ->cancel_txn will truncate | |
1256 | * the event_list. | |
1257 | */ | |
8d2cacbb | 1258 | if (cpuc->group_flag & PERF_EVENT_TXN) |
90151c35 SE |
1259 | return; |
1260 | ||
a4eaf7f1 | 1261 | x86_pmu_stop(event, PERF_EF_UPDATE); |
194002b2 | 1262 | |
1da53e02 SE |
1263 | for (i = 0; i < cpuc->n_events; i++) { |
1264 | if (event == cpuc->event_list[i]) { | |
1265 | ||
1266 | if (x86_pmu.put_event_constraints) | |
1267 | x86_pmu.put_event_constraints(cpuc, event); | |
1268 | ||
1269 | while (++i < cpuc->n_events) | |
1270 | cpuc->event_list[i-1] = cpuc->event_list[i]; | |
1271 | ||
1272 | --cpuc->n_events; | |
6c9687ab | 1273 | break; |
1da53e02 SE |
1274 | } |
1275 | } | |
cdd6c482 | 1276 | perf_event_update_userpage(event); |
241771ef IM |
1277 | } |
1278 | ||
8c48e444 | 1279 | static int x86_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1280 | { |
df1a132b | 1281 | struct perf_sample_data data; |
cdd6c482 IM |
1282 | struct cpu_hw_events *cpuc; |
1283 | struct perf_event *event; | |
11d1578f | 1284 | int idx, handled = 0; |
9029a5e3 IM |
1285 | u64 val; |
1286 | ||
dc1d628a | 1287 | perf_sample_data_init(&data, 0); |
df1a132b | 1288 | |
cdd6c482 | 1289 | cpuc = &__get_cpu_var(cpu_hw_events); |
962bf7a6 | 1290 | |
948b1bb8 | 1291 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
63e6be6d RR |
1292 | if (!test_bit(idx, cpuc->active_mask)) { |
1293 | /* | |
1294 | * Though we deactivated the counter some cpus | |
1295 | * might still deliver spurious interrupts still | |
1296 | * in flight. Catch them: | |
1297 | */ | |
1298 | if (__test_and_clear_bit(idx, cpuc->running)) | |
1299 | handled++; | |
a29aa8a7 | 1300 | continue; |
63e6be6d | 1301 | } |
962bf7a6 | 1302 | |
cdd6c482 | 1303 | event = cpuc->events[idx]; |
a4016a79 | 1304 | |
cc2ad4ba | 1305 | val = x86_perf_event_update(event); |
948b1bb8 | 1306 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
48e22d56 | 1307 | continue; |
962bf7a6 | 1308 | |
9e350de3 | 1309 | /* |
cdd6c482 | 1310 | * event overflow |
9e350de3 | 1311 | */ |
4177c42a | 1312 | handled++; |
cdd6c482 | 1313 | data.period = event->hw.last_period; |
9e350de3 | 1314 | |
07088edb | 1315 | if (!x86_perf_event_set_period(event)) |
e4abb5d4 PZ |
1316 | continue; |
1317 | ||
cdd6c482 | 1318 | if (perf_event_overflow(event, 1, &data, regs)) |
a4eaf7f1 | 1319 | x86_pmu_stop(event, 0); |
a29aa8a7 | 1320 | } |
962bf7a6 | 1321 | |
9e350de3 PZ |
1322 | if (handled) |
1323 | inc_irq_stat(apic_perf_irqs); | |
1324 | ||
a29aa8a7 RR |
1325 | return handled; |
1326 | } | |
39d81eab | 1327 | |
cdd6c482 | 1328 | void perf_events_lapic_init(void) |
241771ef | 1329 | { |
04da8a43 | 1330 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
241771ef | 1331 | return; |
85cf9dba | 1332 | |
241771ef | 1333 | /* |
c323d95f | 1334 | * Always use NMI for PMU |
241771ef | 1335 | */ |
c323d95f | 1336 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1337 | } |
1338 | ||
4177c42a RR |
1339 | struct pmu_nmi_state { |
1340 | unsigned int marked; | |
1341 | int handled; | |
1342 | }; | |
1343 | ||
1344 | static DEFINE_PER_CPU(struct pmu_nmi_state, pmu_nmi); | |
1345 | ||
241771ef | 1346 | static int __kprobes |
cdd6c482 | 1347 | perf_event_nmi_handler(struct notifier_block *self, |
241771ef IM |
1348 | unsigned long cmd, void *__args) |
1349 | { | |
1350 | struct die_args *args = __args; | |
4177c42a RR |
1351 | unsigned int this_nmi; |
1352 | int handled; | |
b0f3f28e | 1353 | |
cdd6c482 | 1354 | if (!atomic_read(&active_events)) |
63a809a2 PZ |
1355 | return NOTIFY_DONE; |
1356 | ||
b0f3f28e PZ |
1357 | switch (cmd) { |
1358 | case DIE_NMI: | |
b0f3f28e | 1359 | break; |
4177c42a RR |
1360 | case DIE_NMIUNKNOWN: |
1361 | this_nmi = percpu_read(irq_stat.__nmi_count); | |
0a3aee0d | 1362 | if (this_nmi != __this_cpu_read(pmu_nmi.marked)) |
4177c42a RR |
1363 | /* let the kernel handle the unknown nmi */ |
1364 | return NOTIFY_DONE; | |
1365 | /* | |
1366 | * This one is a PMU back-to-back nmi. Two events | |
1367 | * trigger 'simultaneously' raising two back-to-back | |
1368 | * NMIs. If the first NMI handles both, the latter | |
1369 | * will be empty and daze the CPU. So, we drop it to | |
1370 | * avoid false-positive 'unknown nmi' messages. | |
1371 | */ | |
1372 | return NOTIFY_STOP; | |
b0f3f28e | 1373 | default: |
241771ef | 1374 | return NOTIFY_DONE; |
b0f3f28e | 1375 | } |
241771ef | 1376 | |
241771ef | 1377 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
4177c42a RR |
1378 | |
1379 | handled = x86_pmu.handle_irq(args->regs); | |
1380 | if (!handled) | |
1381 | return NOTIFY_DONE; | |
1382 | ||
1383 | this_nmi = percpu_read(irq_stat.__nmi_count); | |
1384 | if ((handled > 1) || | |
1385 | /* the next nmi could be a back-to-back nmi */ | |
0a3aee0d TH |
1386 | ((__this_cpu_read(pmu_nmi.marked) == this_nmi) && |
1387 | (__this_cpu_read(pmu_nmi.handled) > 1))) { | |
4177c42a RR |
1388 | /* |
1389 | * We could have two subsequent back-to-back nmis: The | |
1390 | * first handles more than one counter, the 2nd | |
1391 | * handles only one counter and the 3rd handles no | |
1392 | * counter. | |
1393 | * | |
1394 | * This is the 2nd nmi because the previous was | |
1395 | * handling more than one counter. We will mark the | |
1396 | * next (3rd) and then drop it if unhandled. | |
1397 | */ | |
0a3aee0d TH |
1398 | __this_cpu_write(pmu_nmi.marked, this_nmi + 1); |
1399 | __this_cpu_write(pmu_nmi.handled, handled); | |
4177c42a | 1400 | } |
241771ef | 1401 | |
a4016a79 | 1402 | return NOTIFY_STOP; |
241771ef IM |
1403 | } |
1404 | ||
f22f54f4 PZ |
1405 | static __read_mostly struct notifier_block perf_event_nmi_notifier = { |
1406 | .notifier_call = perf_event_nmi_handler, | |
1407 | .next = NULL, | |
166d7514 | 1408 | .priority = NMI_LOCAL_LOW_PRIOR, |
f22f54f4 PZ |
1409 | }; |
1410 | ||
63b14649 | 1411 | static struct event_constraint unconstrained; |
38331f62 | 1412 | static struct event_constraint emptyconstraint; |
63b14649 | 1413 | |
63b14649 | 1414 | static struct event_constraint * |
f22f54f4 | 1415 | x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event) |
1da53e02 | 1416 | { |
63b14649 | 1417 | struct event_constraint *c; |
1da53e02 | 1418 | |
1da53e02 SE |
1419 | if (x86_pmu.event_constraints) { |
1420 | for_each_event_constraint(c, x86_pmu.event_constraints) { | |
63b14649 PZ |
1421 | if ((event->hw.config & c->cmask) == c->code) |
1422 | return c; | |
1da53e02 SE |
1423 | } |
1424 | } | |
63b14649 PZ |
1425 | |
1426 | return &unconstrained; | |
1da53e02 SE |
1427 | } |
1428 | ||
f22f54f4 PZ |
1429 | #include "perf_event_amd.c" |
1430 | #include "perf_event_p6.c" | |
a072738e | 1431 | #include "perf_event_p4.c" |
caff2bef | 1432 | #include "perf_event_intel_lbr.c" |
ca037701 | 1433 | #include "perf_event_intel_ds.c" |
f22f54f4 | 1434 | #include "perf_event_intel.c" |
f87ad35d | 1435 | |
3f6da390 PZ |
1436 | static int __cpuinit |
1437 | x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) | |
1438 | { | |
1439 | unsigned int cpu = (long)hcpu; | |
b38b24ea | 1440 | int ret = NOTIFY_OK; |
3f6da390 PZ |
1441 | |
1442 | switch (action & ~CPU_TASKS_FROZEN) { | |
1443 | case CPU_UP_PREPARE: | |
1444 | if (x86_pmu.cpu_prepare) | |
b38b24ea | 1445 | ret = x86_pmu.cpu_prepare(cpu); |
3f6da390 PZ |
1446 | break; |
1447 | ||
1448 | case CPU_STARTING: | |
1449 | if (x86_pmu.cpu_starting) | |
1450 | x86_pmu.cpu_starting(cpu); | |
1451 | break; | |
1452 | ||
1453 | case CPU_DYING: | |
1454 | if (x86_pmu.cpu_dying) | |
1455 | x86_pmu.cpu_dying(cpu); | |
1456 | break; | |
1457 | ||
b38b24ea | 1458 | case CPU_UP_CANCELED: |
3f6da390 PZ |
1459 | case CPU_DEAD: |
1460 | if (x86_pmu.cpu_dead) | |
1461 | x86_pmu.cpu_dead(cpu); | |
1462 | break; | |
1463 | ||
1464 | default: | |
1465 | break; | |
1466 | } | |
1467 | ||
b38b24ea | 1468 | return ret; |
3f6da390 PZ |
1469 | } |
1470 | ||
12558038 CG |
1471 | static void __init pmu_check_apic(void) |
1472 | { | |
1473 | if (cpu_has_apic) | |
1474 | return; | |
1475 | ||
1476 | x86_pmu.apic = 0; | |
1477 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); | |
1478 | pr_info("no hardware sampling interrupt available.\n"); | |
1479 | } | |
1480 | ||
dda99116 | 1481 | static int __init init_hw_perf_events(void) |
b56a3802 | 1482 | { |
b622d644 | 1483 | struct event_constraint *c; |
72eae04d RR |
1484 | int err; |
1485 | ||
cdd6c482 | 1486 | pr_info("Performance Events: "); |
1123e3ad | 1487 | |
b56a3802 JSR |
1488 | switch (boot_cpu_data.x86_vendor) { |
1489 | case X86_VENDOR_INTEL: | |
72eae04d | 1490 | err = intel_pmu_init(); |
b56a3802 | 1491 | break; |
f87ad35d | 1492 | case X86_VENDOR_AMD: |
72eae04d | 1493 | err = amd_pmu_init(); |
f87ad35d | 1494 | break; |
4138960a | 1495 | default: |
004417a6 | 1496 | return 0; |
b56a3802 | 1497 | } |
1123e3ad | 1498 | if (err != 0) { |
cdd6c482 | 1499 | pr_cont("no PMU driver, software events only.\n"); |
004417a6 | 1500 | return 0; |
1123e3ad | 1501 | } |
b56a3802 | 1502 | |
12558038 CG |
1503 | pmu_check_apic(); |
1504 | ||
33c6d6a7 | 1505 | /* sanity check that the hardware exists or is emulated */ |
4407204c | 1506 | if (!check_hw_exists()) |
004417a6 | 1507 | return 0; |
33c6d6a7 | 1508 | |
1123e3ad | 1509 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1510 | |
3c44780b PZ |
1511 | if (x86_pmu.quirks) |
1512 | x86_pmu.quirks(); | |
1513 | ||
948b1bb8 | 1514 | if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) { |
cdd6c482 | 1515 | WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", |
948b1bb8 RR |
1516 | x86_pmu.num_counters, X86_PMC_MAX_GENERIC); |
1517 | x86_pmu.num_counters = X86_PMC_MAX_GENERIC; | |
241771ef | 1518 | } |
948b1bb8 | 1519 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; |
241771ef | 1520 | |
948b1bb8 | 1521 | if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { |
cdd6c482 | 1522 | WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", |
948b1bb8 RR |
1523 | x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED); |
1524 | x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; | |
703e937c | 1525 | } |
862a1a5f | 1526 | |
d6dc0b4e | 1527 | x86_pmu.intel_ctrl |= |
948b1bb8 | 1528 | ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED; |
241771ef | 1529 | |
cdd6c482 IM |
1530 | perf_events_lapic_init(); |
1531 | register_die_notifier(&perf_event_nmi_notifier); | |
1123e3ad | 1532 | |
63b14649 | 1533 | unconstrained = (struct event_constraint) |
948b1bb8 RR |
1534 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
1535 | 0, x86_pmu.num_counters); | |
63b14649 | 1536 | |
b622d644 PZ |
1537 | if (x86_pmu.event_constraints) { |
1538 | for_each_event_constraint(c, x86_pmu.event_constraints) { | |
a098f448 | 1539 | if (c->cmask != X86_RAW_EVENT_MASK) |
b622d644 PZ |
1540 | continue; |
1541 | ||
948b1bb8 RR |
1542 | c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; |
1543 | c->weight += x86_pmu.num_counters; | |
b622d644 PZ |
1544 | } |
1545 | } | |
1546 | ||
57c0c15b | 1547 | pr_info("... version: %d\n", x86_pmu.version); |
948b1bb8 RR |
1548 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); |
1549 | pr_info("... generic registers: %d\n", x86_pmu.num_counters); | |
1550 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); | |
57c0c15b | 1551 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
948b1bb8 | 1552 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); |
d6dc0b4e | 1553 | pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); |
3f6da390 | 1554 | |
2e80a82a | 1555 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
3f6da390 | 1556 | perf_cpu_notifier(x86_pmu_notifier); |
004417a6 PZ |
1557 | |
1558 | return 0; | |
241771ef | 1559 | } |
004417a6 | 1560 | early_initcall(init_hw_perf_events); |
621a01ea | 1561 | |
cdd6c482 | 1562 | static inline void x86_pmu_read(struct perf_event *event) |
ee06094f | 1563 | { |
cc2ad4ba | 1564 | x86_perf_event_update(event); |
ee06094f IM |
1565 | } |
1566 | ||
4d1c52b0 LM |
1567 | /* |
1568 | * Start group events scheduling transaction | |
1569 | * Set the flag to make pmu::enable() not perform the | |
1570 | * schedulability test, it will be performed at commit time | |
1571 | */ | |
51b0fe39 | 1572 | static void x86_pmu_start_txn(struct pmu *pmu) |
4d1c52b0 | 1573 | { |
33696fc0 | 1574 | perf_pmu_disable(pmu); |
0a3aee0d TH |
1575 | __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN); |
1576 | __this_cpu_write(cpu_hw_events.n_txn, 0); | |
4d1c52b0 LM |
1577 | } |
1578 | ||
1579 | /* | |
1580 | * Stop group events scheduling transaction | |
1581 | * Clear the flag and pmu::enable() will perform the | |
1582 | * schedulability test. | |
1583 | */ | |
51b0fe39 | 1584 | static void x86_pmu_cancel_txn(struct pmu *pmu) |
4d1c52b0 | 1585 | { |
0a3aee0d | 1586 | __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN); |
90151c35 SE |
1587 | /* |
1588 | * Truncate the collected events. | |
1589 | */ | |
0a3aee0d TH |
1590 | __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn)); |
1591 | __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn)); | |
33696fc0 | 1592 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1593 | } |
1594 | ||
1595 | /* | |
1596 | * Commit group events scheduling transaction | |
1597 | * Perform the group schedulability test as a whole | |
1598 | * Return 0 if success | |
1599 | */ | |
51b0fe39 | 1600 | static int x86_pmu_commit_txn(struct pmu *pmu) |
4d1c52b0 LM |
1601 | { |
1602 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1603 | int assign[X86_PMC_IDX_MAX]; | |
1604 | int n, ret; | |
1605 | ||
1606 | n = cpuc->n_events; | |
1607 | ||
1608 | if (!x86_pmu_initialized()) | |
1609 | return -EAGAIN; | |
1610 | ||
1611 | ret = x86_pmu.schedule_events(cpuc, n, assign); | |
1612 | if (ret) | |
1613 | return ret; | |
1614 | ||
1615 | /* | |
1616 | * copy new assignment, now we know it is possible | |
1617 | * will be used by hw_perf_enable() | |
1618 | */ | |
1619 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
1620 | ||
8d2cacbb | 1621 | cpuc->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1622 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1623 | return 0; |
1624 | } | |
1625 | ||
ca037701 PZ |
1626 | /* |
1627 | * validate that we can schedule this event | |
1628 | */ | |
1629 | static int validate_event(struct perf_event *event) | |
1630 | { | |
1631 | struct cpu_hw_events *fake_cpuc; | |
1632 | struct event_constraint *c; | |
1633 | int ret = 0; | |
1634 | ||
1635 | fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO); | |
1636 | if (!fake_cpuc) | |
1637 | return -ENOMEM; | |
1638 | ||
1639 | c = x86_pmu.get_event_constraints(fake_cpuc, event); | |
1640 | ||
1641 | if (!c || !c->weight) | |
1642 | ret = -ENOSPC; | |
1643 | ||
1644 | if (x86_pmu.put_event_constraints) | |
1645 | x86_pmu.put_event_constraints(fake_cpuc, event); | |
1646 | ||
1647 | kfree(fake_cpuc); | |
1648 | ||
1649 | return ret; | |
1650 | } | |
1651 | ||
1da53e02 SE |
1652 | /* |
1653 | * validate a single event group | |
1654 | * | |
1655 | * validation include: | |
184f412c IM |
1656 | * - check events are compatible which each other |
1657 | * - events do not compete for the same counter | |
1658 | * - number of events <= number of counters | |
1da53e02 SE |
1659 | * |
1660 | * validation ensures the group can be loaded onto the | |
1661 | * PMU if it was the only group available. | |
1662 | */ | |
fe9081cc PZ |
1663 | static int validate_group(struct perf_event *event) |
1664 | { | |
1da53e02 | 1665 | struct perf_event *leader = event->group_leader; |
502568d5 PZ |
1666 | struct cpu_hw_events *fake_cpuc; |
1667 | int ret, n; | |
fe9081cc | 1668 | |
502568d5 PZ |
1669 | ret = -ENOMEM; |
1670 | fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO); | |
1671 | if (!fake_cpuc) | |
1672 | goto out; | |
fe9081cc | 1673 | |
1da53e02 SE |
1674 | /* |
1675 | * the event is not yet connected with its | |
1676 | * siblings therefore we must first collect | |
1677 | * existing siblings, then add the new event | |
1678 | * before we can simulate the scheduling | |
1679 | */ | |
502568d5 PZ |
1680 | ret = -ENOSPC; |
1681 | n = collect_events(fake_cpuc, leader, true); | |
1da53e02 | 1682 | if (n < 0) |
502568d5 | 1683 | goto out_free; |
fe9081cc | 1684 | |
502568d5 PZ |
1685 | fake_cpuc->n_events = n; |
1686 | n = collect_events(fake_cpuc, event, false); | |
1da53e02 | 1687 | if (n < 0) |
502568d5 | 1688 | goto out_free; |
fe9081cc | 1689 | |
502568d5 | 1690 | fake_cpuc->n_events = n; |
1da53e02 | 1691 | |
a072738e | 1692 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
502568d5 PZ |
1693 | |
1694 | out_free: | |
1695 | kfree(fake_cpuc); | |
1696 | out: | |
1697 | return ret; | |
fe9081cc PZ |
1698 | } |
1699 | ||
dda99116 | 1700 | static int x86_pmu_event_init(struct perf_event *event) |
621a01ea | 1701 | { |
51b0fe39 | 1702 | struct pmu *tmp; |
621a01ea IM |
1703 | int err; |
1704 | ||
b0a873eb PZ |
1705 | switch (event->attr.type) { |
1706 | case PERF_TYPE_RAW: | |
1707 | case PERF_TYPE_HARDWARE: | |
1708 | case PERF_TYPE_HW_CACHE: | |
1709 | break; | |
1710 | ||
1711 | default: | |
1712 | return -ENOENT; | |
1713 | } | |
1714 | ||
1715 | err = __x86_pmu_event_init(event); | |
fe9081cc | 1716 | if (!err) { |
8113070d SE |
1717 | /* |
1718 | * we temporarily connect event to its pmu | |
1719 | * such that validate_group() can classify | |
1720 | * it as an x86 event using is_x86_event() | |
1721 | */ | |
1722 | tmp = event->pmu; | |
1723 | event->pmu = &pmu; | |
1724 | ||
fe9081cc PZ |
1725 | if (event->group_leader != event) |
1726 | err = validate_group(event); | |
ca037701 PZ |
1727 | else |
1728 | err = validate_event(event); | |
8113070d SE |
1729 | |
1730 | event->pmu = tmp; | |
fe9081cc | 1731 | } |
a1792cda | 1732 | if (err) { |
cdd6c482 IM |
1733 | if (event->destroy) |
1734 | event->destroy(event); | |
a1792cda | 1735 | } |
621a01ea | 1736 | |
b0a873eb | 1737 | return err; |
621a01ea | 1738 | } |
d7d59fb3 | 1739 | |
b0a873eb | 1740 | static struct pmu pmu = { |
a4eaf7f1 PZ |
1741 | .pmu_enable = x86_pmu_enable, |
1742 | .pmu_disable = x86_pmu_disable, | |
1743 | ||
b0a873eb | 1744 | .event_init = x86_pmu_event_init, |
a4eaf7f1 PZ |
1745 | |
1746 | .add = x86_pmu_add, | |
1747 | .del = x86_pmu_del, | |
b0a873eb PZ |
1748 | .start = x86_pmu_start, |
1749 | .stop = x86_pmu_stop, | |
1750 | .read = x86_pmu_read, | |
a4eaf7f1 | 1751 | |
b0a873eb PZ |
1752 | .start_txn = x86_pmu_start_txn, |
1753 | .cancel_txn = x86_pmu_cancel_txn, | |
1754 | .commit_txn = x86_pmu_commit_txn, | |
1755 | }; | |
1756 | ||
d7d59fb3 PZ |
1757 | /* |
1758 | * callchain support | |
1759 | */ | |
1760 | ||
d7d59fb3 PZ |
1761 | static void |
1762 | backtrace_warning_symbol(void *data, char *msg, unsigned long symbol) | |
1763 | { | |
1764 | /* Ignore warnings */ | |
1765 | } | |
1766 | ||
1767 | static void backtrace_warning(void *data, char *msg) | |
1768 | { | |
1769 | /* Ignore warnings */ | |
1770 | } | |
1771 | ||
1772 | static int backtrace_stack(void *data, char *name) | |
1773 | { | |
038e836e | 1774 | return 0; |
d7d59fb3 PZ |
1775 | } |
1776 | ||
1777 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1778 | { | |
1779 | struct perf_callchain_entry *entry = data; | |
1780 | ||
70791ce9 | 1781 | perf_callchain_store(entry, addr); |
d7d59fb3 PZ |
1782 | } |
1783 | ||
1784 | static const struct stacktrace_ops backtrace_ops = { | |
1785 | .warning = backtrace_warning, | |
1786 | .warning_symbol = backtrace_warning_symbol, | |
1787 | .stack = backtrace_stack, | |
1788 | .address = backtrace_address, | |
06d65bda | 1789 | .walk_stack = print_context_stack_bp, |
d7d59fb3 PZ |
1790 | }; |
1791 | ||
56962b44 FW |
1792 | void |
1793 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 | 1794 | { |
927c7a9e FW |
1795 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1796 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1797 | return; |
927c7a9e FW |
1798 | } |
1799 | ||
70791ce9 | 1800 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1801 | |
e8e999cf | 1802 | dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry); |
d7d59fb3 PZ |
1803 | } |
1804 | ||
257ef9d2 TE |
1805 | #ifdef CONFIG_COMPAT |
1806 | static inline int | |
1807 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
74193ef0 | 1808 | { |
257ef9d2 TE |
1809 | /* 32-bit process in 64-bit kernel. */ |
1810 | struct stack_frame_ia32 frame; | |
1811 | const void __user *fp; | |
74193ef0 | 1812 | |
257ef9d2 TE |
1813 | if (!test_thread_flag(TIF_IA32)) |
1814 | return 0; | |
1815 | ||
1816 | fp = compat_ptr(regs->bp); | |
1817 | while (entry->nr < PERF_MAX_STACK_DEPTH) { | |
1818 | unsigned long bytes; | |
1819 | frame.next_frame = 0; | |
1820 | frame.return_address = 0; | |
1821 | ||
1822 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); | |
1823 | if (bytes != sizeof(frame)) | |
1824 | break; | |
74193ef0 | 1825 | |
257ef9d2 TE |
1826 | if (fp < compat_ptr(regs->sp)) |
1827 | break; | |
74193ef0 | 1828 | |
70791ce9 | 1829 | perf_callchain_store(entry, frame.return_address); |
257ef9d2 TE |
1830 | fp = compat_ptr(frame.next_frame); |
1831 | } | |
1832 | return 1; | |
d7d59fb3 | 1833 | } |
257ef9d2 TE |
1834 | #else |
1835 | static inline int | |
1836 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1837 | { | |
1838 | return 0; | |
1839 | } | |
1840 | #endif | |
d7d59fb3 | 1841 | |
56962b44 FW |
1842 | void |
1843 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 PZ |
1844 | { |
1845 | struct stack_frame frame; | |
1846 | const void __user *fp; | |
1847 | ||
927c7a9e FW |
1848 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1849 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1850 | return; |
927c7a9e | 1851 | } |
5a6cec3a | 1852 | |
74193ef0 | 1853 | fp = (void __user *)regs->bp; |
d7d59fb3 | 1854 | |
70791ce9 | 1855 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1856 | |
257ef9d2 TE |
1857 | if (perf_callchain_user32(regs, entry)) |
1858 | return; | |
1859 | ||
f9188e02 | 1860 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
257ef9d2 | 1861 | unsigned long bytes; |
038e836e | 1862 | frame.next_frame = NULL; |
d7d59fb3 PZ |
1863 | frame.return_address = 0; |
1864 | ||
257ef9d2 TE |
1865 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); |
1866 | if (bytes != sizeof(frame)) | |
d7d59fb3 PZ |
1867 | break; |
1868 | ||
5a6cec3a | 1869 | if ((unsigned long)fp < regs->sp) |
d7d59fb3 PZ |
1870 | break; |
1871 | ||
70791ce9 | 1872 | perf_callchain_store(entry, frame.return_address); |
038e836e | 1873 | fp = frame.next_frame; |
d7d59fb3 PZ |
1874 | } |
1875 | } | |
1876 | ||
39447b38 ZY |
1877 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
1878 | { | |
1879 | unsigned long ip; | |
dcf46b94 | 1880 | |
39447b38 ZY |
1881 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) |
1882 | ip = perf_guest_cbs->get_guest_ip(); | |
1883 | else | |
1884 | ip = instruction_pointer(regs); | |
dcf46b94 | 1885 | |
39447b38 ZY |
1886 | return ip; |
1887 | } | |
1888 | ||
1889 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
1890 | { | |
1891 | int misc = 0; | |
dcf46b94 | 1892 | |
39447b38 | 1893 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
dcf46b94 ZY |
1894 | if (perf_guest_cbs->is_user_mode()) |
1895 | misc |= PERF_RECORD_MISC_GUEST_USER; | |
1896 | else | |
1897 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
1898 | } else { | |
1899 | if (user_mode(regs)) | |
1900 | misc |= PERF_RECORD_MISC_USER; | |
1901 | else | |
1902 | misc |= PERF_RECORD_MISC_KERNEL; | |
1903 | } | |
1904 | ||
39447b38 | 1905 | if (regs->flags & PERF_EFLAGS_EXACT) |
ab608344 | 1906 | misc |= PERF_RECORD_MISC_EXACT_IP; |
39447b38 ZY |
1907 | |
1908 | return misc; | |
1909 | } |